73S8024C
Smart Card Interface
Simplifying System Integration™
DATA SHEET
April 2009
DESCRIPTION
FEATURES
The Teridian 73S8024C is a single smart card
interface IC. It provides full electrical compliance
with ISO-7816-3, EMV 4.0 and NDS specifications1.
•
Card Interface:
Complies with ISO-7816-3, EMV 4.0 and NDS1
A DC-DC Converter provides 3V / 5V to the
card from an external power supply input
High-efficiency converter: > 80% @
V DD =3.3 V, V CC =5 V and I CC = 65 mA
Up to 100 mA supplied to the card
ISO-7816-3 Activation / Deactivation
sequencer with emergency automated
deactivation on card removal or fault
detected by the protection circuitry
Protection includes 2 voltage supervisors
which detect voltage drops on card V CC and
on V DD power supplies
The V DD voltage supervisor threshold value
can be externally adjusted
True over-current detection (150 mA max.)
2 card detection inputs, 1 for each possible
user polarity
Auxiliary I/O lines, for C4/C8 contact signals
Card clock up to 20 MHz
•
System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
4 Digital inputs control the card clock
(division rate and card clock stop modes)
1 Digital output, interrupt to the system
controller, allows the system controller to
monitor the card presence and faults.
Crystal oscillator or host clock, up to 27 MHz
•
Power Supply: V DD 2.7 V to 3.6 V
•
Power Down mode
Interfacing with the system controller is done through
the control bus, composed of digital inputs to control
the interface, and one interrupt output to inform the
system controller of the card presence and faults.
Data exchange with the card is managed from the
system controller using the I/O line (and eventually
the auxiliary I/O lines). Hardware support for
auxiliary I/O lines, C4 / C8 contacts, is provided.
The card clock signal can be generated by an on-chip
oscillator using an external crystal or by connection to
a clock signal coming from the system controller.
The Teridian 73S8024C device incorporates an
ISO-7816-3 activation/deactivation sequencer that
controls the card signals. Level shifters drive the
card signals with the selected card voltage (3 V or
5 V), coming from an internal DC-DC converter.
With its high-efficiency DC-DC converter, the
Teridian 73S8024C is a cost-effective solution for
any smart card reader application to be powered
from a single 2.7 V to 3.6 V power supply.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the
protection circuitry. The fault can be a V DD (digital
power supply) or a V CC (card power supply) failure,
a card over-current, or an over-heating fault.
ADVANTAGES
• The only smart card interface IC firmware
compatible with the TDA8004 operating with a
single 2.7 V to 3.6 V power supply (allows
removal of 5 V from the system)
• The inductor-based DC-DC converter provides
higher current and efficiency than the usual
charge-pump capacitor-based converters
Ideal for battery-powered applications
Suitable for high current cards and SAMs:
(100 mA max)
•
•
6 kV ESD Protection on the card interface
•
Package: SO28
APPLICATIONS
•
Set-Top-Boxes , DVD / HDD Recorders
•
Point of Sales and Transaction Terminals
•
Control Access and Identification
Power down mode: 2 µA typical
1
Rev. 1.3
Pending NDS approval.
© 2009 Teridian Semiconductor Corporation
1
73S8024C Data Sheet
DS_8024C_023
FUNCTIONAL DIAGRAM
VDD
LIN
VDDF_ADJ
21
VDD
5
18
6
6
6
7
NC
ICC FAULT
22
VDD VOLTAGE SUPERVISOR
VOLTAGE REFERENCE
GND
4
GND
VDD FAULT
VCC FAULT
DC-DC
CONVERTER
14
GND
8
PWRDN
17
VCC
19
Int_Clk
CMDVCC
DIGITAL
CIRCUITRY
&
FAULT LOGIC
20
RSTIN
3
5V/#V
23
R-C
OSC.
ICC RESET
BUFFER
16
ICC CLOCK
BUFFER
15
RST
OFF
1
CLKDIV1
2
ISO-7816-3
SEQUENCER
CLKDIV2
24
XTALIN
25
XTALOUT
CLK
10
PRES
XTAL
OSC
9
CLOCK
GENERATION
PRES
OVER
TEMP
TEMP FAULT
11
26
IOUC
27
I/O
ICC I/O BUFFERS
AUX1UC
13
AUX1
12
28
AUX2
AUX2UC
Pin number reference to SO28 Package
Figure 1: 73S8024C Block Diagram
2
Rev. 1.3
DS_8024C_023
73S8024C Data Sheet
Table of Contents
1
Pin Description .................................................................................................................................... 4
1.1 Card Interface ............................................................................................................................... 4
1.2 Miscellaneous Inputs and Outputs................................................................................................ 4
1.3 Power supply and ground ............................................................................................................. 4
1.4 Microcontroller Interface ............................................................................................................... 5
2
System Controller Interface ............................................................................................................... 6
3
Oscillator.............................................................................................................................................. 6
4
DC-DC Converter – Card Power Supply ........................................................................................... 7
5
Over-temperature Monitor.................................................................................................................. 7
6
Voltage Supervision ........................................................................................................................... 8
7
Power Down......................................................................................................................................... 8
8
Activation Sequence ........................................................................................................................... 9
9
Deactivation Sequence..................................................................................................................... 10
10
OFF and Fault Detection .................................................................................................................. 11
11
I/O Circuitry and Timing ................................................................................................................... 12
12
Typical Application Schematic ........................................................................................................ 13
13
Electrical Specification..................................................................................................................... 14
13.1 Absolute Maximum Ratings ........................................................................................................ 14
13.2 Recommended Operating Conditions......................................................................................... 14
13.3 Card Interface Characteristics .................................................................................................... 15
13.4 Digital Signals ............................................................................................................................. 18
13.5 DC Characteristics ...................................................................................................................... 18
13.6 Voltage / Temperature Fault Detection Circuits.......................................................................... 18
14
Mechanical Drawings (28-SO).......................................................................................................... 19
15
Package Pin Designation (28-SO) ................................................................................................... 20
16
Ordering Information ........................................................................................................................ 21
17
Related Documentation .................................................................................................................... 21
18
Contact Information .......................................................................................................................... 21
Revision History ........................................................................................................................................ 22
Figures
Figure 1: 73S8024C Block Diagram ............................................................................................................. 2
Figure 2: Power Down Mode Operation........................................................................................................ 9
Figure 3: Activation Sequence – RSTIN low when CMDVCC goes low ....................................................... 9
Figure 4: Activation Sequence – RSTIN high when CMDVCC goes low ................................................... 10
Figure 5: Deactivation Sequence ............................................................................................................... 11
Figure 6: Timing Diagram – Management of the Interrupt Line OFF .......................................................... 11
Figure 7: I/O and I/OUC State Diagram ...................................................................................................... 12
Figure 8: I/O – I/OUC Delays: Timing Diagram........................................................................................... 12
Figure 9: 73S8024C Typical Application Schematic ................................................................................... 13
Figure 10: DC – DC Converter efficiency (V CC = 5 V) ................................................................................ 16
Figure 11: DC – DC Converter Efficiency (V CC = 3 V) ................................................................................ 16
Figure 12: 28 Lead SO ................................................................................................................................ 19
Table
Table 1: Choice of VCC Pin Capacitor .......................................................................................................... 7
Rev. 1.3
3
73S8024C Data Sheet
DS_8024C_023
1 Pin Description
1.1
Card Interface
Name
Pin
(SO)
Description
IO
11
Card I/O: Data signal to/from card. Includes a pull-up resistor to V CC.
AUX1
13
AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V CC.
AUX2
12
AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V CC.
RST
16
Card reset: provides reset (RST) signal to card.
CLK
15
Card clock: provides clock (CLK) signal to card. The rate of this clock is
determined by crystal oscillator frequency and CLKDIV selections.
PRES
10
Card Presence switch: active high indicates card is present. Includes a pulldown current source.
PRES
9
Card Presence switch: active low indicates card is present. Includes a pull-up
current source.
VCC
17
Card power supply: logically controlled by the sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.
GND
14
Card ground.
1.2
Miscellaneous Inputs and Outputs
Name
Pin
(SO)
Description
XTALIN
24
Crystal oscillator input: can either be connected to crystal or driven as a source
for the card clock.
XTALOUT
25
Crystal oscillator output: connected to crystal. Left open if XTALIN is being
used as an external clock input.
VDDF_ADJ
18
V DD fault threshold adjustment input: this pin can be used to adjust the V DDF
value (that controls deactivation of the card). Must be left open if unused.
NC
7
Non-connected pin.
1.3
Power supply and ground
Name
Pin
(SO)
VDD
6, 21
GND
4
DC-DC converter ground.
GND
22
Digital ground.
LIN
5
External inductor. Connect external inductor from pin 5 to V DD . Keep the
inductor close to pin 5.
4
Description
System controller interface supply voltage, supply voltage for internal power
supply and DC-DC converter power supply source.
Rev. 1.3
DS_8024C_023
1.4
73S8024C Data Sheet
Microcontroller Interface
Name
Pin
(SO)
Description
CMDVCC
19
Command V CC (negative assertion): Logic low on this pin causes the DC-DC
converter to ramp the V CC supply to the card and initiates a card activation sequence.
5V/#V
3
5 volt / 3 volt card selection: Logic one selects 5 volts for V CC and card interface, logic
low selects 3 volt operation. When the part is to be used with a single card voltage,
this pin should be tied to either GND or V DD . However, it includes a high impedance
pull-up resistor to default this pin high (selection of 5 V card) when unconnected.
PWRDN
8
Power Down control input (active high): When Power Down (PD) mode is
activated; all internal analog functions are disabled to place the 73S8024C in its
lowest power consumption mode. The PD mode is allowed only out of a card
session (= PWRDN high is not taken into account when CMDVCC = 0). Must be
tied to ground when the power down function is not used.
CLKDIV1
CLKDIV2
1
2
Sets the divide ratio from the XTALIN oscillator (or external clock input) to the card
clock. These pins include pull-down resistors.
CLKDIV1
CLKDIV2
Clock Rate
0
0
XTALIN/8
0
1
XTALIN/4
1
1
XTALIN/2
1
0
XTALIN
OFF
23
Interrupt signal to the processor (active low): Multi-function indicating fault
conditions and card presence. Open drain output configuration; it includes an
internal 20 kΩ pull-up to V DD.
RSTIN
20
Reset Input: This signal is the reset command to the card.
I/OUC
26
System controller data I/O to/from the card. Includes internal pull-up resistor to V DD.
AUX1UC
27
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to V DD.
AUX2UC
28
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to V DD.
Rev. 1.3
5
73S8024C Data Sheet
DS_8024C_023
2 System Controller Interface
•
2 digital inputs allow direct control of the card interface from the host as follows:
Pin CMDVCC: When low, starts an activation sequence if a card is present.
Pin 5V/#V: Defines the card voltage.
•
The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to
the host:
Pin RSTIN: controls the card reset signal (when enabled by the sequencer).
Pin I/OUC: data transfer to card I/O contact.
Pins AUX1UC and AUX2UC (auxiliary I/O lines associated to the auxiliary I/O lines to be
connected to the C4 and C8 card connector contacts).
•
2 digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the card
clock frequency, from the input clock frequency (crystal or external clock). The division rate is defined
as follows:
CLKDIV2
0
CLKDIV1
0
CLK
⅛ XTAL
0
1
1
1
0
1
XTAL
¼ XTAL
½ XTAL
When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the
card clock depends on the duty-cycle and waveform of the signal applied on the pin XTALIN.
When other division rates are used, the 73S8024C circuitry guarantees a duty-cycle in the
range 45% to 55%, conforming to ISO-7816-3, EMV 4.0 and NDS specifications.
•
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about
the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation
sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card
removed during a card session, or voltage fault, or thermal / over-current fault) that automatically
initiates a deactivation sequence.
•
Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8024C in
its Power Down state. This pin can only be activated out of a card session.
3 Oscillator
The 73S8024C device has an on-chip oscillator that can generate the smart card clock using an external
crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the
card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin
XTALOUT should be left unconnected.
6
Rev. 1.3
DS_8024C_023
73S8024C Data Sheet
4 DC-DC Converter – Card Power Supply
An internal DC-DC converter provides the card power supply. This converter is able to provide either 3 V
or 5 V card voltage from the power supply applied on the V DD pin. The digital ISO-7816-3 sequencer
controls the converter. Card voltage selection is carried out by the digital input 5V/#V.
The circuit is an inductive step-up converter/regulator. The external components required are 2 filter
capacitors on the power-supply input V DD (next to the LIN pin, 100 nF + 10 µF), an inductor, and an
output filter capacitor on the card power supply V CC . The circuit performs regulation by activating the
step-up operation when V CC is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage
and the input supply V DD is less than the set point for V CC . When V DD is greater than the set point for V CC
(V DD = 3.6 V, V CC =3 V) the circuit operates as a linear regulator.
Depending on the inductor values, the voltage converter can provide current on V CC as high as 100 mA.
The circuit provides over-current protection and limits I CC to 150 mA. When an over-current condition is
sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host
controller a fault on the interrupt output OFF.
Choice of the inductor
The nominal inductor value is 10 µH, rated for 400 mA. The inductor is connected between LIN (pin 5 in
the SO package, pin 2 in the QFN package) and the V DD voltage. The inductor value can be optimized to
meet a particular configuration (I CC_MAX ). The inductor should be located on the PCB as close as possible
to the LIN pin of the IC.
Choice of the V CC capacitor
Depending on the applications, the requirements in terms of both the V CC minimum voltage and the
transient currents that the interface must provide to the card are different. Table 1 shows the
recommended capacitors for each V CC power supply configuration and applicable specification.
Table 1: Choice of VCC Pin Capacitor
Specification Requirement
Application
Min V CC Voltage
Allowed During
Transient Current
Max Transient
Current Charge
Capacitor
Type
Capacitor
Value
EMV 4.0
4.6 V
30 nAs
3.3 µF
ISO-7816-3
4.5 V
20 nAs
X5R/X7R w/
ESR < 100 mΩ
Specification
1 µF
Table 1: Choice of VCC Pin Capacitor
5 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card
deactivation sequence is initiated, and an error or fault condition is reported to the system controller.
Rev. 1.3
7
73S8024C Data Sheet
DS_8024C_023
6 Voltage Supervision
Two voltage supervisors constantly check the level of the voltages V DD and V CC . A card deactivation
sequence is triggered upon a fault of any of these voltage supervisors.
The digital circuitry is powered by the power supply applied on the VDD pin. V DD also defines the voltage
range for the interface with the system controller. The V DD Voltage supervisor is also used to initialize the
ISO-7816-3 sequencer at power-on, and also to deactivate the card at power-off or upon a fault. The
voltage threshold of the V DD voltage supervisor is internally set by default to 2.3 V nominal. However, it
may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the
SO package, pin 17 in the QFN package) is used to connect an external resistor R EXT to ground to raise
the V DD fault voltage to another value, V DDF . The resistor value is defined as follows:
R EXT = 180 kΩ / (V DDF - 2.33)
An alternative (more accurate) method of adjusting the V DD fault voltage is to use a resistive network of
R3 from the pin to supply and R1 from the pin to ground (see Figure 9). In order to set the new threshold
voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx
is defined as R1/(R1+R3) and is calculated as:
Kx = (2.649 / V TH ) - 0.6042 where V TH is the desired new threshold voltage.
To determine the values of R1 and R3, use the following formulas:
R3 = 72000 / Kx
R1 = R3*(Kx / (1 – Kx))
Taking the example above, where a V DD fault threshold voltage of 2.7 V is desired, solving for Kx gives:
Kx = (2.649 / 2.7) - 0.6042 = 0.377.
Solving for R3 gives:
Solving for R1 gives:
R3 = 72000 / 0.377 = 191 kΩ.
R1 = 191000 *(0.377 / (1 – 0.377)) = 115.6 kΩ.
Using standard 1% resistor values gives R3 = 191 kΩ and R1 = 115 kΩ. These values give an equivalent
resistance of Kx = 0.376, a 0.3% error.
If the 2.3 V default threshold is used, this pin must be left unconnected.
7 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8024C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from
the host controller).
The host controller invokes the power down state when it is desirable to save power. The signals PRES
and PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller
must then set PWRDN low and wait for the internal stabilization time prior to starting any card session
(prior to turning CMDVCC low).
Resumption of the normal mode occurs at approximately 10 ms (stabilization of the internal oscillators
and reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, OFF can be used as an indication that the circuit has completed its
recovery from the power down state. OFF will go high at the end of the stabilization period. Should
CMDVCC go low during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be
taken into account and the card interface will remain inactive. Since CMDVCC is taken into account on
its edges, it should be toggled high and low again after the 10 ms to activate a card.
Figure 2 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
the power down function is not used.
8
Rev. 1.3
DS_8024C_023
73S8024C Data Sheet
PRES
OFF
OFF follows PRES regardless of PWRDN
PWRDN during a card
session has no effect
PWRDN
PWRDN has effect when
the cardi s deactivated
Internal RC OSC
~10ms
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
CMDVCC=0
CMDVCC
EMV / ISO deactivation
time ~= 100 uS
Figure 2: Power Down Mode Operation
8 Activation Sequence
The 73S8024C smart card interface IC has an internal 10 ms delay at power-on reset or upon application
of V DD > V DDF or upon exit of Power-Down mode. The card interface may only be activated when OFF is
high which indicates a card is present. No activation is allowed at this time. CMDVCC (edge triggered)
must then be set low to activate the card.
The following steps and Figure 3 show the activation sequence and the timing of the card control signals
when the system controller sets CMDVCC low while the RSTIN is low:
1. CMDVCC is set low.
2. Next, the internal V CC control circuit checks the presence of V CC at the end of t 1 . In normal operation,
the voltage V CC to the card becomes valid during t 1 . If V CC does not become valid, then OFF goes
low to report a fault to the system controller, and the power V CC to the card is shut down.
3. Turn I/O (AUX1, AUX2) to reception mode at the end of t 2 .
4. Due to the fall of RSTIN, CLK is applied to the card at the end of t 3 .
5. RST is a copy of RSTIN after t 4 . RSTIN may be set high before t 4 , however the sequencer won’t set
RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
IO
CLK
RSTIN
RST
t1
t2
t3
t4
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator)
t2 = 1.5 µs, I/O goes to reception state t3 = >0.5 µs, CLK starts
t4 ≥ 42000 card clock cycles (time for RST to become the copy of RSTIN)
Figure 3: Activation Sequence – RSTIN low when CMDVCC goes low
Rev. 1.3
9
73S8024C Data Sheet
DS_8024C_023
The following steps and Figure 4 show the activation sequence and the timing of the card control signals
when the system controller pulls CMDVCC low while RSTIN is high:
1. CMDVCC is set low.
2. Next, the internal V CC control circuit checks the presence of V CC at the end of t 1 . In normal operation,
the voltage V CC to the card becomes valid during this time. If not, OFF goes low to report a fault to
the system controller and the V CC power to the card is shut down.
3. After the fall of RSTIN at t 2 , turn I/O (AUX1, AUX2) to reception mode.
4. CLK is applied to the card at the end of t 3 after I/O is in reception mode.
5. RST is a copy of RSTIN after t 4 . RSTIN may be set high before t 4 , however the sequencer will not
set RST high until 42,000 clock cycles after the start of CLK.
CMDVCC
VCC
IO
CLK
RSTIN
RST
t1
t2
t3
t4
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5 µs, I/O goes to reception state t3 ≥ 0.5 µs, CLK active
t4 ≥ 42000 card clock cycles (time for RST to become the copy of RSTIN).
Figure 4: Activation Sequence – RSTIN high when CMDVCC goes low
9 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, V DD fault, V CC fault, and card
extraction during the session.
The following steps and Figure 5 show the deactivation sequence and the timing of the card control signals
when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
1.
2.
3.
4.
10
RST goes low at the end of time t 1 .
CLK is set low at the end of time t 2 .
I/O goes low at the end of time t 3 . Out of reception mode.
V CC is turned off at the end of time t 4 . After a delay t 5 (discharge of the V CC capacitor), V CC is low.
Rev. 1.3
DS_8024C_023
73S8024C Data Sheet
CMDVCC
-- OR -OFF
RST
CLK
I/O
VCC
t2
t1
t3
t5
t4
t1≥ 0.5 µs, timing by 1.5 MHz internal Oscillator
t2 ≥ 7.5 µs t3 ≥ 0.5 µs t4 ≥ 0.5 µs
t5 = depends on VCC filter capacitor
For NDS application, CF = 1 µF making t1 + t2 + t3 + t4 + t5 < 100 µs
Figure 5: Deactivation Sequence
10 OFF and Fault Detection
There are two cases for which the system controller can monitor the OFF signal: to query regarding the
card presence outside card sessions, or for fault detection during card sessions.
Monitoring Outside a Card Session
In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is
present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No
deactivation is required during this time.
Monitoring During a Card Session
CMDVCC is always low, and OFF falls low if the card is extracted or if any fault is detected. At the same
time that OFF is set low, the sequencer starts the deactivation process.
Figure 6 shows the timing diagram for the CMDVCC, PRES, and OFF signals during a card session and
outside the card session.
OFF is low by
card extracted
OFF is low by
any fault
PRES
OFF
CMDVCC
VCC
outside card session
within card session
within card
session
Figure 6: Timing Diagram – Management of the Interrupt Line OFF
Rev. 1.3
11
73S8024C Data Sheet
DS_8024C_023
11 I/O Circuitry and Timing
The I/O, AUX1, and AUX2 pins are in the low state after power on reset and they are in the high state
when the activation sequencer turns on the I/O reception state. See Section 8 Activation Sequence for
more details on when the I/O reception is on.
The state of the I/OUC, AUX1UC, and AUX2UC is high after power on reset. Within a card session and
when the I/O reception state is on, the first I/O line on which a falling edge is detected becomes the input
I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, both
I/O lines return to their neutral state.
Figure 7 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output.
The delay between the I/O signals is shown in Figure 8.
Neutral
State
No
I/O
reception
Yes
I/O
&
not I/OUC
No
Yes
I/OUC
&
not I/O
No
Yes
I/OUC
in
I/OICC
in
No
No
I/OUC
I/O
yes
yes
Figure 7: I/O and I/OUC State Diagram
IO
IOUC
tIO_HL
Delay from I/O to I/OUC:
Delay from I/OUC to I/O:
tIO_HL = 100 ns
tI/OUC_HL = 100 ns
tIO_LH
tIOUC_HL
tIOUC_LH
tIO_LH = 25 ns
tI/OUC_LH = 25 ns
Figure 8: I/O – I/OUC Delays: Timing Diagram
12
Rev. 1.3
DS_8024C_023
73S8024C Data Sheet
12 Typical Application Schematic
See NOTE 2
AUX2UC_to/f rom_uC
AUX1UC_to.f rom_uC
IOUC_to/f rom_uC
VDD
See NOTE 6
CLKDIV1_f rom_uC
VDD
See
NOTE 1
CLKDIV2_f rom_uC
5V/3V_select_f rom_uC
See NOTE 3
External_clock_f rom uC
U5
R3
Rext2
C4
C5
VDD
100nF
10uF
L1
See note 8
See NOTE 1
PWRDN_f rom_uC
10uH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
See NOTE 5
CLKDIV1
CLKDIV2
5V3V_
GND
LIN
VDD
NC
PWRDN
PRESB
PRES
I/O
AUX2
AUX1
GND
AUX2UC
AUX1UC
I/OUC
XTALOUT
XTALIN
OFF_
GND
VDD
RSTIN
CMDVCC_
VDD_ADJ
VCC
RST
CLK
73S8024C
SO28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
- OR -
C2
22pF
Y1
C3
C6
22pF
100nF
R1
Rext1
See
note 7
See NOTE 4
OFF_interrupt_to_uC
RSTIN_f rom_uC
CMDVCC_f rom_uC
Card detection
switch is
normally
closed.
8
7
6
5
4
3
2
1
C8
I/O
VPP
GND
C4
CLK
RST
VCC
NOTES:
20K
1) VDD supply must be =2.7V to 3.6V DC.
2) Optional, can be left open
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Pin can not float. Must be driven or connected to GND
if power down function is not used.
6)Internal pull-up allows it to be left open if unused.
7) Rext1 and Rext2 are external resistors to ground and
Vdd to modify the VDDfault voltage. Can be left open
8) Keep L1 close to pin 5
10
9
R2
SW-2
SW-1
VDD
CRY STAL
NDS & ISO7816=1uF, EMV=3.3uF
Low ESR ( 4.6 or 2.7 volts as
selected, L=10 µH
100
I CCmax
Maximum supply current to
the card
I CCF
I CC fault current
V SR
V CC slew rate – Rise rate on
activate
V SF
V CC slew rate – Fall rate on
deactivate
CF
External filter capacitor
(V CC to GND)
L
Inductor (LIN to V DD )
Limax
Imax in inductor
V CC = 5 V, I CC = 65 mA,
V DD = 2.7 V
η
Efficiency
V CC = 5 V, I CC = 65 mA,
V DD = 3.3 V
Rev. 1.3
mA
100
125
180
mA
C F on V CC = 1 µF
0.05
0.15
0.25
V/µs
C F on V CC = 1 µF
0.1
0.3
0.5
V/µs
0.47
1
3.3
µF
µH
10
400
80
mA
%
15
73S8024C Data Sheet
DS_8024C_023
1011B01 Converter efficiency (VCC 5V)
Converter Efficiency (VCC 5 V)
100
95
90
Efficiency [%]
85
80
75
70
2.7V
3.0V
65
3.3V
60
3.6V
55
50
0
20
40
60
80
100
Icc [mA]
Figure 10: DC – DC Converter efficiency (V CC = 5 V)
Output current on V CC at 5 V. Input voltage on V DD at 2.7, 3.0, 3.3 and 3.6 volts.
1011B01
Converter
efficiency
Converter
Efficiency
(V (VCC
3 V)3V)
CC
100
95
90
Efficiency [%]
85
80
75
2.7V
70
3.0V
3.3V (Linear)
65
3.6V (Linear)
60
55
50
0
20
40
60
80
100
Icc [mA]
Figure 11: DC – DC Converter Efficiency (V CC = 3 V)
Output current on V CC at 3 V. Input voltage on V DD at 2.7, 3.0, 3.3 and 3.6 volts.
16
Rev. 1.3
DS_8024C_023
Symbol
Parameter
73S8024C Data Sheet
Condition
Min.
Typ.
Max.
Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC. I SHORTL , I SHORTH , and V INACT requirements do not pertain to I//OUC, AUX1UC, and AUX2UC.
I IL requirements only pertain to I//OUC, AUX1UC, and AUX2UC.
I OH = 0
0.9 V CC
V CC + 0.1
V
Output level, high (I/O, AUX1,
V OH
AUX2)
0.75 V CC
V CC + 0.1
V
I OH = -40 µA
I
=
0
0.9
V
V
+
0.1
V
OH
DD
DD
Output level, high (I/OUC,
V OH
AUX1UC, AUX2UC)
0.75 V DD
V DD + 0.1
V
I OH = -40 µA
V OL
Output level, low
I OL = 1 mA
0.3
V
Input level, high (I/O, AUX1,
V IH
1.8
V CC + 0.30 V
AUX2)
Input level, high (I/OUC,
V IH
1.8
V DD + 0.30 V
AUX1UC, AUX2UC)
V IL
Input level, low
-0.3
0.8
V
I OL = 0
0.1
V
Output voltage when outside
V INACT
of session
I OL = 1 mA
0.3
V
I LEAK
Input leakage
V IH = V CC
10
µA
V IL = 0, CS = 1
0.65
mA
I IL
Input current, low
V IL = 0, CS = 0
5
μA
For output low,
shorted to V CC
I SHORTL
Short circuit output current
15
mA
through 33 Ω
For output high,
shorted to ground
I SHORTH
Short circuit output current
15
mA
through 33 Ω
C L = 80 pF, 10% to
90%. For I/OUC,
tR, tF
Output rise time, fall times
100
ns
AUX1UC, AUX2UC,
CL = 50 pF
t IR , t IF
Input rise, fall times
1
µs
Output stable for
R PU
Internal pull-up resistor
8
11
14
kΩ
> 200ns
MHz
FD MAX
Maximum data rate
1
Delay, I/O to I/OUC,
T FDIO
100
ns
I/OUC to I/O
(falling edge to falling edge)
C IN
Input capacitance
10
pF
Reset and Clock for card interface, RST, CLK
V OH
V OL
Output level, high
Output level, low
V INACT
Output voltage when outside
of a session
I RST_LIM
I CLK_LIM
Output current limit, RST
Output current limit, CLK
tR, tF
δ
Rev. 1.3
I OH = -200 µA
I OL = 200 µA
I OL = 0
I OL = 1 mA
C L = 35 pF for CLK,
10% to 90%
Output rise time, fall time
C L = 200 pF for RST,
10% to 90%
C L =35 pF,
Duty cycle for CLK, except for f
= f XTAL
F CLK ≤ 20 MHz
0.9 V CC
0
45
V CC
0.3
0.1
0.3
30
70
V
V
V
V
mA
mA
8
ns
100
ns
55
%
17
73S8024C Data Sheet
DS_8024C_023
13.4 Digital Signals
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Digital I/O except for OSC I/O
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
1.8
VDD + 0.3
V
VOL
Output Low Voltage
IOL = 2 mA
0.45
V
VOH
Output High Voltage
IOH = -1 mA
ROUT
Pull-up resistor, OFF
|IIL1|
Input Leakage Current
VDD - 0.45
V
20
GND < VIN < VDD
kΩ
-5
5
μA
Oscillator (XTALIN) I/O Parameters
V ILXTAL
Input Low Voltage - XTALIN
-0.3
0.3 V DD
V
V IHXTAL
Input High Voltage - XTALIN
0.7 V DD
V DD + 0.3
V
I ILXTAL
Input Current - XTALIN
-30
30
μA
f MAX
Max freq. Osc or external clock
27
MHz
δin
External input duty cycle limit
52
%
Max.
Unit
GND < V IN < V DD
tR/F < 10% fIN,
45% < δ CLK < 55%
48
13.5 DC Characteristics
Symbol
I PC
I DD_PD
Parameter
Supply Current on V DD
Supply Current on V DD in
Power Down mode
Condition
Linear mode, ICC = 0
I/O, AUX1, AUX2 = high
Step up mode, ICC = 0
I/O, AUX1, AUX2 = high
PWRDN=1,
Start/stop bit = 0
All digital inputs driven
with a true logical 0 or 1
Min.
Typ.
4.9
mA
4.7
mA
0.11
2.5
µA
Typ.
Max.
Unit
13.6 Voltage / Temperature Fault Detection Circuits
Symbol
Parameter
Condition
Min.
V DDF
V DD fault (V DD Voltage
supervisor threshold)
No external resistor on
VDDF_ADJ
2.15
2.4
V
V CCF
V CC fault (V CC Voltage
supervisor threshold)
V CC = 5 V
4.20
4.6
V
V CC = 3 V
2.5
2.7
V
TF
Die over temperature fault
115
145
°C
I CCF
Card over current fault
90
150
mA
18
Rev. 1.3
DS_8024C_023
73S8024C Data Sheet
14 Mechanical Drawings (28-SO)
.050 TYP. (1.270)
.305 (7.747)
.285 (7.239)
PIN NO. 1
BEVEL
.715 (18.161)
.695 (17.653)
.0115 (0.29)
.003 (0.076)
.110 (2.790)
.092 (2.336)
.420 (10.668)
.390 (9.906)
.016 nom (0.40)
.335 (8.509)
.320 (8.128)
Figure 12: 28 Lead SO
Rev. 1.3
19
73S8024C Data Sheet
DS_8024C_023
15 Package Pin Designation (28-SO)
Use handling procedures necessary for a static sensitive component.
CLKDIV1
1
28
AUX2UC
CLKDIV2
2
27
AUX1UC
5V/#V
3
26
I/OUC
GND
4
25
XTALOUT
LIN
5
24
XTALIN
VDD
6
23
OFF
NC
7
22
GND
PWRDN
8
21
VDD
PRES
9
20
RSTIN
PRES
10
19
CMDVCC
I/O
11
18
VDDF_ADJ
AUX2
12
17
VCC
AUX1
13
16
RST
GND
14
15
CLK
73S8024C
(Top View)
Figure 11: 73S8024C 28-SO Pin Out
20
Rev. 1.3
DS_8024C_023
73S8024C Data Sheet
16 Ordering Information
Part Description
Order Number
Packaging Mark
73S8024C-SO 28-pin Lead-Free SO
73S8024C-IL/F
73S8024C-IL
73S8024C-SO 28-pin Lead-Free SO Tape / Reel
73S8024C-ILR/F
73S8024C-IL
17 Related Documentation
The following 73S8024C documents are available from Teridian Semiconductor Corporation:
73S8024C Data Sheet (this document)
73S8024C Demo Board User’s Guide
18 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the
73S8024C, contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: scr.support@teridian.com
For a complete list of worldwide sales offices, go to http://www.teridian.com.
Rev. 1.3
21
73S8024C Data Sheet
DS_8024C_023
Revision History
Revision
Date
Description
1.0
6/21/2005
First publication.
1.1
7/15/2005
Removed QFN package information.
1.2
12/5/2007
Add ISO and EMV logos, remove leaded package option, update 28SO
package dimension.
1.3
4/3/2009
Remove all references to VPC as VPC must be tied to VDD.
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com
22
Rev. 1.3
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