DS1220AD-120

19-5580; Rev 10/10 DS1220AB/AD 16k Nonvolatile SRAM www.maxim-ic.com FEATURES            PIN ASSIGNMENT 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Directly replaces 2k x 8 volatile static RAM or EEPROM Unlimited write cycles Low-power CMOS JEDEC standard 24-pin DIP package Read and write access times of 100 ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full ±10% VCC operating range (DS1220AD) Optional ±5% VCC operating range (DS1220AB) Optional industrial temperature range of -40°C to +85°C, designated IND A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 16 15 14 13 VCC A8 A9 WE OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED PIN DESCRIPTION A0-A10 DQ0-DQ7 CE WE OE VCC GND - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+5V) - Ground DESCRIPTION The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 DS1220AB/AD READ MODE The DS1220AB and DS1220AD execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11 address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing that the CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1220AB and DS1220AD execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1220AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5V. The DS1220AD provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1220AB and 4.5 volts for the DS1220AD. FRESHNESS SEAL Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP, the lithium energy source is enabled for battery backup operation. 2 of 8 DS1220AB/AD ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Operating Temperature Range Commercial: Industrial: Storage Temperature Lead Temperature (soldering, 10s) Note: EDIP is wave or hand soldered only. -0.3V to +6.0V 0°C to +70°C -40°C to +85°C -40°C to +85°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER DS1220AB Power Supply Voltage DS1220AD Power Supply Voltage Logic 1 Logic 0 SYMBOL MIN TYP VCC 4.75 5.0 VCC 4.50 5.0 VIH 2.2 VIL 0.0 DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current CE ≥ VIH ≤ VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE = 2.2V Standby Current CE = VCC-0.5V Operating Current (Commercial) Operating Current (Industrial) Write Protection Voltage (DS1220AB) Write Protection Voltage (DS1220AD) (TA: See Note 10) NOTES (TA: See Note 10) (VCC = 5V ± 5% for DS1220AB) (VCC = 5V ± 10% for DS1220AD) SYMBOL MIN TYP -1.0 IIL -1.0 IIO MAX UNITS +1.0 µA +1.0 µA 10.0 5.0 mA mA mA mA ICC01 75 mA ICCO1 85 mA IOH IOL ICCS1 ICCS2 -1.0 2.0 5.0 3.0 VTP 4.5 4.62 4.75 V VTP 4.25 4.37 4.5 V CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance MAX UNITS 5.25 V 5.50 V VCC V +0.8 V NOTES (TA = +25°C) SYMBOL MIN TYP CIN 5 CI/O 5 3 of 8 MAX UNITS 10 pF 12 pF NOTES DS1220AB/AD AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High from WE Output Active from WE Data Setup Time Data Hold Time (TA: See Note 10) (VCC = 5.0V ± 5% for DS1220AB) (VCC = 5.0V ± 10% for DS1220AD) SYMBOL tRC tACC tOE tCO tCOE DS1220AB-100 DS1220AD-100 MIN MAX 100 100 50 100 5 tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 4 of 8 35 5 100 75 0 0 10 35 5 40 0 10 UNITS NOTES ns ns ns ns ns 5 ns 5 ns ns ns ns ns ns ns ns ns ns ns 3 12 13 5 4 4 12 13 DS1220AB/AD READ CYCLE SEE NOTE 1 WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8 AND 12 WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8 AND 13 5 of 8 DS1220AB/AD POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 POWER-DOWN/POWER-UP TIMING PARAMETER (TA: See Note 10) SYMBOL tPD MIN VCC slew from VTP to 0V tF 300 µs VCC slew from 0V to VTP tR 300 µs VCC Valid to CE and WE Inactive tPU 2 ms VCC Valid to End of Write Protection tREC 125 ms VCC Fail Detect to CE and WE Inactive TYP MAX 1.5 UNITS µs NOTES 11 (TA = +25°C) PARAMETER Expected Data Retention Time SYMBOL MIN TYP tDR 10 MAX UNITS years NOTES 9 WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the battery backup mode. NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or CE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. 6 of 8 DS1220AB/AD 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1220AB and each DS1220AD has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. This parameter is guaranteed by design and is not 100% tested. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to +85°C. 11. In a power down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 , tDH1 are measured from WE going high. 13. tWR2 , tDH2 are measured from CE going high. 14. DS1220 modules are recognized by Underwriters Laboratories (UL) under file E99151. DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open Cycle = 200ns for Operating Current All Voltages Are Referenced to Ground Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns ORDERING INFORMATION PART DS1220AB-100+ DS1220AB-100IND+ DS1220AD-100+ DS1220AD-100IND+ SUPPLY TOLERANCE 5V ± 5% 5V ± 5% 5V ± 10% 5V ± 10% TEMP RANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C PIN-PACKAGE 24 720 EDIP 24 720 EDIP 24 720 EDIP 24 720 EDIP +Denotes a lead(Pb)-free/RoHS-compliant package. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 EDIP MDT24+1 21-0245  7 of 8 DS1220AB/AD REVISION HISTORY REVISION DATE 121907 10/10 DESCRIPTION Added package information table; removed the DIP module package drawing and dimension table Updated the storage and soldering temperature information in the Absolute Maximum Ratings section, removed the unused AC timing specs in the AC Electrical Characteristics table, updated the Ordering Information table, updated the Package Information table 8 of 8 PAGES CHANGED 9 1, 3, 4, 7