DS33Z11
Ethernet Mapper
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS33Z11 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over a PDH/TDM data
stream. The serial link supports bidirectionalsynchronous interconnect up to 52Mbps over xDSL,
T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or
SONET/SDH Tributary.
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) controller
provides fractional bandwidth allocation up to the
line rate in increments of 512kbps. The DS33Z11
can operate with an inexpensive external processor,
EEPROM or in a stand-alone hardware mode.
Committed Information Rate Controller Provides
Fractional Allocations in 512kbps Increments
FUNCTIONAL DIAGRAM
Also Available in a 100-Ball, 10mm CSBGA—
the Hardware/SPI Mode-Only DS33ZH11
52Mbps Synchronous TDM Serial Port with
Independent Transmit and Receive Timing
HDLC/LAPS Encapsulation with Programmable
FCS and Interframe Fill
Programmable BERT for Serial (TDM) Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
SPI Interface and Hardware Mode for Operation
Without a Host Processor
DS33Z11
1.8V Operation with 3.3V Tolerant I/O
TRANSCEIVER/
SERIAL DRIVER
SERIAL
PORT
IEEE 1149.1 JTAG Support
Feature Highlights continued on page 8.
CONFIG
LOADER
BERT
PROM
OR µC
HDLC/X.86
MAPPER
SDRAM
10/100
MAC
MII/RMII
10/100
ETHERNET
PHY
APPLICATIONS
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3,
OC-1/EC-1, G.SHDSL, or HDSL2/4
ORDERING INFORMATION
PART
TEMP RANGE
PIN-PACKAGE
DS33Z11
-40°C to +85°C
169 CSBGA
DS33ZH11
-40°C to +85°C
100 CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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TABLE OF CONTENTS
1
2
DESCRIPTION..................................................................................................................................7
FEATURE HIGHLIGHTS ..................................................................................................................8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
GENERAL .......................................................................................................................................................8
SERIAL INTERFACE .........................................................................................................................................8
HDLC ...........................................................................................................................................................8
COMMITTED INFORMATION RATE (CIR) CONTROLLER ......................................................................................8
X.86 SUPPORT ..............................................................................................................................................8
SDRAM INTERFACE.......................................................................................................................................9
MAC INTERFACE ............................................................................................................................................9
MICROPROCESSOR INTERFACE .......................................................................................................................9
SERIAL SPI INTERFACE—MASTER MODE ONLY ...............................................................................................9
DEFAULT CONFIGURATIONS ............................................................................................................................9
TEST AND DIAGNOSTICS .................................................................................................................................9
SPECIFICATIONS COMPLIANCE ......................................................................................................................10
3
APPLICATIONS .............................................................................................................................11
4
ACRONYMS AND GLOSSARY .....................................................................................................14
5
MAJOR OPERATING MODES.......................................................................................................15
6
BLOCK DIAGRAMS.......................................................................................................................16
7
PIN DESCRIPTIONS ......................................................................................................................17
7.1
8
PIN FUNCTIONAL DESCRIPTION .....................................................................................................................17
FUNCTIONAL DESCRIPTION .......................................................................................................29
8.1 PROCESSOR INTERFACE ...............................................................................................................................29
8.1.1 Read-Write/Data Strobe Modes..........................................................................................................30
8.1.2 Clear on Read.....................................................................................................................................30
8.1.3 Interrupt and Pin Modes .....................................................................................................................30
8.2 SPI SERIAL EEPROM INTERFACE................................................................................................................30
8.3 CLOCK STRUCTURE ...............................................................................................................................31
8.3.1 Serial Interface Clock Modes..............................................................................................................33
8.3.2 Ethernet Interface Clock Modes .........................................................................................................33
8.4 RESETS AND LOW POWER MODES ................................................................................................................34
8.5 INITIALIZATION AND CONFIGURATION .............................................................................................................35
8.6 GLOBAL RESOURCES ...................................................................................................................................35
8.7 PER-PORT RESOURCES ...............................................................................................................................35
8.8 DEVICE INTERRUPTS ....................................................................................................................................36
8.9 SERIAL INTERFACE .......................................................................................................................................38
8.10 CONNECTIONS AND QUEUES .........................................................................................................................38
8.11 ARBITER ......................................................................................................................................................39
8.12 FLOW CONTROL ...........................................................................................................................................40
8.12.1 Full-Duplex Flow Control ....................................................................................................................41
8.12.2 Half Duplex Flow control.....................................................................................................................42
8.12.3 Host-Managed Flow control................................................................................................................42
8.13 ETHERNET INTERFACE PORT .....................................................................................................................43
8.13.1 DTE and DCE Mode ...........................................................................................................................45
8.14 ETHERNET MAC ..........................................................................................................................................46
8.14.1 MII Mode Options................................................................................................................................48
8.14.2 RMII Mode ..........................................................................................................................................48
8.14.3 PHY MII Management Block and MDIO Interface ..............................................................................49
8.15 BERT..........................................................................................................................................................50
8.15.1 Receive Data Interface .......................................................................................................................50
8.15.2 Repetitive Pattern Synchronization ....................................................................................................51
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8.15.3 Pattern Monitoring...............................................................................................................................52
8.15.4 Pattern Generation..............................................................................................................................52
8.16 TRANSMIT PACKET PROCESSOR ...................................................................................................................53
8.17 RECEIVE PACKET PROCESSOR .....................................................................................................................54
8.18 X.86 ENCODING AND DECODING ...................................................................................................................57
8.19 COMMITTED INFORMATION RATE CONTROLLER ..............................................................................................60
8.20 HARDWARE MODE ........................................................................................................................................62
9
DEVICE REGISTERS .....................................................................................................................66
9.1 REGISTER BIT MAPS.....................................................................................................................................67
9.1.1 Global Register Bit Map ......................................................................................................................67
9.1.2 Arbiter Register Bit Map......................................................................................................................68
9.1.3 BERT Register Bit Map.......................................................................................................................68
9.1.4 Serial Interface Register Bit Map ........................................................................................................69
9.1.5 Ethernet Interface Register Bit Map....................................................................................................71
9.1.6 MAC Register Bit Map ........................................................................................................................72
9.2 GLOBAL REGISTER DEFINITIONS ...................................................................................................................74
9.3 ARBITER REGISTERS ....................................................................................................................................83
9.3.1 Arbiter Register Bit Descriptions.........................................................................................................83
9.4 BERT REGISTERS .......................................................................................................................................84
9.5 SERIAL INTERFACE REGISTERS .....................................................................................................................91
9.5.1 Serial Interface Transmit and Common Registers..............................................................................91
9.5.2 Serial Interface Transmit Register Bit Descriptions ............................................................................91
9.5.3 Transmit HDLC Processor Registers .................................................................................................92
9.5.4 X.86 Registers ....................................................................................................................................99
9.5.5 Receive Serial Interface....................................................................................................................101
9.6 ETHERNET INTERFACE REGISTERS ..............................................................................................................114
9.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................114
9.6.2 MAC Registers..................................................................................................................................126
10
FUNCTIONAL TIMING .................................................................................................................142
10.1 FUNCTIONAL SERIAL I/O TIMING..................................................................................................................142
10.2 MII AND RMII INTERFACES .........................................................................................................................143
10.3 SPI INTERFACE MODE AND EEPROM PROGRAM SEQUENCE ......................................................................145
11
OPERATING PARAMETERS.......................................................................................................147
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
12
THERMAL CHARACTERISTICS ......................................................................................................................148
THETA-JA VS. AIRFLOW .............................................................................................................................148
TRANSMIT MII INTERFACE ...........................................................................................................................149
RECEIVE MII INTERFACE.............................................................................................................................150
TRANSMIT RMII INTERFACE ........................................................................................................................151
RECEIVE RMII INTERFACE ..........................................................................................................................152
MDIO INTERFACE ......................................................................................................................................153
TRANSMIT WAN INTERFACE .......................................................................................................................154
RECEIVE WAN INTERFACE .........................................................................................................................155
SDRAM TIMING.........................................................................................................................................156
AC CHARACTERISTICS—MICROPROCESSOR BUS TIMING ............................................................................158
EEPROM INTERFACE TIMING.....................................................................................................................161
JTAG INTERFACE TIMING ...........................................................................................................................162
JTAG INFORMATION ..................................................................................................................163
12.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ............................................................................163
12.2 INSTRUCTION REGISTER .............................................................................................................................166
12.2.1 SAMPLE:PRELOAD .........................................................................................................................167
12.2.2 BYPASS............................................................................................................................................167
12.2.3 EXTEST ............................................................................................................................................167
12.2.4 CLAMP..............................................................................................................................................167
12.2.5 HIGHZ ...............................................................................................................................................167
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12.2.6 IDCODE ............................................................................................................................................167
12.3 JTAG ID CODES........................................................................................................................................168
12.4 TEST REGISTERS .......................................................................................................................................168
12.5 BOUNDARY SCAN REGISTER .......................................................................................................................168
12.6 BYPASS REGISTER .....................................................................................................................................168
12.7 IDENTIFICATION REGISTER ..........................................................................................................................168
12.8 JTAG FUNCTIONAL TIMING .........................................................................................................................168
13
PACKAGE INFORMATION..........................................................................................................170
13.1 169-BALL CSBGA, 14MM X 14MM (56-G6035-001) ...................................................................................170
13.2 100-BALL CSBGA, 10MM X 10MM (DS33ZH11 ONLY) (56-G6008-001) ....................................................171
14
REVISION HISTORY ....................................................................................................................172
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LIST OF FIGURES
Figure 3-1 Ethernet to WAN Extension (No Framing)............................................................................................. 11
Figure 3-2 Ethernet to WAN Extension (T1E1 Framing and LIU) ........................................................................... 12
Figure 3-3 Ethernet to WAN Extension with T3/E3 Framing................................................................................... 12
Figure 3-4 Ethernet over DSL.................................................................................................................................. 13
Figure 3-5 Copper to Fiber Connection................................................................................................................... 13
Figure 6-1 Detailed Block Diagram ......................................................................................................................... 16
Figure 7-1 DS33Z11 169-Ball CSBGA Pinout......................................................................................................... 27
Figure 7-2 DS33ZH11 100-Ball CSBGA Pinout (Hardware or SPI Mode Only) ..................................................... 28
Figure 8-1 Clocking for the DS33Z11...................................................................................................................... 32
Figure 8-2 Device Interrupt Information Flow Diagram ........................................................................................... 37
Figure 8-3 Flow Control Using Pause Control Frame ............................................................................................. 42
Figure 8-4 IEEE 802.3 Ethernet Frame................................................................................................................... 43
Figure 8-5 Configured as DTE Connected to an Ethernet PHY in MII Mode.......................................................... 45
Figure 8-6 DS33Z11 Configured as a DCE in MII Mode......................................................................................... 46
Figure 8-7 RMII Interface......................................................................................................................................... 48
Figure 8-8 MII Management Frame......................................................................................................................... 49
Figure 8-9 PRBS Synchronization State Diagram .................................................................................................. 51
Figure 8-10 Repetitive Pattern Synchronization State Diagram ............................................................................. 52
Figure 8-11 HDLC Encapsulation of MAC Frame ................................................................................................... 56
Figure 8-12 LAPS Encoding of MAC Frames Concept ........................................................................................... 57
Figure 8-13 X.86 Encapsulation of the MAC field ................................................................................................... 58
Figure 8-14 CIR in the WAN Transmit Path ............................................................................................................ 61
Figure 10-1 TX Serial Interface Functional Timing................................................................................................ 142
Figure 10-2 RX Serial Interface Functional Timing ............................................................................................... 142
Figure 10-3 Transmit Byte Sync Functional timing ............................................................................................... 143
Figure 10-4 Receive Byte Sync Functional Timing ............................................................................................... 143
Figure 10-5 MII Transmit Functional Timing.......................................................................................................... 144
Figure 10-6 MII Transmit Half Duplex with a Collision Functional Timing............................................................. 144
Figure 10-7 MII Receive Functional Timing........................................................................................................... 144
Figure 10-8 RMII Transmit Interface Functional Timing........................................................................................ 144
Figure 10-9 RMII Receive Interface Functional Timing......................................................................................... 145
Figure 10-10 SPI Master Functional Timing.......................................................................................................... 145
Figure 11-1 Transmit MII Interface ........................................................................................................................ 149
Figure 11-2 Receive MII Interface Timing ............................................................................................................. 150
Figure 11-3 Transmit RMII Interface ..................................................................................................................... 151
Figure 11-4 Receive RMII Interface Timing........................................................................................................... 152
Figure 11-5 MDIO Timing ...................................................................................................................................... 153
Figure 11-6 Transmit WAN Timing........................................................................................................................ 154
Figure 11-7 Receive WAN Timing......................................................................................................................... 155
Figure 11-8 SDRAM Interface Timing ................................................................................................................... 157
Figure 11-9 Intel Bus Read Timing (HWMODE = 0, MODEC = 00) ..................................................................... 159
Figure 11-10 Intel Bus Write Timing (HWMODE = 0, MODEC = 00).................................................................... 159
Figure 11-11 Motorola Bus Read Timing (HWMODE = 0, MODEC = 01) ............................................................ 160
Figure 11-12 Motorola Bus Write Timing (HWMODE = 0, MODEC = 01) ............................................................ 160
Figure 11-13 EEPROM Interface Timing............................................................................................................... 161
Figure 11-14 JTAG Interface Timing Diagram ...................................................................................................... 162
Figure 12-1 JTAG Functional Block Diagram........................................................................................................ 163
Figure 12-2 TAP Controller State Diagram ........................................................................................................... 166
Figure 12-3 JTAG Functional Timing .................................................................................................................... 169
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LIST OF TABLES
Table 2-1 T1-Related Telecommunications Specifications ..................................................................................... 10
Table 7-1 Detailed Pin Descriptions ........................................................................................................................ 17
Table 8-1 Clocking Options for the Ethernet Interface ............................................................................................ 31
Table 8-2 Reset Functions ...................................................................................................................................... 34
Table 8-3 Registers Related to Connections and Queues...................................................................................... 39
Table 8-4 Options for Flow Control ......................................................................................................................... 40
Table 8-5 Registers Related to Setting the Ethernet Port ....................................................................................... 44
Table 8-6 MAC Control Registers ........................................................................................................................... 47
Table 8-7 MAC Status Registers ............................................................................................................................. 47
Table 8-8 Hardware Mode and Typical Applications............................................................................................... 62
Table 8-9 Specific Functional Default Values for Hardware Mode ......................................................................... 63
Table 8-10 Hardware Mode Pins............................................................................................................................. 65
Table 9-1 Register Address Map............................................................................................................................. 66
Table 9-2 Global Register Bit Map .......................................................................................................................... 67
Table 9-3 Arbiter Register Bit Map .......................................................................................................................... 68
Table 9-4 BERT Register Bit Map ........................................................................................................................... 68
Table 9-5 Serial Interface Register Bit Map ............................................................................................................ 69
Table 9-6 Ethernet Interface Register Bit Map ........................................................................................................ 71
Table 9-7 MAC Indirect Register Bit Map................................................................................................................ 72
Table 10-1 EEPROM Program Memory Map........................................................................................................ 146
Table 10-2 EEPROM Program Sequence and Example for Indirect MAC Registers........................................... 146
Table 11-1 Recommended DC Operating Conditions........................................................................................... 147
Table 11-2 DC Electrical Characteristics............................................................................................................... 147
Table 11-3 SDRAM Interface Timing .................................................................................................................... 156
Table 12-1 Instruction Codes for IEEE 1149.1 Architecture ................................................................................. 167
Table 12-2 ID Code Structure................................................................................................................................ 168
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1
DESCRIPTION
The DS33Z11 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN
Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a
10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86 (LAPS) mapper,
SDRAM interface, control ports, and bit error-rate tester (BERT). The packet interface consists of an Ethernet
interface using several physical-layer protocols. The Ethernet interface can be configured for 10 Mbps or 100
Mbps service. The DS33Z11 encapsulates Ethernet traffic with HDLC or X.86 (LAPS) to be transmitted over the
WAN interface. The WAN interface also receives encapsulated Ethernet packets and transmits the extracted
packets over the Ethernet port. The WAN physical interface supports a serial data stream up to 52 Mbps. The
WAN interface can be connected to the Dallas Semiconductor/Maxim T1/E1/J1 framers, line interface units
(LIUs), and single-chip transceivers (SCTs). The WAN interface can also be connected to the Dallas
Semiconductor/Maxim T3/E3/STS-1 framers, LIUs, and SCTs to provide T3, E3, and STS1 connectivity. Refer to
Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of a complete
LAN to WAN solution.
The DS33Z11 is controlled through an 8-bit microcontroller port. A serial EEPROM (SPI) interface and hardware
mode are also included for applications without a host processor. The DS33Z11 has a 100MHz SDRAM controller
and interfaces to a 32-bit wide 128 Mbit SDRAM. The SDRAM is used to buffer the data from the Ethernet and
WAN ports for transport. The external SDRAM can accommodate up to 8192 frames with a maximum frame size
of 2016 bytes.
Operation without an external host simplifies and reduces the cost of typical applications such as connectivity to
T1/T3 and E1/E3 front ends. The DS33Z11 operates with a 1.8V core supply and 3.3V I/O supply.
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2
2.1
FEATURE HIGHLIGHTS
General
•
•
•
•
•
•
2.2
Serial Interface
•
•
•
2.3
One HDLC controller engine
Compatible with polled or interrupt driven environments
Programmable FCS insertion and extraction
Programmable FCS type
Supports FCS error insertion
Programmable packet size limits (minimum 64 bytes and maximum 2016 bytes)
Supports bit stuffing/destuffing
Selectable packet scrambling/descrambling (X43 + 1)
Separate FCS errored packet and aborted packet counts
Programmable inter-frame fill for transmit HDLC
Committed Information Rate (CIR) Controller
•
•
•
2.5
Supports line speeds up to 52 Mbps
Supports data enable and gapped clocking
Supports byte synchronization input and output for X.86 applications
HDLC
•
•
•
•
•
•
•
•
•
•
2.4
169-pin CSBGA package (DS33Z11)
100-pin CSBGA package for hardware/SPI modes only (DS33ZH11)
1.8V supply with 3.3V tolerant inputs and outputs
IEEE 1149.1 JTAG boundary scan
Software access to device ID and silicon revision
Development support includes evaluation kit, driver source code, and reference designs
CIR rate controller limits transmission of data from the Ethernet interface to the serial interface
CIR granularity at 512 kbps
CIR Averaging for smoothing traffic peaks
X.86 Support
•
•
•
•
•
•
•
•
•
•
•
Programmable X.86 address/control fields for transmit and receive
Programmable 2-byte protocol (SAPI) field for transmit and receive
32 bit FCS
Transmit Transparency processing—7E is replaced by 7D, 5E
Transmit Transparency processing—7D replaced by 7D, 5D
Receive rate adaptation (7D, DD) is deleted
Receive Transparency processing—7D, 5E is replaced by 7E
Receive Transparency processing—7D, 5D is replaced by 7D
Receive Abort Sequence the LAPS packet is dropped if 7D7E is detect
Self-synchronizing X43 + 1 payload scrambling.
Frame indication due to bad address/control/SAPI, FCS error, abort sequence, or frame size longer
than preset max
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2.6
SDRAM Interface
•
•
•
•
•
•
2.7
MAC Interface
•
•
•
•
•
•
•
•
•
•
•
•
2.8
MAC port with standard MII (less TX_ER) or RMII
10 Mbps and 100 Mbps Data rates
Configurable DTE or DCE modes
Facilitates auto-negotiation by host microprocessor
Programmable half and full-duplex modes
Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
Programmable Maximum MAC frame size up to 2016 bytes
Minimum MAC frame size: 64 bytes
Discards frames greater than Programmed Maximum MAC frame size and Runt, non-octet bounded,
or bad-FCS frames upon reception
Configurable for promiscuous broadcast-discard mode.
Programmable threshold for SDRAM queues to initiate flow control and status indication
MAC loopback support for transmit data looped to Receive Data at the MII/RMII interface
Microprocessor Interface
•
•
•
•
2.9
Interface for 128 Mb, 32-bit wide SDRAM
SDRAM Interface speed up to 100 MHz
Auto refresh timing
Automatic precharge
Master clock provided to the SDRAM
No external components required for SDRAM connectivity
8-bit data bus
Nonmultiplexed Intel and Motorola timing modes
Internal software reset and external hardware reset-input pin
Global interrupt output pin
Serial SPI Interface—Master Mode Only
•
•
•
Provides chip select and clock for external EEPROM
Operation up to 8.33 MHz
4-signal interface
2.10 Default Configurations
•
•
•
Default Hardware Configuration for operation without an external microprocessor
Hardware modes set for easy connection to T1/T3 E1/E3 WAN systems
Hardware pins provide some flexibility for configuration
2.11 Test and Diagnostics
•
•
•
•
IEEE 1149.1 support
Programmable on-chip BERT
Patterns include pseudorandom QRSS, Daly, and user-defined repetitive patterns
Loopbacks (remote, local, analog, and per-channel loopback)
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2.12 Specifications Compliance
The DS33Z11 meets relevant telecommunications specifications. The following table provides the specifications
and relevant sections that are applicable to the DS33Z11.
Table 2-1 T1-Related Telecommunications Specifications
IEEE 802.3-2002—CSMA/CD access method and physical layer specifications
RFC1662—PPP in HDLC-like framing
RFC2615—PPP over SONET/SDH
X.86—Ethernet over LAPS
RMII—Industry Implementation Agreement for “Reduced MII Interface,” Sept 1997
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3
APPLICATIONS
The DS33Z11 is designed for use in the following applications:
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4
Refer also to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for an example of
a complete LAN to WAN design.
Figure 3-1 Ethernet to WAN Extension (No Framing)
HDLC
Serial
Stream
T1/T3 LIU
DS21Q48
DS3154
Port
RMII, MII
10 Base T
100 Base T
DS33Z11
Ethernet
Clock
Sources
SDRAM
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Figure 3-2 Ethernet to WAN Extension (T1E1 Framing and LIU)
T1
Framer/LIU
DS21Q55
DS26528
Port
HDLC
Serial
Stream
RMII, MII
10 Base T
100 Base T
DS33Z11
Ethernet
Clock
Sources
SDRAM
Figure 3-3 Ethernet to WAN Extension with T3/E3 Framing
T3
Framer/LIU
DS3154
DS3144
Port
HDLC
Serial
Streams
RMII, MII
10 Base T
100 Base T
DS33Z11
Ethernet
Clock
Sources
SDRAM
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Figure 3-4 Ethernet over DSL
HDLC
Serial
Streams
RMII, MII
10 Base T
100 Base T
DSL
DS33Z11
Ethernet
Clock
Sources
SDRAM
Figure 3-5 Copper to Fiber Connection
HDLC
Serial
Streams
Optical
I/F
&
connector
Fiber
Phy
RMII
MII
DS33Z11
Ethernet
Clock
Sources
SDRAM
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4
ACRONYMS AND GLOSSARY
•
•
•
•
•
•
•
•
•
BERT: Bit Error-Rate Tester
DCE: Data Communication Interface
DTE: Data Terminating Interface
FCS: Frame Check Sequence
HDLC: High-Level Data Link Control
MAC: Media Access Control
MII: Media Independent Interface
RMII: Reduced Media Independent Interface
WAN: Wide Area Network
Note 1: Previous versions of this document used the term “Subscriber” to refer to the Ethernet Interface function.
The register names have been allowed to remain with a “SU.” prefix to avoid register renaming.
Note 2: Previous versions of this document used the term “Line” to refer to the Serial Interface. The register
names have been allowed to remain with a “LI.” prefix to avoid register renaming.
Note 3: The terms “Transmit Queue” and “Receive Queue” are with respect to the Ethernet Interface. The
Receive Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and
stored in the SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and
stored in the SDRAM to be sent to the MAC transmitter.
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5
MAJOR OPERATING MODES
The DS33Z11 has three major modes of operation: microprocessor controlled, EEPROM initialized, and
Hardware mode.
Microprocessor control is possible through the 8-bit parallel control port. More information on microprocessor
control is available in Section 8.1.
EEPROM initialization is enabled by the built-in SPI master that reads a serial EEPROM connected to the SPI
port after device reset and initializes the device. More information on EEPROM operation is available in Section
8.2.
Hardware mode allows configuration of the device without a host microprocessor or EEPROM. More information
on Hardware mode is available in Section 8.20.
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6
BLOCK DIAGRAMS
Figure 6-1 Detailed Block Diagram
Eprom
SPI_SCLK (max 8.33Mhz)
50 or 25 Mhz Oscillator
Buffer
Dev
Div by 1,2,4,10
Output clocks:
50,25 Mhz,2.5 Mhz
Microport
REF_CLK
TSER
TCLKI1
Line 1
RCLKI1
RSER
HDLC
+
Serial
Interface
TX_CLK1
CIR
MAC
RMII
MII
Arbiter
RXD
RX_CLK1
TXD
X.86
MDC
100 Mhz Oscillator
JTAG
Buffer Dev
Div by 2,4,12
Output Clocks
25,50
Mhz
SDRAM
Interface
SDCLKO
REF_CLKO
50 or 25 Mhz
SDRAM
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7
PIN DESCRIPTIONS
7.1
Pin Functional Description
Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG
patterns. JTAG pins are not available on the Hardware mode/SPI-only DS33ZH11 (10mm CSBGA)
Note: I = Input; O = Output; Ipu = Input, with pullup; Oz = Output, with tri-state; IO = Bidirectional pin; IOz = Bidirectional pin, with tri-state
Table 7-1 Detailed Pin Descriptions
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
TCLKI
F1
B1
TSER
F2
A2
TDEN/
TBSYNC
F5
—
SERIAL INTERFACE IO PINS
Serial Interface Transmit Clock Input: The clock
reference for TSER, which is output on the rising edge of
I
the clock. TCLKI supports gapped clocking, up to a
maximum frequency of 52 MHz.
Transmit Serial Data Output: Output on the rising edge
of TCLKI. Selective clock periods can be skipped for
O
output of TSER dependent on the TDEN settings or
gapped clock input (TCLKI). The maximum data rate is 52
Mbps.
Transmit Data Enable (Input): The transmit data enable
is programmable to selectively block/enable the transmit
data. The TDEN signal must occur one clock edge prior to
the affected data bit. The active polarity of TDEN is
programmable in register LI.TSLCR. It is recommended
for both T1/E1 and T3/E3 applications that use gapped
clocks. The TDEN signal is provided for interfacing to
framers that do not have a gapped clock facility.
IO
Transmit Byte Sync (Output): This output can be used
by an external Serial to Parallel to convert TSER stream to
byte wide data. This output indicates the last bit of the
byte data sent serially on TSER. This signal is only active
in the X.86 Mode.
RCLKI
G2
B2
I
RSER
H1
B3
I
Note that while in Hardware mode with HDLC (non X.86)
operation, this pin must be tied high.
Serial Interface Receive Clock Input: Reference clock
for receive serial data on RSER. Gapped clocking is
supported, up to the maximum RCLKI frequency of 52
MHz.
Receive Serial Data Input: Receive Serial data arrives on
the rising edge of the clock.
17 of 172
DS33Z11 Ethernet Mapper
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
Receive Data Enable: The receive data enable is
programmable to block the receive data. The RDEN must
be coincident with the RSER data bit to be blocked or
enabled. The active polarity of RDEN is programmable in
register LI.RSLCR. It is recommended for both T1/E1 and
T3/E3 applications that use gapped clocks. The RDEN
signal is provided for interfacing to framers that do not
have a gapped clock facility.
RDEN/
RBSYNC
H2
—
Receive Byte Synchronization Input: Provides byte
synchronization input to X.86 decoder. This signal will go
high at the first bit of the byte as it arrives. This signal can
occur at maximum rate every 8 bits. Note that a long as
the Z11 receives one RBSYNC indicator. The X.86
receiver will determine the byte boundary. Hence the Z11
does not require a continuous 8-bit sync indicator. A new
sync pulse is required if the byte boundary changes.
I
Note that while in Hardware mode with HDLC (non X.86)
operation, this pin must be tied high.
MII/RMII PORT
Reference Clock (RMII and MII): When in RMII mode, all
signals from the PHY are synchronous to this clock input
for both transmit and receive. This required clock can be
up to 50 MHz and should have ±100 ppm accuracy.
REF_CLK
REF_CLKO
D13
E13
—
G10
I
O
When in MII mode in DCE operation, the DS33Z11 uses
this input to generate the RX_CLK and TX_CLK outputs
as required for the Ethernet PHY interface. When the MII
interface is used with DTE operation, this clock is not
required and should be tied low.
In DCE and RMII modes, this input must have a stable
clock input before setting the RST pin high for normal
operation.
Reference Clock Output (RMII and MII): A derived clock
output up to 50 MHz, generated by internal division of the
SYSCLKI signal. Frequency accuracy of the REF_CLKO
signal will be proportional to the accuracy of the usersupplied SYSCLKI signal. See Section 8.3.2 for more
information.
Transmit Clock (MII): Timing reference for TX_EN and
TXD[3:0]. The TX_CLK frequency is 25 MHz for 100 Mbps
operation and 2.5 MHz for 10 Mbps operation.
TX_CLK
A8
A6
IO
In DTE mode, this is a clock input provided by the PHY. In
DCE mode, this is an output derived from REF_CLK
providing 2.5 MHz (10 Mbps operation) or 25 MHz (100
Mbps operation).
18 of 172
DS33Z11 Ethernet Mapper
NAME
TX_EN
PIN #
DS33Z11
CSBGA
(169)
E10
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
B6
O
Transmit Enable (MII): This pin is asserted high when
data TXD [3:0] is being provided by the DS33Z11. The
signal is deasserted prior to the first nibble of the next
frame. This signal is synchronous with the rising edge
TX_CLK. It is asserted with the first bit of the preamble.
Transmit Enable (RMII): When this signal is asserted, the
data on TXD [1:0] is valid. This signal is synchronous to
the REF_CLK.
TXD[0]
B9
A8
TXD[1]
C9
B7
TXD[2]
D9
B8
TXD[3]
E9
A9
O
RX_CLK
A10
B10
RXD[0]
B11
D9
RXD[1]
C11
D10
Transmit Data 0 through 3(MII): TXD [3:0] is presented
synchronously with the rising edge of TX_CLK. TXD [0] is
the least significant bit of the data. When TX_EN is low
the data on TXD should be ignored.
Transmit Data 0 through 1(RMII): Two bits of data TXD
[1:0] presented synchronously with the rising edge of
REF_CLK.
IO
Receive Clock (MII): Timing reference for RX_DV,
RX_ERR and RXD[3:0], which are clocked on the rising
edge. RX_CLK frequency is 25 MHz for 100 Mbps
operation and 2.5 MHz for 10 Mbps operation. In DTE
mode, this is a clock input provided by the PHY. In DCE
mode, this is an output derived from REF_CLK providing
2.5 MHz (10 Mbps operation) or 25 MHz (100 Mbps
operation).
Receive Data 0 through 3(MII): Four bits of received
data, sampled synchronously with the rising edge of
RX_CLK. For every clock cycle, the PHY transfers 4 bits
to the DS33Z11. RXD[0] is the least significant bit of the
data. Data is not considered valid when RX_DV is low.
I
RXD[2]
D11
C9
RXD[3]
A11
C10
RX_DV
RX_CRS/
CRS_DV
D10
A10
Receive Data 0 through 1(RMII): Two bits of received
data, sampled synchronously with REF_CLK with 100
Mbps Mode. Accepted when CRS_DV is asserted. When
configured for 10 Mbps Mode, the data is sampled once
every 10 clock periods.
I
Receive Data Valid (MII): This active high signal indicates
valid data from the PHY. The data RXD is ignored if
RX_DV is not asserted high.
Receive Carrier Sense (MII): Should be asserted (high)
when data from the PHY (RXD[3:0) is valid. For each
clock pulse 4 bits arrive from the PHY. Bit 0 is the least
significant bit. In DCE mode, connect to VDD.
C8
C8
I
Carrier Sense/Receive Data Valid (RMII): This signal is
asserted (high) when data is valid from the PHY. For each
clock pulse 2 bits arrive from the PHY. In DCE mode, this
signal must be grounded.
19 of 172
DS33Z11 Ethernet Mapper
NAME
RX_ERR
COL_DET
MDC
MDIO
PIN #
DS33Z11
CSBGA
(169)
B12
B13
C12
C13
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
B9
—
—
—
I
I
Receive Error (MII): Asserted by the MAC PHY for one or
more RX_CLK periods indicating that an error has
occurred. Active High indicates Receive code group is
invalid. If CRS_DV is low, RX_ERR has no effect. This is
synchronous with RX_CLK. In DCE mode, this signal must
be grounded.
Receive Error (RMII): Signal is synchronous to
REF_CLK.
Collision Detect (MII): Asserted by the MAC PHY to
indicate that a collision is occurring. In DCE Mode this
signal should be connected to ground. This signal is only
valid in half duplex mode, and is ignored in full duplex
mode
O
Management Data Clock (MII): Clocks management data
between the PHY and DS33Z11. The clock is derived from
SYSCLKI, with a maximum frequency is 1.67 MHz. The
user must leave this pin unconnected in the DCE Mode.
IO
MII Management Data IO (MII): Data path for control
information between the PHY and DS33Z11. When not
used, pull to logic high externally through a 10kΩ resistor.
The MDC and MDIO pins are used to write or read up to
32 Control and Status Registers in 32 PHY Controllers.
This port can also be used to initiate Auto-Negotiation for
the PHY. The user must leave this pin unconnected in the
DCE Mode.
MICRO PORT/SPI
Address Bit 0: Address bit 0 of the microprocessor
interface. Least Significant Bit
A0/BREO
A1
Potential
future
revision to
add on
ball A5
I
BREO (Hardware Mode): Used in Hardware Mode to
reverse the ordering of HDLC transmit and receive
functions. Active high input. When 0, the first bit received
is the MSB. When 1, bit the first bit received is the LSB.
The software registers used for control of this function are
LI.RPPCL and LI.TPPCL.
Address Bit 1: Address bit 1 of the microprocessor
interface.
A1/SCD
B1
Potential
future
revision to
add on
ball D8
—
SCD (Hardware Mode): Used in Hardware Mode to
disable X43+1 bit scrambling for both the transmit and
receive paths. Applies to HDLC and X.86 transport. When
1, X43+1 scrambling is disabled. When 0, X43+1
scrambling is enabled. The software registers used for
control of this function are LI.RPPCL and LI.TPPCL.
20 of 172
DS33Z11 Ethernet Mapper
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
Address Bit 2: Address bit 2 of the microprocessor
interface.
A2/X86ED
A2
Potential
future
revision to
add on
ball B4
A3
B2
—
—
A4
C2
—
—
A5
A3
—
—
A6
B3
—
—
A7
C3
—
—
A8
A4
—
—
A9
B4
—
—
D0/MOSI
A5
E8
IOZ
—
X86ED (Hardware Mode): When in Hardware Mode,
setting this pin high enables X.86 encapsulation for both
the transmit and receive data. When 0, HDLC
encapsulation is used. The register used to control this
function in Software Mode is LI.TX86EDE.
Address Bit 3: Address bit 3 of the microprocessor
interface.
Address Bit 4: Address bit 4 of the microprocessor
interface.
Address Bit 5: Address bit 5 of the microprocessor
interface.
Address Bit 6: Address bit 6 of the microprocessor
interface.
Address Bit 7: Address bit 7 of the microprocessor
interface.
Address Bit 8: Address bit 8 of the microprocessor
interface.
Address Bit 9: Address bit 9 of the microprocessor
interface. Most Significant Bit.
Data Bit 0: Bi-directional data bit 0 of the microprocessor
interface. Least Significant Bit. Not driven when CS = 1 or
RST = 0.
Master Out Slave In (SPI Mode): Data stream that
provides the instruction and address information to the
external EEPROM when in SPI Master Mode. MOSI is
updated on the rising edge when CKPHA is set high, and
on the falling edge when set low.
Data Bit 1: Bidirectional data bit 1 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
D1/MISO
D2/SPICK
A6
A7
E9
E10
IOZ
IOZ
Master In Slave Out (SPI Mode): Data path from the SPI
EEPROM to the DS33Z11. Must be synchronous with
SPICK. The Serial EEPROM SPI Interface will provide
data to the DS33Z11, MSB first. MISO is sampled on the
falling edge when CKPHA is set high, and on the rising
edge when set low.
Data Bit 2: Bidirectional data bit 2 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
SPICK: Provides clocking for SPI transactions.
D3
B5
—
IOZ
D4
B6
—
IOZ
D5
B7
—
IOZ
Data Bit 3: Bidirectional data bit 3 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
Data Bit 4: Bidirectional data bit 4 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
Data Bit 5: Bidirectional data bit 5 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
21 of 172
DS33Z11 Ethernet Mapper
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
D6
C5
—
IOZ
Data Bit 6: Bidirectional data bit 6 of the microprocessor
interface. Not driven when CS = 1 or RST = 0.
D7
C6
—
IOZ
Data Bit 7: Bidirectional data bit 7 of the microprocessor
interface. Most Significant Bit. CS = 1 or RST = 0.
SPI_CS
B8
B5
O
Active-Low SPI Chip Select: Provides the chip select to
the external EEPROM, when the SPI port is in master
mode.
CKPHA
F6
—
I
SPI Clock Phase: MISO is sampled on the falling edge
when CKPHA is set high, and on the rising edge when set
low.
MOSI is updated on the rising edge when CKPHA is set
high, and on the falling edge when set low.
CS
RD/DS
WR/RW
C1
—
I
Active-Low Chip Select: This pin must be taken low for
read/write operations. When CS is high, the RD/DS and
WR signals are ignored.
Active-Low Read-Data Strobe (Intel Mode): The
DS33Z11 drives the data bus (D0-D7) with the contents of
the addressed register while RD and CS are both low.
E1
E2
—
—
I
I
INT
F3
—
OZ
RST
D8
C1
I
Active-Low Data Strobe (Motorola Mode): Used to latch
data through the microprocessor interface. DS must be
low during read and write operations.
Active-Low Write (Intel Mode): The DS33Z11 captures
the contents of the data bus (D0-D7) on the rising edge of
WR and writes them to the addressed register location.
CS must be held low during write operations.
Read Write (Motorola Mode): Used to indicate read or
write operation. RW must be set high for a register read
cycle and low for a register write cycle.
Active-Low Interrupt Output: Outputs a logic zero when
an unmasked interrupt event is detected. INT is
deasserted when all interrupts have been acknowledged
and serviced. Inactive state is programmable in register
GL.CR1.
Active-Low Reset: An active low signal on this pin resets
the internal registers and logic. This pin should remain low
until power, SYSCLKI, RX_CLK, and TX_CLK are stable,
then set high for normal operation. In DCE and RMII
modes, the REF_CLK input must also have a stable clock
input before setting RST high for normal operation. This
input requires a clean edge with a rise time of 25ns or less
to properly reset the device.
22 of 172
DS33Z11 Ethernet Mapper
NAME
HWMODE
MODEC[0]
PIN #
DS33Z11
CSBGA
(169)
D5
D6
PIN #
DS33ZH1
1
TYPE
FUNCTION
I
Hardware Mode: Connect to VDD to place the device in
Hardware Mode. MODEC[1:0] determines the default
hardware setting to be used. This pin must be held low for
control by a microprocessor or an external EEPROM.
BGA(100)
A3
Mode Control:
Software Mode Options (HWMODE = 0)
00 = Read/Write Strobe Used (Intel Mode)
01 = Data Strobe Used (Motorola Mode)
10 –SPI Master Mode (External EEPROM)
11- Reserved. Do not use.
—
I
MODEC[1]
DCEDTES
RMIIMIIS
FULLDS
H10S
D7
A13
C4
A9
B10
A4
—
—
—
—
I
I
I
I
Hardware Mode Options (HWMODE = 1)
00 = Default Hardware Mode. See Table 8-8.
01 = Reserved. Do not use.
10 = Hardware Mode for T3/E3 rates. See Table 8-8.
11 = Reserved. Do not use.
Note that in the 100-pin CSBGA (DS33ZH11) package,
only MODEC[1] is available to the user. MODEC[0] is
internally connected to VSS.
DCE or DTE Selection: The user must set this pin high
for DCE Mode selection or low for DTE Mode. This input
affects operation in both software and hardware mode. In
DCE Mode, the DS33Z11 MAC port can be directly
connected to another MAC. In DCE Mode, the Transmit
clock (TX_CLK) and Receive clock (RX_CLK) are output
by the DS33Z11.
Note that there is no software bit selection of DCEDTES.
Note that DCE Mode is only relevant when the MAC
interface is in MII mode.
RMII or MII Selection: Set high to configure the MAC for
RMII interfacing. Set low for MII interfacing. This pin is tied
low in the 100 pin CSBGA (DS33ZH11) package option.
Full Duplex Selection (Hardware Mode): When in
Hardware Mode, this pin must be set to 1 for proper
operation (Full Duplex Mode). In software mode, this pin
has no effect and duplex selection is controlled in the
SU.GCR register. This pin is tied high in the 100 pin
CSBGA (DS33ZH11) package option.
100Mb/10Mb (Hardware Mode): When in Hardware
Mode, this pin selects the packet PHY data rate. Set high
for 100 Mbps. Set low for the MII/RMII interface to run at
10 Mbps. In the software mode this pin has no effect and
the rate selection is controlled in the SU.GCR register.
Note that in the 100-pin CSBGA (DS33ZH11) package,
this pin is internally tied to VDD.
23 of 172
DS33Z11 Ethernet Mapper
NAME
AFCS
PIN #
DS33Z11
CSBGA
(169)
C10
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
—
I
Automatic Flow Control (Hardware Mode): When in
Hardware Mode, set high to enable automatic flow control
pause and backpressure application. In the software
mode this pin has no effect and the rate selection is
controlled by the SU.GCR register.
Note that in the 100-pin CSBGA (DS33ZH11) package,
this pin is internally tied to VDD.
SDRAM CONTROLLER
SDATA[0]
SDATA[1]
SDATA[2]
SDATA[3]
SDATA[4]
SDATA[5]
SDATA[6]
SDATA[7]
SDATA[8]
SDATA[9]
SDATA[10]
SDATA[11]
SDATA[12]
SDATA[13]
SDATA[14]
SDATA[15]
SDATA[16]
SDATA[17]
SDATA[18]
SDATA[19]
SDATA[20]
SDATA[21]
SDATA[22]
SDATA[23]
SDATA[24]
SDATA[25]
SDATA[26]
SDATA[27]
SDATA[28]
SDATA[29]
SDATA[30]
SDATA[31]
M1
L2
N1
M2
N2
N4
N3
L4
J3
M3
H3
J1
J2
K1
K2
L1
M12
H11
M11
N13
N11
L13
N12
K13
J13
J12
H13
H12
G12
F11
G11
L10
H1
F2
J1
G2
K1
K2
J2
C3
D3
E2
C2
F1
G1
D1
D2
E1
K6
G7
J7
K8
K7
J8
H7
K9
J9
H8
H9
C7
G9
G8
G6
C6
SDA[0]
N9
J5
SDA[1]
N10
K5
SDA[2]
L11
H6
SDA[3]
K11
F9
SDA[4]
L7
C4
SDA[5]
L8
H4
IOZ
SDRAM Data Bus (Bits 0 through 31): The 32 pins of
the SDRAM data bus are inputs for read operations and
outputs for write operations. At all other times, these pins
are high-impedance.
Note: All SDRAM operations are controlled entirely by the
DS33Z11. No user programming for SDRAM buffering is
required.
O
SDRAM Address Bus 0 through 11: The 12 pins of the
SDRAM address bus output the row address first, followed
by the column address. The row address is determined by
SDA0 to SDA11 at the rising edge of clock. Column
address is determined by SDA0-SDA9 and SDA11 at the
rising edge of the clock. SDA10 is used as an autoprecharge signal.
Note: All SDRAM operations are controlled entirely by the
24 of 172
DS33Z11 Ethernet Mapper
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
SDA[6]
L9
G5
SDA[7]
L5
G4
SDA[8]
M5
F8
SDA[9]
M7
F5
SDA[10]
M8
H5
SDA[11]
N8
K4
SBA[0]
M6
F7
DS33Z11. No user programming for SDRAM buffering is
required.
SDRAM Bank Select: These two bits select 1 of 4 banks
for the read/write/precharge operations.
I
SBA[1]
N7
J4
SRAS
K6
K3
O
SCAS
H4
F4
O
SWE
M4
G3
O
SDMASK[0]
N6
F3
SDMASK[1]
G4
E3
SDMASK[2]
M10
J6
SDMASK[3]
M9
C5
SDCLKO
N5
J3
O
(4mA)
SYSCLKI
G13
K10
I
SDCS
L6
H3
O
O
Note: All SDRAM operations are controlled entirely by the
DS33Z11. No user programming for SDRAM buffering is
required.
Active-Low SDRAM Row Address Strobe: Used to latch
the row address on rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode
Register Write.
Active-Low SDRAM Column Address Strobe: Used to
latch the column address on the rising edge of SDCLKO.
It is used with commands for Bank Activate, Precharge,
and Mode Register Write.
Active-Low SDRAM Write Enable: This output enables
write operation and auto precharge.
SDRAM Mask 0 through 3: When high, a write is done
for that byte. The least significant byte is SDATA7 to
SDATA0. The most significant byte is SDATA31 to
SDATA24.
SDRAM CLK Out: System clock output to the SDRAM.
This clock is a buffered version of SYSCLKI.
System Clock In: 100MHz System Clock input to the
DS33Z11, used for internal operation. This clock is
buffered and provided at SDCLKO for the SDRAM
interface. The DS33Z11 also provides a divided version
output at the REF_CLKO pin. A clock supply with ±100
ppm frequency accuracy is suggested.
Active-Low SDRAM Chip Select: This output enables
SDRAM access.
QUEUE STATUS
QOVF
C7
—
O
Queue Overflow: This pin goes high when the transmit or
receive queue has overflowed. This pin goes low when the
high watermark is reached again. This pin functions in
both software and hardware mode.
25 of 172
DS33Z11 Ethernet Mapper
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
TYPE
FUNCTION
BGA(100)
JTAG INTERFACE
JTRST
E6
—
Ipu
Active-Low JTAG Reset: JTRST is used to
asynchronously reset the test access port controller. After
power-up, a rising edge on JTRST will reset the test port
and cause the device IO enter the JTAG DEVICE ID
mode. Pulling JTRST low restores normal device
operation. JTRST is pulled HIGH internally via a 10kΩ
resistor operation. If boundary scan is not used, this pin
should be held low.
JTCLK
D4
—
Ipu
JTAG Clock: This signal is used to shift data into JTDI on
the rising edge and out of JTDO on the falling edge.
JTDO
E5
—
Oz
JTAG Data Out: Test instructions and data are clocked
out of this pin on the falling edge of JTCLK. If not used,
this pin should be left unconnected.
JTDI
E4
—
Ipu
JTAG Data In: Test instructions and data are clocked into
this pin on the rising edge of JTCLK. This pin has a 10kΩ
pullup resistor.
Ipu
JTAG Mode Select: This pin is sampled on the rising
edge of JTCLK and is used to place the test access port
into the various defined IEEE 1149.1 states. This pin has
a 10kΩ pullup resistor.
JTMS
F7
—
POWER SUPPLIES
VDD3.3
VDD1.8
VSS
G5–G10,
H5–H10
D2, D3,
D12, E3,
E11, E12,
F4, F10,
J4, K4,
L3, L12,
M13
A12, D1,
E7, E8,
F8, F9,
F12, F13,
J5–J11,
K3, K5,
K7, K8,
K9, K10,
K12
A7, D4–
D8, H10
I
Connect to 3.3V Power Supply
A1, F6,
F10, H2,
J10
I
Connect to 1.8V Power Supply
A5, B4,
E4–E7
I
Connect to the Common Supply Ground
26 of 172
DS33Z11 Ethernet Mapper
Figure 7-1 DS33Z11 169-Ball CSBGA Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
A
A0
A2
A5
A8
D0
D1
D2
TX_CLK
FULLDS
RX_CLK
RXD3
VSS
DCEDTES
B
A1
A3
A6
A9
D3
D4
D5
SPI_CS
TXD0
H10S
RXD0
RX_ERR
COL_DET
C
CS
A4
A7
RMIIMIIS
D6
D7
QOVF
RX_CRS
TXD1
AFCS
RXD1
MDC
MDIO
D
VSS
VDD1.8
VDD1.8
JTCLK
MODEC1
RST
TXD2
RX_DV
RXD2
VDD1.8
REF_CLK
E
RD/DS
WR/RW
VDD1.8
JTDI
JTDO
JTRST
VSS
VSS
TXD3
TX_EN
VDD1.8
VDD1.8
REF_CLKO
F
TCLKI
TSER
INT
VDD1.8
TDEN
CKPHA
JTMS
VSS
VSS
VDD1.8
SDATA29
VSS
VSS
G
N.C.
RCLKI
N.C.
SDMASK1
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
SDATA30
SDATA28
SYSCLKI
H
RSER
RDEN
SDATA10
SCAS
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
SDATA17
SDATA27
SDATA26
J
SDATA11
SDATA12
SDATA8
VDD1.8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SDATA25
SDATA24
K
SDATA13
SDATA14
VSS
VDD1.8
VSS
SRAS
VSS
VSS
VSS
VSS
SDA3
VSS
SDATA23
L
SDATA15
SDATA1
VDD1.8
SDATA7
SDA7
SDCS
SDA4
SDA5
SDA6
SDATA31
SDA2
VDD1.8
SDATA21
M
SDATA0
SDATA3
SDATA9
SWE
SDA8
SBA0
SDA9
SDA10
SDATA16
VDD1.8
N
SDATA2
SDATA4
SDATA6
SDATA5
SDCLKO
SDMASK0
SBA1
SDA11
SDATA22
SDATA19
HWMODE MODEC0
27 of 172
SDMASK3 SDMASK2 SDATA18
SDA0
SDA1
SDATA20
DS33Z11 Ethernet Mapper
Figure 7-2 DS33ZH11 100-Ball CSBGA Pinout (Hardware or SPI Mode Only)
1
2
3
4
5
6
7
8
9
10
A
VDD1.8
TSER
HWMODE
MODEC1
VSS
(Future
A0)
TX_CLK
VDD3
TXD0
TXD3
RX_DV
B
TCLKI
RCLKI
RSER
VSS
(Future
A2)
SPI_CS
TX_EN
TXD1
TXD2
RX_ERR
RX_CLK
C
RST
SDATA10
SDATA7
SDA4
SDMASK3
SDATA31
SDATA27
RX_CRS
RXD2
RXD3
D
SDATA13
SDATA14
SDATA8
VDD3
VDD3
VDD3
VDD3
VDD3
(Future
A1)
RXD0
RXD1
E
SDATA15
SDATA9
SDMASK1
VSS
VSS
VSS
VSS
MOSI
MISO
SPICK
F
SDATA11
SDATA1
SDMASK0
SCAS
SDA9
VDD1.8
SBA0
SDA8
SDA3
VDD1.8
G
SDATA12
SDATA3
SWE
SDA7
SDA6
SDATA30
SDATA17
SDATA29
SDATA28
REF_CLK
O
H
SDATA0
VDD1.8
SDCS
SDA5
SDA10
SDA2
SDATA22
SDATA25
SDATA26
VDD3
J
SDATA2
SDATA6
SDCLKO
SBA1
SDA0
SDMASK2
SDATA18
SDATA21
SDATA24
VDD1.8
K
SDATA4
SDATA5
SRAS
SDA11
SDA1
SDATA16
SDATA20
SDATA19
SDATA23
SYSCLKI
Note that pins A5, D8, and B4 have been reserved for future device enhancements for addition of the signals A0,
A1, and A2. These ball assignments will allow for the potential future revision to be placed in application designed
for the initial device and maintain the same functionality.
Note that the JTAG pins are not available for use in the DS33ZH11 100-pin package.
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DS33Z11 Ethernet Mapper
8
FUNCTIONAL DESCRIPTION
The DS33Z11 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN
Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a
10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86(LAPS) Mapper,
SDRAM interface, control ports, and Bit Error Rate Tester (BERT).
The Ethernet Packet interface supports MII and RMII interfaces allowing DSZ33Z11 to connect to commercially
available Ethernet PHY and MAC devices. The Ethernet interface can be configured for 10 Mbps or 100 Mbps
service, in DTE and DCE configurations. The DS33Z11 MAC interface rejects frames with bad FCS and short
frames (less than 64 bytes).
Ethernet frames are queued and stored in external 32-bit SDRAM. The DS33Z11 SDRAM controller enables
connection to a 128Mbit SDRAM without external glue logic, at clock frequencies up to 100 MHz. The SDRAM is
used for both the Transmit and Receive Data Queues. The Receive Queue stores data to be sent from the Packet
interface to the WAN interface. The Transmit Queue stores data to be sent from the WAN interface to the Packet
interface. The external SDRAM can accommodate up to 8192 frames with a maximum frame size of 2016 bytes.
The sizing of the queues can be adjusted by software. The user can also program high and low watermarks for
each queue that can be used for automatic or manual flow control. The packet data stored in the SDRAM is
encapsulated in HDLC or X.86 (LAPS) to be transmitted over the WAN interface. The device also provides the
capability for bit and packet scrambling.
The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet port. The WAN physical interface supports serial data streams up to 52 Mbps. The WAN serial port can
operate with a gapped clock, and can be connected to a framer, electrical LIU, optical transceiver, or T/E-Carrier
transceiver for transmission to the WAN. The WAN interface can be connected to the Dallas
Semiconductor/Maxim T1/E1/J1 framers, LIUs, and SCTs. The WAN interface can also be connected to the
Dallas Semiconductor/Maxim T3/E3/STS-1 framers, LIUs, and SCTs to provide T3, E3, and STS1 connectivity.
The DS33Z11 can be configured through an 8-bit microprocessor interface port. A serial EEPROM (SPI) interface
and hardware mode are also included for applications without a host microprocessor. Operation without an
external host simplifies and reduces the cost of typical applications such as connectivity to T1/T3 and E1/E3 front
ends. The DS33Z11 also provides two on-board clock dividers for the System Clock input and Reference Clock
Input for the 802.3 interfaces, further reducing the need for ancillary devices.
8.1
Processor Interface
Microprocessor control of the DS33Z11 is accomplished through the 20 interface pins of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0]
pins. When MODEC[1:0] = 00 and HWMODE = 0, bus timing is in Intel mode, as shown in Figure 11-9 and
Figure 11-10. When MODEC[1:0] = 01 and HWMODE = 0, bus timing is in Motorola mode, as shown in Figure
11-11 and Figure 11-12. The address space is mapped through the use of 8 address lines, A0-A7. Multiplexed
Mode is not supported on the processor interface.
The Chip Select (CS) pin must be brought to a logic low level to gain read and write access to the microprocessor
port. With Intel timing selected, the Read (RD) and Write (WR) pins are used to indicate read and write operations
and latch data through the interface. With Motorola timing selected, the Read-Write (RW) pin is used to indicate
read and write operations while the Data Strobe (DS) pin is used to latch data through the interface.
The interrupt output pin (INT) is an open-drain output that will assert a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The register
map is shown in Table 9-1.
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DS33Z11 Ethernet Mapper
8.1.1
Read-Write/Data Strobe Modes
The processor interface can operate in either read-write strobe mode or data strobe mode. When MODEC[1:0] =
00 and HWMODE pin = 0 the read-write strobe mode is enabled and a negative pulse on RD performs a read
cycle, and a negative pulse on WR performs a write cycle. When MODEC[1:0] pins = 01 and HWMODE pin = 0
the data strobe mode is enabled and a negative pulse on DS when RW is high performs a read cycle, and a
negative pulse on DS when RW is low performs a write cycle. The read-write strobe mode is commonly called the
“Intel” mode, and the data strobe mode is commonly called the “Motorola” mode.
8.1.2
Clear on Read
The latched status registers will clear on a read access. It is important to note that in a multi-task software
environment, the user should handle all status conditions of each register at the same time to avoid inadvertently
clearing status conditions. The latched status register bits are carefully designed so that an event occurrence
cannot collide with a user read access.
8.1.3
Interrupt and Pin Modes
The interrupt (INT) pin is configurable to drive high or float when not active. The INTM bit controls the pin
configuration, when it is set the INT pin will drive high when not active. After reset, the INT pin is in highimpedance mode until an interrupt source is active and enabled to drive the interrupt pin.
8.2
SPI Serial EEPROM Interface
The SPI interface is a 4 signal serial interface that allows connection to a serial EEPROM for initialization
information. The DS33Z11 will act as an SPI Master when configured with MODEC[1:0] to read from an external
Serial EEPROM. The reading sequence is commenced upon initial reset or rising edge of the RST input pin. The
CKPHA pin controls the sampling and update edges of the MISO and MOSI signals. The MISO data can be
sampled on rising or falling edge of SPICK. The MOSI (Master Out Slave In) can be selectively output on the
rising or falling edge of SPICK. The SPICK is generated by the DS33Z11 at a frequency of 8.33 MHz. This
frequency is derived from an external SYSCLKI (100 MHz). The instruction to initiate a read is 0000x011; this is
followed by the address location 0. The SPI_CS is low till the data addressed (Table 10-1) is read and latched.
The DS33Z11 will provide the starting address (0000000) and the data is sequentially latched till the last data is
read and latched. The MAC specific registers, which are addressed indirectly, are written at the end of the normal
control registers. More details of the programming sequence an functional timing information can be found in
Section 10.3. The indirect registers related to the MAC are programmed using a special command format as
shown in Table 10-2.
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DS33Z11 Ethernet Mapper
8.3
CLOCK STRUCTURE
The DS33Z11 clocks sources and functions are as follows:
•
Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data
from the serial interface. These clocks can be continuous or gapped.
•
System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with ±100 ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SDCLKO pin for the operation of the SDRAM. A divided and buffered version of this clock is
provided on the SPICK pin for Serial EEPROM operation. A divided and buffered version of this clock is
provided on REF_CLKO for the RMII/MII interface.
•
Packet Interface Reference clock (REF_CLK) input that can be 25 or 50 MHz. This clock is used as the
timing reference for the RMII/MII interface.
•
The Transmit and Receive clocks for the MII Interface (TX_CLK and RX_CLK). In DTE mode, these are
input pins and accept clocks provided by an Ethernet PHY. In the DCE mode, these are output pins and
will output an internally generated clock to the Ethernet PHY. The output clocks are generated by internal
division of REF_CLK. In RMII mode, only the REF_CLK input is used.
•
REF_CLKO is an output clock that is generated by dividing the 100 MHz System clock (SYSCLKI) by 2 or
4.
•
A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67 MHz.
The following table provides the different clocking options for the Ethernet interface.
Table 8-1 Clocking Options for the Ethernet Interface
RMIIMIIS
Pin
0 (MII)
0 (MII)
0 (MII)
1 (RMII)
1 (RMII)
Speed
10
Mbps
10
Mbps
100
Mbps
10
Mbps
100
Mbps
DCE/
DTE
REF_CLKO
Output
DTE
25 MHz
DCE
25 MHz
DCE
25 MHz
-
50 MHz
-
50 MHz
REF_CLK
Input
25 MHz
+/- 100 ppm
25 MHz
+/- 100 ppm
25 MHz
+/- 100 ppm
50 MHz
+/- 100 ppm
50 MHz
+/- 100 ppm
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MDC
Output
RX_CLK
TX_CLK
Input from
PHY
2.5 MHz
(Output)
25 MHz
(Output)
Input from
PHY
2.5 MHz
(Output)
25 MHz
(Output)
1.67 MHz
Not Applicable
Not Applicable
1.67 MHz
Not Applicable
Not Applicable
1.67 MHz
1.67 MHz
1.67 MHz
DS33Z11 Ethernet Mapper
Figure 8-1 Clocking for the DS33Z11
Eprom
SPI_SCLK (max 8.33Mhz)
50 or 25 Mhz Oscillator
Buffer
Dev
Div by 1,2,4,8,10
Output clocks:
50,25 Mhz,2.5 Mhz
Microport
REF_CLKI
TSER
TCLKI1
Line 1
RCLKI1
RSER
HDLC
+
Serial
Interface
TX_CLK1
MAC
RMII
MII
CIR
Arbiter
RXD
RX_CLK1
TXD
X.86
MDC
100 Mhz Oscillator
JTAG
Buffer Dev
Div by 2,4,12
Output Clocks
25,50
Mhz
SDRAM
Interface
SDCLKO
REF_CLKO
50 or 25 Mhz
SDRAM
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SYSCLKI
DS33Z11 Ethernet Mapper
8.3.1
Serial Interface Clock Modes
The Serial Interface timing is determined by the line clocks. Both the transmit and receive clocks (TCLKI and
RCLKI) are inputs, and can be gapped.
8.3.2
Ethernet Interface Clock Modes
The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation.
Table 8-1 outlines the possible clocking modes for the Ethernet Interface. The buffered REF_CLKO output is
generated by division of the 100 MHz system clock input by the user on SYSCLKI. The frequency of the
REF_CLKO pin is automatically determined by the DS33Z11 based on the state of the RMIIMIIS pin. The
REF_CLKO function can be turned off with the GL.CR1.RFOO bit.
In RMII mode, receive and transmit timing is always synchronous to a 50 MHz clock input on the REF_CLK pin.
The source of REF_CLK is expected to be the external PHY. More information on RMII mode can be found in
Section 8.14.2.
While using MII mode with DTE operation, the MII clocks (RX_CLK and TX_CLK) are inputs that are expected to
be provided by the external PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and
RX_CLK) are output by the DS33Z11, and are derived from the 25 MHz REF_CLK input. Note that in DCE and
RMII operating modes, the REF_CLKO signal should not be used to provide an input to REF_CLK, due to the
reset requirements in these operating modes. More information on MII mode can be found in Section 8.14.1.
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DS33Z11 Ethernet Mapper
8.4
Resets and Low Power Modes
The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset
signal resets the status and control registers on the chip (except the GL.CR1. RST bit) to their default values and
resets all the other flops to their reset values. The processor bus output signals are also placed in highimpedance mode when the RST pin is active (low). The global reset bit (GL.CR1. RST) stays set after a one is
written to it, but is reset to zero when the external RST pin is active or when a zero is written to it. Allow 5
milliseconds after initiating a reset condition for the reset operation to complete.
The Serial Interface reset bit in LI.RSTPD resets all the status and control registers on the Serial interface to their
default values, except for the LI.RSTPD.RST bit. The Serial Interface includes the HDLC encoder/decoder, X86
encoder and decoder and the corresponding serial port. The Serial Interface reset bit (LI.RSTPD.RST) stays set
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
If DS33Z11 is configured to use an external EEPROM, the DS33Z11 will provide the startup sequence to read the
device settings upon the rising edge of the external RST pin. When using the external EEPROM the device is
configured within 5 ms. This is dependent on an EEPROM clock of 8.33 MHz. The functional timing is provided by
Figure 10-10.
Table 8-2 Reset Functions
RESET FUNCTION
LOCATION
COMMENTS
Hardware Device Reset
RST Pin
Transition from a logic 0 to a logic 1
resets the device.
Hardware JTAG Reset
JTRST Pin
Resets the JTAG test port.
Global Software Reset
GL.CR1
Writing to this bit resets the device.
Serial interface Reset
LI.RSTPD
Writing to this bit resets the Serial
Interface.
Queue Pointer Reset
GL.C1QPR
Writing to this bit resets the Queue
Pointers
There are several features in the DS33Z11 to reduce power consumption. The reset bit in the LI.RSTPD register
minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1.RST bit may be held in reset
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization
and configuration. For the lowest possible standby current, clocks may be externally gated.
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DS33Z11 Ethernet Mapper
8.5
Initialization and Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE:
STEP 1: Apply 3.3V supplies, then apply 1.8V supplies.
STEP 2: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 8.4.
Clear all reset bits. Allow 5 milliseconds for the reset recovery.
STEP 3: Check the Device ID in the GL.IDRL and GL.IDRH registers.
STEP 4: Configure the system clocks. Allow the clock system to properly adjust.
STEP 5: Initialize the entire remainder of the register space with 00h (or otherwise if specifically noted in the
register’s definition), including the reserved bits and reserved register locations.
STEP 6: Write FFFFFFFFh to the MAC indirect addresses 010Ch through 010Fh.
STEP 7: Setup connection in the GL.CON1 register.
STEP 8: Configure the Serial Port register space as needed.
STEP 9: Configure the Ethernet Port register space as needed.
STEP 10: Configure the Ethernet MAC indirect registers as needed.
STEP 11: Configure the external Ethernet PHY through the MDIO interface.
STEP 12: Clear all counters and latched status bits.
STEP 13: Set the queue size in the Arbiter and reset the queue pointers for the Ethernet and Serial interfaces.
STEP 14: Enable Interrupts as needed.
STEP 15: Begin handling interrupts and latched status events.
8.6
Global Resources
In order to maintain software compatibility with the multiport devices in the product family, a set of Global registers
are located at 0F0h-0FFh. The global registers include Global resets, global interrupt status, interrupt masking,
clock configuration, and the Device ID registers. See the Global Register Definitions in Table 9-2.
8.7
Per-Port Resources
Multi-port devices in this product family share a common set of global registers, BERT, and Arbiter. All other
resources are per-port.
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DS33Z11 Ethernet Mapper
8.8
Device Interrupts
Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global
Latched Status registers GL.LIS, GL.SIS, GL.BIS, and GL.TRQIS to initially determine the source of the interrupt.
The host can then read the LI.TQCTLS, LI.TPPSRL, LI.RPPSRL, LI.RX86S, SU.QCRLS, or BSRL registers to
further identify the source of the interrupt(s). In order to maintain software compatibility with the multiport devices
in the product family, the global interrupt status and interrupt enable registers have been preserved, but do not
need to be used. If GL.TRQIS is determined to be the interrupt source, the host will then read the LI.TPPSRL and
LI.RPPSRL registers for the cause of the interrupt. If GL.LIS is determined to be the interrupt source, the host will
then read the LI.TQCTLS, LI.TPPSRL, LI.RPPSRL, and LI.RX86S registers for the source of the interrupt. If
GL.SIS is the source, the host will then read the SU.QCRLS register for the source of the interrupt. If GL.BIS is
the source, the host will then read the BSRL register for the source of the interrupt. All Global Interrupt Status
Register bits are real-time bits that will clear once the appropriate interrupt has been serviced and cleared, as
long as no additional, enabled interrupt conditions are present in the associated status register. All Latched
Status bits must be cleared by the host writing a “1” to the bit location of the interrupt condition that has been
serviced. In order for individual status conditions to transmit their status to the next level of interrupt logic, they
must be enabled by placing a “1” in the associated bit location of the correct Interrupt Enable Register. The
Interrupt enable registers are LI.TPPSRIE, LI.RPPSRIE, LI.RX86LSIE, BSRIE, SU.QRIE, GL.LIE, GL.SIE,
GL.BIE, and GL.TRQIE. Latched Status bits that have been enabled via Interrupt Enable registers are allowed to
pass their interrupt conditions to the Global Interrupt Status Registers. The Interrupt enable registers allow
individual Latched Status conditions to generate an interrupt, but when set to zero, they do not prevent the
Latched Status bits from being set. Therefore, when servicing interrupts, the user should AND the Latched Status
with the associated Interrupt Enable Register in order to exclude bits for which the user wished to prevent
interrupt service. This architecture allows the application host to periodically poll the latched status bits for noninterrupt conditions, while using only one set of registers. Note the bit-orders of SU.QRIE and SU.QCRLS are
different.
Note that the inactive state of the interrupt output pin is configurable. The INTM bit in GL.CR1 controls the
inactive state of the interrupt pin, allowing selection of a pull-up resistor or active driver.
The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. The
latched status bits for the interrupting entity must be read to clear the interrupt. Also reading the latched status bit
will reset all bits in that register. During a reset condition, interrupts cannot be generated. The interrupts from any
source can be blocked at a global level by the placing a zero in the global interrupt enable registers (GL.LIE,
GL.SIE, GL.BIE, and GL.TRQIE). Reading the Latched Status bit for all interrupt generating events will clear the
interrupt status bit and Interrupt signal will be de-asserted.
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DS33Z11 Ethernet Mapper
SAPI High is not equal to LI.TRX86SAPIH
SAPI Low is not equal to LI.TRX86SAPIL
Control is not equal to LI.TRX8C
Address is not equal to LI.TRX86A
Transmit Queue FIFO Overflowed
Transmit Queue Overflow
Transmit Queue for Connection Exceeded Low Threshold
Transmit Queue for Connection Exceeded High
Threshold
Receive Queue FIFO Overflowed
Receive Queue Overflow
Receive Queue for Connection Exceeded Low Threshold
Receive Queue for Connection Exceeded High Threshold
Performance Monitor Update
Bit Error Detected
Bit Error Count
Out Of Synchronization
LI.RPPSRIE
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
37 of 172
Interrupt Pin
GL.TRQIE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
GL.LIE
GL.SIE
Transmit Errored Packet Insertion Finished
Register Name
GL.BIE
Interrupt
Enable
Registers
GL.TRQIS
Register Name
GL.LIS
Interrupt Status
Registers
GL.SIS
Drawing Legend:
GL.BIS
LI.TPPSRIE
LI.RX86LSIE
LI.TQTIE
Receive Size Violation Packet Count
SU.QRIE
Receive Aborted Packet Count
BSRIE
Receive FCS Errored Packet Count
LI.TPPSRL
Receive Large Packet Detected
LI.RX86S
Receive Small Packet Detected
LI.TQCTLS
Receive Invalid Packet Detected
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
SU.QCRLS
Receive Aborted Packet
BSRL
Receive FCS Errored Packet
LI.RPPSL
Figure 8-2 Device Interrupt Information Flow Diagram
DS33Z11 Ethernet Mapper
8.9
Serial Interface
The Serial (WAN) interface supports time-division multiplexed, serial data input and output up to 52 Mbps. The
Serial interface receives and transmits encapsulated Ethernet packets. The Serial Interface block consists of the
physical serial port and HDLC / X.86 engine. The physical interface consists of a Transmit Data, Transmit Clock,
Transmit Enable, Receive Data, Receive Clock, and Receive Enable. The WAN serial port can operate with a
gapped clock, and can be connected to a framer, electrical LIU, optical transceiver, or T/E-Carrier transceiver for
transmission to the WAN. The WAN interface can be connected to the Dallas Semiconductor/Maxim T1/E1/J1
framers, LIUs, and SCTs such as the DS26401, DS21348, and DS2155. The WAN interface can also be
connected to the Dallas Semiconductor/Maxim T3/E3/STS-1 framers, LIUs, and SCTs such as the DS3144 or
DS3154 to provide T3, E3, and STS1 connectivity.
8.10 Connections and Queues
The multiport devices in this product family provide bidirectional cross-connections between the multiple Ethernet
ports and Serial ports when operating in software mode. A single connection is preserved in this single-port
device to provide software compatibility with multi-port devices. The connection will have an associated transmit
and receive queue. Note that the terms “Transmit Queue” and “Receive Queue” are with respect to the Ethernet
Interface. The Receive queue is for data arriving from Ethernet interface to be transmitted to the WAN interface.
The Transmit queue is for data arriving from the WAN to be transmitted to the Ethernet interface. Hence the
transmit and receive direction terminology is the same as is used for the Ethernet MAC port.
The user can define the connection and the size of the transmit and receive queues. The size is adjustable in
units of 32(by 2048 byte) packets. The external SDRAM can hold up to 8192 packets of data. The user must
ensure that all the connection queues do no exceed this limit. The user also must ensure that the transmit and
receive queues do not overlap each other. Unidirectional connections are not supported.
When the user changes the queue sizes, the connection must be torn down and re-established. When a
connection is disconnected all transmit and receive queues associated with the connection are flushed and a “1’
is sourced towards the Serial transmit and the HDLC receiver. The clocks to the HDLC are sourced a “0.”
The user can also program High and Low watermarks. If the queue size grows past the High watermark, an
interrupt is generated if enabled. The registers of relevance are described in Table 8-3. The AR.TQSC1 size
provides the size of the transmit queue for the connection. The High Watermark will set a latched status bit. The
latched status bit will clear when the register is read. The status bit is indicated by LI.TQCTLS.TQHTS. Interrupts
can be enabled on the latched bit events by LI.TQTIE. A latched status bit (LI.TQCTLS.TQLTS) is also set when
the queue crosses a low watermark.
The Receive Queue functions in a similar manner. Note that the user must ensure that sizes and watermarks are
set in accordance with the configuration speed of the Ethernet and Serial interfaces. The DS33Z11 does not
provide error indication if the user creates a connection and queue that overwrites data for another connection
queue. The user must take care in setting the queue sizes and watermarks. The registers of relevance are
AR.RQSC1and SU.QCRLS. Queue size should never be set to 0.
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DS33Z11 Ethernet Mapper
It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers
must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data
may be transmitted. The proper procedure for setting up a connection follows:
•
Set up the queue sizes for both transmit and receive queue (AR.TQSC1 and AR.RQSC1).
•
Set up the high/low thresholds and interrupt enables if desired (GL.TRQIE, LI.TQTIE, SU.QRIE)
•
Reset all the pointers for the connection desired (GL.C1QPR)
•
Set up the connections (GL.CON1)
•
If a connection is disconnected, reset the queue pointers after the disconnection.
Table 8-3 Registers Related to Connections and Queues
Register
GL.CON1
Enables connection between the Ethernet Interface and the Serial Interface.
Note that once connection is set up, then the queues and thresholds can be
setup for that connection.
AR.TQSC1
Size for the Transmit Queue in Number of 32—2K packets.
AR.RQSC1
Size for the Receive Queue in Number of 32—2K packets.
GL.TRQIE
Interrupt enable for items related to the connections at the global level
GL.TRQIS
Interrupt enable status for items related to the connections at the global level
LI.TQTIE
Enables for the Transmit queue crossing high and low thresholds
LI.TQCTLS
Latched status bits for connection high and low thresholds for the transmit
queue.
SU.QRIE
Enables for the receive queue crossing high and low thresholds
SU.QCRLS
Latched status bits for receive queue high and low thresholds.
GL.C1QPR
Resets the connection pointer.
8.11 Arbiter
The Arbiter manages the transport between the Ethernet port and the Serial port. It is responsible for queuing and
dequeuing packets to a single external SDRAM. The arbiter handles requests from the HDLC and MAC to
transfer data to and from the SDRAM.
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8.12 Flow Control
Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33Z11
allows for optional flow control based on the queue high watermark or through host processor intervention. There
are 2 basic mechanisms that are used for flow control:
•
In half duplex mode, a jam sequence is sent that causes collisions at the far end. The collisions cause the
transmitting node to reduce the rate of transmission.
•
In full duplex mode, flow control is initiated by the receiving node sending a pause frame. The pause
frame has a timer parameter that determines the pause timeout to be used by the transmitting node.
Note that the terms “transmit queue” and “receive queue” are with respect to the Ethernet Interface. The Receive
Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and stored in the
SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and stored in the
SDRAM to be sent to the MAC transmitter.
The following flow control options are possible:
•
Automatic flow control can be enabled in hardware mode by the AFCS pin.
•
Automatic flow control can be enabled in software mode with the SU.GCR.ATFLOW bit. Note that the
user does not have control over SU.MACFCR.FCE and FCB bits if ATFLOW is set. The mechanism of
sending pause or jam is dependent only on the receive queue high threshold.
•
Manual flow control can be performed through software when SU.GCR.ATFLOW = 0. The host processor
must monitor the receive queues and generate pause frames (full duplex) and/or jam bytes through the
SU.MACFCR.FCB, SU.GCR.JAME, and SU.MACFCR.FCE bits.
Note that in order to use flow control, the receive queue size (in AR.RQSC1) must be 02h or greater. The receive
queue high threshold (in SU.RQHT) must be set to 01h or greater, but must be less than the queue size. If the
high threshold is set to the same value as the queue size, automatic flow control will not be effective. The high
threshold must always be set to less than the corresponding queue size.
The following table provides all the options on flow control mechanism for DS33Z11.
Table 8-4 Options for Flow Control
Configuration
HWMODE Pin
AFCS Pin
ATFLOW Bit
JAME Bit
FCB Bit
(Pause)
FCE Bit
Pause Timer
HARDWARE MODE
Full duplex,
Full duplex,
Flow control
No flow
With respect
control
to SU.RQHT
1
1
0
1
N/A
N/A
SOFTWARE MODE
Half Duplex;
Manual Flow
Control
Half Duplex;
Automatic
Flow Control
Full Duplex;
Manual Flow
Control
Full Duplex;
Automatic
Flow Control
0
N/A
0
0
N/A
1
0
N/A
0
0
N/A
1
N/A
N/A
Controlled By
User
Controlled
Automatically
N/A
N/A
N/A
Controlled
Automatically
N/A
N/A
Controlled by
User
Controlled
Automatically
N/A
Set to AFCS
pin = High
Controlled By
User
Controlled
Automatically
Controlled By
User
Controlled
Automatically
N/A
Set to 140h
N/A
N/A
Programmed
by User
Programmed
by User
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8.12.1 Full-Duplex Flow Control
In the software mode automatic flow control is enabled by default. The host processor can disable this
functionality with SU.GCR.ATFLOW. In hardware mode, the user must apply a logic high level to the AFCS pin to
enable automatic flow control. The flow control mechanism is governed by the high watermarks (SU.RQHT). The
SU.RQLT low threshold can be used as indication that the network congestion is clearing up. The value of
SU.RQLT does not affect the flow control. When the connection queue high threshold is exceeded the DS33Z11
will send a pause frame with the timer value programmed by the user. See Table 8-6 for more information. It is
recommended that 80 slots (80 by 64 bytes or 5120 bytes) be used as the standard timer value.
The pause frame causes the distant transmitter to “pause for a time” before starting transmission again. The
pause command has a multicast address 01-80-62-00-00-01. The high and low thresholds for the receive queue
are configurable by the user but it is recommended that the high threshold be set approximately 96 packets from
the maximum size of the queue and the low threshold 96 packets lower than the high threshold. The DS33Z11
will send a pause frame as the queue has crossed the high threshold and a frame is received. Pause is sent
every time a frame is received in the “high threshold state”. Pause control will only take care of temporary
congestion. Pause control does not take care of systems where the traffic throughput is too high for the queue
sizes selected. If the flow control is not effective the receive queue will eventually overflow. This is indicated by
SU.QCRLS.RQOVFL latched bit. If the receive queue is overflowed any new frames will not be received.
The user has the option of not enabling automatic flow control. In this case the thresholds and corresponding
interrupt mechanism to send pause frame by writing to flow control busy bit in the MAC flow control registers
SU.MACFCR.FCB, SU.GCR.JAME, and SU.MACFCR. This allows the user to set not only the watermarks but
also to decide when to send a pause frame or not based on watermark crossings.
On the receive side the user has control over whether to respond to the pause frame sent by the distant end (PCF
bit). Note that if automatic flow control is enabled the user cannot modify the FCE bit in the MAC flow control
register. On the Transmit queue the user has the option of setting high and low thresholds and corresponding
interrupts. There is no automatic flow control mechanism for data received from the Serial side waiting for
transmission over the Ethernet interface during times of heavy Ethernet congestion.
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Figure 8-3 Flow Control Using Pause Control Frame
8
Receive Queue Low
Water
Rx
Data
Receive Queue
Growth
Receive Queue High
Water Mark
Initiate Flow control
8.12.2 Half Duplex Flow control
Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving
node jams the first 4 bytes of a packet that are received from the MAC in order to cause collisions at the distant
end. In both 100 Mbps and 10 Mbps MII/RMII modes, 4 bytes are jammed upon reception of a new frame. Note
that the jamming mechanism does not jam the current frame that is being received during the watermark
crossing, but will wait to jam the next frame after the SU.RQHT bit is set. If the queue remains above the high
threshold, received frames will continue to be jammed. This jam sequence is stopped when the queue falls below
the high threshold.
8.12.3 Host-Managed Flow control
Although automatic flow control is recommended, flow control by the host processor is also possible. By utilizing
the high watermark interrupts, the host processor can manually issue pause frames or jam incoming packets to
exert backpressure on the transmitting node. Pause frames can be initiated with SU.MACFCR.FCB bit. Jam
sequences can be initiated be setting SU.GCR.JAME. The host can detect pause frames by monitoring
SU.RFSB3.UF and SU.RFSB3.CF. Jammed frames will be indistinguishable from packet collisions.
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8.13 ETHERNET Interface Port
The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100
Mbps MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains 7 signals with a
reference clock of 50 MHz. In MII operation, the interface contains 17 signals and a clock reference of 25 MHz.
The DS33Z11 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS. If the port is configured
for MII in DCE mode, REF_CLK must be 25 MHz. The DS33Z11 will internally generate the TX_CLK and
RX_CLK outputs (at 25 MHz for 100Mbps, 2.5 MHz for 10Mbps) required for DCE mode from the REF_CLK
input. In MII mode with DTE operation, the TX_CLK and RX_CLK signals are generated by the PHY and are
inputs to the DS33Z11. For more information on clocking the Ethernet Interface, see Section 8.3.
The data received from the MII or RMII interface is processed by the internal IEEE 802.3 compliant Ethernet
MAC. The user can select the maximum frame size (up to 2016 bytes) that is received with the SU.RMFSRH and
SU.RMFSRL registers. The maximum frame length (in bits) is the number specified in SU.RMFSRH and
SU.RMFSRL multiplied by 8. Any programmed value greater than 2016 bytes will result in unpredictable
behavior and should be avoided. The maximum frame size is shown in Figure 8-4. The length includes only
destination address, source address, VLAN tag (2 bytes), type length field, data and CRC32. The frame size is
different than the 802.3 “type length field”.
Frames coming from the Ethernet PHY or received from the packet processor are rejected if greater than the
maximum frame size specified. Each Ethernet frame sent or received generates status bits (SU.TFSH and
SU.TFSL and SU.RFSB0 to SU.RFSB3). These are real time status registers and will change as each frame is
sent or received. Hence they are useful to the user only when one frame is sent or received and the status is
associated with the frame sent or received.
Figure 8-4 IEEE 802.3 Ethernet Frame
Preamble
SFD
Destination Adrs
Source Address
Type
Lenght
Data
CRC32
7
1
6
6
2
46-1500
4
Max Frame Length
The distant end will normally reject the sent frames if jabber timeout, Loss of carrier, excessive deferral, late
collisions, excessive collisions, under run, deferred or collision errors occur. Transmission of a frame under any of
theses errors will generate a status bit in SU.TFSL, SU.TFSH. The DS33Z11 provides user the option to
automatically retransmit the frame if any of the errors have occurred through the bit settings in SU.TFRC.
Deferred frames and heartbeat fail have separate resend control bits (SU.TFRC.TFBFCB and
SU.TFRC.TPRHBC). If there is no carrier (indicated by the MAC Transmit Packet Status), the transmit queue
(data from the Serial Interface to the SDRAM to Ethernet Interface) can be selectively flushed. This is controlled
by SU.TFRC.NCFQ.
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The MAC circuitry generates a frame status for every frame that is received. This real time status can be read by
SU.RFSB0 to SU.RFSB3. Note the frame status is the “real time” status and hence the value will change as new
frames are received. Hence the real time status reflects the status in time and may not correspond to the current
received frame being processed. This is also true for the transmitted frames.
Frames with errors are usually rejected by the DS33Z11. The user has the option of accepting frames by settings
in Receive Frame Rejection Control register (SU.RFRC). The user can program whether to reject or accept
frames with the following errors:
•
MII error asserted during the reception of the frame
•
Dribbling bits occurred in the frame
•
CRC error occurred
•
Length error occurred—the length indicated by the frame length is inconsistent with the number of bytes
received
•
Control frame was received. The mode must be full duplex
•
Unsupported control frame was received
Note that frames received that are runt frames or frames with collision will automatically be rejected. In Hardware
Mode any frame received with errors is rejected and any frame transmitted with an error is retransmitted
Table 8-5 Registers Related to Setting the Ethernet Port
Register
Comment
SU.TFRC
This register determines if the current frame is retransmitted due to various
transmit errors
SU.TFSL and SU.TFSH
These 2 registers provide the real time status of the transmit frame. Only apply
to the last frame transmitted.
SU.RFSB0 to 3
These registers provide the real time status for the received frame. Only apply
to the last frame received.
SU.RFRC
This register provides settings for reception or rejection of frame based on
errors detected by the MAC.
SU.RMFSRH and SU.RMFSRL
The settings for this register provide the maximum size of frames to be
accepted from the MII/RMII receive interface.
SU.MACCR
This register provides configuration control for the MAC
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8.13.1 DTE and DCE Mode
The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE
Mode it can be connected to an Ethernet PHY. In DCE mode, the port can be connected to MII/RMII MAC
devices other than an Ethernet PHY. The DTE/DCE connections for the DS33Z11 in MII mode are shown in the
following 2 figures.
In DCE Mode, the DS33Z11 transmitter is connected to an external receiver and DS33Z11 receiver is connected
to an external MAC transmitter. The selection of DTE or DCE mode is done by the hardware pin DCEDTES.
Figure 8-5 Configured as DTE Connected to an Ethernet PHY in MII Mode
DS33Z11
Rx
Ethernet Phy
RXD[3:0]
DTE
Arbiter
WAN
MAC
RXD[3:0]
RXDV
RX_CLK
RXDV
RX_CLK
RX_ERR
RX_ERR
RX_CRS
RX_CRS
COL_DET
COL_DET
TXD[3:0]
TXD[3:0]
TX_CLK
TX_CLK
TX_EN
Rx
DCE
Tx
Tx
TX_EN
MDIO
MDC
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MDIO
MDC
DS33Z11 Ethernet Mapper
Figure 8-6 DS33Z11 Configured as a DCE in MII Mode
DS33Z11
DTE
DCE
Rx
Tx
RXD[3:0]
WAN
Arbiter
MAC
Tx
TXD[3:0]
RXDV
RX_CLK
TX_EN
TX_CLK
RX_ERR
TX_ERR
RX_CRS
RX_CRS
COL_DET
COL_DET
TXD[3:0]
RXD[3:0]
TX_CLK
RX_CLK
MAC
Rx
TX_EN
MDIO
MDC
RXDV
MDIO
MDC
8.14 Ethernet MAC
Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the
SU.MACWD0-3 registers to be written with 4 bytes of data. The address must be written to SU.MACAWL and
SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one to
SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33Z11 when the operation is complete.
Reading from the MAC registers requires the SU.MACRADH and SU.MACRADL registers to be written with the
address for the read operation. A read command is issued by writing a one to SU.MACRWC.MCRW and a zero
to SU.MACRWC.MCS. SU.MACRWC.MCS is cleared by the DS33Z11 when the operation is complete. After
MCS is clear, valid data is available in SU.MACRD0-SU.MACRD3. Note that only one operation can be initiated
(read or write) at one time. Data cannot be written or read from the MAC registers until the MCS bit has been
cleared by the device. The MAC Registers are detailed in the following table.
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Table 8-6 MAC Control Registers
Address
Register
0000h-0003h
SU.MACCR
0004h-0007h
SU.MACAH
0008h-000Bh
SU.MACAL
0014h-0017h
SU.MACMIIA
0018h-001Bh
SU.MACMIID
001Ch-001Fh
SU.MACFCR
0100h-0103h
SU.MMCCTRL
Register Description
MAC Control Register. This register is used for
programming full duplex, half duplex, promiscuous mode,
and back-off limit for half duplex. The transmit and receive
enable bits must be set for the MAC to operate.
MAC Address High Register. This provides the physical
address for this MAC.
MAC Address Low Register. This provides the physical
address for this MAC.
MII Address Register. The address for PHY access
through the MDIO interface.
MII Data Register. Data to be written to (or read from) the
PHY through MDIO interface.
Flow Control Register
MMC Control Register bit 0 for resetting the status
counters
Table 8-7 MAC Status Registers
Address
0200h-0203h
0204h-0207h
0300h-0303h
0308h-030Bh
030Ch-030Fh
0334h-0337h
0338h-033Bh
Register
SU.RxFrmCntr
SU.RxFrmOKCtr
SU.TxFrmCtr
SU.TxBytesCtr
SU.TxBytesOkCtr
SU.TxFrmUndr
SU.TxBdFrmsCtr
Register Description
All Frames Received counter
Number of Received Frames that are Good
Number of Frames Transmitted
Number of Bytes Transmitted
Number of Bytes Transmitted with good frames
Transmit FIFO underflow counter
Transmit Number of Frames Aborted
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8.14.1 MII Mode Options
The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII
interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see
Section 8.3. Diagrams of system connections for MII operation are shown in Figure 8-5 and Figure 8-6.
8.14.2 RMII Mode
The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high. RMII
interface operates synchronously from the external 50 MHz reference (REF_CLK). Only 7 signals are required.
The following figure shows the RMII architecture. Note that DCE mode is not supported for RMII mode and RMII
is valid only for full duplex operation.
Figure 8-7 RMII Interface
MAC MII to RMII
PHY RMII to MII
TX_EN
TX_EN
TXD[1:0]
TXD[3:0]
TX_EN
TX_ERR
TXD[3:0]
TX_ERR
TX_CLK
TX_CLK
CRS
RX_CRS
CRS_DV
RX_DV
RX_DV
RXD[1:0]
RXD[3:0]
RX_CRS
REF_CLK
RX_ER
RX_CLK
RX_CLK
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8.14.3 PHY MII Management Block and MDIO Interface
The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block
communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for
data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management
Interface is shown Figure 8-8. The read/write control of the MII Management is accomplished through the indirect
SU.MACMIIA MII Management Address Register and data is passed through the indirect SU.MACMIID Data
Register. These indirect registers are accessed through the MAC Control Registers defined in Table 8-6. The
MDC clock is internally generated and runs at 1.67 MHz.
Figure 8-8 MII Management Frame
Preamble
Start
Opco
de
Phy Adrs
Phy Reg
32 bits
2 bits
2 bits
5 bits
5 bits
Turn
Aroun
d
2 bits
READ
111...111
01
10
PHYA[4:0]
PHYR[4:0]
ZZ
ZZZZZZZZZ
Z
WRITE
111...111
01
01
PHYA[4:0]
PHYR[4:0]
10
PHYD[15:0]
Z
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Data
Idle
16
bits
1
Bit
DS33Z11 Ethernet Mapper
8.15 BERT
The BERT can be used for generation and detection of BERT patterns. The BERT is a software programmable
test pattern generator and monitor capable of meeting most error performance requirements for digital
transmission equipment. The following restrictions are related to the BERT:
•
The RDEN and TDEN are inputs that can be used to “gap” bits.
•
BERT will transmit even when the device is set for X.86 mode and TDEN is configured as an output.
•
The normal traffic flow is halted while the BERT is in operation.
•
If the BERT is enabled for a Serial port, it will override the normal connection.
• If there is a connection overridden by the BERT, when BERT operation is terminated the normal operation is
restored.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream. The receive direction extracts the test pattern payload from the receive data stream, and monitors the test
pattern payload for the programmable test pattern.
BERT Features
•
•
•
•
PRBS and QRSS patterns of 29-1, 215-1 223-1 and QRSS pattern support
Programmable repetitive pattern. The repetitive pattern length and pattern are programmable
(length n = 1 to 32 and pattern = 0 to (2n – 1)).
24-bit error count and 32-bit bit count registers
Programmable bit error insertion. Errors can be inserted individually
8.15.1 Receive Data Interface
8.15.1.1 Receive Pattern Detection
The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the
incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant
bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern
(generating polynomial xn + xy + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n),
the feedback is bit n. The values for n and y are individually programmable (1 to 32). The output of the receive
pattern generator is the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output
is forced to one if the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS
patterns, the feedback is forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern
programmed, pattern detection performs either PRBS synchronization or repetitive pattern synchronization.
8.15.1.2 PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern.
If at least is incoming bits in the current 64-bit window do not match the receive pattern generator, automatic
pattern resynchronization is initiated. Automatic pattern resynchronization can be disabled.
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Figure 8-9 PRBS Synchronization State Diagram
Sync
f6
err
ors
6o
32
ors
err
bi t
sw
ith
th
wi
its
out
4b
1 bit error
Verify
Load
32 bits loaded
8.15.2 Repetitive Pattern Synchronization
Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match
the incoming pattern. If at least sis incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern resynchronization is initiated. Automatic pattern resynchronization can be
disabled.
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Figure 8-10 Repetitive Pattern Synchronization State Diagram
Sync
f6
err
ors
6o
32
ors
err
bi t
sw
ith
th
wi
its
out
4b
1 bit error
Verify
Match
Pattern Matches
8.15.3 Pattern Monitoring
Pattern monitoring monitors the incoming data stream for Out Of Synchronization (OOS) condition, bit errors, and
counts the incoming bits. An OOS condition is declared when the synchronization state machine is not in the
“Sync” state. An OOS condition is terminated when the synchronization state machine is in the “Sync” state.
Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If
they do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the
bit count is incremented. The bit count and bit error count are not incremented when an OOS condition exists.
8.15.4 Pattern Generation
Pattern Generation generates the outgoing test pattern, and passes it onto Error Insertion. The transmit pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial xn + xy + 1), the
feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n
and y are individually programmable. The output of the receive pattern generator is the feedback. If QRSS is
enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros.
QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback is forced to one if bits 1 through
31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a pattern value before pattern
generation starts. The pattern value is programmable (0 – 2n - 1). When PRBS and QRSS patterns are generated
the seed value is all ones.
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8.15.4.1 Error Insertion
Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time Single bit
error insertion can be initiated from the microprocessor interface. If pattern inversion is enabled, the data stream
is inverted before the overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).
8.15.4.2 Performance Monitoring Update
All counters stop counting at their maximum count. A counter register is updated by asserting (low to high
transition) the performance monitoring update signal (PMU). During the counter register update process, the
performance monitoring status signal (PMS) is de-asserted. The counter register update process consists of
loading the counter register with the current count, resetting the counter, forcing the zero count status indication
low for one clock cycle, and then asserting PMS. No events shall be missed during an update procedure.
8.16 Transmit Packet Processor
The Transmit Packet Processor accepts data from the Transmit FIFO, performs bit reordering, FCS processing,
packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The
data output from the Transmit Packet Processor to the Transmit Serial Interface is a serial data stream (bit
synchronous mode). HDLC processing can be disabled (clear channel enable). Disabling HDLC processing
disables FCS processing, packet error insertion, stuffing, packet abort sequence insertion, and inter-frame
padding. Only bit reordering and packet scrambling are not disabled.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the outgoing 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output from the Transmit FIFO with the MSB in
TFD[7] (or 15, 23, or 31) and the LSB in TFD[0] (or 8, 16, or 24) of the transmit FIFO data TFD[7:0] 15:8, 23:16,
or 31:24). If bit reordering is enabled, the outgoing 8-bit data stream DT[1:8] is output from the Transmit FIFO with
the MSB in TFD[0] and the LSB in TFD[7] of the transmit FIFO data TFD[7:0]. In bit synchronous mode, DT [1] is
the first bit transmitted. Bit Reordering can be controlled by address pin A0 in Hardware Mode.
FCS processing calculates an FCS and appends it to the packet. FCS calculation is a CRC-16 or CRC-32
calculation over the entire packet. The polynomial used for FCS-16 is x16 + x12 + x5 + 1. The polynomial used for
FCS-32 is x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1. The FCS is inverted after
calculation. The FCS type is programmable. If FCS append is enabled, the calculated FCS is appended to the
packet. If FCS append is disabled, the packet is transmitted without an FCS. The FCS append mode is
programmable. If packet processing is disabled, FCS processing is not performed.
Packet error insertion inserts errors into the FCS bytes. A single FCS bit is corrupted in each errored packet. The
FCS bit corrupted is changed from errored packet to errored packet. Error insertion can be controlled by a
register or by the manual error insertion input (LI.TMEI.TMEI). The error insertion initiation type (register or input)
is programmable. If a register controls error insertion, the number and frequency of the errors are programmable.
If FCS append is disabled, packet error insertion will not be performed. If packet processing is disabled, packet
error insertion is not performed.
Stuffing inserts control data into the packet to prevent packet data from mimicking flags. A packet start indication
is received, and stuffing is performed until, a packet end indication is received. Bit stuffing consists of inserting a
'0' directly following any five contiguous '1's. If packet processing is disabled, stuffing is not performed.
There is at least one flag plus a programmable number of additional flags between packets. The inter-frame fill
can be flags or all '1's followed by a start flag. If the inter-frame fill is all '1's, the number of '1's between the end
and start flags does not need to be an integer number of bytes, however, there must be at least 15 consecutive
'1's between the end and start flags. The inter-frame padding type is programmable. If packet processing is
disabled, inter-frame padding is not performed.
Packet abort insertion inserts a packet abort sequences as necessary. If a packet abort indication is detected, a
packet abort sequence is inserted and inter-frame padding is done until a packet start flag is detected. The abort
sequence is FFh. If packet processing is disabled, packet abort insertion is not performed.
The packet scrambler is a x43 + 1 scrambler that scrambles the entire packet data stream. The packet scrambler
runs continuously, and is never reset. In bit synchronous mode, scrambling is performed one bit at a time. In byte
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DS33Z11 Ethernet Mapper
synchronous mode, scrambling is performed 8 bits at a time. Packet scrambling is programmable. Note in
Hardware Mode, the scrambling is controlled by A1/SD.
Once all packet processing has been completed serial data stream is passed on to the Transmit Serial Interface.
8.17 Receive Packet Processor
The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling,
packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error
monitoring, FCS byte extraction, and bit reordering. The data coming from the Receive Serial Interface is a serial
data stream. Packet processing can be disabled (clear channel enable). Disabling packet processing disables
packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error
monitoring, and FCS byte extraction. Only packet descrambling and bit reordering are not disabled.
The packet descrambler is a self-synchronous x43 + 1 descrambler that descrambles the entire packet data
stream. Packet descrambling is programmable. The descrambler runs continuously, and is never reset. The
descrambling is performed one bit at a time. Packet descrambling is programmable. If packet processing is
disabled, the serial data stream is demultiplexed in to an 8-bit data stream before being passed on. Note in
Hardware Mode, the scrambling is controlled by A1/SD.
If packet processing is disabled, a packet boundary is arbitrarily chosen and the data is divided into "packets" of
programmable size (dependent on maximum packet size setting). These packets are then passed on to bit
reordering with packet start and packet end indications. Data then bypasses packet delineation, inter-frame fill
filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, and FCS byte extraction.
Packet delineation determines the packet boundary by identifying a packet start or end flag. Each time slot is
checked for a flag sequence (7Eh). Once a flag is found, it is identified as a start/end flag and the packet
boundary is set. The flag check is performed one bit at a time. If packet processing is disabled, packet delineation
is not performed.
Inter-frame fill filtering removes the inter-frame fill between packets. When a packet end flag is detected, all data
is discarded until a packet start flag is detected. The inter-frame fill can be flags or all '1's. The number of '1's
between flags does not need to be an integer number of bytes, and if at least 7 '1's are detected in the first 16 bits
after a flag, all data after the flag is discarded until a start flag is detected. There may be only one flag between
packets. When the inter-frame fill is flags, the flags may have a shared zero (011111101111110). If there is less
than 16 bits between two flags, the data is discarded. If packet processing is disabled, inter-frame fill filtering is
not performed.
Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag,
if an abort sequence is detected, the packet is marked with an abort indication, the aborted packet count is
incremented, and all subsequent data is discarded until a packet start flag is detected. The abort sequence is
seven consecutive ones. If packet processing is disabled, packet abort detection is not performed.
Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. A start
flag is detected, a packet start is set, the flag is discarded, destuffing is performed until an end flag is detected, a
packet end is set, and the flag is discarded. In bit synchronous mode, bit destuffing is performed. Bit destuffing
consists of discarding any '0' that directly follows five contiguous '1's. After destuffing is completed, the serial bit
stream is demultiplexed into an 8-bit parallel data stream and passed on with packet start, packet end, and
packet abort indications. If there is less than eight bits in the last byte, an invalid packet flag is raised, the packet
is tagged with an abort indication, and the packet size violation count is incremented. If packet processing is
disabled, destuffing is not performed.
Packet size checking checks each packet for a programmable maximum and programmable minimum size. As
the packet data comes in, the total number of bytes is counted. If the packet length is below the minimum size
limit, the packet is marked with an aborted indication, and the packet size violation count is incremented. If the
packet length is above the maximum size limit, the packet is marked with an aborted indication, the packet size
violation count is incremented, and all packet data is discarded until a packet start is received. The minimum and
maximum lengths include the FCS bytes, and are determined after destuffing has occurred. If packet processing
is disabled, packet size checking is not performed.
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DS33Z11 Ethernet Mapper
FCS error monitoring checks the FCS and aborts errored packets. If an FCS error is detected, the FCS errored
packet count is incremented and the packet is marked with an aborted indication. If an FCS error is not detected,
the receive packet count is incremented. The FCS type (16-bit or 32-bit) is programmable. If FCS processing or
packet processing is disabled, FCS error monitoring is not performed.
FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the
packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet.
If FCS processing or packet processing is disabled, FCS byte extraction is not performed.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[7]
(or 15, 23, or 31) and the LSB in RFD[0] (or 8, 16, or 24) of the receive FIFO data RFD[7:0] (or 15:8, 23:16, or
31:24). If bit reordering is enabled, the incoming 8-bit data stream DT[1:8] is output to the Receive FIFO with the
MSB in RFD[0] and the LSB in RFD[7] of the receive FIFO data RFD[7:0]. DT[1] is the first bit received from the
incoming data stream. Bit reordering can be controlled by pin A0 in Hardware Mode.
Once all of the packet processing has been completed, The 8-bit parallel data stream is demultiplexed into a 32bit parallel data stream. The Receive FIFO data is passed on to the Receive FIFO with packet start, packet end,
packet abort, and modulus indications. At a packet end, the 32-bit word may contain 1, 2, 3, or 4 bytes of data
depending on the number of bytes in the packet. The modulus indications indicate the number of bytes in the last
data word of the packet.
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DS33Z11 Ethernet Mapper
Figure 8-11 HDLC Encapsulation of MAC Frame
Number of Bytes
Flag(0x7E)
1
Destination Adrs(DA)
6
Source Adrs(SA)
6
Length/Type
2
MAC Client Data
46-1500
PAD
FCS for MAC
4
FCS for HDLC
0/2/4
Flag(0x7E)
MSB
LSB
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DS33Z11 Ethernet Mapper
8.18 X.86 Encoding and Decoding
X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides HDLC type
framing structure for encapsulation of Ethernet frames. LAPS encapsulated frames can be used to send data
onto a SONET/SDH network. The DS33Z11 expects a byte synchronization signal to provide the byte boundary
for the X.86 receiver. This is provided by the RBSYNC pin. The functional timing is shown in Figure 10-4. The
X.86 transmitter provides a byte boundary indicator with the signal TBSYNC. The functional timing is shown in
Figure 10-3. Note that in some cases, additional logic may be required to meet RBSYNC/TBSYNC sychronization
timing requirements when operating in X.86 mode.
Figure 8-12 LAPS Encoding of MAC Frames Concept
IEEE
802.3 MAC Frame
LAPS
Rate Adaption
SDH
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DS33Z11 Ethernet Mapper
Figure 8-13 X.86 Encapsulation of the MAC field
Number of Bytes
Flag(0x7E)
1
Address(0x04)
1
Control(0x03)
1
1st Octect of SAPI(0xfe)
1
2nd Octect of SAPI(0x01)
1
Destination Adrs(DA)
6
Source Adrs(SA)
6
Length/Type
2
MAC Client Data
46-1500
PAD
FCS for MAC
4
FCS for LAPS
4
Flag(0x7E)
MSB
LSB
The DS33Z11 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured
for X.86 mode in the register LI.TX86E. The DS33Z11 provides the following functions:
•
•
•
Control Registers for Address, SAPI, Destination Address, Source Address
32 bit FCS enabled
Programmable X43+1 scrambling
The sequence of processing performed by the receiver is as follows:
•
•
•
•
•
•
•
Programmable octets X43+1 descrambling
Detect the Start Flag (7E)
Remove Rate adaptation octets 7D, DD.
Perform transparency-processing 7D, 5E is converted to 7E and 7D, 5D is converted to 7D.
Check for a valid Address, Control and SAPI fields (LI.TRX86A to LI.TRX86SAPIL)
Perform FCS checking
Detect the closing flag.
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The X86 received frame is aborted if:
•
•
•
•
•
If 7D,7E is detected. This is an abort packet sequence in X.86
Invalid FCS is detected
The received frame has less than 6 octets
Control, SAPI and address field are mismatched to the programmed value
Octet 7D and octet other than 5D, 5E, 7E, or DD is detected
For the transmitter if X.86 is enabled the sequence of processing is as follows:
•
•
•
•
•
Construct frame including start flag SAPI, Control and MAC frame
Calculate FCS
Perform transparency processing - 7E is translated to 7D5E, 7D is translated to 7D5D
Append the end flag(7E)
Scramble the sequence X43+1
Note that the Serial transmit and receive registers apply to the X.86 implementations with specific exceptions. The
exceptions are outlined in the Serial Interface transmit and receive register sections.
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8.19 Committed Information Rate Controller
The DS33Z11 provides a CIR provisioning facility. The CIR can be used restricts the transport of received MAC
data to a programmable rate. This is shown in Figure 8-14. The CIR will restrict the data flow from the Receive
MAC to Transmit HDLC. This can be used for provisioning and billing functions towards the WAN. The user must
set the CIR register to control the amount of data throughput from the MAC to HDLC transmit. The CIR register is
in granularity of 500 kbps with a range of 0 to 52 Mbps. The operation of the CIR is as follows:
•
The CIR block counts the credits that are accumulated at the end of every 125 ms
•
If data is received and stored in the SDRAM to be sent to the Serial Interface, the interface will request
the data if there is a positive credit balance. If the credit balance is negative, transmit interface does not
request data
•
New credit balance is calculated credit balance = old credit balance – frame size in bytes after the frame
is sent
•
The credit balance is incremented every 125 milliseconds by CIR/8
•
Credit balances not used in 250 milliseconds are reset to 0
•
The maximum value of CIR can not exceed the transmit line rate
•
If the data rate received from the Ethernet interface is higher than the CIR, the receive queue buffers will
fill and the high threshold watermark will invoke flow control to reduce the incoming traffic rate.
•
The CIR function is only available for software mode of operation only
•
CIR function is only available in data received at the Ethernet Interface to be sent to WAN. There is not
CIR functionality for data arriving from the WAN to be sent to the Ethernet Interface
•
Negative credits are not allowed, if there is not a credit balance, no frames are sent until there is a credit
balance again.
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DS33Z11 Ethernet Mapper
Figure 8-14 CIR in the WAN Transmit Path
Eprom
SPI_SCLK (max 8.33Mhz)
Buffer
Dev
Div by 1,2,4,10
Output clocks:
50,25 Mhz,2.5 Mhz
50 or 25 Mhz Oscillator
REF_CLK
TSER
TCLKI1
Line 1
RCLKI1
RSER
HDLC
+
Serial
Interface
TX_CLK1
CIR
MAC
RMII
MII
Arbiter
X.86
RXD
RX_CLK1
TXD
MDC
Buffer Dev
Div by 2,4,12
Output Clocks
25,50
Mhz
SDRAM
Interface
SDCLKO
REF_CLKO
50 or 25 Mhz
SDRAM
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100 Mhz Oscillator
SYSCLKI
DS33Z11 Ethernet Mapper
8.20 Hardware Mode
The hardware mode settings are provided for users who do not want to utilize a Microprocessor or EEPROM. The
hardware mode default queue sizes and watermark thresholds can be selected for various line rates using the
MODEC pins. The user can control the DTE/DCE and RMII/MII settings with hardware pins DCEDTES, and
RMIIMIIS. The flow control (pause and back pressure) can be configured with the AFCS hardware pins. The user
can also control bit order, data scrambling, and X.86 encapsulation using the A0, A1, and A2 pins respectively.
Half-Duplex operation is not available in hardware mode. Note that in the 100-pin CSBGA package option
(DS33ZH11), three pins are reserved for these three signals in future package revisions, but may not be included
in the current version. Contact the factory at www.maxim-ic.com/support for more details.
The DS33Z11 has 3 different default hardware settings. This is outlined in the following tables. The typical
applications for each of the Hardware Modes are outlined in following tables. Note that in the hardware only mode
the following restrictions apply:
•
The ports are powered up and ready to transmit/receive after reset
•
BERT functionality is not supported in Hardware Mode.
•
Queue size and watermarks are fixed
•
Receive and Transmit HDLC FCS are 16 bits
•
Transmit Packets are resent if errors occur, Receive Packets are rejected if errors occur
•
MII, RMII, Full and Half Duplex, Automatic flow control, DTE, DCE, 100 or 10 Mbps can be selected
through Hardware Pins
•
TDEN and RDEN are not supported and should be tied high
•
CIR function is not supported in Hardware Mode.
Table 8-8 Hardware Mode and Typical Applications
Modec Pin Settings
Applications
00
Serial Interface connected to a T1/E1 Line, Ethernet Interface set to
10 Mbps or 100 Mbps MII/RMII.
Transmitter and receiver are enabled for communication.
10
Serial Interface connected to a T3/E3 line, Ethernet Interface set to 10
Mbps or 100 Mbps MII/RMII.
Transmitter and receiver are enabled for communication.
The specific registers and detailed functions for each of the hardware modes are detailed in the following tables.
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DS33Z11 Ethernet Mapper
Table 8-9 Specific Functional Default Values for Hardware Mode
Functional Block
Register Reference
Default Value in
Hardware Mode
Description
Global
Connection between Serial and
Ethernet Interfaces
GL.CON1
0000 0001b
Connection established for Serial 1 to Ethernet 1.
Transmit Serial Interface
Configuration
LI.TSLCR
0000 0000b
Transmit Data enable is not supported and should be
tied high. The user must provide gapped clocks to mask
bits if needed. The Transmit Serial data will output on
the rising edge of TCLKI1-4.
Serial Interface Reset and
Power-down
LI.RSTPD
0000 0000b
In default hardware mode the Serial Interface
Transmitter is powered up and ready to go.
Transmit FCS
LI.TPPCL
0001 0000b*
FCS is set to 16 bits for the HDLC Transmitter.
Serial Data
Transmit Inter Frame Gap
LI.TIFGC
0000 0001b
Transmit inter frame gap is one byte. The value is 7E.
Receive FCS
LI.RPPCL
0001 0000b*
Receive HDLC FCS is set to 16 bits. Receive
scrambling and bit ordering controlled by hardware pins
Receive Maximum Packet
Length
LI.RMPSC
2016 bytes
The receive maximum packet length is set to 2016
bytes not including the HDLC FCS.
Receive Serial Port
Configuration
LI.RSLCR
0000 0000b
Receive RDEN enable will not be supported and should
be tied high. The Received data is sampled on the
falling edge and gapped clock is supported.
Transmit packet Resend
Criteria
SU.TFRC
0000 0000b
Any error: Jabber timeout, Loss of carrier, Excessive
deferral, Late collision, Excessive collisions, Under run,
collision, deferred, heartbeat fail will result in resending
of packets
Receive Packet Rejection
Control
SU.RFRC
0000 0000b
Broadcast frames, Control frames, and Errored packets
are rejected.
Receiver Maximum Frame Size
SU.RMFSRH
0000 0111
SU.RMFSRL
1110 0000b
The maximum receiver packet size is 2016 bytes
including the MAC FCS. Any packet larger that 2016 is
rejected
SU.MACCR
0000 0000
(MSB to LSB)
Any packets greater than 2016 bytes are rejected.
Ethernet
MAC Control Register
0001 0100
0000 0000
0000 1100b*
MAC Flow Control Register
SU.MACFCR
0000 0001
Flow control is determined by the AFCS pin.
0100 0000
Pause Timer = 320 (140h) Slots
0000 0000
(MSB to LSB)
0000 0000b*
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DS33Z11 Ethernet Mapper
Functional Block
Register Reference
Default Value in
Hardware Mode
Description
Queue Size and thresholds
Transmit Queue Size
AR.TQSC1
0001 0100b
640 packets, Modec[1:0] = 00
AR.TQSC1
0001 1000b
768 packets, Modec[1:0] = 10
LI.TQHT
0000 1100b
384 packets, Modec[1:0] = 00
LI.TQHT
0000 1100b
384 packets, Modec[1:0] = 10
LI.TQLT
0000 0110b
192 packets*, Modec[1:0] = 00
LI.TQLT
0000 0110b
192 packets*, Modec[1:0] = 10
Receive Queue Size
AR.RQSC1
0010 1100b
1408 packets*, Modec[1:0] = 00
AR.RQSC1
0010 1000b
1280 packets*, Modec[1:0] = 10
Receive Queue Low Threshold
SU.RQLT
0000 1111b
480 packets*, Modec[1:0] = 00
SU.RQLT
0000 1100b
384 packets*, Modec[1:0] = 10
SU.RQHT
0001 1110b
960 packets*, Modec[1:0] = 00
SU.RQHT
0001 1000b
768 packets*, Modec[1:0] = 10
Transmit Queue High Threshold
Transmit Queue Low Threshold
Receive Queue High Threshold
* The default values for these registers are different than in the Software mode.
Note: The RMIIMIIS, FULLDS, and H10S pins are internally connected in the 100 pin CSBGA (DS33ZH11)
package option, and are unavailable for user configuration.
Note: Each “packet” above is 2048 bytes.
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DS33Z11 Ethernet Mapper
Table 8-10 Hardware Mode Pins
PIN
HARDWARE MODE FUNCTION
HWMODE
0 = Hardware Mode disabled.
1 = Hardware Mode enabled.
Select the hardware mode default settings.
MODEC[1:0]
RMIIMIIS
0 = MII Operation.
1 = RMII operation.
Note that this pin is internally tied low in the 100 pin
CSBGA (DS33ZH11) package option.
DCEDTES
1 = DCE Operation
0 = DTE Operation
Must be set to 1 for proper operation (Full Duplex).
FULLDS
Note that this pin is internally tied high in the 100 pin
CSBGA (DS33ZH11) package option.
A2/X86ED
A1/SCD
A0/BREO
0 = X.86 mode is disabled.
1 = X.86 mode is enabled for transmit and receive.
0 = X43+1 scrambling/descrambling is enabled.
1 = X43+1 scrambling/descrambling is disabled.
0 = HDLC transmit and receive bits are normal. The
MSB is transmitted and received first.
1 = HDLC transmit and receive bits are reversed. The
LSB is transmitted and received first.
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9
DEVICE REGISTERS
Ten address lines are used to address the register space. Table 9-1 shows the register map for the DS33Z11 is
shown in. The addressable range for the device is 0000h to 08FFh. Each register section is 64 bytes deep.
Global Registers are preserved for software compatibility with multiport devices. The Serial Interface (Line)
Registers are used to configure the serial port and the associated transport protocol. The Ethernet Interface
(Subscriber) registers are used to control and observe each of the Ethernet ports. The registers associated with
the MAC must be configured through indirect register write /read access due to the architecture of the device.
When writing to a register input values for unused bits and registers (those designated with “-“) should be zero, as
these bits and registers are reserved. When a register is read from, the values of the unused bits and registers
should be ignored. A latched status bit is set when an event happens and is cleared when read.
The register details are provided in the following tables.
Table 9-1 Register Address Map
Global Registers
0000h – 003Fh
Port 1
Arbiter
0040h – 007Fh
-
-
BERT
0080h – 00BFh
-
Unused address space: 180h - 7FFh
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Serial Interface
Ethernet
Interface
-
-
00C0h – 013Fh
0140h – 017Fh
DS33Z11 Ethernet Mapper
9.1
Register Bit Maps
Table 9-2, Table 9-3, Table 9-4, Table 9-5, Table 9-6, and Table 9-7 contain the registers of the DS33Z11. Bits
that are reserved are noted with a single dash “-“. All registers not listed are reserved and should be initialized
with a value of 00h for proper operation, unless otherwise noted.
9.1.1
Global Register Bit Map
Table 9-2 Global Register Bit Map
Name
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDR
00h
GL.IDRL
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
01h
GL.IDRH
ID15
ID14
ID13
ID12
ID11
ID10
ID09
ID08
02h
GL.CR1
-
-
-
-
-
REF_CLKO
INTM
RST
03h
GL.BLR
-
-
-
-
-
-
-
GL.BLC1
04h
GL.RTCAL
-
-
-
RLCALS1
-
-
-
TLCALS1
05h
GL.SRCALS
-
-
-
-
-
-
REFCLKS
SYSCLS
06h
GL.LIE
-
-
-
LIN1TIE
-
-
-
LIN1RIE
07h
GL.LIS
-
-
-
LIN1TIS
-
-
-
LIN1RIS
08h
GL.SIE
-
-
-
-
-
-
-
SUB1IE
09h
GL.SIS
-
-
-
-
-
-
-
SUB1IS
0Ah
GL.TRQIE
-
-
-
TQ1IE
-
-
-
RQ1IE
0Bh
GL.TRQIS
-
-
-
TQ1IS
-
-
-
RQ1IS
0Ch
GL.BIE
-
-
-
-
-
-
-
BIE
0Dh
GL.BIS
-
-
-
-
-
-
-
BIS
0Eh
GL.CON1
-
-
-
-
-
-
-
LINE0
0Fh
Reserved
-
-
-
-
-
-
-
-
10h
Reserved
-
-
-
-
-
-
-
-
11h
Reserved
-
-
-
-
-
-
-
-
12h
GL.C1QPR
-
-
-
-
C1MRPRR
C1HWPRR
C1MHPR
C1HRPR
13h
Reserved
-
-
-
-
-
-
-
-
14h
Reserved
-
-
-
-
-
-
-
-
15h
Reserved
-
-
-
-
-
-
-
-
20h
GL.BISTEN
-
-
-
-
-
-
-
BISTE
21h
GL.BISTPF
-
-
-
-
-
-
BISTDN
BISTPF
03Ah
GL.SDMODE1
-
-
-
-
WT
BL2
BL1
BL0
03Bh
GL.SDMODE2
-
-
-
-
-
LTMOD2
LTMOD1
LTMOD0
03Ch
GL.SDMODEWS
-
-
-
-
-
-
-
SDMW
03Dh
GL.SDRFTC
SREFT7
SREFT6
SREFT5
SREFT4
SREFT3
SREFT2
SREFT1
SREFT0
All address locations not listed are reserved.
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DS33Z11 Ethernet Mapper
9.1.2
Arbiter Register Bit Map
Table 9-3 Arbiter Register Bit Map
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDR
40h
AR.RQSC1
RQSC7
RQSC6
RQSC5
RQSC4
RQSC3
RQSC2
RQSC1
RQSC0
41h
AR.TQSC1
TQSC7
TQSC6
TQSC5
TQSC4
TQSC3
TQSC2
TQSC1
TQSC0
9.1.3
BERT Register Bit Map
Table 9-4 BERT Register Bit Map
ADDR NAME
080h BCR
081h Reserved
082h BPCLR
083h BPCHR
084h BSPB0R
085h BSPB1R
086h BSPB2R
087h BSPB3R
088h TEICR
08Ah Reserved
08Bh Reserved
08Ch BSR
08Dh Reserved
08Eh BSRL
08Fh Reserved
90h BSRIE
91h Reserved
92h Reserved
93h Reserved
94h RBECB0R
95h RBECB1R
96h RBECB2R
97h Reserved
98h RBCB0
99h RBCB1
9Ah RBCB2
9Bh RBCB3
9Ch Reserved
9Dh Reserved
9Eh Reserved
9Fh Reserved
BIT 7
BSP7
BSP15
BSP23
BSP31
BEC7
BEC15
BEC23
BC7
BC15
BC23
BC31
-
BIT 6
PMU
QRSS
BSP6
BSP14
BSP22
BSP30
BEC6
BEC14
BEC22
BC6
BC14
BC22
BC30
-
BIT 5
BIT 4
RNPL
PTS
BSP5
BSP13
BSP21
BSP29
TIER2
BEC5
BEC13
BEC21
BC5
BC13
BC21
BC29
-
RPIC
PLF4
PTF4
BSP4
BSP12
BSP20
BSP28
TIER1
BEC4
BEC12
BEC20
BC4
BC12
BC20
BC28
-
68 of 172
BIT 3
MPR
PLF3
PTF3
BSP3
BSP11
BSP19
BSP27
TIER0
PMS
PMSL
PMSIE
BEC3
BEC11
BEC19
BC3
BC11
BC19
BC27
-
BIT 2
APRD
PLF2
PTF2
BSP2
BSP10
BSP18
BSP26
BEI
BEL
BEIE
BEC2
BEC10
BEC18
BC2
BC10
BC18
BC26
-
BIT 1
TNPL
PLF1
PTF1
BSP1
BSP9
BSP17
BSP25
TSEI
BEC
BECL
BECIE
BEC1
BEC9
BEC17
BC1
BC9
BC17
BC25
-
BIT 0
TPIC
PLF0
PTF0
BSP0
BSP8
BSP16
BSP24
OOS
OOSL
OOSIE
BEC0
BEC8
BEC16
BC0
BC8
BC16
BC24
-
DS33Z11 Ethernet Mapper
9.1.4
Serial Interface Register Bit Map
Table 9-5 Serial Interface Register Bit Map
ADDR NAME
0C0h LI.TSLCR
0C1h LI.RSTPD
0C2h LI.LPBK
0C3h Reserved
0C4h LI.TPPCL
0C5h LI.TIFGC
0C6h LI.TEPLC
0C7h LI.TEPHC
0C8h LI.TPPSR
0C9h LI.TPPSRL
0CAh LI.TPPSRIE
0CBh Reserved
0CCh LI.TPCR0
0CDh LI.TPCR1
0CEh LI.TPCR2
0CFh Reserved
0D0h LI.TBCR0
0D1h LI.TBCR1
0D2h LI.TBCR2
0D3h LI.TBCR3
0D4h LI.TMEI
0D5h Reserved
0D6h LI.THPMUU
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TIFG7
TPEN7
MEIMS
TPC7
TPC15
TPC23
TBC7
TBC15
TBC23
TBC31
-
TIFG6
TPEN6
TPER6
TPC6
TPC14
TPC22
TBC6
TBC14
TBC22
TBC30
-
TFAD
TIFG5
TPEN5
TPER5
TPC5
TPC13
TPC21
TBC5
TBC13
TBC21
TBC29
-
TF16
TIFG4
TPEN4
TPER4
TPC4
TPC12
TPC20
TBC4
TBC12
TBC20
TBC28
-
TIFV
TIFG3
TPEN3
TPER3
TPC3
TPC11
TPC19
TBC3
TBC11
TBC19
TBC27
-
TSD
TIFG2
TPEN2
TPER2
TPC2
TPC10
TPC18
TBC2
TBC10
TBC18
TBC26
-
RESET
TBRE
TIFG1
TPEN1
TPER1
TPC1
TPC9
TPC17
TBC1
TBC9
TBC17
TBC25
-
TDENPLT
QLP
TIFG0
TPEN0
TPER0
TEPF
TEPFL
TEPFIE
TPC0
TPC8
TPC16
TBC0
TBC8
TBC16
TBC24
TMEI
-
-
-
-
-
-
-
-
TPMUU
-
-
-
-
-
-
TPMUS
-
-
-
-
-
-
X86ED
X86TRA6
X86TRC6
TRSAPIH6
TRSAPIL6
CIR6
RMX6
RMX14
RAPL
RAPIE
X86TRA5
X86TRC5
TRSAPIH5
TRSAPIL5
CIR5
RFPD
RMX5
RMX13
RIPDL
RIPDIE
X86TRA4
X86TRC4
TRSAPIH4
TRSAPIL4
CIR4
RF16
RMX4
RMX12
RSPDL
RSPDIE
X86TRA3
X86TRC3
TRSAPIH3
TRSAPIL3
CIR3
RFED
RMX3
RMX11
RLPDL
RLPDIE
X86TRA2
X86TRC2
TRSAPIH2
TRSAPIL2
CIR2
RDD
RMX2
RMX10
REPC
REPCL
REPCIE
X86TRA1
X86TRC1
TRSAPIH1
TRSAPIL1
CIR1
RBRE
RMX1
RMX9
RAPC
RAPCL
RAPCIE
X86TRA0
X86TRC0
TRSAPIH0
TRSAPIL0
CIR0
RDENPLT
RCCE
RMX0
RMX8
RSPC
RSPCL
RSPCIE
RPC6
RPC14
RPC22
RPC5
RPC13
RPC21
RPC4
RPC12
RPC20
RPC3
RPC11
RPC19
RPC2
RPC10
RPC18
RPC1
RPC09
RPC17
RPC0
RPC08
RPC16
0D7h
LI.THPMUS
-
0D8h
LI.TX86EDE
-
0D9h
0DAh
0DBh
0DCh
0DDh
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
LI.TRX86A
X86TRA7
X86TRC7
LI.TRX86SAPIH TRSAPIH7
LI.TRX86SAPIL TRSAPIL7
CIRE
LI.CIR
LI.RSLCR
LI.RPPCL
RMX7
LI.RMPSCL
RMX15
LI.RMPSCH
LI.RPPSR
REPL
LI.RPPSRL
REPIE
LI.RPPSRIE
Reserved
RPC7
LI.RPCB0
RPC15
LI.RPCB1
RPC23
LI.RPCB2
LI.TRX8C
LI.RFPCB0
RFPC7
RFPC6
RFPC5
RFPC4
RFPC3
RFPC2
RFPC1
RFPC0
LI.RFPCB1
RFPC15
RFPC23
RFPC14
RFPC22
RFPC13
RFPC21
RFPC12
RFPC20
RFPC11
RFPC19
RFPC10
RFPC18
RFPC9
RFPC17
RFPC8
RFPC16
RAPC7
RAPC15
RAPC23
RAPC6
RAPC14
RAPC22
RAPC5
RAPC13
RAPC21
RAPC4
RAPC12
RAPC20
RAPC3
RAPC11
RAPC19
RAPC2
RAPC10
RAPC18
RAPC1
RAPC9
RAPC17
RAPC0
RAPC8
RAPC16
LI.RFPCB2
Reserved
LI.RAPCB0
LI.RAPCB1
LI.RAPCB2
69 of 172
DS33Z11 Ethernet Mapper
ADDR NAME
113h Reserved
114h LI.RSPCB0
115h LI.RSPCB1
116h LI.RSPCB2
118h LI.RBC0
119h LI.RBC1
11Ah LI.RBC2
11Bh LI.RBC3
11Ch LI.RAC0
11Dh LI.RAC1
11Eh LI.RAC2
11Fh LI.RAC3
120h LI.RHPMUU
121h
LI.RHPMUS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RSPC7
RSPC15
RSPC23
RBC7
RBC15
RBC23
RBC31
REBC7
REBC15
REBC23
REBC31
RSPC6
RSPC14
RSPC22
RBC6
RBC14
RBC22
RBC30
REBC6
REBC14
REBC22
REBC30
RSPC5
RSPC13
RSPC21
RBC5
RBC13
RBC21
RBC29
REBC5
REBC13
REBC21
REBC29
RSPC4
RSPC12
RSPC20
RBC4
RBC12
RBC20
RBC28
REBC4
REBC12
REBC20
REBC28
RSPC3
RSPC11
RSPC19
RBC3
RBC11
RBC19
RBC27
REBC3
REBC11
REBC19
REBC27
RSPC2
RSPC10
RSPC18
RBC2
RBC10
RBC18
RBC26
REBC2
REBC10
REBC18
REBC26
RSPC1
RSPC9
RSPC17
RBC1
RBC9
RBC17
RBC25
REBC1
REBC9
REBC17
REBC25
RSPC0
RSPC8
RSPC16
RBC0
RBC8
RBC16
RBC24
REBC0
REBC8
REBC16
REBC24
-
-
-
-
-
-
-
RPMUU
-
-
-
-
-
-
-
RPMUUS
TQLT5
TQHT5
-
TQLT4
TQHT4
-
CNE
CNE3LIM
TQLT1
TQHT1
TQHTIE
TQHTLS
ANE
ANE4IM
TQLT0
TQHT0
TQLTIE
TQLTLS
122h LI.RX86S
123h LI.RX86LSIE
TQLT7
TQLT6
124h LI.TQLT
TQHT7
TQHT6
125h LI.TQHT
126h LI.TQTIE
127h LI.TQCTLS
0DEh – 0FFh, 128h – 13Fh are reserved.
70 of 172
SAPIHNE
SAPILNE
SAPINE01IM
SAPINEFEIM
TQLT3
TQHT3
TFOVFIE
TFOVFLS
TQLT2
TQHT2
TQOVFIE
TQOVFLS
DS33Z11 Ethernet Mapper
9.1.5
Ethernet Interface Register Bit Map
Table 9-6 Ethernet Interface Register Bit Map
BIT 7
ADDR NAME
MACRA7
140h SU.MACRADL
MACRA15
SU.MACRADH
141h
MACRD7
142h SU.MACRD0
MACRD15
SU.MACRD1
143h
MACRD23
144h SU.MACRD2
MACRD31
SU.MACRD3
145h
MACWD7
SU.MACWD0
146h
MACWD15
SU.MACWD1
147h
MACWD23
148h SU.MACWD2
MACD31
SU.MACWD3
149h
MACAW
7
SU.MACAWL
14Ah
MACAW
15
SU.MACAWH
14Bh
14Ch SU.MACRWC
RESERVED
14Eh
SU.LPBK
14Fh
SU.GCR
150h
SU.TFRC
151h
UR
SU.TFSL
152h
PR
153h SU.TFSH
FL7
SU.RFSB0
154h
RF
155h SU.RFSB1
SU.RFSB2
156h
MF
SU.RFSB3
157h
RMPS7
158h SU.RMFSRL
RMPS15
SU.RMFSRH
159h
RQLT7
15Ah SU.RQLT
RQHT7
SU.RQHT
15Bh
15Ch SU.QRIE
SU.QCRLS
15Dh
SU.RFRC
15Eh
15Fh – 17Fh are reserved.
BIT 6
BIT 5
MACRA6
MACRA14
MACRD6
MACRD14
MACRD22
MACRD30
MACWD6
MACWD14
MACWD22
MACD30
MACAW 6
MACAW 14
EC
HBF
FL6
WT
RMPS6
RMPS14
RQLT6
RQHT6
UCFR
MACRA5
MACRA13
MACRD5
MACRD13
MACRD21
MACRD29
MACWD5
MACWD13
MACWD21
MACD29
MACAW 5
MACAW 13
LC
CC3
FL5
FL13
CRCE
RMPS5
RMPS13
RQLT5
RQHT5
CFRR
BIT 4
MACRA4
MACRA12
MACRD4
MACRD12
MACRD20
MACRD28
MACWD4
MACWD12
MACWD20
MACD28
MACAW4
MACAW12
ED
CC2
FL4
FL12
DB
BF
RMPS4
RMPS12
RQLT4
RQHT4
LERR
71 of 172
BIT 3
MACRA3
MACRA11
MACRD3
MACRD11
MACRD19
MACRD27
MACWD3
MACWD11
MACWD19
MACD27
MACAW3
MACAW11
CRCS
NCFQ
LOC
CC1
FL3
FL11
MIIE
MCF
RMPS3
RMPS11
RQLT3
RQHT3
RFOVFIE
RFOVFLS
CRCERR
BIT 2
MACRA2
MACRA10
MACRD2
MACRD10
MACRD18
MACRD26
MACWD2
MACWD10
MACWD18
MACD26
MACAW2
MACAW10
H10S
TPDFCB
NOC
CC0
FL2
FL10
FT
UF
RMPS2
RMPS10
RQLT2
RQHT2
RQVFIE
RQOVFLS
DBR
BIT 1
MACRA1
MACRA09
MACRD1
MACRD9
MACRD17
MACRD25
MACWD1
MACWD09
MACWD17
MACD25
MACAW1
MACAW9
MCRW
ATFLOW
TPRHBC
LCO
FL1
FL9
CS
CF
RMPS1
RMPS09
RQLT1
RQHT1
RQLTIE
RQHTLS
MIIER
BIT 0
MACRA0
MACRA08
MACRD0
MACRD8
MACRD16
MACRD24
MACWD0
MACWD08
MACWD16
MACD24
MACAW0
MACAW8
MCS
QLP
JAME
TPRCB
FABORT
DEF
Fl0
Fl8
FTL
LE
RMPS0
RMPS08
RQLT0
RQHT0
RQHTIE
RQLTLS
BFR
DS33Z11 Ethernet Mapper
9.1.6
MAC Register Bit Map
Table 9-7 MAC Indirect Register Bit Map
ADDR
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
100h
101h
102h
103h
10Ch
10Dh
10Eh
10Fh
NAME
SU.MACCR
31:24
23:16
15:8
7:0
SU.MACAH
31:24
23:16
15:8
7:0
SU.MACAL
31:24
23:16
15:8
7:0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SU.MACMIIA
31:24
23:16
15:8
7:0
SU.MACMIID
31:24
23:16
15:8
7:0
SU.MACFCR
31:24
23:16
15:8
7:0
SU.MMCCTRL
31:24
23:16
15:8
7:0
RESERVED –
initialize to FF
RESERVED –
initialize to FF
RESERVED –
initialize to FF
RESERVED –
initialize to FF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
HDB
PS
Reserved
Reserved
Reserved
DRO
Reserved
BOLMT1
OML1
Reserved
BOLMT0
OML0
Reserved
DC
F
LCC
Reserved
PM
Reserved
TE
PAM
DRTY
RE
Reserved
Reserved
Reserved
Reserved
ASTP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PADR47
PADR39
Reserved
PADR46
PADR38
Reserved
PADR45
PADR37
Reserved
PADR44
PADR36
Reserved
PADR43
PADR35
Reserved
PADR42
PADR34
Reserved
PADR41
PADR33
Reserved
PADR40
PADR32
PADR31
PADR30
PADR29
PADR28
PADR27
PADR26
PADR25
PADR24
PADR23
PADR15
PADR07
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PADR22
PADR14
PADR06
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PADR21
PADR13
PADR05
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PADR20
PADR12
PADR04
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PADR19
PADR11
PADR03
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PADR18
PADR10
PADR02
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PADR17
PADR09
PADR01
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PADR16
PADR08
PADR00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PHYA4
MIIA1
Reserved
PHYA3
MIIA0
Reserved
PHYA2
Reserved
Reserved
PHYA1
Reserved
Reserved
PHYA0
Reserved
Reserved
MIIA4
Reserved
Reserved
MIIA3
MIIW
Reserved
MIIA2
MIIB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MIID15
MIID07
Reserved
MIID14
MIID06
Reserved
MIID13
MIID05
Reserved
MIID12
MIID04
Reserved
MIID11
MIID03
Reserved
MIID10
MIID02
Reserved
MIID09
MIID01
Reserved
MIID08
MIID00
PT15
PT14
PT13
PT12
PT11
PT10
PT09
PT08
PT07
Reserved
Reserved
PT06
Reserved
Reserved
PT05
Reserved
Reserved
PT04
Reserved
Reserved
PT03
Reserved
Reserved
PT02
Reserved
PCF
PT01
Reserved
FCE
PT00
Reserved
FCB
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MXFRM4
Reserved
Reserved
MXFRM3
Reserved
MXFRM10
MXFRM2
Reserved
MXFRM9
MXFRM1
Reserved
MXFRM8
MXFRM0
Reserved
MXFRM7
Reserved
Reserved
MXFRM6
Reserved
Reserved
MXFRM5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
72 of 172
DS33Z11 Ethernet Mapper
ADDR
110h
111h
112h
113h
200h
201h
202h
203h
204h
205h
206h
207h
300h
301h
302h
303h
308h
309h
30Ah
30Bh
30Ch
30Dh
30Eh
30Fh
334h
335h
336h
337h
338h
339h
33Ah
33Bh
NAME
RESERVED –
initialize to FF
RESERVED –
initialize to FF
RESERVED –
initialize to FF
RESERVED –
initialize to FF
SU.RxFrmCtr
31:24
23:16
15:8
7:0
SU.RxFrmOKCtr
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RXFRMC31 RXFRMC30 RXFRMC29 RXFRMC28 RXFRMC27 RXFRMC26 RXFRMC25 RXFRMC24
RXFRMC23 RXFRMC22 RXFRMC21 RXFRMC20 RXFRMC19 RXFRMC18 RXFRMC17 RXFRMC16
RXFRMC15 RXFRMC14 RXFRMC13 RXFRMC12 RXFRMC11 RXFRMC10 RXFRMC9 RXFRMC8
RXFRMC7 RXFRMC6 RXFRMC5 RXFRMC4 RXFRMC3 RXFRMC2 RXFRMC1 RXFRMC0
RXFRMOK31
RXFRMOK30
RXFRMOK29
RXFRMOK28
RXFRMOK27
RXFRMOK26
RXFRMOK25
RXFRMOK24
RXFRMOK23
RXFRMOK22
RXFRMOK21
RXFRMOK20
RXFRMOK19
RXFRMOK18
RXFRMOK17
RXFRMOK16
15:8
RXFRMOK15
RXFRMOK14
RXFRMOK13
RXFRMOK12
RXFRMOK11
RXFRMOK10
RXFRMOK9
RXFRMOK8
7:0
RXFRMOK7
RXFRMOK6
RXFRMOK5
RXFRMOK4
RXFRMOK3
RXFRMOK2
RXFRMOK1
RXFRMOK0
SU.TxFrmCtr
TXFRMC31
TXFRMC30
TXFRMC29
TXFRMC28
TXFRMC27
TXFRMC26
TXFRMC25
TXFRMC24
23:16
TXFRMC23
TXFRMC22
TXFRMC21
TXFRMC20
TXFRMC19
TXFRMC18
TXFRMC17
TXFRMC16
15:8
TXFRMC15
TXFRMC14
TXFRMC13
TXFRMC12
TXFRMC11
TXFRMC10
TXFRMC9
TXFRMC8
7:0
TXFRMC7
TXFRMC6
TXFRMC5
TXFRMC4
TXFRMC3
TXFRMC2
TXFRMC1
TXFRMC0
SU.TxBytesCtr
TXBYTEC31
TXBYTEC30
TXBYTEC29
TXBYTEC28
TXBYTEC27
TXBYTEC26
TXBYTEC25
TXBYTEC24
23:16
TXBYTEC23
TXBYTEC22
TXBYTEC21
TXBYTEC20
TXBYTEC19
TXBYTEC18
TXBYTEC17
TXBYTEC16
15:8
TXBYTEC15
TXBYTEC14
TXBYTEC13
TXBYTEC12
TXBYTEC11
TXBYTEC10
TXBYTEC9
TXBYTEC8
7:0
TXBYTEC7
TXBYTEC6
TXBYTEC5
TXBYTEC4
TXBYTEC3
TXBYTEC2
TXBYTEC1
TXBYTEC0
31:24
23:16
SU.TxBytesOkCtr TXBYTEOK31 TXBYTEOK30 TXBYTEOK29 TXBYTEOK28 TXBYTEOK27 TXBYTEOK26 TXBYTEOK25 TXBYTEOK24
23:16
15:8
TXBYTEOK23 TXBYTEOK22 TXBYTEOK21 TXBYTEOK20 TXBYTEOK19 TXBYTEOK18 TXBYTEOK17 TXBYTEOK16
TXBYTEOK15 TXBYTEOK14 TXBYTEOK13 TXBYTEOK12 TXBYTEOK11 TXBYTEOK10 TXBYTEOK9
TXBYTEOK8
7:0
TXBYTEOK7
TXBYTEOK6
TXBYTEOK5
TXBYTEOK4
TXBYTEOK3
TXBYTEOK2
TXBYTEOK1
TXBYTEOK0
SU.TxFrmUndr
TXFRMU31
TXFRMU30
TXFRMU29
TXFRMU28
TXFRMU27
TXFRMU26
TXFRMU25
TXFRMU24
23:16
TXFRMU23
TXFRMU22
TXFRMU21
TXFRMU20
TXFRMU19
TXFRMU18
TXFRMU17
TXFRMU16
15:8
TXFRMU15
TXFRMU14
TXFRMU13
TXFRMU12
TXFRMU11
TXFRMU10
TXFRMU9
TXFRMU8
7:0
TXFRMU7
TXFRMU6
TXFRMU5
TXFRMU4
TXFRMU3
TXFRMU2
TXFRMU1
TXFRMU0
TXFRMBD31
TXFRMBD30
TXFRMBD29
TXFRMBD28
TXFRMBD27
TXFRMBD26
TXFRMBD25
TXFRMBD24
23:16
TXFRMBD23
TXFRMBD22
TXFRMBD21
TXFRMBD20
TXFRMBD19
TXFRMBD18
TXFRMBD17
TXFRMBD16
15:8
TXFRMBD15
TXFRMBD14
TXFRMBD13
TXFRMBD12
TXFRMBD11
TXFRMBD10
TXFRMBD9
TXFRMBD8
7:0
TXFRMBD7
TXFRMBD6
TXFRMBD5
TXFRMBD4
TXFRMBD3
TXFRMBD2
TXFRMBD1
TXFRMBD0
SU.TxBdFrmCtr
Note that the addresses in the table above are the indirect addresses that must be provided to the
SU.MACAWH and SU.MACAWL. All unused and reserved locations must be initialized to zero for proper
operation.
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DS33Z11 Ethernet Mapper
9.2
Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status,
framer interrupt status, MCLK configuration, and BPCLK configuration. These registers are preserved to provide
code compatibility with the multiport devices in this product family. The global registers bit descriptions are
presented below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ID07
0
GL.IDRL
Global ID Low Register
00h
6
ID06
0
5
ID05
1
4
ID04
1
3
ID03
0
2
ID02
0
1
ID01
0
0
ID00
0
Bit 7: ID07 Reserved for future use
Bit 6: ID06 Reserved for future use
Bit 5: ID05 If this bit is set the device contains a RMII interface
Bit 4: ID04 If this bit is set the device contains a MII interface
Bit 3: ID03 If this bit is set the device contains an Ethernet PHY
Bits 0-2: ID00-ID02 A three-bit count that is equal to 000b for the first die revision, and is incremented with each
successive die revision. May not match the two-letter die revision code on the top brand of the device.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ID15
0
GL.IDRH
Global ID High Register
01h
6
ID14
0
5
ID13
0
4
ID12
0
3
ID11
0
Bits 5-7: ID13-15 Number of ports in the device minus 1. (i.e. 000 = 1 port)
Bit 4: ID12 If this bit is set the device has LIU functionality
Bit 3: ID11 If this bit is set the device has a framer
Bit 2: ID10 Reserved for future use
Bit 1: ID09 If this bit is set the device has HDLC or X.86 encapsulation
Bit 0: ID08 If this bit is set the device has inverse multiplexing functionality
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2
ID10
0
1
ID09
1
0
ID08
0
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
GL.CR1
Global Control Register 1
02h
6
-
5
-
4
-
3
-
2
REF_CLKO
0
1
INTM
0
0
RST
0
Bit 2: REF_CLKO OFF (REF_CLKO) This bit determines if the REF_CLKO is turned off
1 = REF_CLKO is disabled and outputs an active low signal.
0 = REF_CLKO is active and in accordance with RMII/MII Selection
Bit 1: INT pin mode (INTM) This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
1 = Pin is high impedance when not active
0 = Pin drives high when not active
Bit 0: Reset (RST). When this bit is set to 1, all of the internal data path and status and control registers (except
this RST bit), on all ports, are reset to their default state. This bit must be set high for a minimum of 100ns.
0 = Normal operation
1 = Reset and force all internal registers to their default values
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.BLR
Global BERT Connect Register
03h
6
0
5
0
4
0
3
0
2
0
1
0
0
BLC1
0
Bit 0: BERT Connect 1 (BLC1) If this bit is set to 1, the BERT is connected to Serial Interface 1. The BERT
transmitter is connected to the transmit serial port and receive to receive serial port. When the BERT is
connected, normal data transfer is interrupted. Note that connecting the BERT overrides a connection to the
Serial Interface, if a connection exists. When the BERT is disconnected, the connection is restored. The BERT is
unavailable in Hardware Mode.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
GL.RTCAL
Global Receive and Transmit Serial Port Clock Activity Latched Status
04h
6
-
5
-
4
RLCALS1
-
3
-
2
-
1
-
0
TLCALS1
-
Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1) This bit is set to 1 if the receive
clock for Serial Interface 1 has activity. This bit is cleared upon read.
Bit 0: Transmit Serial Interface Clock Activity Latched Status 1 (TSCALS1) This bit is set to 1 if the transmit
clock for Serial Interface 1 has activity. This bit is cleared upon read.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
GL.SRCALS
Global SDRAM Reference Clock Activity Latched Status
05h
6
-
5
-
4
-
3
-
2
-
1
REFCLKS
-
0
SYSCLS
-
Bit 1: Reference Clock Activity Latched Status (REFCLKS) This bit is set to 1 if REF_CLK has activity. This bit
is cleared upon read.
Bit 0: System Clock Input Latched Status (SYSCLS) This bit is set to 1 if SYSCLKI has activity. This bit is
cleared upon read.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.LIE
Global Serial Interface Interrupt Enable
06h
6
0
5
0
4
LIN1TIE
0
3
0
2
0
1
0
0
LIN1RIE
0
Bit 4: Serial Interface 1 TX Interrupt Enable (LINE1TIE) Setting this bit to 1 enables an interrupt on LIN1TIS
Bit 0: Serial Interface 1 RX Interrupt Enable (LINE1RIE) Setting this bit to 1 enables an interrupt on LIN1RIS
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.LIS
Global Serial Interface Interrupt Status
07h
6
0
5
0
4
LIN1TIS
0
3
0
2
0
1
0
0
LIN1RIS
0
Bit 4: Serial Interface 1 TX Interrupt Status (LINE1TIS) This bit is set if Serial Interface 1 Transmit has an
enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.
Bit 0: Serial Interface 1 RX Interrupt Status (LINER1IS) This bit is set if Serial Interface 1 Receive has an
enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.SIE
Global Ethernet Interface Interrupt Enable
08h
6
0
5
0
4
0
3
0
2
0
1
0
0
SUB1IE
0
Bit 0: Ethernet Interface 1 Interrupt Enable (SUB1IE) Setting this bit to 1 enables an interrupt on SUB1S.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.SIS
Global Ethernet Interface Interrupt Status
09h
6
0
5
0
4
0
3
0
2
0
1
0
0
SUB1IS
0
Bit 0: Ethernet Interface 1 Interrupt Status (SUB1IS) This bit is set to 1 if Ethernet Interface 1 has an enabled
interrupt generating event. The Ethernet Interface consists of the MAC and The RMII/MII port.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.TRQIE
Global Transmit Receive Queue Interrupt Enable
0Ah
6
0
5
0
4
TQ1IE
0
3
0
2
0
1
0
0
RQ1IE
0
Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE) Setting this bit to 1 enables an interrupt on TQ1IS.
Bit 0: Receive Queue 1 Interrupt Enable (RQ1IE) Setting this bit to 1 enables an interrupt on RQ1IS.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.TRQIS
Global Transmit Receive Queue Interrupt Status
0Bh
6
0
5
0
4
TQ1IS
0
3
0
2
0
1
0
0
RQ1IS
0
Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IS) If this bit is set to 1, the Transmit Queue 1 has interrupt
status event. Transmit queue events are transmit queue-crossing thresholds and queue overflows.
Bit 0: Receive Queue 1 Interrupt Status (RQ1IS) If this bit is set to 1, the Receive Queue 1 has interrupt status
event. Receive queue events are transmit queue-crossing thresholds and queue overflows.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.BIE
Global BERT Interrupt Enable
0Ch
6
0
5
0
4
0
3
0
2
0
Bit 0: BERT Interrupt Enable (BIE) Setting this bit to 1 enables an interrupt on BIS.
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1
0
0
BIE
0
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
GL.BIS
Global BERT Interrupt Status
0Dh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
BIS
0
Bit 0: BERT Interrupt Status (BIS) This bit is set to 1 if the BERT has an enabled interrupt generating event.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.CON1
Connection Register for Ethernet Interface 1
0Eh
6
0
5
0
4
0
3
0
2
0
1
0
0
LINE1[0]
1
Bit 0: LINE1[0] This bit is preserved to provide software compatibility with multiport devices. The LINE1[0] bit
selects the Ethernet port that is to be connected to the Serial Interface. Note that Bi-directional connection is
assumed between the Serial and Ethernet Interfaces. The connection register and corresponding queue size
must be defined for proper operation. Writing a 0 to this register will disconnect the connection. When a
connection is disconnected, “1”s are sourced to the Serial Interface transmit and to the HDLC receiver and the
clocks to the HDLC transmitter/receiver are disabled.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.C1QPR
Connection 1 Queue Pointer Reset
12h
6
0
5
0
4
0
3
C1MRPRR
0
2
C1HWPRR
0
1
C1MHPR
0
0
C1HRPR
0
Bit 3: MAC Read Pointer Reset (C1MRPR) Setting this bit to 1 resets the receive queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 2: HDLC Write Pointer Reset (C1HWPR) Setting this bit to 1 resets the receive queue write pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 1: HDLC Read Pointer Reset (C1MHPR) Setting this bit to 1 resets the transmit queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 0: MAC Transmit Write Pointer Reset (C1HRPR) Setting this bit to 1 resets the transmit queue write pointer
for connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must
clear the bit before subsequent reset operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.BISTEN
BIST Enable
20h
6
0
5
0
4
0
3
0
2
0
1
0
0
BISTE
0
Bit 0: BIST Enable (BISTE) If this bit is set the DS33Z11 performs BIST test on the SDRAM. Normal data
communication is halted while BIST enable is high. The user must reset the DS33Z11 after completion of BIST
test before normal dataflow can begin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.BISTPF
BIST PassFail
21h
6
0
5
0
4
0
3
0
2
0
1
BISTDN
0
0
BISTPF
0
Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33Z11 has completed the BIST Test initiated by BISTE.
The pass fail result is available in BISTPF.
Bit 0: BIST PassFail (BISTPF) This bit is equal to 0 after the DS33Z11 performs BIST testing on the SDRAM
and the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and
the BIST DN bit is set. If set this bit can only be cleared by resetting the DS33Z11.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.SDMODE1
Global SDRAM Mode Register 1
3Ah
6
0
5
0
4
0
3
WT
0
2
BL2
0
1
BL1
1
0
BL0
1
Bit 3: Wrap Type (WT) This bit is used to configure the wrap mode.
0 = Sequential
1 = Interleave
Bits 0- 2: Burst Length 0 through 2 (BL0 – BL2) These bits are used to determine the Burst Length.
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.SDMODE2
Global SDRAM Mode Register 2
3Bh
6
0
5
0
4
0
3
0
2
LTMOD2
0
1
LTMOD1
1
0
LTMOD0
0
Bits 0 - 2: CAS Latency Mode (LTMOD0 - LTMOD2) These bits are used to setup CAS Latency
Note: Only CAS Latency of 2 or 3 is allowed
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
GL.SDMODEWS
Global SDRAM Mode Register Write Status
3Ch
6
0
5
0
4
0
3
0
2
0
1
0
0
SDMW
0
Bit 0: SDRAM Mode Write (SDMW) Setting this bit to 1 will write the current values of the mode control and
refresh time control registers to the SDRAM. The user must clear this bit and set it again for subsequent write
operations.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description
Register Address:
Bit #
Name
Default
7
SREFT7
0
GL.SDRFTC
Global SDRAM Refresh Time Control
3Dh
6
SREFT6
1
5
SREFT5
0
4
SREFT4
0
3
SREFT3
0
2
SREFT2
1
1
SREFT1
1
0
SREFT0
0
Bits 0 - 7: SDRAM Refresh Time Control (SREFT0 – SREFT7) These 8 bits are used to control the SDRAM
refresh frequency. The refresh rate will be equal to this register value x 8 x 100 Mhz.
Note: This register has a non-zero default value. This should be taken into consideration when initializing
the device.
Note: After changing the value of this register, the user must toggle the GL.SDMODEWS.SDMW bit to
write the new values to the SDRAM.
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DS33Z11 Ethernet Mapper
9.3
Arbiter Registers
The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for
queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to
transfer data to/from the SDRAM. The base address of the Arbiter register space is 0040h.
9.3.1
Arbiter Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RQSC7
0
AR.RQSC1
Arbiter Receive Queue Size Connection
40h
6
RQSC6
0
5
RQSC5
1
4
RQSC4
1
3
RQSC3
1
2
RQSC2
1
1
RQSC1
0
0
RQSC0
1
Bits 0-7: Receive Queue Size (RQSC[0:7]) These 7 bits of the size of receive queue associated with the
connection. Receive queue is for data arriving from the MAC to be sent to the WAN. The Queue address size is
defined in increments of 32 x 2048 bytes. The queue size is AR.RQSC1 multiplied by 32 to determine the number
of 2048 byte packets that can be stored in the queue. This queue is constructed in the external SDRAM. Note:
Queue size of 0 is not allowed and should never be set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TQSC7
0
AR.TQSC1
Arbiter Transmit Queue Size Connection 1
41h
6
TQSC6
0
5
TQSC5
0
4
TQSC4
0
3
TQSC3
0
2
TQSC2
0
1
TQSC1
1
0
TQSC0
1
Bits 0-7: Transmit Queue Size (TQSC[0:7]) This is size of transmit queue associated with the connection. The
queue address size is defined in increments of 32 packets. The range of bytes will depend on the external
SDRAM connected to the DS33Z11. Transmit queue is the data queue for data arriving on the WAN that is sent
to the MAC. Note that queue size of 0 is not allowed and should never be set.
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DS33Z11 Ethernet Mapper
9.4
BERT Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
BCR
BERT Control Register
80h
6
PMU
0
5
RNPL
0
4
RPIC
0
3
MPR
0
2
APRD
0
1
TNPL
0
0
TPIC
0
Bit 7: This bit must be kept low for proper operation.
Bit 6: Performance Monitoring Update (PMU) This bit causes a performance monitoring update to be initiated.
A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the
counters reset (0 or 1). For a second performance monitoring update to be initiated, this bit must be set to 0, and
back to 1. If PMU goes low before the PMS bit goes high, an update might not be performed.
Bit 5: Receive New Pattern Load (RNPL) A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF [4:0}, PTF [4:0], and BSP [31:0]) to be loaded in to the receive pattern generator. This
bit must be changed to zero and back to one for another pattern to be loaded. Loading a new pattern will forces
the receive pattern generator out of the “Sync” state which causes a resynchronization to be initiated. Note:
QRSS, PTS, PLF [4:0}, PTF [4:0], and BSP [31:0] must not change from the time this bit transitions from 0 to 1
until four RCLKI clock cycles after this bit transitions from 0 to 1.
Bit 4: Receive Pattern Inversion Control (RPIC) When 0, the receive incoming data stream is not altered.
When 1, the receive incoming data stream is inverted.
Bit 3: Manual Pattern Resynchronization (MPR) A zero to one transition of this bit will cause the receive
pattern generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for
another resynchronization to be initiated. Note: A manual resynchronization forces the receive pattern generator
out of the “Sync” state.
Bit 2: Automatic Pattern Resynchronization Disable (APRD) When 0, the receive pattern generator will
automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the
incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern
generator will not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is
prevented by not allowing the receive pattern generator to automatically exit the “Sync” state.
Bit 1: Transmit New Pattern Load (TNPL) A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0]) to be loaded in to the transmit pattern generator. This bit
must be changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0}, PTF[4:0],
and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four TCLKI clock cycles after this
bit transitions from 0 to 1.
Bit 0: Transmit Pattern Inversion Control (TPIC) When 0, the transmit outgoing data stream is not altered.
When 1, the transmit outgoing data stream is inverted.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
BPCLR
BERT Pattern Configuration Low Register
82h
Bit #
7
6
5
4
3
2
1
0
Name
QRSS
PTS
PLF4
PLF3
PLF2
PLF1
PLF0
Default
0
0
0
0
0
0
0
0
The BERT’s BPCLR, BPCHR, and BSPB registers are used for polynomial-based pattern generation, with a
formula of xn + xy + 1. The initial value for x (the seed) is placed in the BSPB (bert seed/pattern) register. The
BERT generates a series of bits by iteration of the formula.
Bit 6: QRSS Enable (QRSS) When 0, the pattern generator configuration is controlled by PTS, PLF[0:4], and
PTF[0:4], and BSP[0:31]. When 1, the pattern generator configuration is forced to a QRSS pattern with a
generating polynomial of x20 + x17 + 1. The output of the pattern generator is forced to one if the next fourteen
output bits are all zero.
Bit 5: Pattern Type Select (PTS) When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]) These five bits control the “length” feedback of the pattern
generator. The “length” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n. The values possible are
outlined in Section 8.15.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
BPCHR
BERT Pattern Configuration High Register
83h
6
0
5
0
4
PTF4
0
3
PTF3
0
2
PTF2
0
1
PTF1
0
0
PTF0
0
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]) These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y. The
values possible are outlined in Section 8.15.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BSP7
0
BSPB0R
BERT Pattern Byte0 Register
84h
6
BSP6
0
5
BSP5
0
4
BSP4
0
3
BSP3
0
2
BSP2
0
1
BSP1
0
0
BSP0
0
Bits 0 to 7: BERT Pattern (BSP[7:0]) Lower eight bits of 32 bits. Register description follows next register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BSP15
0
BSPB1R
BERT Pattern Byte 1 Register
85h
6
BSP14
0
5
BSP13
0
4
BSP12
0
3
BSP11
0
2
BSP10
0
1
BSP9
0
0
BSP8
0
1
BSP17
0
0
BSP16
0
1
BSP25
0
0
BSP24
0
Bits 0 to 7: BERT Pattern (BSP[15:8]) 8 bits of 32 bits. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BSP23
0
BSPB2R
BERT Pattern Byte2 Register
86h
6
BSP22
0
5
BSP21
0
4
BSP20
0
3
BSP19
0
2
BSP18
0
Bits 0 to 7: BERT Pattern (BSP[23:16]) 8 bits of 32 bits. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BSP31
0
BSPB3R
BERT Seed/Pattern Byte3 Register
87h
6
BSP30
0
5
BSP29
0
4
BSP28
0
3
BSP27
0
2
BSP26
0
Bits 0 to 8: BERT Pattern (BSP[31:24]) Upper 8 bits of 32 bits. Register description below.
BERT Pattern (BSP[31:0]) These 32 bits are the programmable seed for a transmit PRBS pattern, or the
programmable pattern for a transmit or receive repetitive pattern. BSP(31) is the first bit output on the transmit
side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) is the first bit input on the receive side for a 32bit repetitive pattern.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
TEICR
Transmit Error Insertion Control Register
88h
6
0
5
TIER2
0
4
TIER1
0
3
TIER0
0
2
BEI
0
1
TSEI
0
0
0
Bits 3 – 5: Transmit Error Insertion Rate (TEIR[2:0]) These three bits indicate the rate at which errors are
inserted in the output data stream. One out of every 10n bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0]
value of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A
TEIR[2:0] value of 2 results in every 100th bit being inverted. Error insertion starts when this register is written to
with a TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process,
the new error rate is started after the next error is inserted.
Bit 2: Bit Error Insertion Enable (BEI) When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) This bit causes a bit error to be inserted in the transmit data stream if
and single bit error insertion is enabled. A 0 to 1 transition causes a single bit error to be inserted. For a second
bit error to be inserted, this bit must be set to 0, and back to 1. Note: If this bit transitions more than once between
error insertion opportunities, only one error is inserted.
All other bits in this register besides BEI and TSEI and TIER must be reset to 0 for proper operation.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
BSR
BERT Status Register
8Ch
6
0
5
0
4
0
3
PMS
0
2
0
1
BEC
0
0
OOS
0
Bit 3: Performance Monitoring Update Status (PMS) This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS
is asynchronously forced low when the PMU bit goes low. TCLKI and RCLKI must be present.
Bit 1: Bit Error Count (BEC) When 0, the bit error count is zero. When 1, the bit error count is one or more.
Bit 0: Out Of Synchronization (OOS) When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
BSRL
BERT Status Register Latched
8Eh
6
-
5
-
4
-
3
PMSL
-
2
BEL
-
1
BECL
-
0
OOSL
-
Bit 3: Performance Monitor Update Status Latched (PMSL) This bit is set when the PMS bit transitions from 0
to 1.
Bit 2: Bit Error Detected Latched (BEL) This bit is set when a bit error is detected.
Bit 1: Bit Error Count Latched (BECL) This bit is set when the BEC bit transitions from 0 to 1.
Bit 0: Out Of Synchronization Latched (OOSL) This bit is set when the OOS bit changes state.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
BSRIE
BERT Status Register Interrupt Enable
90h
6
0
5
0
4
0
3
PMSIE
0
2
BEIE
0
1
BECIE
0
0
OOSIE
0
Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE) This bit enables an interrupt if the
PMSL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Bit Error Interrupt Enable (BEIE) This bit enables an interrupt if the BEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Bit Error Count Interrupt Enable (BECIE) This bit enables an interrupt if the BECL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Out Of Synchronization Interrupt Enable (OOSIE) This bit enables an interrupt if the OOSL bit is set.
0 = interrupt disabled
1 = interrupt enabled
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BEC7
0
RBECB0R
Receive Bit Error Count Byte 0 Register
94h
6
BEC6
0
5
BEC5
0
4
BEC4
0
3
BEC3
0
2
BEC2
0
1
BEC1
0
0
BEC0
0
Bits 0 - 7: Bit Error Count (BEC[0:7]) Lower eight bits of 24 bits. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BEC15
0
RBECB1R
Receive Bit Error Count Byte 1 Register
95h
6
BEC14
0
5
BEC13
0
4
BEC12
0
3
BEC11
0
2
BEC10
0
1
BEC9
0
0
BEC8
0
Bits 0 - 7: Bit Error Count (BEC[8:15]) Eight bits of a 24 bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BEC23
0
RBECR2
Receive Bit Error Count Byte 2 Register
96h
6
BEC22
0
5
BEC21
0
4
BEC20
0
3
BEC19
0
2
BEC18
0
1
BEC17
0
0
BEC16
0
Bits 0 - 7: Bit Error Count (BEC[16:23]) Upper 8-bits of the register.
Bit Error Count (BEC[0:23]) These twenty-four bits indicate the number of bit errors detected in the incoming
data stream. This count stops incrementing when it reaches a count of FF FFFFh. The associated bit error
counter will not incremented when an OOS condition exists.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BC7
0
RBCB0
Receive Bit Count Byte 0 Register
98h
6
BC6
0
5
BC5
0
4
BC4
0
3
BC3
0
2
BC2
0
Bits 0 - 7: Bit Count (BC[0:7]) Eight bits of a 32 bit value. Register description below.
Register Name:
Register Description:
Register Address:
RBCB1
Receive Bit Count Byte 1 Register #1
99h
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1
BC1
0
0
BC0
0
DS33Z11 Ethernet Mapper
Bit #
Name
Default
7
BC15
0
6
BC14
0
5
BC13
0
4
BC12
0
3
BC11
0
2
BC10
0
1
BC9
0
0
BC8
0
1
BC17
0
0
BC16
0
Bits 0 - 7: Bit Count (BC[8:15]) Eight bits of a 32 bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BC23
0
RBCB2
Receive Bit Count Byte 2 Register
9Ah
6
BC22
0
5
BC21
0
4
BC20
0
3
BC19
0
2
BC18
0
Bits 0 - 7: Bit Count (BC[16:23]) Eight bits of a 32 bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BC31
0
RBCB3
Receive Bit Count Byte 3 Register
9Bh
6
BC30
0
5
BC29
0
4
BC28
0
3
BC27
0
2
BC26
0
1
BC25
0
0
BC24
0
Bits 0 - 7: Bit Count (BC[24:31]) Upper 8-bits of the register.
Bit Count (BC[0:31]) These thirty-two bits indicate the number of bits in the incoming data stream. This count
stops incrementing when it reaches a count of FFFF FFFFh. The associated bit counter will not incremented
when an OOS condition exists.
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9.5
Serial Interface Registers
The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial
Interface register map consists of registers that are common functions, transmit functions, and receive functions.
Bits that are underlined are read-only; all other bits can be written. All reserved registers and bits with “-“
designation should be written to zero, unless specifically noted in the register definition. When read, the
information from reserved registers and bits designated with “-“ should be discarded.
Counter registers are updated by asserting (low to high transition) the associated performance monitoring update
signal (xxPMU). During the counter register update process, the associated performance monitoring status signal
(xxPMS) is deasserted. The counter register update process consists of loading the counter register with the
current count, resetting the counter, forcing the zero count status indication low for one clock cycle, and then
asserting xxPMS. No events are missed during this update procedure.
A latched bit is set when the associated event occurs, and remains set until it is cleared by reading. Once
cleared, a latched bit will not be set again until the associated event occurs again. Reserved configuration bits
and registers should be written to zero.
9.5.1
Serial Interface Transmit and Common Registers
Serial Interface Transmit Registers are used to control the HDLC transmitter associated with each Serial
Interface. The register map is shown in the following table. Note that throughout this document the HDLC
processor is also referred to as a “packet processor.”
9.5.2
Serial Interface Transmit Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.TSLCR
Transmit Serial Interface Configuration Register
0C0h
6
0
5
0
4
0
3
0
2
0
1
0
0
TDENPLT
0
Bit 0: Transmit Data Enable Polarity (TDENPLT) If set to 1, TDEN is active low for enable. In the default mode,
when TDEN is logic high, the data is enabled and output by the DS33Z11.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.RSTPD
Serial Interface Reset Register
0C1h
6
0
5
0
4
0
3
0
2
0
1
RESET
0
0
0
Bit 1: RESET If this bit set to 1, the Data Path and Control and Status for this interface are reset. The Serial
Interface is held in Reset as long as this bit is high. This bit must be high for a minimum of 200 nsec for a valid
reset to occur.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.LPBK
Serial Interface Loopback Control Register
0C2h
6
0
5
0
4
0
3
0
2
0
1
0
0
QLP
0
Bit 0: Queue Loopback Enable (QLP) If this bit set to 1, data received on the Serial Interface is looped back to
the Serial Interface transmitter. Received data will not be sent from the Serial Interface to the Ethernet Interface.
Buffered packet data will remain in queue until the loopback is removed.
9.5.3
Transmit HDLC Processor Registers
Register Name:
Register Description:
Register Address:
LI.TPPCL
Transmit Packet Processor Control Low Register
0C4h
Bit #
7
6
5
4
3
2
1
Name
TFAD
TF16
TIFV
TSD
TBRE
Default
0
0
0
0
0
0
0
Note: The user should take care not to modify this register value during packet error insertion.
0
TIAEI
0
Bits 5 - 6: Transmit FCS Append Disable (TFAD) – This bit controls whether or not an FCS is appended to the
end of each packet. When equal to 0, the calculated FCS bytes are appended to packets. When set to 1, packets
are transmitted without FCS. In X.86 Mode, FCS is always 32 bits and is always appended to the packet.
Bit 4: Transmit FCS-16 Enable (TF16) – When 0, the FCS processing uses a 32-bit FCS. When 1, the FCS
processing uses a 16-bit FCS. In X.86 Mode, 32-bit FCS processing is enabled.
Bit 3: Transmit Bit Synchronous Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag
sequence (7Eh). When 1, inter-frame fill is done with all '1's. This bit is ignored in byte synchronous mode. In X.86
mode the interframe flag is always 7E.
Bit 2: Transmit Scrambling Disable (TSD) – When equal to 0, X43+1 scrambling is performed. When set to 1,
scrambling is disabled. Note that in hardware mode, transmit scrambling is controlled by the SCD hardware pin.
Bit 1: Transmit Bit Reordering Enable (TBRE) – When equal to 0, bit reordering is disabled (The first bit
transmitted is from the MSB of the transmit FIFO byte TFD [7]). When set to 1, bit reordering is enabled (The first
bit transmitted is from the LSB of the transmit FIFO byte TFD [0]). Note that this function can be controlled in
Hardware mode with the BREO hardware pin.
Bit 0: Transmit Initiate Automatic Error Insertion (TIAEI) – This write-only bit initiates error insertion. See the
LI.TEPHC register definition for details of usage.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TIFG7
0
LI.TIFGC
Transmit Inter-Frame Gapping Control Register
0C5h
6
TIFG6
0
5
TIFG5
0
4
TIFG4
0
3
TIFG3
0
2
TIFG2
0
1
TIFG1
0
0
TIFG0
1
Bits 0 - 7: Transmit Inter-Frame Gapping (TIFG[7:0]) – These eight bits indicate the number of additional flags
and bytes of inter-frame fill to be inserted between packets. The number of flags and bytes of inter-frame fill
between packets is at least the value of TIFG[7:0] plus 1. Note: If inter-frame fill is set to all 1’s, a TFIG value of 2
or 3 will result in a flag, two bytes of 1’s, and an additional flag between packets.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TPEN7
0
LI.TEPLC
Transmit Errored Packet Low Control Register
0C6h
6
TPEN6
0
5
TPEN5
0
4
TPEN4
0
3
TPEN3
0
2
TPEN2
0
1
TPEN1
0
0
TPEN0
0
Bits 0 – 7: Transmit Errored Packet Insertion Number (TPEN[7:0]) – These eight bits indicate the total number
of errored packets to be transmitted when triggered by TIAEI. Error insertion will end after this number of errored
packets have been transmitted. A value of FFh results in continuous errored packet insertion at the specified rate.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
MEIMS
0
LI.TEPHC
Transmit Errored Packet High Control Register
0C7h
6
TPER6
0
5
TPER5
0
4
TPER4
0
3
TPER3
0
2
TPER2
0
1
TPER1
0
0
TPER0
0
Bit 7: Manual Error Insert Mode Select (MEIMS) – When 0, the transmit manual error insertion signal (TMEI)
will not cause errors to be inserted. When 1, TMEI will cause an error to be inserted when it transitions from a 0 to
a 1. Note: Enabling TMEI does not disable error insertion using TCER[6:0] and TCEN[7:0].
Bits 0 – 6: Transmit Errored Packet Insertion Rate (TPER[6:0]) – These seven bits indicate the rate at which
errored packets are to be output. One out of every x * 10y packets is to be an errored packet. TPER[3:0] is the
value x, and TPER[6:4] is the value y which has a maximum value of 6. If TPER[3:0] has a value of 0h errored
packet insertion is disabled. If TPER[6:4] has a value of 6xh or 7xh the errored packet rate is x * 106. A TPER[6:0]
value of 01h results in every packet being errored. A TPER[6:0] value of 0Fh results in every 15th packet being
errored. A TPER[6:0] value of 11h results in every 10th packet being errored.
To initiate automatic error insertion, use the following routine:
1) Configure LI.TEPLC and LI.TEPHC for the desired error insertion mode.
2) Write the LI.TPPCL.TIAEI bit to 1. Note that this bit is write-only.
3) If not using continuous error insertion (LI.TPELC is not equal to FFh), the user should monitor the
LI.TPPSR.TEPF bit for completion of the error insertion. If interrupt on completion of error insertion is enabled
(LI.TPPSRIE.TEPFIE = 1), the user only needs to wait for the interrupt condition.
4) Proceed with the cleanup routine listed below.
Cleanup routine:
1) Write LI.TEPLC and LI.TEPHC each to 00h.
2) Write the LI.TPPCL.TIAEI bit to 0.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.TPPSR
Transmit Packet Processor Status Register
0C8h
6
0
5
0
4
0
3
0
2
0
1
0
0
TEPF
0
Bit 0: Transmit Errored Packet Insertion Finished (TEPF) – This bit is set when the number of errored packets
indicated by the TPEN[7:0] bits in the TEPC register have been transmitted. This bit is cleared when errored
packet insertion is disabled, or a new errored packet insertion process is initiated.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
LI.TPPSRL
Transmit Packet Processor Status Register Latched
0C9h
6
-
5
-
4
-
3
-
2
-
1
-
0
TEPFL
-
Bit 0: Transmit Errored Packet Insertion Finished Latched (TEPFL) – This bit is set when the TEPF bit in the
TPPSR register transitions from zero to one.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.TPPSRIE
Transmit Packet Processor Status Register Interrupt Enable
0CAh
6
0
5
0
4
0
3
0
2
0
1
0
0
TEPFIE
0
Bit 0: Transmit Errored Packet Insertion Finished Interrupt Enable (TEPFIE) – This bit enables an interrupt if
the TEPFL bit in the LI.TPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TPC7
0
LI.TPCR0
Transmit Packet Count Byte 0
0CCh
6
TPC6
0
5
TPC5
0
4
TPC4
0
3
TPC3
0
2
TPC2
0
1
TPC1
0
0
TPC0
0
Bits 0 – 7: Transmit Packet Count (TPC[7:0]) – Eight bits of 24 bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TPC15
0
LI.TPCR1
Transmit Packet Count Byte 1
0CDh
6
TPC14
0
5
TPC13
0
4
TPC12
0
3
TPC11
0
2
TPC10
0
1
TPC9
0
0
TPC8
0
Bits 0 – 7: Transmit Packet Count (TPC[15:8]) – Eight bits of 24 bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TPC23
0
LI.TPCR2
Transmit Packet Count Byte 2
0CEh
6
TPC22
0
5
TPC21
0
4
TPC20
0
3
TPC19
0
2
TPC18
0
1
TPC17
0
0
TPC16
0
Bits 0 – 7: Transmit Packet Count (TPC[23:16]) – These twenty-four bits indicate the number of packets
extracted from the Transmit FIFO and output in the outgoing data stream.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TBC7
0
LI.TBCR0
Transmit Byte Count Byte 0
0D0h
6
TBC6
0
5
TBC5
0
4
TBC4
0
3
TBC3
0
2
TBC2
0
1
TBC1
0
0
TBC0
0
Bits 0 – 7: Transmit Byte Count (TBC[0:7]) – Eight bits of 32 bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TBC15
0
LI.TBCR1
Transmit Byte Count Byte 1
0D1h
6
TBC14
0
5
TBC13
0
4
TBC12
0
3
TBC11
0
2
TBC10
0
1
TBC9
0
0
TBC8
0
Bits 0 – 7: Transmit Byte Count (TBC[15:8]) - Eight bits of 32 bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TBC23
0
LI.TBCR2
Transmit Byte Count Byte 2
0D2h
6
TBC22
0
5
TBC21
0
4
TBC20
0
3
TBC19
0
2
TBC18
0
1
TBC17
0
0
TBC16
0
Bits 0 – 7: Transmit Byte Count (TBC[23:16]) - Eight bits of 32 bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TBC31
0
LI.TBCR3
Transmit Byte Count Byte 3
0D3h
6
TBC30
0
5
TBC29
0
4
TBC28
0
3
TBC27
0
2
TBC26
0
1
TBC25
0
0
TBC24
0
Bits 0 – 7: Transmit Byte Count (TBC[31:24]) – These thirty-two bits indicate the number of packet bytes
inserted in the outgoing data stream.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.TMEI
Transmit Manual Error Insertion
0D4h
6
0
5
0
4
0
3
0
2
0
1
0
0
TMEI
0
Bit 0: Transmit Manual Error Insertion (TMEI) A zero to one transition will insert a single error in the Transmit
direction.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.THPMUU
Serial Interface Transmit HDLC PMU Update Register
0D6h
6
0
5
0
4
0
3
0
2
0
1
0
0
TPMUU
0
Bit 0: Transmit PMU Update (TPMUU) This signal causes the transmit cell/packet processor block performance
monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to
be updated with the latest data, and the counters reset (0 or 1). This update updates performance monitoring
counters for the Serial Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.THPMUS
Serial Interface Transmit HDLC PMU Update Status Register
0D7h
6
0
5
0
4
0
3
0
2
0
1
0
0
TPMUS
0
Bit 0: Transmit PMU Update Status (TPMUS) This bit is set when the Transmit PMU Update is completed. This
bit is cleared when TPMUU is reset.
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9.5.4
X.86 Registers
X.86 Transmit and common Registers are used to control the operation of the X.86 encoder and decoder.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.TX86EDE
X.86 Encoding Decoding Enable
0D8h
6
0
5
0
4
0
3
0
2
0
1
0
0
X86ED
0
Bit 0: X.86 Encoding Decoding (X86ED) If this bit is set to 1, X.86 encoding and decoding is enabled for the
Transmit and Receive paths. The MAC Frame is encapsulated in the X.86 Frame for Transmit and the X.86
headers are checked for in the received data. If X.86 functionality is selected, the X.86 receiver byte boundary is
provided by the RBSYNC signal and the DS33Z11 provides the transmit byte synchronization TBSYNC. No
HDLC encapsulation is performed.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
X86TRA7
0
LI.TRX86A
Transmit Receive X.86 Address
0D9h
6
X86TRA6
0
5
X86TRA5
0
4
X86TRA4
0
3
X86TRA3
0
2
X86TRA2
1
1
X86TRA1
0
0
X86TRA0
0
Bits 0 - 7: X86 Transmit Receive Address (X86TRA0-7) This is the address field for the X.86 transmitter and for
the receiver. The register default value is 0x04.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
X86TRC7
0
LI.TRX8C
Transmit Receive X.86 Control
0DAh
6
X86TRC6
0
5
X86TRC5
0
4
X86TRC4
0
3
X86TRC3
0
2
X86TRC2
0
1
X86TRC1
1
0
X86TRC0
1
Bits 0 - 7: X86 Transmit Receive Control (X86TRC0-7) This is the control field for the X.86 transmitter and
expected value for the receiver. The register is reset to 0x03
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LI.TRX86SAPIH
Transmit Receive X.86 SAPIH
0DBh
7
6
5
4
3
2
1
0
TRSAPIH7
TRSAPIH6
TRSAPIH5
TRSAPIH4
TRSAPIH3
TRSAPIH2
TRSAPIH1
TRSAPIH0
1
1
1
1
1
1
1
0
Bits 0 - 7: X86 Transmit Receive Address (TRSAPIH0-7) This is the address field for the X.86 transmitter and
expected for the receiver. The register is reset to 0xfe.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LI.TRX86SAPIL
Transmit Receive X.86 SAPIL
0DCh
7
6
5
4
3
2
1
0
TRSAPIL7
TRSAPIL6
TRSAPIL5
TRSAPIL4
TRSAPIL3
TRSAPIL2
TRSAPIL1
TRSAPIL0
0
0
0
0
0
0
0
1
Bits 0 – 7: X86 Transmit Receive Control (TRSAPIL0-7) This is the address field for the X.86 transmitter and
expected value for the receiver. The register is reset to 0x01
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CIRE
0
LI.CIR
Committed Information Rate
0DDh
6
CIR6
0
5
CIR5
0
4
CIR4
0
3
CIR3
0
2
CIR2
0
1
CIR1
0
0
CIR0
1
Bit 7: Committed Information Rate Enable (CIRE) Set this bit to 1 to enable the Committed Information Rate
Controller feature.
Bits 0 – 6: Committed Information Rate (CIR0-6) These bits provide the value for the committed information
rate. The value is multiplied by 500 kbps to get the CIR value. The user must ensure that the CIR value is less
than or equal to the maximum Serial Interface transmit rate. The valid range is from 1 to 104. Any values outside
this range will result in unpredictable behavior. Note that a value of 104 translates to a 52 Mbps line rate. Hence if
the CIR is above the line rate, the rate is not restricted by the CIR. For instance, if using a T1 line and the CIR is
programmed with a value of 104, it has no effect in restricting the rate.
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9.5.5
Receive Serial Interface
Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that
throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet
processor block has seventeen registers.
9.5.5.1 Register Bit Descriptions
Register Name:
LI.RSLCR
Register Description:
Receive Serial Interface Configuration Register
Register Address:
100h
Bit #
Name
Default
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RDENPLT
0
Bit 0: Receive Data Enable Polarity (RDENPLT) Receive Data Enable Polarity. If set to 1, RDEN Low enables
reception of the bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.RPPCL
Receive Packet Processor Control Low Register
101h
6
0
5
RFPD
0
4
RF16
0
3
RFED
0
2
RDD
0
1
RBRE
0
0
RCCE
0
Bit 5: Receive FCS Processing Disable (RFPD) – When equal to 0, FCS processing is performed and FCS is
appended to packets. When set to 1, FCS processing is disabled (the packets do not have an FCS appended). In
X.86 mode, FCS processing is always enabled.
Bit 4: Receive FCS-16 Enable (RF16) – When 0, the error checking circuit uses a 32-bit FCS. When 1, the error
checking circuit uses a 16-bit FCS. This bit is ignored when FCS processing is disabled. In X.86 mode, the FCS
is always 32 bits.
Bit 3: Receive FCS Extraction Disable (RFED) – When 0, the FCS bytes are discarded. When 1, the FCS bytes
are passed on. This bit is ignored when FCS processing is disabled. In X.86 mode, FCS bytes are discarded.
Bit 2: Receive Descrambling Disable (RDD) – When equal to 0, X43+1 descrambling is performed. When set to
1, descrambling is disabled.
Bit 1: Receive Bit Reordering Enable (RBRE) – When equal to 0, reordering is disabled and the first bit
received is expected to be the MSB DT [7] of the byte. When set to 1, bit reordering is enabled and the first bit
received is expected to be the LSB DT [0] of the byte. Note that function is controlled by the BREO in Hardware
Mode.
Bit 0: Receive Clear Channel Enable (RCCE) – When equal to 0, packet processing is enabled. When set to 1,
the device is in clear channel mode and all packet-processing functions except descrambling and bit reordering
are disabled.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RMX7
1
LI.RMPSCL
Receive Maximum Packet Size Control Low Register
102h
6
RMX6
1
5
RMX5
1
4
RMX4
0
3
RMX3
0
2
RMX2
0
1
RMX1
0
0
RMX0
0
Bits 0 - 7: Receive Maximum Packet Size (RMX[7:0]) Eight bits of a sixteen bit value. Register description
below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RMX15
0
LI.RMPSCH
Receive Maximum Packet Size Control High Register
103h
6
RMX14
0
5
RMX13
0
4
RMX12
0
3
RMX11
0
2
RMX10
1
1
RMX9
1
0
RMX8
1
Bits 0-7: Receive Maximum Packet Size (RMX[8:15]) These sixteen bits indicate the maximum allowable
packet size in bytes. The size includes the FCS bytes, but excludes bit/byte stuffing. Note: If the maximum packet
size is less than the minimum packet size, all packets are discarded. When packet processing is disabled, these
sixteen bits indicate the "packet" size the incoming data is to be broken into.
The maximum packet size allowable is 2016 bytes plus the FCS bytes. Any values programmed that are greater
than 2016 + FCS will have the same effect as 2016+ FCS value.
In X.86 mode, the X.86 encapsulation bytes are included in maximum size control.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.RPPSR
Receive Packet Processor Status Register
104h
6
0
5
0
4
0
3
0
2
REPC
0
1
RAPC
0
0
RSPC
0
Bit 2: Receive FCS Errored Packet Count (REPC) This read only bit indicates that the receive FCS errored
packet count is non-zero.
Bit 1: Receive Aborted Packet Count (RAPC) This read only bit indicates that the receive aborted packet count
is non-zero.
Bit 0: Receive Size Violation Packet Count (RSPC) This read only bit indicates that the receive size violation
packet count is non-zero.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
REPL
-
LI.RPPSRL
Receive Packet Processor Status Register Latched
105h
6
RAPL
-
5
RIPDL
-
4
RSPDL
-
3
RLPDL
-
2
REPCL
-
1
RAPCL
-
0
RSPCL
-
Bit 7: Receive FCS Errored Packet Latched (REPL) This bit is set when a packet with an errored FCS is
detected.
Bit 6: Receive Aborted Packet Latched (RAPL) This bit is set when a packet with an abort indication is
detected.
Bit 5: Receive Invalid Packet Detected Latched (RIPDL) This bit is set when a packet with a non-integer
number of bytes is detected.
Bit 4: Receive Small Packet Detected Latched (RSPDL) This bit is set when a packet smaller than the
minimum packet size is detected.
Bit 3: Receive Large Packet Detected Latched (RLPDL) This bit is set when a packet larger than the maximum
packet size is detected.
Bit 2: Receive FCS Errored Packet Count Latched (REPCL) This bit is set when the REPC bit in the RPPSR
register transitions from zero to one.
Bit 1: Receive Aborted Packet Count Latched (RAPCL) This bit is set when the RAPC bit in the RPPSR
register transitions from zero to one.
Bit 0: Receive Size Violation Packet Count Latched (RSPCL) This bit is set when the RSPC bit in the RPPSR
register transitions from zero to one.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
REPIE
0
LI.RPPSRIE
Receive Packet Processor Status Register Interrupt Enable
106h
6
RAPIE
0
5
RIPDIE
0
4
RSPDIE
0
3
RLPDIE
0
2
REPCIE
0
1
RAPCIE
0
0
RSPCIE
0
Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE) This bit enables an interrupt if the REPL bit in the
LI.RPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 6: Receive Aborted Packet Interrupt Enable (RAPIE) This bit enables an interrupt if the RAPL bit in the
LI.RPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 5: Receive Invalid Packet Detected Interrupt Enable (RIPDIE) This bit enables an interrupt if the RIPDL bit
in the LI.RPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 4: Receive Small Packet Detected Interrupt Enable (RSPDIE) This bit enables an interrupt if the RSPDL bit
in the LI.RPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: Receive Large Packet Detected Interrupt Enable (RLPDIE) This bit enables an interrupt if the RLPDL bit
in the LI.RPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Receive FCS Errored Packet Count Interrupt Enable (REPCIE) This bit enables an interrupt if the
REPCL bit in the LI.RPPSRL register is set. Must be set low when the packets do not have an FCS appended.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Receive Aborted Packet Count Interrupt Enable (RAPCIE) This bit enables an interrupt if the RAPCL bit
in the LI.RPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Receive Size Violation Packet Count Interrupt Enable (RSPCIE) This bit enables an interrupt if the
RSPCL bit in the LI.RPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPC7
0
LI.RPCB0
Receive Packet Count Byte 0 Register
108h
6
RPC6
0
5
RPC5
0
4
RPC4
0
3
RPC3
0
2
RPC2
0
1
RPC1
0
0
RPC0
0
Bits 0 - 7: Receive Packet Count (RPC [7:0]) Eight bits of a 24-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPC15
0
LI.RPCB1
Receive Packet Count Byte 1 Register
109h
6
RPC14
0
5
RPC13
0
4
RPC12
0
3
RPC11
0
2
RPC10
0
1
RPC09
0
0
RPC08
0
Bits 0 - 7: Receive Packet Count (RPC [15:8]) Eight bits of a 24-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPC23
0
LI.RPCB2
Receive Packet Count Byte 2 Register
10Ah
6
RPC22
0
5
RPC21
0
4
RPC20
0
3
RPC19
0
2
RPC18
0
1
RPC17
0
0
RPC16
0
Bits 0 – 7: Receive Packet Count (RPC [23:16]) These twenty-four bits indicate the number of packets stored in
the receive FIFO without an abort indication. Note: Packets discarded due to system loopback or an overflow
condition are included in this count. This register is valid when clear channel is enabled.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RFPC7
0
LI.RFPCB0
Receive FCS Errored Packet Count Byte 0 Register
10Ch
6
RFPC6
0
5
RFPC5
0
4
RFPC4
0
3
RFPC3
0
2
RFPC2
0
1
RFPC1
0
0
RFPC0
0
Bits 0 – 7: Receive FCS Errored Packet Count (RFPC[7:0]) Eight bits of a 24-bit value. Register description
below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RFPC15
0
LI.RFPCB1
Receive FCS Errored Packet Count Byte 1 Register
10Dh
6
RFPC14
0
5
RFPC13
0
4
RFPC12
0
3
RFPC11
0
2
RFPC10
0
1
RFPC9
0
0
RFPC8
0
Bits 0 – 7: Receive FCS Errored Packet Count (RFPC[15:8]) Eight bits of a 24-bit value. Register description
below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RFPC23
0
LI.RFPCB2
Receive FCS Errored Packet Count Byte 2 Register
10Eh
6
RFPC22
0
5
RFPC21
0
4
RFPC20
0
3
RFPC19
0
2
RFPC18
0
1
RFPC17
0
0
RFPC16
0
Receive FCS Errored Packet Count (RFPC[23:16]) These twenty-four bits indicate the number of packets
received with an FCS error. The byte count for these packets is included in the receive aborted byte count
register REBCR.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RAPC7
0
LI.RAPCB0
Receive Aborted Packet Count Byte 0 Register
110h
6
RAPC6
0
5
RAPC5
0
4
RAPC4
0
3
RAPC3
0
2
RAPC2
0
1
RAPC1
0
0
RAPC0
0
Bits 0 - 7: Receive Aborted Packet Count (RAPC [7:0]) Eight bits of a 24-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RAPC15
0
LI.RAPCB1
Receive Aborted Packet Count Byte 1 Register
111h
6
RAPC14
0
5
RAPC13
0
4
RAPC12
0
3
RAPC11
0
2
RAPC10
0
1
RAPC9
0
0
RAPC8
0
Bits 0 - 7: Receive Aborted Packet Count (RAPC[15:8]) Eight bits of a 24-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RAPC23
0
LI.RAPCB2
Receive Aborted Packet Count Byte 2 Register
112h
6
RAPC22
0
5
RAPC21
0
4
RAPC20
0
3
RAPC19
0
2
RAPC18
0
1
RAPC17
0
0
RAPC16
0
Bits 0 – 7: Receive Aborted Packet Count (RAPC [23:16]) The twenty-four bit value from these three registers
indicates the number of packets received with a packet abort indication. The byte count for these packets is
included in the receive aborted byte count register REBCR.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSPC7
0
LI.RSPCB0
Receive Size Violation Packet Count Byte 0 Register
114h
6
RSPC6
0
5
RSPC5
0
4
RSPC4
0
3
RSPC3
0
2
RSPC2
0
1
RSPC1
0
0
RSPC0
0
Bits 0 - 7: Receive Size Violation Packet Count (RSPC [7:0]) Eight bits of a 24-bit value. Register description
below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSPC15
0
LI.RSPCB1
Receive Size Violation Packet Count Byte 1 Register
115h
6
RSPC14
0
5
RSPC13
0
4
RSPC12
0
3
RSPC11
0
2
RSPC10
0
1
RSPC9
0
0
RSPC8
0
Bits 0 - 7: Receive Size Violation Packet Count (RSPC [15:8]) Eight bits of a 24-bit value. Register description
below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RSPC23
0
LI.RSPCB2
Receive Size Violation Packet Count Byte 2 Registers
116h
6
RSPC22
0
5
RSPC21
0
4
RSPC20
0
3
RSPC19
0
2
RSPC18
0
1
RSPC17
0
0
RSPC16
0
Bits 0 – 7: Receive Size Violation Packet Count (RSPC [23:16]) These twenty-four bits indicate the number of
packets received with a packet size violation (below minimum, above maximum, or non-integer number of bytes).
The byte count for these packets is included in the receive aborted byte count register REBCR.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RBC7
0
LI.RBC0
Receive Byte Count 0 Register
118h
6
RBC6
0
5
RBC5
0
4
RBC4
0
3
RBC3
0
2
RBC2
0
1
RBC1
0
0
RBC0
0
Bits 0 - 7: Receive Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RBC15
0
LI.RBC1
Receive Byte Count 1 Register
119h
6
RBC14
0
5
RBC13
0
4
RBC12
0
3
RBC11
0
2
RBC10
0
1
RBC9
0
0
RBC8
0
Bits 0 - 7: Receive Byte Count (RBC [15:8]) Eight bits of a 32-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RBC23
0
LI.RBC2
Receive Byte Count 2 Register
11Ah
6
RBC22
0
5
RBC21
0
4
RBC20
0
3
RBC19
0
2
RBC18
0
1
RBC17
0
0
RBC16
0
Bits 0 - 7: Receive Byte Count (RBC [23:16]) Eight bits of a 32-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RBC31
0
LI.RBC3
Receive Byte Count 3 Register
11Bh
6
RBC30
0
5
RBC29
0
4
RBC28
0
3
RBC27
0
2
RBC26
0
1
RBC25
0
0
RBC24
0
Bits 0 – 7: Receive Byte Count (RBC [31:24]) These thirty-two bits indicate the number of bytes contained in
packets stored in the receive FIFO without an abort indication. Note: Bytes discarded due to FCS extraction,
system loopback, FIFO reset, or an overflow condition may be included in this count.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
REBC7
0
LI.RAC0
Receive Aborted Byte Count 0 Register
11Ch
6
REBC6
0
5
REBC5
0
4
REBC4
0
3
REBC3
0
2
REBC2
0
1
REBC1
0
0
REBC0
0
Bits 0 - 7: Receive Aborted Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
REBC15
0
LI.RAC1
Receive Aborted Byte Count 1 Register
11Dh
6
REBC14
0
5
REBC13
0
4
REBC12
0
3
REBC11
0
2
REBC10
0
1
REBC9
0
0
REBC8
0
Bits 0 - 7: Receive Aborted Byte Count (RBC [15:8]) Eight bits of a 32-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
REBC23
0
LI.RAC2
Receive Aborted Byte Count 2 Register
11Eh
6
REBC22
0
5
REBC21
0
4
REBC20
0
3
REBC19
0
2
REBC18
0
1
REBC17
0
0
REBC16
0
Bits 0 - 7: Receive Aborted Byte Count (RBC [16:23]) Eight bits of a 32-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
REBC31
0
LI.RAC3
Receive Aborted Byte Count 3 Register
11Fh
6
REBC30
0
5
REBC29
0
4
REBC28
0
3
REBC27
0
2
REBC26
0
1
REBC25
0
0
REBC24
0
Bits 0 – 7: Receive Aborted Byte Count (REBC[31:24]) These thirty-two bits indicate the number of bytes
contained in packets stored in the receive FIFO with an abort indication. Note: Bytes discarded due to FCS
extraction, system loopback, FIFO reset, or an overflow condition may be included in this count.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LI.RHPMUU
Serial Interface Receive HDLC PMU Update Register
120h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RPMUU
0
Bit 0: Receive PMU Update (RPMUU) This signal causes the receive cell/packet processor block performance
monitoring registers (counters) to be updated. A 0 to 1 transition causes the performance monitoring registers to
be updated with the latest data, and the counters reset (0 or 1). This update updates performance-monitoring
counters for the Serial Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
LI.RHPMUS
Serial Interface Receive HDLC PMU Update Status Register
121h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RPMUUS
0
Bit 0: Receive PMU Update Status (RPMUUS) This bit is set when the Transmit PMU Update is completed. This
bit is cleared when RPMUU is set to 0.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
LI.RX86S
Receive X.86 Latched Status Register
122h
6
-
5
-
4
-
3
SAPIHNE
-
2
SAPILNE
-
1
CNE
-
0
ANE
-
Bit 3: SAPI High is not equal to LI.TRX86SAPIH Latched Status (SAPIHNE) This latched status bit is set if
SAPIH is not equal to LI.TRX86SAPIH. This latched status bit is cleared upon read.
Bit 2: SAPI Low is not equal to LI.TRX86SAPIL Latched Status (SAPILNE) This latched status bit is set if
SAPIL is not equal to LI.TRX86SAPIL. This latched status bit is cleared upon read.
Bit 1: Control is not equal to LI.TRX8C (CNE) This latched status bit is set if the control field is not equal to
LI.TRX8C. This latched status bit is cleared upon read.
Bit 0: Address is not equal to LI.TRX86A (ANE) This latched status bit is set if the X.86 Address field is not
equal to LI.TRX86A. This latched status bit is cleared upon read.
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Register Name:
Register Description:
Register Address:
LI.RX86LSIE
Receive X.86 Interrupt Enable
123h
Bit #
Name
7
-
6
-
5
-
4
-
3
SAPINE01IM
2
SAPINEFEIM
Default
0
0
0
0
0
0
1
CNE3LI
M
0
0
ANE4IM
0
Bit 3: SAPI Octet not equal to LI.TRX86SAPIH Interrupt Enable (SAPINE01IM) If this bit is set to 1,
LI.RX86S.SAPIHNE will generate an interrupt.
Bit 2: SAPI Octet not equal to LI.TRX86SAPIL Interrupt Enable (SAPINEFEIM) If this bit is set to 1,
LI.RX86S.SAPILNE will generate an interrupt.
Bit 1: Control not equal to LI.TRX8C Interrupt Enable (CNE3LIM) If this bit is set to 1, LI.RX86S.CNE will
generate an interrupt.
Bit 0: Address not equal to LI.TRX86A Interrupt Enable (ANE4IM) If this bit is set to 1, LI.RX86S.ANE will
generate an interrupt.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TQLT7
0
LI.TQLT
Serial Interface Transmit Queue Low Threshold (Watermark)
124h
6
TQLT6
0
5
TQLT5
0
4
TQLT4
0
3
TQLT3
0
2
TQLT2
0
1
TQLT1
0
0
TQLT0
0
Bits 0 - 7: Transmit Queue Low Threshold (TQLT[0:7]) The transmit queue low threshold for the connection, in
increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
determine the byte location of the threshold. Note that the transmit queue is for data that was received from the
Serial Interface to be sent to the Ethernet Interface.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TQHT7
0
LI.TQHT
Serial Interface Transmit Queue High Threshold (Watermark)
125h
6
TQHT6
0
5
TQHT5
0
4
TQHT4
0
3
TQHT3
0
2
TQHT2
0
1
TQHT1
0
0
TQHT0
0
Bits 0 – 7: Transmit Queue High Threshold (TQHT[0:7]) The transmit queue high threshold for the connection,
in increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
determine the byte location of the threshold. Note that the transmit queue is for data that was received from the
Serial Interface to be sent to the Ethernet Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
LI.TQTIE
Serial Interface Transmit Queue Cross Threshold Interrupt Enable
126h
6
0
5
0
4
0
3
TFOVFIE
0
2
TQOVFIE
0
1
TQHTIE
0
0
TQLTIE
0
Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE) If this bit is set, the watermark
interrupt is enabled for TFOVFLS.
Bit 2: Transmit Queue Overflow for Connection Interrupt Enable (TQOVFIE) If this bit is set, the watermark
interrupt is enabled for TQOVFLS.
Bit 1: Transmit Queue for Connection High Threshold Interrupt Enable (TQHTIE) If this bit is set, the
watermark interrupt is enabled for TQHTS.
Bit 0: Transmit Queue for Connection Low Threshold Interrupt Enable (TQLTIE) If this bit is set, the
watermark interrupt is enabled for TQLTS.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
LI.TQCTLS
Serial Interface Transmit Queue Cross Threshold Latched Status
127h
6
-
5
-
4
-
3
TFOVFLS
-
2
TQOVFLS
-
1
TQHTLS
-
0
TQLTLS
-
Bit 3: Transmit Queue FIFO Overflowed Latched Status (TFOVFLS) This bit is set if the transmit queue FIFO
has overflowed. This register is cleared after a read. This FIFO is for data to be transmitted from the HDLC to be
sent to the SDRAM.
Bit 2: Transmit Queue Overflow Latched Status (TQOVFLS) This bit is set if the transmit queue has
overflowed. This register is cleared after a read.
Bit 1: Transmit Queue for Connection Exceeded High Threshold Latched Status (TQHTLS) This bit is set if
the transmit queue crosses the High Watermark. This register is cleared after a read.
Bit 0: Transmit Queue for Connection Exceeded Low Threshold Latched Status (TQLTLS) This bit is set if
the transmit queue crosses the Low Watermark. This register is cleared after a read.
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9.6
Ethernet Interface Registers
The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters
as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers
below are used to perform indirect read or write operations to the MAC registers. The MAC Status Registers are
shown in Table 9-7. Accessing the MAC Registers is described in the Section 8.14.
9.6.1
Ethernet Interface Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACRA7
0
SU.MACRADL
MAC Read Address Low Register
140h
6
MACRA6
0
5
MACRA5
0
4
MACRA4
0
3
MACRA3
0
2
MACRA2
0
1
MACRA1
0
0
MACRA0
0
Bits 0 – 7: MAC Read Address (MACRA0-7) Low byte of the MAC address. Used only for read operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACRA1
5
0
SU.MACRADH
MAC Read Address High Register
141h
6
MACRA1
4
0
5
MACRA1
3
0
4
MACRA1
2
0
3
MACRA1
1
0
2
MACRA1
0
0
1
MACRA9
0
MACRA8
0
0
Bits 0 – 7: MAC Read Address (MACRA8-15) High byte of the MAC address. Used only for read operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACRD7
0
SU.MACRD0
MAC Read Data Byte 0
142h
6
MACRD6
0
5
MACRD5
0
4
MACRD4
0
3
MACRD3
0
2
MACRD2
0
1
MACRD1
0
0
MACRD0
0
Bits 0 – 7: MAC Read Data 0 (MACRD0-7) One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MACRWC.MCS bit is zero.
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Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACRD1
5
0
SU.MACRD1
MAC Read Data Byte 1
143h
6
MACRD1
4
0
5
MACRD1
3
0
4
MACRD1
2
0
3
MACRD1
1
0
2
MACRD1
0
0
1
MACRD9
0
MACRD8
0
0
Bits 0 - 7: MAC Read Data 1 (MACRD8-15) One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MACRWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACRD2
3
0
SU.MACRD2
MAC Read Data Byte 2
144h
6
MACRD2
2
0
5
MACRD2
1
0
4
MACRD2
0
0
3
MACRD1
9
0
2
MACRD1
8
0
1
MACRD1
7
0
0
MACRD1
6
0
Bits 0 – 7: MAC Read Data 2 (MACRD16-23) One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MACRWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACRD3
1
0
SU.MACRD3
MAC Read Data byte 3
145h
6
MACRD3
0
0
5
MACRD2
9
0
4
MACRD2
8
0
3
MACRD2
7
0
2
MACRD2
6
0
1
MACRD2
5
0
0
MACRD2
4
0
Bits 0 – 7: MAC Read Data 3 (MACRD24-31) One of four bytes of data read from the MAC. Valid after a read
command has been issued and the SU.MACRWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACWD7
0
SU.MACWD0
MAC Write Data 0
146h
6
MACWD6
0
5
MACWD5
0
4
MACWD4
0
3
MACWD3
0
2
MACWD2
0
1
MACWD1
0
0
MACWD0
0
Bits 0 – 7: MAC Write Data 0 (MACWD0-7) One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MACRWC.MCS bit is zero.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
MACWD1
5
0
SU.MACWD1
MAC Write Data 1
147h
6
MACWD1
4
0
5
MACWD1
3
0
4
MACWD1
2
0
3
MACWD1
1
0
2
MACWD1
0
0
1
MACWD0
9
0
0
MACWD0
8
0
Bits 0 – 7: MAC Write Data 1 (MACWD8-15) One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MACRWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACWD2
3
0
SU.MACWD2
MAC Write Data Register 2
148h
6
MACWD2
2
0
5
MACWD2
1
0
4
MACWD2
0
0
3
MACWD1
9
0
2
MACWD1
8
0
1
MACWD1
7
0
0
MACWD16
0
Bits 0 - 7: MAC Write Data 2 (MACWD16-23) One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MACRWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACD31
0
SU.MACWD3
MAC Write Data 3
149h
6
MACD30
0
5
MACD29
0
4
MACD28
0
3
MACD27
0
2
MACD26
0
1
MACD25
0
0
MACD24
0
Bits 0 – 7: MAC Write Data 3 (MACD24-31) One of four bytes of data to be written to the MAC. Data has been
written after a write command has been issued and the SU.MACRWC.MCS bit is zero.
Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACAW 7
0
SU.MACAWL
MAC Address Write Low
14Ah
6
MACAW 6
0
5
MACAW 5
0
4
MACAW4
0
3
MACAW3
0
2
MACAW2
0
1
MACAW1
0
0
MACAW0
0
Bits 0 -7: MAC Write Address (MACAW0-7) Low byte of the MAC address. Used only for write operations.
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Register Name:
Register Description:
Register Address:
Bit #
Name
7
MACAW
15
0
SU.MACAWH
MAC Address Write High
14Bh
6
MACAW
14
0
5
MACAW
13
0
4
MACAW1
2
0
3
MACAW1
1
0
2
MACAW1
0
0
1
MACAW9
0
MACAW8
0
0
Bits 0 – 7: MAC Write Address (MACAW8-15) High byte of the MAC address. Used only for write operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
SU.MACRWC
MAC Read Write Command Status
14Ch
6
0
5
0
4
0
3
0
2
0
1
MCRW
0
0
MCS
0
Bit 1: MAC Command RW (MCRW) If this bit is written to 1, a read is performed from the MAC. If this bit is
written to 0, a write operation is performed. Address information for write operations must be located in
SU.MACAWH and SU.MACAWL. Address information for read operations must be located in SU.MACRADH and
SU.MACRADL. The user must also write a 1 to the MCS bit, and the DS33Z11 will clear MCS when the operation
is complete.
Bit 0: MAC Command Status (MCS) Setting MCS in conjunction with MCRW will initiate a read or write to the
MAC registers. Upon completion of the read or write this bit is cleared. Once a read or write command has been
initiated the host must poll this bit to see when the operation is complete.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
SU.LPBK
Ethernet Interface Loopback Control Register
14Fh
6
0
5
0
4
0
3
0
2
0
1
0
0
QLP
0
Bit 0: Queue Loopback Enable (QLP) If this bit is set to 1, data from the Ethernet Interface receive queue is
looped back to the transmit queue. Buffered data from the serial interface will remain until the loopback is
removed.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
SU.GCR
Ethernet Interface General Control Register
150h
6
0
5
0
4
0
3
CRCS
0
2
H10S
0
1
ATFLOW
1
0
JAME
0
Bit 3: CRCS If this bit is zero (default), the received MAC or Ethernet Frame CRC is stripped before the data is
encapsulated and transmitted on the serial interface. Data received from the serial interface is decapsulated, a
CRC is recalculated and appended to the packet for transmission to the Ethernet interface. If this bit is set to 1,
the CRC is not stripped from received packets prior to encapsulation and transmission to the serial interface, and
data received from the serial interface is decapsulated directly. No CRC recalculation is performed on data
received from the serial interface. Note that the maximum packet size supported by the Ethernet interface is still
2016 (this includes the 4 bytes of CRC).
Bit 2: H10S This bit controls the 10/100 selection for RMII and DCE Mode. When in RMII mode, setting this bit
to 1 will cause the MAC will operate at 100 Mbps and setting this bit to zero will cause the MAC to operate at 10
Mbps. When in DCE mode, the bit function is inverted – setting this bit to 1 will cause the MAC to operate at 10
Mbps. In DTE and MII mode, the MAC determines the data rate from the incoming TX_CLK and RX_CLK.
Bit 1: Automatic Flow Control Enable (ATFLOW) If this bit is set to 1, automatic flow control is enabled based
on the connection receive queue size and high watermarks. Pause frames are sent automatically in full duplex
mode. The pause time must be programmed through SU.MACFCR. The jam sequence will not be sent
automatically in half duplex mode unless the JAME bit is set. This bit is applicable only in software mode.
Bit 0: Jam Enable (JAME) If this bit is set to 1, a Jam sequence is sent for a duration of 4 bytes. This function is
only valid in half duplex mode, and will only function if Automatic Flow Control is disabled. Note that if the receive
queue size is less than receive high threshold, setting a JAME will JAM one received frame. If JAME is set and
the receiver queue size is higher than the high threshold, all received frames are jammed until the queue empties
below the threshold.
Note that SU.GCR is only valid in the software mode. In hardware mode, pins are used to control Automatic flow
control and 100/10-speed selection.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
SU.TFRC
Transmit Frame Resend Control
151h
6
0
5
0
4
0
3
NCFQ
0
2
TPDFCB
0
1
TPRHBC
0
0
TPRCB
0
Bit 3: No Carrier Queue Flush Bar (NCFQ) If this bit is set to 1, the queue for data passing from Serial Interface
to Ethernet Interface will not be flushed when loss of carrier is detected.
Bit 2: Transmit Packet Deferred Fail Control Enable (TPDFCB) If this bit if set to 1, the current frame is
transmitted immediately instead of being deferred. If this bit is set to 0, the frame is deferred if CRS is asserted
and sent when the CRS is unasserted indicating the media is idle.
Bit 1: Transmit Packet HB Fail Control Bar (TPRHBC) If this bit is set to 1, the current frame will not be
retransmitted if a heartbeat failure is detected.
Bit 0: Transmit Packet Resend Control Bar (TPRCB) If this bit is set to 1, the current frame will not be
retransmitted if any of the following errors have occurred:
•
Jabber time out
•
Loss of carrier
•
Excessive deferral
•
Late collision
•
Excessive collisions
•
Under run
•
Collision
Note that blocking retransmission due to collision (applicable in MIII/Half Duplex Mode) can result in
unpredictable system level behavior.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
UR
0
SU.TFSL
Transmit Frame Status Low
152h
6
EC
0
5
LC
0
4
ED
0
3
LOC
0
2
NOC
0
1
0
0
FABORT
0
Bit 7: Under Run (UR) When this bit is set to 1, the frame was aborted due to a data under run condition of the
transmit buffer.
Bit 6: Excessive Collisions (EC) When this bit is set to 1, a frame has been aborted after 16 successive
collisions while attempting to transmit the current frame. If the Disable Retry bit is set to 1, then Excessive
Collisions will be set to 1 after the first collision.
Bit 5: Late Collision (LC) When this bit is set to 1, a frame was aborted by collision after the 64-bit collision
window. Not valid if an under run has occurred.
Bit 4: Excessive Deferral (ED) When this bit is set to 1, a frame was aborted due to excessive deferral.
Bit 3: Loss Of Carrier (LOC) When this bit is set to 1, a frame was aborted due to loss of carrier for one or more
bit times. Valid only for non-collided frames. Valid only in half-duplex operation.
Bit 2: No Carrier (NOC) When this bit is set to 1, a frame was aborted because no carrier was found for
transmission.
Bit 1: Reserved
Bit 0: Frame Abort (FABORT) When this bit is set to 1, the MAC has aborted a frame for one of the above
reasons. When this bit is clear, the previous frame has been transmitted successfully.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
PR
0
SU.TFSH
Transmit Frame Status High
153h
6
HBF
0
5
CC3
0
4
CC2
0
3
CC1
0
2
CC0
0
1
LCO
0
0
DEF
0
Bit 7: Packet Resend (PR) When this bit is set, the current packet must be retransmitted due to a collision.
Bit 6: Heartbeat Failure (HBF) When this bit is set, the device failed to detect a heart beat after transmission.
This bit is not valid if an under run has occurred.
Bits 2-5: Collision Count (CC0-3) These 4 bits indicate the number of collisions that occurred prior to successful
transmission of the previous frame. Not valid if Excessive Collisions is set to 1.
Bit 1: Late Collision (LCO) When set to 1, the MAC observed a collision after the 64-byte collision window.
Bit 0: Deferred Frame (DEF) When set to 1, the current frame was deferred due to carrier assertion by another
node after being ready to transmit.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
FL7
0
SU.RFSB0
Receive Frame Status Byte 0
154h
6
FL6
0
5
FL5
0
4
FL4
0
3
FL3
0
2
FL2
0
1
FL1
0
0
FL0
0
Bits 0 - 7: Frame Length (FL[0:7]) These 8 bits are the low byte of the length (in bytes) of the received frame,
with FCS and Padding. If Automatic Pad Stripping is enabled, this value is the length of the received packet
without PCS or Pad bytes. The upper 6 bits are contained in SU.RFSB1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RF
0
SU.RFSB1
Receive Frame Status Byte 1
155h
6
WT
0
5
FL13
0
4
FL12
0
3
FL11
0
2
FL10
0
1
FL9
0
0
FL8
0
Bit 7: Runt Frame (RF) This bit is set to 1 if the received frame was altered by a collision or terminated within the
collision window.
Bit 6: Watchdog Timeout (WT) This bit is set to 1 if a packet receive time exceeds 2048 byte times. After 2048
byte times the receiver is disabled and the received frame will fail CRC check.
Bits 0-5: Frame Length (FL[8:13]) These 6 bits are the upper bits of the length (in bytes) of the received frame,
with FCS and Padding. If Automatic Pad Stripping is enabled, this value is the length of the received packet
without PCS or Pad bytes.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
SU.RFSB2
Receive Frame Status Byte 2
156h
6
0
5
CRCE
0
4
DB
0
3
MIIE
0
2
FT
0
1
CS
0
0
FTL
0
Bit 5: CRC Error (CRCE) This bit is set to 1 if the received frame does not contain a valid CRC value.
Bit 4: Dribbling Bit (DB) This bit is set to 1 if the received frame contains a non-integer multiple of 8 bits. It does
not indicate that the frame is invalid. This bit is not valid for runt or collided frames.
Bit 3: MII Error (MIIE) This bit is set to 1 if an error was found on the MII bus.
Bit 2: Frame Type (FT) This bit is set to 1 if the received frame exceeds 1536 bytes. It is equal to zero if the
received frame is an 802.3 frame. This bit is not valid for runt frames.
Bit 1: Collision Seen (CS) This bit is set to 1 if a late collision occurred on the received packet. A late collision is
one that occurs after the 64-byte collision window.
Bit 0: Frame Too Long (FTL) This bit is set to 1 if a frame exceeds the 1518 byte maximum standard Ethernet
frame. This bit is only an indication, and causes no frame truncation.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
MF
0
SU.RFSB3
Receive Frame Status Byte 3
157h
6
0
5
0
4
BF
0
3
MCF
0
2
UF
0
1
CF
0
0
LE
0
Bit 7: Missed Frame (MF) This bit is set to 1 if the packet is not successfully received from the MAC by the
packet Arbiter.
Bit 4: Broadcast Frame (BF) This bit is set to 1 if the current frame is a broadcast frame.
Bit 3: Multicast Frame (MCF) This bit is set to 1 if the current frame is a multicast frame.
Bit 2: Unsupported Control Frame (UF) This bit is set to 1 if the frame received is a control frame with an
opcode that is not supported. If the Control Frame bit is set, and the Unsupported Control Frame bit is clear, then
a pause frame has been received and the transmitter is paused.
Bit 1: Control Frame (CF) This bit is set to 1 when the current frame is a control frame. This bit is only valid in
full-duplex mode.
Bit 0: Length Error (LE) This bit is set to 1 when the frames length field and the actual byte count are unequal.
This bit is only valid for 802.3 frames.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RMPS7
1
SU.RMFSRL
Receiver Maximum Frame Low Register
158h
6
RMPS6
1
5
RMPS5
1
4
RMPS4
0
3
RMPS3
0
2
RMPS2
0
1
RMPS1
0
0
RMPS0
0
Bits 7- 0: Receiver Maximum Frame (RMPS[0:7]) Eight bits of sixteen-bit value. Register description below.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RMPS15
0
SU.RMFSRH
Receiver Maximum Frame High Register
159h
6
RMPS14
0
5
RMPS13
0
4
RMPS12
0
3
RMPS11
0
2
RMPS10
1
1
RMPS9
1
0
RMPS8
1
Bits 7- 0: Receiver Maximum Frame (RMPS[8:15]) This value is the receiver’s maximum frame size (in bytes),
up to a maximum of 2016 bytes. Any frame received greater than this value is rejected. The frame size includes
destination address, source address, type/length, data and crc-32. The frame size is not the same as the frame
length encoded within the IEEE 802.3 frame. Any values programmed that are greater than 2016 will have
unpredictable behavior and should be avoided.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RQLT7
0
SU.RQLT
Receive Queue Low Threshold (Watermark)
15Ah
6
RQLT6
0
5
RQLT5
0
4
RQLT4
0
3
RQLT3
0
2
RQLT2
0
1
RQLT1
0
0
RQLT0
0
Bits 0 - 7: Receive Queue Low Threshold (RQLT[0:7]) The receive queue low threshold for the connection, in
increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
determine the byte location of the threshold. Note that the receive queue is for data that was received from the
Ethernet Interface to be sent to the Serial Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RQHT7
0
SU.RQHT
Receive Queue High Threshold (Watermark)
15Bh
6
RQHT6
0
5
RQHT5
0
4
RQHT4
0
3
RQHT3
0
2
RQHT2
0
1
RQHT1
0
0
RQHT0
0
Bits 0 – 7: Receive Queue High Threshold (RQTH[0:7]) The receive queue high threshold for the connection,
in increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
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determine the byte location of the threshold. Note that the receive queue is for data that was received from the
Ethernet Interface to be sent to the Serial Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
SU.QRIE
Receive Queue Cross Threshold enable
15Ch
7
0
6
0
5
0
4
0
3
RFOVFIE
0
2
RQVFIE
0
1
RQLTIE
0
0
RQHTIE
0
Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE) If this bit is set, the interrupt is enabled for
RFOVFLS.
Bit 2: Receive Queue Overflow Interrupt Enable (RQVFIE) If this bit is set, the interrupt is enabled for
RQOVFLS.
Bit 1: Receive Queue Crosses Low Threshold Interrupt Enable (RQLTIE) If this bit is set, the watermark
interrupt is enabled for RQLTS.
Bit 0: Receive Queue Crosses High Threshold Interrupt Enable (RQHTIE) If this bit is set, the watermark
interrupt is enabled for RQHTS.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
-
SU.QCRLS
Queue Cross Threshold Latched Status
15Dh
6
-
5
-
4
-
3
RFOVFLS
-
2
RQOVFLS
-
1
RQHTLS
-
0
RQLTLS
-
Bit 3: Receive FIFO Overflow latched Status (RFOVFLS) This bit is set if the receive FIFO overflows for the
data to be transmitted from the MAC to the SDRAM.
Bit 2: Receive Queue Overflow Latched Status (RQOVFLS) This bit is set if the receive queue has overflowed.
This register is cleared after a read.
Bit 1: Receive Queue for Connection Crossed High Threshold Latched Status (RQHTLS) This bit is set if the
receive queue crosses the high Watermark. This register is cleared after a read.
Bit 0: Receive Queue for Connection Crossed Low Threshold latched status (RQLTLS) This bit is set if the
receive queue crosses the low Watermark. This register is cleared after a read.
Note the bit order differences in the high/low threshold indications in SU.QCRLS and the interrupt enables in
SU.QRIE.
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
0
SU.RFRC
Receive Frame Rejection Control
15Eh
6
UCFR
0
5
CFRR
0
4
LERR
0
3
CRCERR
0
2
DBR
0
1
MIIER
0
0
BFR
0
Bit 6: Uncontrolled Control Frame Reject (UCFR) When set to 1, Control Frames other than Pause Frames are
allowed. When this bit is equal to zero, non-pause control frames are rejected.
Bit 5: Control Frame Reject (CFRR) When set to 1, control frames are allowed. When this bit is equal to zero, all
control frames are rejected.
Bit 4: Length Error Reject (LERR) When set to 1, frames with an unmatched frame length field and actual
number of bytes received are allowed. When equal to zero, only frames with matching length fields and actual
bytes received will be allowed.
Bit 3: CRC Error Reject (CRCERR) When set to 1, frames received with a CRC error or MII error are allowed.
When equal to zero, frames with CRC or MII errors are rejected.
Bit 2: Dribbling Bit Reject (DBR) When set to 1, frames with lengths of non-integer multiples of 8 bits are
allowed. When equal to zero, frames with dribbling bits are rejected. The dribbling bit setting is only valid only if
there is not a collision or runt frame.
Bit 1: MII Error Reject (MIIER) When set to 1, frames are allowed with MII Receive Errors. When equal to zero,
frames with MII errors are rejected.
Bit 0: Broadcast Frame Reject (BFR) When set to 1, broadcast frames are allowed. When equal to zero,
broadcast frames are rejected.
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9.6.2
MAC Registers
The control Registers related to the control of the individual Mac’s are shown in the following table. The DS33Z11
keeps statistics for the packet traffic sent and received. The register address map is shown in the following table.
Note that the addresses listed are the indirect addresses that must be provided to SU.MACRADH/SU.MACRADL
or SU.MACAWH/SU.MACAWL.
Register Name:
Register Description:
Register Address:
SU.MACCR
MAC Control Register
0000h (indirect)
0000h:
Bit #
Name
Default
31
Reserved
0
30
Reserved
0
29
Reserved
0
28
HDB
0
27
PS
0
26
Reserved
0
25
Reserved
0
24
Reserved
0
0001h:
Bit #
Name
Default
23
DRO
0
22
Reserved
0
21
OML0
0
20
F
0
19
PM
1
18
PAM
0
17
Reserved
0
16
Reserved
0
0002h:
Bit #
Name
Default
15
Reserved
0
14
Reserved
0
13
Reserved
0
12
LCC
0
11
Reserved
0
10
DRTY
0
09
Reserved
0
08
ASTP
0
0003h:
Bit #
Name
Default
07
BOLMT1
0
06
BOLMT0
0
05
DC
0
04
Reserved
0
03
TE
0
02
RE
0
01
Reserved
0
00
Reserved
0
Bit 28: Heartbeat Disable (HDB) When set to 1, the heartbeat (SQE) function is disabled. This bit should be set
to 1 when operating in MII mode.
Bit 27: Port Select (PS) This bit should be equal to 0 for proper operation.
Bit 23: Disable Receive Own (DRO) When set to 1, the MAC disables the reception of frames while TX_EN is
asserted. When this bit equals zero, transmitted frames are also received by the MAC. This bit should be cleared
when operating in full-duplex mode. This bit must be set to 1 for half-duplex operation.
Bit 21: Loopback Operating Mode (OMLO) When set to 1, data is looped from the transmit side, back to the
receive side, without being transmitted to the PHY.
Bit 20: Full-Duplex Mode Select (F) When set to 1, the MAC transmits and receives data simultaneously. When
in full-duplex mode, the heartbeat check is disabled and the heartbeat fail status should be ignored.
Bit 19: Promiscuous Mode (PM) When set to 1, the MAC is in Promiscuous Mode and forwards all frames. Note
that the default value is 1.
Bit 18: Pass All Multicast (PAM) When set to 1, the MAC forwards Multicast Frames.
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Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the
collision period. When this bit is clear, retransmission of late collisions is disabled.
Bit 10: Disable Retry (DRTY) When set to 1, the MAC makes only a single attempt to transmit each frame. If a
collision occurs, the MAC ignores the current frame and proceeds to the next frame. When this bit equals 0, the
MAC will retry collided packets 16 times before signaling a retry error.
Bit 8: Automatic Pad Stripping (ASTP) When set to 1, all incoming frames with less than 46 byte length are
automatically stripped of the pad characters and FCS.
Bits 6 - 7: Back-Off Limit (BOLMT[0:1]) These two bits allow the user to set the back-off limit used for the
maximum retransmission delay for collided packets. Default operation limits the maximum delay for
retransmission to a countdown of 10 bits from a random number generator. The user can reduce the maximum
number of counter bits as described in the table below. See IEEE 802.3 for details of the back-off algorithm.
Bit 7
0
0
1
1
Bit 6
0
1
0
1
Random Number Generator Bits Used
10
8
4
1
Bit 5: Deferral Check (DC) When set to 1, the MAC will abort packet transmission if it has deferred for more than
24,288 bit times. The deferral counter starts when the transmitter is ready to transmit a packet, but is prevented
from transmission because CRS is active. If the MAC begins transmission but a collision occurs after the
beginning of transmission, the deferral counter is reset again. If this bit is equal to zero, then the MAC will defer
indefinitely.
Bit 3: Transmitter Enable (TE) When set to 1, packet transmission is enabled. When equal to zero, transmission
is disabled.
Bit 2: Receiver Enable (RE) When set to 1, packet reception is enabled. When equal to zero, packets are not
received.
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Register Name:
Register Description:
Register Address:
SU.MACAH
MAC Address High Register
0004h (indirect)
0004h:
Bit #
Name
Default
31
Reserved
1
30
Reserved
1
29
Reserved
1
28
Reserved
1
27
Reserved
1
0005h:
Bit #
Name
Default
23
Reserved
1
22
Reserved
1
21
Reserved
1
20
Reserved
1
19
Reserved
1
0006h:
Bit #
Name
Default
15
PADR47
1
14
PADR46
1
13
PADR45
1
12
PADR44
1
0007h:
Bit #
Name
Default
07
PADR39
1
06
PADR38
1
05
PADR37
1
04
PADR36
1
26
Reserved
1
25
Reserved
1
24
Reserved
1
18
Reserved
1
17
Reserved
1
16
Reserved
1
11
PADR43
1
10
PADR42
1
09
PADR41
1
08
PADR40
1
03
PADR35
1
02
PADR34
1
01
PADR33
1
00
PADR32
1
Bits 00 – 31: PADR[32:47] These 32 bits should be initialized with the upper 4 bytes of the Physical Address for
this MAC device.
Register Name:
Register Description:
Register Address:
SU.MACAL
MAC Address Low Register
0008h (indirect)
0008h:
Bit #
Name
Default
31
PADR31
1
30
PADR30
1
29
PADR29
1
28
PADR28
1
27
PADR27
1
26
PADR26
1
25
PADR25
1
24
PADR24
1
0009h:
Bit #
Name
Default
23
PADR23
1
22
PADR22
1
21
PADR21
1
20
PADR20
1
19
PADR19
1
18
PADR18
1
17
PADR17
1
16
PADR16
1
000Ah:
Bit #
Name
Default
15
PADR15
1
14
PADR14
1
13
PADR13
1
12
PADR12
1
11
PADR11
1
10
PADR10
1
09
PADR09
1
08
PADR08
1
000Bh:
Bit #
Name
Default
07
PADR07
1
06
PADR06
1
05
PADR05
1
04
PADR04
1
03
PADR03
1
02
PADR02
1
01
PADR01
1
00
PADR00
1
Bits 00 – 31: PADR[00:31] These 32 bits should be initialized with the lower 4 bytes of the Physical Address for
this MAC device.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
SU.MACMIIA
MAC MII Management (MDIO) Address Register
0014h (indirect)
0014h:
Bit #
Name
Default
31
Reserved
0
30
Reserved
0
29
Reserved
0
28
Reserved
0
27
Reserved
0
26
Reserved
0
25
Reserved
0
24
Reserved
0
0015h:
Bit #
Name
Default
23
Reserved
0
22
Reserved
0
21
Reserved
0
20
Reserved
0
19
Reserved
0
18
Reserved
0
17
Reserved
0
16
Reserved
0
0016h:
Bit #
Name
Default
15
PHYA4
0
14
PHYA3
1
13
PHYA2
0
12
PHYA1
1
11
PHYA0
1
10
MIIA4
0
09
MIIA3
1
08
MIIA2
0
0017h:
Bit #
Name
Default
07
MIIA1
1
06
MIIA0
1
05
Reserved
0
04
Reserved
0
03
Reserved
0
02
Reserved
0
01
MIIW
0
00
MIIB
0
Bits 11 - 15: PHY Address (PHYA[0:4]) These 5 bits select one of the 32 available PHY address locations to
access through the PHY management (MDIO) bus.
Bits 6 - 10: MII Address (MIIA[0:4]) - These 5 bits are the address location within the PHY that is being
accessed.
Bit 1: MII Write (MIIW) Write this bit to 1 in order to execute a write instruction over the MDIO interface. Write the
bit to zero to execute a read instruction.
Bit 0: MII Busy (MIIB) This bit is set to 1 by the DS33Z11 during execution of a MII management instruction
through the MDIO interface, and is set to zero when the DS33Z11 has completed the instruction. The user should
read this bit and ensure that it is equal to zero prior to beginning a MDIO instruction.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
SU.MACMIID
MAC MII (MDIO) Data Register
0018h (indirect)
0018h:
Bit #
Name
Default
31
Reserved
0
30
Reserved
0
29
Reserved
0
28
Reserved
0
27
Reserved
0
26
Reserved
0
25
Reserved
0
24
Reserved
0
0019h:
Bit #
Name
Default
23
Reserved
0
22
Reserved
0
21
Reserved
0
20
Reserved
0
19
Reserved
0
18
Reserved
0
17
Reserved
0
16
Reserved
0
001Ah:
Bit #
Name
Default
15
MIID15
0
14
MIID14
0
13
MIID13
0
12
MIID12
0
11
MIID11
0
10
MIID10
0
09
MIID09
0
08
MIID08
0
001Bh:
Bit #
Name
Default
07
MIID07
0
06
MIID06
0
05
MIID05
0
04
MIID04
0
03
MIID03
0
02
MIID02
0
01
MIID01
0
00
MIID00
0
Bits 0 – 15: MII (MDIO) Data (MIID[00:15]) These two bytes contain the data to be written to or the data read
from the MII management interface (MDIO).
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
SU.MACFCR
MAC Flow Control Register
001Ch (indirect)
001Ch:
Bit #
Name
Default
31
PT15
0
30
PT14
0
29
PT13
0
28
PT12
0
27
PT11
0
26
PT10
0
25
PT09
0
24
PT08
0
001Dh:
Bit #
Name
Default
23
PT07
0
22
PT06
1
21
PT05
0
20
PT04
1
19
PT03
0
18
PT02
0
17
PT01
0
16
PT00
0
001Eh:
Bit #
Name
Default
15
Reserved
0
14
Reserved
0
13
Reserved
0
12
Reserved
0
11
Reserved
0
10
Reserved
0
09
Reserved
0
08
Reserved
0
001Fh:
Bit #
Name
07
Reserved
05
Reserved
04
Reserved
03
Reserved
02
Reserved
01
FCE
00
FCB
Default
0
06
Reserve
d
0
0
0
0
0
1
0
Bits 16 - 31: Pause Time (PT[00:15]) These bits are used for the Pause Time Field in transmitted Pause
Frames. This value is the number of time slots the remote node should wait prior to transmission.
Bit 1: Flow Control Enable (FCE) When set to 1, the MAC automatically detects pause frames and will disable
the transmitter for the requested pause time.
Bit 0: Flow Control Busy (FCB) The host can set this bit to 1 in order to initiate transmission of a pause frame.
During transmission of a pause frame, this bit remains set. The DS33Z11 will clear this bit when transmission of
the pause frame has been completed. The user should read this bit and ensure that this bit is equal to zero prior
to initiating a pause frame.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
SU.MMCCTRL
MAC MMC Control Register
0100h (indirect)
0100h:
Bit #
Name
Default
31
Reserved
0
30
Reserved
0
29
Reserved
0
28
Reserved
0
27
Reserved
0
26
Reserved
0
25
Reserved
0
24
Reserved
0
0101h:
Bit #
Name
Default
23
Reserved
0
22
Reserved
0
21
Reserved
0
20
Reserved
0
19
Reserved
0
18
Reserved
0
17
Reserved
0
16
Reserved
0
0102h:
Bit #
Name
15
Reserved
14
Reserved
12
MXFRM9
11
MXFRM8
10
MXFRM7
09
MXFRM6
08
MXFRM5
Default
0
0
13
MXFRM1
0
1
0
1
1
1
1
0103h:
Bit #
Name
Default
07
MXFRM4
0
05
MXFRM2
1
04
MXFRM1
1
03
MXFRM0
0
02
Reserved
0
01
Reserved
1
00
Reserved
0
06
MXFRM3
1
Bits 3 - 13: Maximum Frame Size (MXFRM[0:10]) These bits indicate the maximum packet size value. All
transmitted frames larger than this value are counted as long frames.
Bit 1: Reserved - Note that this bit must be written to a “1” for proper operation.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Reserved
MAC Reserved Control Register
010Ch (indirect)
010Ch:
Bit #
Name
Default
31
Reserved
0
30
Reserved
0
29
Reserved
0
28
Reserved
0
27
Reserved
0
26
Reserved
0
25
Reserved
0
24
Reserved
0
010Dh:
Bit #
Name
Default
23
Reserved
0
22
Reserved
0
21
Reserved
0
20
Reserved
0
19
Reserved
0
18
Reserved
0
17
Reserved
0
16
Reserved
0
010Eh:
Bit #
Name
Default
15
Reserved
0
14
Reserved
0
13
Reserved
0
12
Reserved
0
11
Reserved
0
10
Reserved
0
09
Reserved
0
08
Reserved
0
010Fh:
Bit #
Name
07
Reserved
05
Reserved
04
Reserved
03
Reserved
02
Reserved
01
Reserved
00
Reserved
Default
0
06
Reserve
d
0
0
0
0
0
0
0
Note: Addresses 10Ch through 10Fh must each be initialized with all 1’s (FFh) for proper software-mode
operation.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
Reserved
MAC Reserved Control Register
0110h (indirect)
0110h:
Bit #
Name
Default
31
Reserved
0
30
Reserved
0
29
Reserved
0
28
Reserved
0
27
Reserved
0
26
Reserved
0
25
Reserved
0
24
Reserved
0
0111h:
Bit #
Name
Default
23
Reserved
0
22
Reserved
0
21
Reserved
0
20
Reserved
0
19
Reserved
0
18
Reserved
0
17
Reserved
0
16
Reserved
0
0112h:
Bit #
Name
Default
15
Reserved
0
14
Reserved
0
13
Reserved
0
12
Reserved
0
11
Reserved
0
10
Reserved
0
09
Reserved
0
08
Reserved
0
0113h:
Bit #
Name
07
Reserved
05
Reserved
04
Reserved
03
Reserved
02
Reserved
01
Reserved
00
Reserved
Default
0
06
Reserve
d
0
0
0
0
0
0
0
Note: Addresses 110h through 113h must each be initialized with all 1’s (FFh) for proper software-mode
operation.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
0200h:
Bit #
Name
Default
0201h:
Bit #
Name
Default
0202h:
Bit #
Name
Default
0203h:
Bit #
Name
Default
SU.RxFrmCtr
MAC All Frames Received Counter
0200h (indirect)
31
30
29
28
27
26
25
24
RXFRMC3
1
RXFRMC3
0
RXFRMC2
9
RXFRMC2
8
RXFRMC2
7
RXFRMC2
6
RXFRMC2
5
RXFRMC2
4
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
RXFRMC2
3
RXFRMC2
2
RXFRMC2
1
RXFRMC2
0
RXFRMC1
9
RXFRMC1
8
RXFRMC1
7
RXFRMC1
6
0
0
0
0
0
0
0
0
15
14
13
12
11
10
09
08
RXFRMC1
5
RXFRMC1
4
RXFRMC1
3
RXFRMC1
2
RXFRMC1
1
RXFRMC1
0
RXFRMC9
RXFRMC8
0
0
0
0
0
0
0
0
07
06
05
04
03
02
01
00
RXFRMC7
RXFRMC6
RXFRMC5
RXFRMC4
RXFRMC3
RXFRMC2
RXFRMC1
RXFRMC0
0
0
0
0
0
0
0
0
Bits 0 - 31: All Frames Received Counter (RXFRMC[0:31]) 32 bit value indicating the number of frames
received. Each time a frame is received, this counter is incremented by 1. This counter resets only upon device
reset, does not saturate, and rolls-over to zero upon reaching the maximum value. The user should ensure that
the measurement period is less than the minimum length of time required for the counter to increment 2^32-1
times at the maximum frame rate. The user should store the value from the beginning of the measurement period
for later calculations, and take into account the possibility of a rollover to occurring.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
0204h:
Bit #
Name
Default
0205h:
Bit #
Name
Default
0206h:
Bit #
Name
Default
0207h:
Bit #
Name
Default
SU.RxFrmOkCtr
MAC Frames Received OK Counter
0204h (indirect)
31
30
29
28
27
26
25
24
RXFRMOK
31
RXFRMOK
30
RXFRMOK
29
RXFRMOK
28
RXFRMOK
27
RXFRMOK
26
RXFRMOK
25
RXFRMOK
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
RXFRMOK
23
RXFRMOK
22
RXFRMOK
21
RXFRMOK
20
RXFRMOK
19
RXFRMOK
18
RXFRMOK
17
RXFRMOK
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
09
08
RXFRMOK
15
RXFRMOK
14
RXFRMOK
13
RXFRMOK
12
RXFRMOK
11
RXFRMOK
10
RXFRMOK
9
RXFRMOK
8
0
0
0
0
0
0
0
0
07
06
05
04
03
02
01
00
RXFRMOK
7
RXFRMOK
6
RXFRMOK
5
RXFRMOK
4
RXFRMOK
3
RXFRMOK
2
RXFRMOK
1
RXFRMOK
0
0
0
0
0
0
0
0
0
Bits 0 - 31: Frames Received OK Counter (RXFRMOK[0:31]) 32 bit value indicating the number of frames
received and determined to be valid. Each time a valid frame is received, this counter is incremented by 1. This
counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum
value. The user should ensure that the measurement period is less than the minimum length of time required for
the counter to increment 2^32-1 times at the maximum frame rate. The user should store the value from the
beginning of the measurement period for later calculations, and take into account the possibility of a rollover to
occurring.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
0300h:
Bit #
Name
Default
0301h:
Bit #
Name
Default
0302h:
Bit #
Name
Default
0303h:
Bit #
Name
Default
SU.TxFrmCtr
MAC All Frames Transmitted Counter
0300h (indirect)
31
30
29
28
27
26
25
24
TXFRMC3
1
TXFRMC3
0
TXFRMC2
9
TXFRMC2
8
TXFRMC2
7
TXFRMC2
6
TXFRMC2
5
TXFRMC2
4
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
TXFRMC2
3
TXFRMC2
2
TXFRMC2
1
TXFRMC2
0
TXFRMC1
9
TXFRMC1
8
TXFRMC1
7
TXFRMC1
6
0
0
0
0
0
0
0
0
15
14
13
12
11
10
09
08
TXFRMC1
5
TXFRMC1
4
TXFRMC1
3
TXFRMC1
2
TXFRMC1
1
TXFRMC1
0
TXFRMC9
TXFRMC8
0
0
0
0
0
0
0
0
07
06
05
04
03
02
01
00
TXFRMC7
TXFRMC6
TXFRMC5
TXFRMC4
TXFRMC3
TXFRMC2
TXFRMC1
TXFRMC0
0
0
0
0
0
0
0
0
Bits 0 - 31: All Frames Transmitted Counter (TXFRMC[0:31]) 32 bit value indicating the number of frames
transmitted. Each time a frame is transmitted, this counter is incremented by 1. This counter resets only upon
device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. The user should ensure
that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1
times at the maximum frame rate. The user should store the value from the beginning of the measurement period
for later calculations, and take into account the possibility of a rollover to occurring.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
0308h:
Bit #
Name
Default
0309h:
Bit #
Name
Default
030Ah:
Bit #
Name
Default
030Bh:
Bit #
Name
Default
SU.TxBytesCtr
MAC All Bytes Transmitted Counter
0308h (indirect)
31
30
29
28
27
26
25
24
TXBYTEC3
1
TXBYTEC3
0
TXBYTEC2
9
TXBYTEC2
8
TXBYTEC2
7
TXBYTEC2
6
TXBYTEC2
5
TXBYTEC2
4
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
TXBYTEC2
3
TXBYTEC2
2
TXBYTEC2
1
TXBYTEC2
0
TXBYTEC1
9
TXBYTEC1
8
TXBYTEC1
7
TXBYTEC1
6
0
0
0
0
0
0
0
0
15
14
13
12
11
10
09
08
TXBYTEC1
5
TXBYTEC1
4
TXBYTEC1
3
TXBYTEC1
2
TXBYTEC1
1
TXBYTEC1
0
TXBYTEC9
TXBYTEC8
0
0
0
0
0
0
0
0
07
06
05
04
03
02
01
00
TXBYTEC7
TXBYTEC6
TXBYTEC5
TXBYTEC4
TXBYTEC3
TXBYTEC2
TXBYTEC1
TXBYTEC0
0
0
0
0
0
0
0
0
Bits 0 - 31: All Bytes Transmitted Counter (TXBYTEC[0:31]) 32 bit value indicating the number of bytes
transmitted. Each time a byte is transmitted, this counter is incremented by 1. This counter resets only upon
device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. The user should ensure
that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1
times at the maximum data rate. The user should store the value from the beginning of the measurement period
for later calculations, and take into account the possibility of a rollover to occurring.
138 of 172
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
030Ch:
Bit #
Name
Default
030Dh:
Bit #
Name
Default
030Eh:
Bit #
Name
Default
030Fh:
Bit #
Name
Default
SU.TxBytesOkCtr
MAC Bytes Transmitted OK Counter
030Ch (indirect)
31
30
29
28
27
26
25
24
TXBYTEOK
31
TXBYTEOK
30
TXBYTEOK
29
TXBYTEOK
28
TXBYTEOK
27
TXBYTEOK
26
TXBYTEOK
25
TXBYTEOK
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
TXBYTEOK
23
TXBYTEOK
22
TXBYTEOK
21
TXBYTEOK
20
TXBYTEOK
19
TXBYTEOK
18
TXBYTEOK
17
TXBYTEOK
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
09
08
TXBYTEOK
15
TXBYTEOK
14
TXBYTEOK
13
TXBYTEOK
12
TXBYTEOK
11
TXBYTEOK
10
TXBYTEOK
9
TXBYTEOK
8
0
0
0
0
0
0
0
0
07
06
05
04
03
02
01
00
TXBYTEOK
7
TXBYTEOK
6
TXBYTEOK
5
TXBYTEOK
4
TXBYTEOK
3
TXBYTEOK
2
TXBYTEOK
1
TXBYTEOK
0
0
0
0
0
0
0
0
0
Bits 0 - 31: Bytes Transmitted OK Counter (TXBYTEOK[0:31]) 32 bit value indicating the number of bytes
transmitted and determined to be valid. Each time a valid byte is transmitted, this counter is incremented by 1.
This counter resets only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum
value. The user should ensure that the measurement period is less than the minimum length of time required for
the counter to increment 2^32-1 times at the maximum frame rate. The user should store the value from the
beginning of the measurement period for later calculations, and take into account the possibility of a rollover to
occurring.
139 of 172
DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
0334h:
Bit #
Name
Default
0335h:
Bit #
Name
Default
0336h:
Bit #
Name
Default
0337h:
Bit #
Name
Default
31
SU.TXFRMUNDR
MAC Transmit Frame Under Run Counter
0334h (indirect)
30
29
28
27
26
25
24
TXFRMU3
1
TXFRMU30
TXFRMU2
9
TXFRMU28
TXFRMU2
7
TXFRMU26
TXFRMU2
5
TXFRMU2
4
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
TXFRMU2
3
TXFRMU22
TXFRMU2
1
TXFRMU20
TXFRMU1
9
TXFRMU18
TXFRMU1
7
TXFRMU1
6
0
0
0
0
0
0
0
0
15
14
13
12
11
10
09
08
TXFRMU1
5
TXFRMU14
TXFRMU1
3
TXFRMU12
TXFRMU1
1
TXFRMU10
TXFRMU9
TXFRMU8
0
0
0
0
0
0
0
0
07
06
05
04
03
02
01
00
TXFRMU7
TXFRMU6
TXFRMU5
TXFRMU4
TXFRMU3
TXFRMU2
TXFRMU1
TXFRMU0
0
0
0
0
0
0
0
0
Bits 0 - 31: Frames Aborted Due to FIFO Under Run Counter (TXFRMU[0:31]) 32 bit value indicating the
number of frames aborted due to FIFO under run. Each time a frame is aborted due to FIFO under run, this
counter is incremented by 1. This counter resets only upon device reset, does not saturate, and rolls-over to zero
upon reaching the maximum value. The user should ensure that the measurement period is less than the
minimum length of time required for the counter to increment 2^32-1 times at the maximum frame rate. The user
should store the value from the beginning of the measurement period for later calculations, and take into account
the possibility of a rollover to occurring.
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DS33Z11 Ethernet Mapper
Register Name:
Register Description:
Register Address:
0338h:
Bit #
Name
Default
0339h:
Bit #
Name
Default
033Ah:
Bit #
Name
Default
033Bh:
Bit #
Name
Default
SU.TxBdFrmCtr
MAC All Frames Aborted Counter
0338h (indirect)
31
30
29
28
27
26
25
24
TXFRMBD
31
TXFRMBD
30
TXFRMBD
29
TXFRMBD
28
TXFRMBD
27
TXFRMBD
26
TXFRMBD
25
TXFRMBD
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
TXFRMBD
23
TXFRMBD
22
TXFRMBD
21
TXFRMBD
20
TXFRMBD
19
TXFRMBD
18
TXFRMBD
17
TXFRMBD
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
09
08
TXFRMBD
15
TXFRMBD
14
TXFRMBD
13
TXFRMBD
12
TXFRMBD
11
TXFRMBD
10
TXFRMBD
9
TXFRMBD
8
0
0
0
0
0
0
0
0
07
06
05
04
03
02
01
00
TXFRMBD
7
TXFRMBD
6
TXFRMBD
5
TXFRMBD
4
TXFRMBD
3
TXFRMBD
2
TXFRMBD
1
TXFRMBD
0
0
0
0
0
0
0
0
0
Bits 0 to 31: All Frames Aborted Counter (TXFRMBD[0:31]) 32 bit value indicating the number of frames
aborted due to any reason. Each time a frame is aborted, this counter is incremented by 1. This counter resets
only upon device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. The user
should ensure that the measurement period is less than the minimum length of time required for the counter to
increment 2^32-1 times at the maximum frame rate. The user should store the value from the beginning of the
measurement period for later calculations, and take into account the possibility of a rollover to occurring.
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DS33Z11 Ethernet Mapper
10 FUNCTIONAL TIMING
10.1 Functional Serial I/O Timing
The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces. TDEN is an
input signal that can be used to enable or block the TSER data. The “shaded bits” are not clocked by the
DS33Z11. The TDEN must occur one bit before the effected bit in the TSER stream. Note that polarity of the
TDEN is selectable through LI.TSLCR. In the figure below, TDEN is active low , allowing the bits to clock and
inactive high, causing the next data bit not be clocked. TCLK can be gapped as shown in the following figure.
Similarly, the receiver function is governed by RCLKI, RDEN and RSER. RSER data will not be provided to the
receiver for the bits blocked when RDEN is inactive. The RDEN polarity can be programmed by LI.RSLCR. The
RDEN signal must be coincident with the RSER bit that needs to be blocked.
Figure 10-1 TX Serial Interface Functional Timing
TCLKI
TDEN
TCLK
gapped
TSER
TCLK Gapped
TSER
TSER
Figure 10-2 RX Serial Interface Functional Timing
RCLKI
RDEN
RSER
RCLK Gapped
RSER
TSER
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DS33Z11 Ethernet Mapper
The DS33Z11 provides the TBSYNC signal as a byte boundary indication to an external interface when X.86
(LAPS) functionality is selected. The functional timing of TBSYNC is shown in the following figure. TBSYNC is
active high on the last bit of the byte being shifted out, and occurs every 8 bits. For the serial receiver interface,
RBSYNC is used to provide byte boundary indication to the DS33Z11 when X.86 (LAPS) mode is used. The
functional timing is shown in Figure 10-3. In X.86 Mode, the receiver expects the RBSYNC byte indicator as
shown in Figure 10-4.
Figure 10-3 Transmit Byte Sync Functional timing
TCLKI
TBYSYNC
TSER
last bit
1st bit
Figure 10-4 Receive Byte Sync Functional Timing
RCLKI
RBYSYNC
RSER
last bit
1st bit
10.2 MII and RMII Interfaces
The MII Interface Transmit Port has its own TX_CLK and data interface. The data TXD [3:0] operates
synchronously with TX_CLK. The LSB is presented first. TX_CLK should be 2.5 MHz for 10 Mbps operation and
25 MHz for 100 Mbps operation. TX_EN is valid at the same time as the first byte of the preamble. In DTE Mode
TX_CLK is input from the external PHY. In DCE Mode, the DS33Z11 provides TX_CLK, derived from an external
reference (SYSCLKI).
In Half-Duplex (DTE) Mode, the DS33Z11 supports CRS and COL signals. CRS is active when the PHY detects
transmit or receive activity. If there is a collision as indicated by the COL input, the DS33Z11 will replace the data
nibbles with jam nibbles. After a “random“ time interval, the packet is retransmitted. The MAC will try to send the
packet a maximum of 16 times. The jam sequence consists of 55555555h. Note that the COL signal and CRS
can be asynchronous to the TX_CLK and are only valid in half duplex mode.
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DS33Z11 Ethernet Mapper
Figure 10-5 MII Transmit Functional Timing
TX_CLK
P
TXD[3:0]
R
E
A
E
M
B
L
F
E
C
S
TX_EN
Figure 10-6 MII Transmit Half Duplex with a Collision Functional Timing
TX_CLK
TXD[3:0]
P
R
E
A
M
B
L
E
J
J
J
J
J
J
J
J
TX_EN
CRS
COL
Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal is
2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation. RX_DV is asserted by the PHY from the first
nibble of the preamble in 100 Mbps operation or first nibble of SFD for 10 Mbps operation. The data on RXD[3:0]
is not accepted by the MAC if RX_DV is low or RX_ERR is high (in DTE mode). RX_ERR should be tied low
when in DCE Mode.
Figure 10-7 MII Receive Functional Timing
RX_CLK
P
RXD[3:0]
R
E
A
E
M
B
L
E
F
C
S
In RMII Mode, TX_EN is high with the first bit of the preamble. The TXD[1:0] is synchronous with the 50 MHz
REF_CLK. For 10 Mbps operation, the data bit outputs are updated every 10 clocks.
Figure 10-8 RMII Transmit Interface Functional Timing
REF_CLK
TXD[1:0]
P
R
E
A
M
B
L
E
F
TX_EN
144 of 172
C
S
DS33Z11 Ethernet Mapper
RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50 MHz REF_CLK. The
data is only valid if CRS_DV is high. The external PHY asynchronously drives CRS_DV low during carrier loss.
Figure 10-9 RMII Receive Interface Functional Timing
REF_CLK
RXD[1:0]
P
R
E
A
M
B
L
E
F
C
S
CRS_DV
10.3 SPI Interface Mode and EEPROM Program Sequence
The DS33Z11 will act as an SPI Master when configured with MODEC[1:0] to read the configuration from an
external Serial EEPROM, such as the Atmel AT25160A. The EEPROM must be programmed with the data
structure shown in Table 10-1. The MOSI (Master Out Slave In) signal can be selectively output on the rising or
falling edge of SPICK. The MISO data can be sampled on rising or falling edge of SPICK based on the CKPHA
pin input. The SPICK is generated by the DS33Z11 at a frequency of 8.33 MHz, derived from an external
SYSCLKI of 100 MHz. The initialization sequence is commenced immediately after power up reset or a rising
edge of the RST input pin. The SPI master initiates a read with the instruction code 0000x011b; followed by the
address location. The SPI_CS is held low until the data addressed is read and latched. The DS33Z11 begins
reading the EEPROM at address 0000h. Data is sequentially latched until the last data byte is read and latched.
The indirect MAC registers require a special program sequence at the end of the EEPROM file. Four MAC
registers can be programmed in the EEPROM Mode: SU.MACCR, SU.MACMIIA, SU.MACMIID, and
SU.MACFCR. All other indirect MAC registers do not need to be initialized for EEPROM mode operation. The
indirect MAC registers are programmed using four separate seven-byte records from the EEPROM. An example
is shown in Table 10-2.
Figure 10-10 SPI Master Functional Timing
0
1
2
3
4
5
6
7
8
9
10
11
20
21
22
23
0
0
00
X
0
1
1
0
0
0
0
0
0
0
0
24
25
26
27
7
6
5
4
28
29
30
31
SPI_CS*
SPICK
CKPHA=0
SPICK
CKPHA=1
MOSI
0
MISO
145 of 172
3
2
1
0
DS33Z11 Ethernet Mapper
Table 10-1 EEPROM Program Memory Map
Functional Block
Address Range for Data in EEPROM (in hex)
Global Registers
000 to 03F
Arbiter Registers
040 to 07F
BERT Registers
080 to 0BF
Serial Interface Tx Registers
0C0 to 0FF
Serial Interface Rx Registers
100 to 13F
Ethernet Interface Registers
140 to 17F
MAC Register Write 1
180 to 186 (special for indirect addresses)
MAC Register Write 2
187 to 18D (special for indirect addresses)
MAC Register Write 3
18E to 194 (special for indirect addresses)
MAC Register Write 4
195 to 19B (special for indirect addresses)
Table 10-2 EEPROM Program Sequence and Example for Indirect MAC Registers
EEPROM File
Byte function
EEPROM Memory Location
Example EEPROM
Address Location
Example Data, using
MAC Register Write 1
to initialize MACCR
MAC Data Byte 1
Base + 00h
180h
2Ch - written to SU.MACWD0
MAC Data Byte 2
Base + 01h
181h
00h - written to SU.MACWD1
MAC Data Byte 3
Base + 02h
182h
04h - written to SU.MACWD2
MAC Data Byte 4
Base + 03h
183h
90h - written to SU.MACWD3
MAC Address Low
Base + 04h
184h
00h - written to SU.MACAWL
MAC Address High
Base + 05h
185h
00h - written to SU.MACAWH
MAC Write Command
Base + 06h
186h
01h - written to SU.MACRWC to initiate
the indirect write
Note: Base EEPROM address of MAC instructions = 180h
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DS33Z11 Ethernet Mapper
11 OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Lead with Respect to VSS (except VDD)…………………………………………..–0.5V to
+5.5V
Supply Voltage Range (VDD3.3) with Respect to VSS……………………………………………………..–0.3V to
+3.6V
Supply Voltage Range (VDD1.8) with Respect to VSS……………………………………………………..–0.3V to
+2.0V
Ambient Operating Temperature Range…………………………………………………………………...–40°C to
+85°C
Junction Operating Temperature Range………………………………………………………………….–40°C to
+125°C
Storage Temperature Range……………………………………………………………………………….–55°C to
+125°C
Soldering Temperature…………………………………………………………See IPC/JEDEC J-STD-020
Specification
These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
Ambient Operating Temperature Range is assuming the device is mounted on a JEDEC standard test board in a convection-cooled JEDEC
test enclosure.
Note: The “typ” values listed below are not production tested.
Table 11-1 Recommended DC Operating Conditions
(VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40°C to +85°C.)
PARAMETER
Logic 1
Logic 0
Supply (VDD3.3) ±5%
Supply (VDD1.8) ±5%
SYMBOL
CONDITIONS
VIH
VIL
VDD3.3
VDD1.8
MIN
TYP
MAX
UNITS
2.0
-0.3
3.135
1.71
3.300
1.8
3.465
+0.8
3.465
1.89
V
V
V
V
MIN
TYP
MAX
UNITS
Table 11-2 DC Electrical Characteristics
(VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
I/O Supply Current
(VDD3.3 = 3.465V)
Core Supply Current
(VDD1.8 = 1.89)
I/O Standby Current in Reset
(VDD3.3 = 3.465V)
Core Standby Current in Reset
(VDD1.8 = 1.89)
I/O Static Current
(VDD3.3 = 3.465V)
Core Static Current
(VDD1.8 = 1.89)
Lead Capacitance
Input Leakage
IDDIO
(Notes 1, 2)
35
125
mA
IDDCORE
(Notes 1, 2)
35
125
mA
IDDD
(Notes 2, 3)
15
mA
IDDDCORE
(Notes 2, 3)
35
mA
IDDD
(Notes 2, 4)
15
30
mA
IDDDCORE
(Notes 2, 4)
0.2
2
mA
+10
pF
µA
CIO
IIL
7
-10
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DS33Z11 Ethernet Mapper
PARAMETER
Input Leakage
Output Leakage (when Hi-Z)
Output Voltage (IOH = -4.0mA)
Output Voltage (IOL = +4.0mA)
Output Voltage (IOH = -8.0mA)
Output Voltage (IOL = +12.0mA)
Input Voltage
SYMBOL
IILP
ILO
VOH
VOL
VOH
VOL
VIL
CONDITIONS
All Outputs
All Outputs
REF_CLKO
TSER
MIN
-50
-10
2.4
TYP
MAX
-10
+10
0.4
2.4
0.4
0.8
UNITS
µA
µA
V
V
V
V
V
2.0
VIH
V
Note 1: Typical power is 145mW.
Note 2: All outputs loaded with rated capacitance; all inputs between VDD and VSS; inputs with pullups connected to VDD.
Note 3: RST pin held low, or RST bit set.
Note 4: RST pin held low, or RST bit set. All clocks stopped.
11.1 Thermal Characteristics
PARAMETER
MIN
Ambient Temperature (Note 1)
TYP
-40°C
MAX
+85°C
Junction Temperature
+125°C
Theta-JA (θJA) in Still Air for 169-pin
14mm CSBGA (Note 2)
Theta-JA (θJA) in Still Air for 100-pin
10mm CSBGA (Note 2)
+52.7°C/W
+47.1°C/W
Note 1: The package is mounted on a four-layer JEDEC standard test board.
Note 2: Theta-JA (θJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC
standard test board.
11.2 Theta-JA vs. Airflow
AIR FLOW
(m/s)
0
1
2.5
THETA-JA
169-Pin 14mm CSBGA
(°C/W)
52.7
45.8
43.8
100-Pin 10mm CSBGA
(°C/W)
47.1
40.8
38.4
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DS33Z11 Ethernet Mapper
11.3 Transmit MII Interface
PARAMETER
10 Mbps
SYMBOL
MIN
TYP
100 Mbps
MAX
MIN
TYP
400
MAX
40
UNITS
TX_CLK Period
t1
TX_CLK Low Time
t2
140
260
14
26
ns
TX_CLK High Time
t3
140
260
14
26
ns
TX_CLK to TXD, TX_EN
Delay
t4
0
20
0
20
ns
Figure 11-1 Transmit MII Interface
t1
TX_CLK
t2
t3
t4
TXD[3:0]
t4
TX_EN
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DS33Z11 Ethernet Mapper
11.4 Receive MII Interface
PARAMETER
10 Mbps
SYMBOL
MIN
TYP
100 Mbps
MAX
MIN
TYP
400
MAX
40
UNITS
RX_CLK Period
t5
ns
RX_CLK Low Time
t6
140
260
14
26
ns
RX_CLK High Time
t7
140
260
14
26
ns
RXD, RX_DV to RX_CLK
Setup Time
t8
5
5
ns
RX_CLK to RXD, RX_DV
Hold Time
t9
5
5
ns
Figure 11-2 Receive MII Interface Timing
t5
t7
RX_CLK
t6
t8
t9
RXD[3:0]
t9
t8
RX_DV
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DS33Z11 Ethernet Mapper
11.5 Transmit RMII Interface
PARAMETER
SYMBOL
10 Mbps
MIN
REF_CLK Frequency
100 Mbps
TYP
MAX
MIN
TYP
50MHz,
±50ppm
50MHz,
±50ppm
20
20
MAX
UNITS
REF_CLK Period
t1
REF_CLK Low Time
t2
7
13
7
13
ns
REF_CLK High Time
t3
7
13
7
13
ns
REF_CLK to TXD,
TX_EN Delay
t4
5
10
5
10
ns
Figure 11-3 Transmit RMII Interface
t1
REF_CLK
t2
t3
t4
TXD[1:0]
t4
TX_EN
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DS33Z11 Ethernet Mapper
11.6 Receive RMII Interface
PARAMETER
10 Mbps
SYMBOL
MIN
REF_CLK Frequency
TYP
100 Mbps
MAX
MIN
TYP
50MHz,
±50ppm
50MHz,
±50ppm
20
20
MAX
UNITS
REF_CLK Period
t1
ns
REF_CLK Low Time
t2
7
13
7
13
ns
REF_CLK High Time
t3
7
13
7
13
ns
RXD, CRS_DV to
REF_CLK Setup Time
t8
5
5
ns
REF_CLK to RXD,
CRS_DV Hold Time
t9
5
5
ns
Figure 11-4 Receive RMII Interface Timing
t5
t7
REF_CLK
t6
t8
t9
RXD[1:0]
t9
t8
CRS_DV
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DS33Z11 Ethernet Mapper
11.7 MDIO Interface
PARAMETER
SYMBOL
MIN
MDC Frequency
TYP
MAX
UNITS
1.67
MHz
MDC Period
t1
540
600
660
ns
MDC Low Time
t2
270
300
330
ns
MDC High Time
t3
270
300
330
ns
MDC to MDIO Output
Delay
t4
20
10
ns
MDIO Setup Time
t5
10
ns
MDIO Hold Time
t6
20
ns
Figure 11-5 MDIO Timing
t1
MDC
t2
t3
t4
MDIO
MDC
t5
t6
MDIO
153 of 172
DS33Z11 Ethernet Mapper
11.8 Transmit WAN Interface
PARAMETER
SYMBOL
MIN
TYP
TCLKI Frequency
MAX
UNITS
52
MHz
TCLKI Period
t1
19.2
ns
TCLKI Low Time
t2
8
ns
TCLKI High Time
t3
8
ns
TCLKI to TSER Output
Delay
t4
3
TBSYNC Setup Time
t5
3.5
ns
TBSYNC Hold Time
t6
7
ns
10
ns
Figure 11-6 Transmit WAN Timing
t1
TCLKI
t2
t3
t4
TSER
t5
TBSYNC
t6
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DS33Z11 Ethernet Mapper
11.9 Receive WAN Interface
PARAMETER
SYMBOL
MIN
TYP
RCLKI Frequency
MAX
UNITS
52
MHz
RCLKI Period
t1
19.2
ns
RCLKI Low Time
t2
8
ns
RCLKI High Time
t3
8
ns
RSER Setup Time
t4
7
ns
RDEN Setup Time
t4
7
ns
RBSYNC Setup Time
t4
7
ns
RDEN Setup Time
t4
7
ns
RBSYNC Setup Time
t4
7
ns
RSER Hold Time
t5
2
ns
RBSYNC Hold Time
t5
2
ns
RDEN Hold Time
t5
2
ns
RBSYNC Hold Time
t5
2
ns
Figure 11-7 Receive WAN Timing
t1
RCLKI
t2
t3
t4
t5
RSER
t4
t5
RDEN
t4
t5
RBSYNC
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DS33Z11 Ethernet Mapper
11.10 SDRAM Timing
Table 11-3 SDRAM Interface Timing
PARAMETER
SYMBOL
100 MHz
TYP
10
MAX
10.3
UNITS
SDCLKO Period
t1
MIN
9.7
SDCLKO Duty Cycle
t2
4
SDCLKO to SDATA Valid;
Write to SDRAM
t3
SDCLKO to SDATA Drive On;
Write to SDRAM
t4
4
ns
SDCLKO to SDATA Invalid;
Write to SDRAM
t5
3
ns
SDCLKO to SDATA Drive Off;
Write to SDRAM
t6
SDATA to SDCLKO Setup Time;
Read from SDRAM
t7
SDCLKO to SDATA Hold Time;
Read from SDRAM
t8
2
ns
SDCLKO to SRAS, SCAS, SWE,
SDCS Active;
Read or Write to SDRAM
t9
5
ns
SDCLKO to SRAS, SCAS, SWE,
SDCS Inactive;
Read or Write to SDRAM
t10
SDCLKO to SDA, SBA Valid;
Read or Write to SDRAM
t11
SDCLKO to SDA, SBA Invalid;
Read or Write to SDRAM
t12
SDCLKO to SDMASK Valid;
Read or Write to SDRAM
t13
SDCLKO to SDMASK Invalid;
Read or Write to SDRAM
t14
6
ns
7
ns
4
2
ns
7
2
ns
ns
5
156 of 172
ns
ns
2
2
ns
ns
ns
DS33Z11 Ethernet Mapper
Figure 11-8 SDRAM Interface Timing
t1
SDCLKO
(output)
t2
t3
t5
SDATA
(output)
t4
t6
t7
t8
SDATA
(input)
SRAS, SCAS,
SWE, SDCS
(output)
t9
t10
t11
t12
t13
t14
SDA, SBA
(output)
SDMASK
(output)
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DS33Z11 Ethernet Mapper
11.11 AC Characteristics—Microprocessor Bus Timing
(VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8 ±5%; Tj = -40°C to +85°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
Setup Time for A[12:0] Valid to CS Active
t1
0
ns
Setup Time for CS Active to Either RD or
WR Active
t2
0
ns
Delay Time from Either RD or DS Active to
DATA[7:0] Valid
t3
Hold Time from Either RD or WR Inactive to
CS Inactive
t4
0
Hold Time from CS or RD or DS Inactive to
DATA[7:0] Tri-state
t5
5
Wait Time from RW Active to Latch Data
t6
80
ns
Data Setup Time to DS Active
t7
10
ns
Data Hold Time from RW Inactive
t8
2
ns
Address Hold from RW Inactive
t9
0
ns
Write Access to Subsequent Write/Read
Access Delay Time
t10
80
ns
75
158 of 172
UNITS
ns
ns
20
ns
DS33Z11 Ethernet Mapper
Figure 11-9 Intel Bus Read Timing (HWMODE = 0, MODEC = 00)
t9
ADDR[12:0]
Address Valid
Data Valid
DATA[7:0]
t5
WR
t1
CS
t2
t3
t4
RD
t10
Figure 11-10 Intel Bus Write Timing (HWMODE = 0, MODEC = 00)
t9
ADDR[12:0]
Address Valid
DATA[7:0]
t7
t8
RD
t1
CS
t2
t6
t4
WR
t10
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DS33Z11 Ethernet Mapper
Figure 11-11 Motorola Bus Read Timing (HWMODE = 0, MODEC = 01)
t9
ADDR[12:0]
Address Valid
Data Valid
DATA[7:0]
t5
RW
t1
CS
t2
t3
t4
DS
t10
Figure 11-12 Motorola Bus Write Timing (HWMODE = 0, MODEC = 01)
t9
ADDR[12:0]
Address Valid
DATA[7:0]
t7
t8
RW
t1
CS
t2
t6
t4
DS
t10
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DS33Z11 Ethernet Mapper
11.12 EEPROM Interface Timing
PARAMETER
SYMBOL
MIN
TYP
MAX
120
UNITS
SPICK Period
t1
ns
SPICK Low Time
t2
55
65
ns
SPICK High Time
t3
55
65
ns
MOSI Setup Delay
t4
50
ns
MISO Hold
t5
50
ns
MISO Setup
T6
10
ns
MISO Hold
T7
10
ns
SPI_CS Hold
T8
60
ns
Figure 11-13 EEPROM Interface Timing
–
t2
SPI_CS
t3
t1
t8
t4
t5
MOSI
t6
MISO
t7
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DS33Z11 Ethernet Mapper
11.13 JTAG Interface Timing
(VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8 ±5%; Tj = -40°C to +85°C.)
PARAMETER
SYMBOL
JTCLK Clock Period
MIN
TYP
t1
JTCLK Clock High: Low Time
(Note 1)
JTCLK to JTDI, JTMS Setup
Time
JTCLK to JTDI, JTMS Hold Time
MAX
UNITS
1000
ns
500
ns
t2:t3
50
t4
2
ns
t5
2
ns
JTCLK to JTDO Delay
t6
2
50
ns
JTCLK to JTDO HIZ Delay
t7
2
50
ns
JTRST Width Low Time
t8
100
ns
Note 1: Clock can be stopped high or low.
Figure 11-14 JTAG Interface Timing Diagram
t1
t2
t3
JTCLK
t4
t5
JTDI, JTMS
t6
t7
JTD0
t8
JTRST
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DS33Z11 Ethernet Mapper
12 JTAG INFORMATION
The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP, and IDCODE. See Table 12-1. The DS33Z11 contains the following as
required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The Test Access Port has the necessary interface pins: JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin
descriptions for details. Refer to IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994 for details
about the Boundary Scan Architecture and the Test Access Port.
Figure 12-1 JTAG Functional Block Diagram
Boundary Scan
Register
Identification
Register
Mux
Bypas
Register
Instruction
Register
Select
Test Access Port
Controller
10K
10K
JTDI
JTMS
Tri-State
10K
JTCLK
JTRST
JTDO
12.1 JTAG TAP Controller State Machine Description
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP
controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
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DS33Z11 Ethernet Mapper
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
See Figure 12-2 for a diagram of the state machine operation.
Test-Logic-Reset
Upon power-up, the TAP Controller is in the Test-Logic-Reset state. The Instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test
registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the
Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the
controller to the Select-IR-Scan state.
Capture-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does
not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its
current value. On the rising edge of JTCLK, the controller will go to the Shift-DR state if JTMS is LOW or it will go
to the Exit1-DR state if JTMS is HIGH.
Shift-DR
The test data register selected by the current instruction is connected between JTDI and JTDO and will shift data
one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which terminates the
scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the PauseDR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will
retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK
with JTMS HIGH will put the controller in the Exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and
terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-DR state.
164 of 172
DS33Z11 Ethernet Mapper
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this state. With
JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan
sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the
Test-Logic-Reset state.
Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is
loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the
Exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will enter the Shift-IR state.
Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one
stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test registers,
remains at their previous states. A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1-IR
state. A rising edge on JTCLK with JTMS LOW will keep the controller in the Shift-IR state while moving data one
stage thorough the instruction shift register.
Exit1-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-IR state. If JTMS is HIGH on the
rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process.
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK will put the
controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is LOW during a rising
edge on JTCLK.
Exit2-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the Update-IR state. The controller will loop
back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state.
Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge
of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A
rising edge on JTCLK with JTMS held low will put the controller in the Run-Test-Idle state. With JTMS HIGH, the
controller will enter the Select-DR-Scan state.
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DS33Z11 Ethernet Mapper
Figure 12-2 TAP Controller State Diagram
1
Test Logic
Reset
0
0
Run Test/
Idle
1
Select
DR-Scan
1
Select
IR-Scan
0
1
0
1
Capture DR
Capture IR
0
Shift DR
0
Shift IR
0
1
Exit IR
Pause IR
0
1
0
Exit2 DR
1
0
0
Pause DR
0
1
1
Exit DR
1
0
1
0
Exit2 IR
1
1
Update DR
Update IR
1
1
0
0
12.2 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When
the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO.
While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial
output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the
controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift
register to the instruction parallel output. Instructions supported by the DS33Z11 and its respective operational
binary codes are shown in Table 12-1.
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DS33Z11 Ethernet Mapper
Table 12-1 Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION
SAMPLE:PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
SELECTED REGISTER
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
INSTRUCTION CODES
010
111
000
011
100
001
12.2.1 SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal
operation of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data
into the boundary scan register via JTDI using the Shift-DR state.
12.2.2 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal
operation.
12.2.3 EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR will sample
all digital inputs into the boundary scan register.
12.2.4 CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the
bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
12.2.5 HIGHZ
All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected between
JTDI and JTDO.
12.2.6 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code is loaded into the identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
ID code will always have a ‘1’ in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number
and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
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DS33Z11 Ethernet Mapper
12.3 JTAG ID Codes
Table 12-2 ID Code Structure
DEVICE
REVISION
ID[31:28]
DEVICE CODE
ID[27:12]
MANUFACTURER’S CODE
ID[11:1]
REQUIRED
ID[0]
DS33Z11
0000
0000 0000 0110 0001
000 1010 0001
1
12.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An
optional test register has been included with the DS33Z11 design. This test register is the identification register
and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
12.5 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O
cells and is n bits in length.
12.6 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions,
which provides a short path between JTDI and JTDO.
12.7 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
12.8 JTAG Functional Timing
This functional timing for the JTAG circuits shows:
•
The JTAG controller starting from reset state
•
Shifting out the first 4 LSB bits of the IDCODE
•
Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern
•
Shifting the TDI pin to the TDO pin through the bypass shift register
•
An asynchronous reset occurs while shifting
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DS33Z11 Ethernet Mapper
Figure 12-3 JTAG Functional Timing
(INST)
(STATE)
IDCODE
Run Test
Idle
Reset
Select DR
Scan
Capture
DR
Exit1
DR
Shift
DR
IDCODE
BYPASS
Update
DR
Select DR
Scan
Select IR
Scan
Capture
IR
Shift IR
Exit1
IR
Update
IR
Select DR
Scan
Capture
DR
Shift
DR
Test
Logic Idle
JTCLK
JTRST
JTMS
JTDI
X
X
X
X
JTDO
Output
Pin
X
Output pin level change if in "EXTEST" instruction mode
169 of 172
X
DS33Z11 Ethernet Mapper
13 PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for
each package is a link to the latest package outline information.)
13.1 169-Ball CSBGA, 14mm x 14mm (56-G6035-001)
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DS33Z11 Ethernet Mapper
13.2 100-Ball CSBGA, 10mm x 10mm (DS33ZH11 Only) (56-G6008-001)
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DS33Z11 Ethernet Mapper
14 REVISION HISTORY
REVISION
021805
030106
122006
DESCRIPTION
New Product Release.
Added TCLKI to TSER Output Delay Minimum of 3ns.
Added TCLKI to TBSYNC Setup Time Minimum of 3.5ns.
Corrected typo in Table 8-9, Transmit Queue High Threshold entry.
Clarified definition of GL.IDR.ID5-7.
Added definition for BPCLR.PLF[4:0].
Corrected ball assignment shown in the SDATA[3] pin listing for the 100-pin CSBGA package.
Corrected pin description of MDC.
Corrected default value listed in the SU.RMFSRL register definition.
Added Figure 8-11, HDLC Encapsulation of MAC Frame.
Corrected FULLDS pin description for Hardware Mode.
Corrected SU.MACCR.DRO bit description.
Clarified pin description of RMIIMIIS
Clarified pin description of FULLDS
Clarified pin description of H10S
Clarified RMIIMIIS, FULLDS, and H10S internal ties in the 100 pin package.
Clarified Hardware Mode operation with MODEC[1:0] = 10.
Added power supply sequence to the Example Device Initialization Sequence.
Added GL.SDMODE1, GL.SDMODE2, GL.SDMODEWS, and GL.SDRFTC register definitions.
Clarified the GL.C1QPR register definition.
Clarified the 169 Pin package outline drawing and added side view.
Added SU.MACCR.PM and SU.MACCR.PAM bit definitions.
Added GL.SDMODE1, GL.SDMODE2, GL.SDMODEWS, and GL.SDRFTC registers to the
register bit map.
Corrected pin description of RST.
Corrected pin description of REF_CLK
Clarified text regarding use of REF_CLKO in DCE and RMII modes.
Corrected SU.GCR.H10S bit definition.
Corrected the SU.RQLT and SU.RQHT default values to zero.
Clarified section 8.18 on X.86 mode synchronization.
Corrected value of “Receiver Maximum Frame Size” listed in Table 8-9.
Corrected low-power mode information in Section 8.4.
Added D/C operating current maximum values.
Updated D/C operating current typical values.
Added D/C Characteristic entries for Supply currents in “standby” conditions.
Updated package drawings.
172 of 172
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor
product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any
time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.