19-4584; Rev 1; 6/10
KIT
ATION
EVALU
E
L
B
AVAILA
12-Channel, High-Voltage
Battery-Pack Fault Monitors
The MAX11080/MAX11081 are battery-pack fault-monitor ICs capable of monitoring up to 12 lithium-ion (Li+)
battery cells. This device is designed to provide an
overvoltage or undervoltage fault indication when any
of the cells cross the user-selectable threshold for
longer than the set program-delay interval. The overvoltage levels are pin selectable from +3.3V to +4.8V
in 100mV increments, and have a guaranteed accuracy of ±25mV over the entire temperature range. The
undervoltage level is also user selectable from +1.6V
to +2.8V in 200mV increments. These levels are guaranteed to ±100mV over the entire temperature range.
Undervoltage detection can be disabled as one of the
user-configuration options.
The MAX11080/MAX11081 have a built-in level-shifter
that allows up to 31 MAX11080/MAX11081 devices to
be connected in a daisy-chain fashion to reduce the
number of interface signals needed for large stacks of
series batteries. Each cell is monitored differentially and
compared to the overvoltage and undervoltage thresholds. When any of the cells exceed this threshold for
longer than the set program delay interval, the
MAX11080/MAX11081 inhibit the heartbeat signal from
being passed down the daisy-chain. Built-in comparator hysteresis prevents threshold chattering.
The MAX11080/MAX11081 are designed to be the perfect complement to the MAX11068 high-voltage measurement IC for redundant fault-monitoring applications.
This device is offered in a 9.7mm x 4.4mm, 38-pin
TSSOP package with 0.5mm pin spacing. The package
is lead-free and RoHS compliant with an extended
operating temperature range of -40°C to +105°C.
Features
o Up to 12-Cell Li+ Battery Voltage Fault Detection
o Operation from 6.0V to 72V
o Pin-Selectable Overvoltage Threshold from +3.3V
to +4.8V in 100mV Increments
±25mV Overvoltage-Detection Accuracy
o Pin-Selectable Undervoltage Threshold from
+1.6V to +2.8V in 200mV Increments
±100mV Undervoltage-Detection Accuracy
o Overvoltage/Undervoltage-Threshold Detection
Hysteresis
MAX11080: 300mV
MAX11081: 37.5mV
o Programmable Delay Time of Alarm Detection
from 3.0ms to 3.32s with an External Capacitor
o Daisy-Chained Alarm and Shutdown Functions
with Heartbeat Status Signal
Up to 31 Devices Can Be Connected
o Ultra-Low-Power Dissipation
Operating-Mode Current Drain: 80µA
Shutdown-Mode Current: 2µA
o Wide Operating Temperature Range from -40°C to
+105°C (AEC-Q100, Type 2)
o 9.7mm x 4.4mm, 38-Pin TSSOP Package
o Lead(Pb)-Free and RoHS Compliant
Applications
High-Voltage, Multicell-Series-Stacked Battery
Systems
Ordering Information
PART
TEMP RANGE
Electric Vehicles
MAX11080GUU/V+
-40°C to +105°C
38 TSSOP
Hybrid Electric Vehicles
MAX11081GUU/V+
-40°C to +105°C
38 TSSOP
Electric Bikes
PIN-PACKAGE
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
High-Power Battery Backup
Solar Cell Battery Backup
Pin Configuration appears at end of data sheet.
Super-Cap Battery Backup
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX11080/MAX11081
General Description
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
ABSOLUTE MAXIMUM RATINGS
ESD Rating
C_, REF, VAA, VDDU, GNDU,
DCIN, SHDN, CP+, CP-, HV,
OVSEL_, UVSEL_, TOPSEL,
ALRMU, ALRML,
AGND, CD ..............................±2kV (Human Body Model, Note 3)
Continuous Power Dissipation (TA = +70°C)
38-Pin TSSOP (derate 15.9mW/°C above +70°C) ....1095.9mW
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-55°C to +150°C
Junction Temperature (continuous) .................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
HV, VDDU, GNDU, DCIN to AGND.........................-0.3V to +80V
HV to DCIN and C12 ................................................-0.3V to +6V
Cn+1 to Cn, where n = 1 to 11...............................-0.3V to +80V
C1 to C0 ...................................................-0.3V to +20V (Note 1)
C1 to AGND ..............................-0.3V to (VDCIN + 0.6V) (Note 2)
C0 to AGND...........................................................-0.3V to +0.9V
C2–C12 to AGND ....................................-0.3V to (VDCIN + 0.6V)
SHDN, VAA to AGND ................................................-0.3V to +4V
VDDU to GNDU .........................................................-0.3V to +6V
OVSEL_, UVSEL_, TOPSEL to AGND .........-0.3V to (VAA + 0.3V)
CD, ALRML to AGND..................................-0.3V to (VAA + 0.3V)
ALRMU to GNDU ...................................-0.3V to (+VDDU + 0.3V)
CP+ to AGND ...........................(GNDU - 0.3V) to (VDDU + 0.3V)
CP- to AGND...........................................-0.3V to (GNDU + 0.3V)
CP- to VDDU .......................................................................+0.3V
Note 1: The C1 to C0 differential input path is tolerant to 80V as long as the SHDN pin is deasserted.
Note 2: The C1 input is tolerant to a maximum VDCIN + 0.6V with SHDN = 1. If SHDN = 0, 20V is the maximum rating.
Note 3: Human Body Model to Specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = TMIN to TMAX, unless otherwise noted. VDCIN = VGNDU = +6.0V to +72V, typical values are at TA = +25°C, unless otherwise
specified from -40°C to +105°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
C_ INPUTS
Differential Input Range
VCELLXIN
Input Current
ICXIN
Overvoltage Threshold
VOV
Any two inputs Cn to Cn+1,
where n = 1 to 11 (Note 4)
1.5
72
C1 to C0 with SHDN = 1
1.5
72
C1 to C0 with SHDN = 0
1.5
VCELL = 3.0V
-1
Undervoltage Threshold
±5
VUV
+1.6
Undervoltage-Threshold
Accuracy
Comparator Hysteresis (Note 4)
16
0.05
+3.3
Overvoltage-Threshold Accuracy
±20
VHYS
MAX11080
V
+1
µA
+4.8
V
±25
mV
+2.8
V
±100
mV
300
MAX11081
12
37.5
77
4.35
6.1
7.65
mV
CD PIN
CD Current
ICD
VCD = 0.4V
CD Trip Voltage
VCD
Internal at comparator
1.23
V
Excluding CDLY variation
±20
%
Delay-Time Accuracy
µA
STATUS/CONTROL PORT
Shutdown Disable (SHDN High
Voltage)
SHDN/VIH
Shutdown Asserted (SHDN Low
Voltage)
SHDN/VIL
2
2.1
_______________________________________________________________________________________
V
0.6
V
12-Channel, High-Voltage
Battery-Pack Fault Monitors
(TA = TMIN to TMAX, unless otherwise noted. VDCIN = VGNDU = +6.0V to +72V, typical values are at TA = +25°C, unless otherwise
specified from -40°C to +105°C.)
PARAMETER
SYMBOL
CONDITIONS
VDDU Output High
VDDU
VOH
VDDU Output Low
VDDU
VOL
ALRML Output Voltage High
ALRML
VOH
ISOURCE = 150µA
ALRML Output Voltage Low
ALRML
VOL
ISINK = 150µA
ALRMU Input Voltage High
ALRMU
VIH
ALRMU Input Voltage Low
ALRMU
VIL
Alarm Voltage Output “Heartbeat”
Frequency
ALRML
fOUT
Alarm Voltage Output Duty Cycle
MIN
TYP
MAX
VGNDU
+ 2.4
V
VGNDU
+ 0.3
Daisy-chained ALRMU signal as
coupled through a 3.3nF high-voltage
capacitor and a 150kΩ resistor as
referred to GNDU
Daisy-chained ALRMU signal as
coupled through a 3.3nF high-voltage
capacitor and a 150kΩ resistor as
referred to GNDU
Heartbeat clock rate with no alarm
condition
2.4
VGNDU
+ 2.1
Heartbeat clock rate with no alarm
condition
49.0
6V < VDCIN < 72V, ILOAD = 0A
3.0
V
V
0.6
4032
UNITS
V
V
4096
VGNDU
+ 0.9
V
4157
Hz
51.0
%
72
V
LINEAR REGULATOR (VAA)
Input-Voltage Range
Output Voltage
VDCIN
VAAOUT
Short-Circuit Current
Power-On-Reset Trip Level
(Note 5)
IAASHORTCIRCUIT VAA = 0V, 6V < VDCIN < 36V
VAARESET
Falling VAA
VAAVALID
VAAHYS
Thermal Shutdown
6
TSHUT
3.3
3.6
V
50
mA
2.8
V
Rising VAA
3.0
Hysteresis on rising VAA
37
mV
+145
°C
Rising temperature
POWER-SUPPLY REQUIREMENTS (DCIN)
Current Consumption
IDCIN
IGNDU Operating Mode
Operating mode, SHDN = 1, 12
battery cells, alarm inactive,
VDCIN = VGNDU = 36V
35
Shutdown mode, SHDN = 0, 12
battery cells, VDCIN = VGNDU = 36V
1.3
2
SHDN = 1, battery cells, alarm
inactive, VDCIN = VGNDU = 36V
35
40
40
µA
µA
LOGIC INPUTS AND OUTPUTS
Threshold Setting
VIH
UVSEL0/UVSEL1/UVSEL2, TOPSEL
VIL
OVSELO/OVSEL1/OVSEL2/OVSEL3
VAA - 0.1
0.1
V
Note 4: Limits guaranteed by design and characterization statistical analysis, not production tested.
Note 5: Guaranteed by design and not production tested.
_______________________________________________________________________________________
3
MAX11080/MAX11081
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MEAN
1.59
1.58
1.57
MIN
1.56
1.55
1.90
1.88
MEAN
1.86
MIN
1.84
-20
0
40
20
60
80
100
-40
4.794
-20
0
20
40
60
80
-40
100
-20
0
20
40
60
OVERVOLTAGE CLEAR THRESHOLD
vs. TEMPERATURE (MAX11080)
CD CURRENT DISTRIBUTION
CD CHARGING CURRENT
vs. TEMPERATURE
30
DEVICE COUNT
4.51
4.50
20
15
MIN
4.48
VCD = 0.4V
-20
0
20
40
60
80
5.97
5.96
5.4
100
5.6
5.8
6.0
6.2
6.4
6.6
-20
-40
0
CD PIN CURRENT (µA)
40
60
GNDU SUPPLY CURRENT
vs. GNDU VOLTAGE
55
MAX11080 toc07
4.8V OVERVOLTAGE THRESHOLD
VCELL = VDCIN/12
20
TEMPERATURE (°C)
50
IGNDU (µA)
50
TA = +105°C
45
60
IDCIN (µA)
5.99
5
DCIN SUPPLY CURRENT vs. VDCIN
40
TA = +25°C
35
TA = -40°C
30
TA = +105°C
40
6.00
5.98
TEMPERATURE (°C)
70
6.01
10
0
4.47
25
30
TA = +25°C
20
TA = -40°C
15
20
0
10
20
30
40
VDCIN (V)
4
50
60
70
100
6.02
CD CURRENT (µA)
25
80
6.03
MAX11080 toc05
MAX11080 toc04
35
MEAN
-40
MIN
4.796
TEMPERATURE (°C)
MAX
4.49
4.798
TEMPERATURE (°C)
4.8V SET POINT
4.52
MEAN
4.800
TEMPERATURE (°C)
4.54
4.53
4.802
4.792
1.82
-40
MAX
MAX11080 toc03
MAX
4.8V SET POINT
4.804
MAX11080 toc08
1.60
1.92
4.806
OVERVOLTAGE SET THRESHOLD (V)
1.61
1.6V SET POINT
MAX11080 toc02
MAX
1.62
1.94
UNDERVOLTAGE CLEAR THRESHOLD (V)
1.6V SET POINT
MAX11080 toc01
UNDERVOLTAGE SET THRESHOLD (V)
1.64
1.63
OVERVOLTAGE SET THRESHOLD
vs. TEMPERATURE
UNDERVOLTAGE CLEAR THRESHOLD
vs. TEMPERATURE (MAX11080)
80
0
10
20
30
40
50
60
VGNDU (V)
_______________________________________________________________________________________
70
80
80
100
MAX11080 toc06
UNDERVOLTAGE SET THRESHOLD
vs. TEMPERATURE
OVERVOLTAGE CLEAR THRESHOLD (V)
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
12-Channel, High-Voltage
Battery-Pack Fault Monitors
PIN
NAME
FUNCTION
1
DCIN
DC Power-Supply Input. DCIN supplies the internal 3.3V regulator. This pin should be connected as shown
in the application diagrams.
2
HV
High-Voltage Bias. HV is biased by the output of the charge pump to provide a DC supply above the DCIN
level. It is used internally to bias the cell-comparator circuitry. Bypass to DCIN with a 1µF capacitor.
3, 33
N.C.
No Connection. Not internally connected.
4
C12
Cell 12 Plus Connection. Top of battery module stack.
5
C11
Cell 12 Minus Connection and Cell 11 Plus Connection
6
C10
Cell 11 Minus Connection and Cell 10 Plus Connection
7
C9
Cell 10 Minus Connection and Cell 9 Plus Connection
8
C8
Cell 9 Minus Connection and Cell 8 Plus Connection
9
C7
Cell 8 Minus Connection and Cell 7 Plus Connection
10
C6
Cell 7 Minus Connection and Cell 6 Plus Connection
11
C5
Cell 6 Minus Connection and Cell 5 Plus Connection
12
C4
Cell 5 Minus Connection and Cell 4 Plus Connection
13
C3
Cell 4 Minus Connection and Cell 3 Plus Connection
14
C2
Cell 3 Minus Connection and Cell 2 Plus Connection
15
C1
Cell 2 Minus Connection and Cell 1 Plus Connection
16
C0
Cell 1 Minus Connection. Connect to AGND.
17
UVSEL0
18
UVSEL1
19
UVSEL2
20
OVSEL0
21
OVSEL1
22
OVSEL2
23
OVSEL3
Undervoltage Threshold Select 0 to 2. Used to select one of eight undervoltage alarm threshold settings.
The parts have internal pulldown; these pins should only be tied to VAA or AGND to set the logic state.
Overvoltage Threshold Select 0 to 3. Used to select one of 16 overvoltage alarm threshold settings.
The parts have internal pulldown; these pins should only be tied to VAA or AGND to set the logic state.
_______________________________________________________________________________________
5
MAX11080/MAX11081
Pin Description
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
Pin Description (continued)
PIN
NAME
24
VAA
25
AGND
Analog Ground. Should be connected to the negative terminal of cell 1.
SHDN
Active-Low Shutdown Input. This pin completely shuts down the MAX11080/MAX11081 internal regulators
and oscillators when the pin is less than 0.6V as referenced to AGND. The host controller should drive
SHDN for the first pack. See Figure 2 for the SHDN daisy-chained module connection.
27
ALRML
Lower Port Alarm Output. This output is an alarm indicator for overvoltage, undervoltage, and setup faults.
The alarm signal is daisy-chained and driven from the highest module down to the lowest. The alarm output
is nominally a clocked “heartbeat” signal that provides a 4kHz clock when no alarm is present. The ALRML
can also be configured as level signal and set to “low” for no alarm and “high” for alarm state. See the
TOPSEL Function section for details. This signal swings between VAA and AGND, and is active high in the
alarm state.
28
CD
29, 30, 32
TST1,
TST2,
TST3
31
TOPSEL
Input to Indicate Topmost Device in the Daisy-Chain. This pin should be connected to AGND for all devices
except the topmost. For the top device, this pin should be connected to VAA.
34
ALRMU
Upper Port Alarm Input. This input receives the ALRML output signal from an upper neighboring module. It
swings between VDDU and GNDU.
35
GNDU
Level-Shifted Upper Port Ground. Upper port-supply return and supply input for the charge-pump supply.
This pin should be connected to the DCIN takeoff point on the battery stack as shown in the application
diagrams.
36
VDDU
Level-Shifted Upper Port Supply. Upper port-supply output for the daisy-chained bus. This is a regulated
output voltage from the internal charge pump that is level-shifted above the DCIN pin voltage level. It
should be bypassed with a 1µF capacitor to GNDU.
37, 38
CP-, CP+
26
6
FUNCTION
+3.3V Analog Supply Output. Bypass with a 1µF capacitor to AGND.
Programmable Delay Time. Connect a capacitor from this pin to AGND to set the hold time required for a
fault condition before the alarm is set. The capacitor should be a ceramic capacitor in the 15nF to 16.5µF
range.
Production Test Pins. Connect to AGND.
Charge-Pump Capacitor. Negative/positive input for the internal charge pump. Connect a 0.01µF highvoltage capacitor between CP+ and CP-.
_______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
MAX11080/MAX11081
HV
DCIN
C12
LINEAR
REGULATOR
CELL COMPARATORS
VAA
C11
UPPER
PORT
CELL COMPARATORS
C10
VDDU
ALRMU
GNDU
CELL COMPARATORS
C9
CELL COMPARATORS
LEVEL
SHIFT
C8
CP+
CP-
CELL COMPARATORS
C7
CELL COMPARATORS
C6
FAULT
FAULT
CELL COMPARATORS
LOWER
PORT
ALRML
SHDN
C5
CELL COMPARATORS
OVSEL3
C4
OVSEL2
CELL COMPARATORS
C3
CELL COMPARATORS
OVSEL1
FAULT-STATE
MACHINE
AND
CONTROL LOGIC
OVSEL0
TOPSEL
C2
CELL COMPARATORS
UVSEL2
C1
UVSEL1
CELL COMPARATORS
UVSEL0
C0
MAX11080
MAX11081
AGND
CD
Figure 1. Functional Diagram
_______________________________________________________________________________________
7
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
MODULE
N+1
CELL STACK
MODULE
N+1
GND REFERENCE
22Ω
FUSE
MODULE-(N+1)
GNDU
22Ω
100kΩ
RDCIN
5kΩ
BUS BAR
CDCIN
0.1µF
80V
MODULE+(N)
CELL 12
CELL 11
CHV
1µF
16V
SMCJ70
HV
R13
R12
R11
BAT46
DCIN
C12
VDDU
C11
ALRMU
GNDU
C12
C11
R10
C10
C9
CELL 9
R9
C9
MAX11080
MAX11081
CPVAA
C8
CELL 8
R8
CP+
C8
C7
CELL 7
R7
C7
R6
R5
ALRML
AGND
SEE TEXT FOR GNDU
CONNECTION OPTIONS
GNDU
R4
C6
S1B
R3
GNDU
R2
68nF
C4
OVSEL3
OVSEL2
C3
OVSEL1
OVSEL0
UVSEL2
C2
UVSEL1
UVSEL0
C1
C0
MODULE-(N)
TOPSEL
AGND
LOCAL
GROUND
BUS BAR
5.6V
VAA
C1
CELL 1
ISOLATOR
AND
CONTROL
INTERFACE
1kΩ
C5
C2
CELL 2
100nF
5.6V
CA
1µF
6V
200kΩ
C3
CELL 3
150Ω
SHDN
CP
0.01µF
100V
C4
CELL 4
MODULE
N+1
C3DC
3.3nF
630V
SHDN
C5
CELL 5
R1DC
150kΩ
ALRML
C6
CELL 6
5.6V
GNDU
GNDU
C10
CELL 10
DAISY-CHAIN BUS
TO UPPER MODULES
BAT46
CDD
1µF
10V
CD
CDLY
15nF TO 16.5µF CERAMIC CAPACITOR
R2–R13 = 10kΩ
C1–C12 = 0.1µF/80V
MODULE
N-1
CELL STACK
MODULE
N-1
GNDU TAKEOFF
Figure 2. Application Circuit Diagram for a 12-Cell System
8
_______________________________________________________________________________________
JUMPER BANK
12-Channel, High-Voltage
Battery-Pack Fault Monitors
MODULE
N+1
GND REFERENCE
22Ω
FUSE
MODULE-(N+1)
MAX11080/MAX11081
MODULE
N+1
CELL STACK
22Ω
GNDU
100kΩ
RDCIN
5kΩ
CDCIN
0.1µF
80V
BUS BAR
CHV
1µF
6V
SMCJ70
MODULE+(N)
HV
BAT46
CDD
1µF
10V
DCIN
C12
VDDU
C11
ALRMU
R11
R10
C10
C9
CELL 9
R9
C9
R8
C8
MAX11080
MAX11081
C8
CELL 8
CP+
CPVAA
C7
CELL 7
R7
C7
R6
C6
R5
C5
ALRML
AGND
GNDU
SHDN
CP
0.01µF
100V
S1B
R4
RSHD
200kΩ
GNDU
R3
C4
68nF
R2
OVSEL1
OVSEL0
C2
UVSEL2
UVSEL0
C0
TOPSEL
AGND
LOCAL
GROUND
BUS BAR
MODULE
N-1
CELL STACK
MODULE
N-1
GNDU TAKEOFF
JUMPER BANK
UVSEL1
C1
MODULE-(N)
RSHD2
1kΩ
OVSEL2
C3
C1
CELL 1
5.6V
OVSEL3
C2
CELL 2
ISOLATOR
AND
CONTROL
INTERFACE
VAA
C3
CELL 3
100nF
5.6V
CA
1µF
6V
C4
CELL 4
150Ω
SHDN
C5
CELL 5
MODULE
N+1
C3DC
3.3nF
630V
ALRML
C6
CELL 6
R1DC
150kΩ
SEE TEXT FOR GNDU
CONNECTION OPTIONS
C10
CELL 10
5.6V
GNDU
GNDU
GNDU
DAISY-CHAIN BUS
TO UPPER MODULES
BAT46
CD
CDLY
15nF TO 16.5µF CERAMIC CAPACITOR
R2–R11 = 10kΩ
C1–C10 = 0.1µF/80V
Figure 3. Application Circuit Diagram for a 10-Cell System
_______________________________________________________________________________________
9
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
MODULE
N+1
CELL STACK
MODULE-(N+1)
MODULE
N+1
GND REFERENCE
22Ω
FUSE
22Ω
GNDU
100kΩ
RDCIN
5kΩ
BUS BAR
CDCIN
0.1µF
80V
CHV
1µF
16V
SMCJ70
MODULE+(N)
HV
BAT46
CDD
1µF
10V
DCIN
C12
VDDU
C11
ALRMU
GNDU
GNDU
C9
MAX11080
MAX11081
R9
CPVAA
C8
CELL 8
R8
C8
C7
CELL 7
R7
C7
R6
R5
GNDU
ALRML
AGND
GNDU
R4
C6
S1B
R3
GNDU
R2
68nF
C4
RSHD2
1kΩ
OVSEL3
OVSEL2
C3
OVSEL1
OVSEL0
C2
UVSEL2
UVSEL1
UVSEL0
C1
C0
MODULE-(N)
TOPSEL
AGND
LOCAL
GROUND
BUS BAR
5.6V
VAA
C1
CELL 1
ISOLATOR
AND
CONTROL
INTERFACE
C5
C2
CELL 2
100nF
5.6V
CA
1µF
6V
RSHD
200kΩ
C3
CELL 3
150Ω
SHDN
CP
0.01µF
100V
C4
CELL 4
MODULE
N+1
C3DC
3.3nF
630V
SHDN
C5
CELL 5
R1DC
150kΩ
ALRML
C6
CELL 6
5.6V
SEE TEXT FOR GNDU
CONNECTION OPTIONS
C10
CP+
DAISY-CHAIN BUS
TO UPPER MODULES
BAT46
CD
CDLY
15nF TO 16.5µF CERAMIC CAPACITOR
R2–R9 = 10kΩ
C1–C8 = 0.1µF/80V
MODULE
N-1
CELL STACK
MODULE
N-1
GNDU TAKEOFF
Figure 4. Application Circuit Diagram for an 8-Cell System
10
______________________________________________________________________________________
JUMPER BANK
12-Channel, High-Voltage
Battery-Pack Fault Monitors
MODULE
N+1
GND REFERENCE
MAX11080/MAX11081
MODULE
N+1
CELL STACK
SHDN
CD
ALRML
SHDN
TOPSEL
HV
UVSEL2
UVSEL1
UVSEL0
OVSEL3
OVSEL2
OVSEL1
OVSEL0
CP-
CP+
GNDU
SCLL
SDAL
C0
C1
C2
C3
C4
AGND
C5
C7
C8
C9
C10
C11
C12
ISOLATOR
AND
CONTROL
INTERFACE
FOR FIRST
MODULE
ALRML
(MAX11068)
VAA
MAX11080
MAX11081
DCIN
C6
MODULE-(N+1)
VDDU
ALRMU
ALRML
(MAX11080)
GPIO
BUS BAR
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
C13
DCIN
R26
MODULE+(N)
HV
R13
CELL 12
R12 C12
CELL 11
R11 C11
CELL 10
R10 C10
DCIN
C12
VDDU
C11
ALRMU
C10
SCLU
SDAU
C9
CELL 9
R9
C9
GNDU
C8
CELL 8
R8
C8
MAX11068
CP+
C7
CELL 7
R7
C7
CPC6
CELL 6
R6
VAA
C6
C5
CELL 5
R5
VDDL
C5
C4
CELL 4
R4
SCLL
C4
C3
CELL 3
R3
C3
CELL 2
R2
C2
CELL 1
R1
C1
MODULE-(N)
BATTERY
CONNECTOR
BUS BAR
C0
LOCAL GROUND
SDAL
C2
ALRML
C1
SHDN
C0
GNDL
THRM
GPIO0
GPIO1
GPIO2
AUXIN2
AUXIN1
AGND
REF
MODULE N-1
CELL STACK
REFER TO EACH DEVICE'S APPLICATION REFERENCE CIRCUITS FOR COMPONENTS AND VALUES NOT SHOWN ON THIS SIMPLIFIED SYSTEM-LEVEL SCHEMATIC.
Figure 5. Battery Module System with Redundant Fault-Detection Application Schematic
______________________________________________________________________________________
11
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
HV
VDDU
6V
DCIN
CP+
6V
ALRMU
80V
C12
80V
GNDU
80V
CPC1 TO C11
VAA
ALRML
SHDN
ESD DIODES
CD
MAX11080
MAX11081
TOPSEL
4V
4V
6V
OVSEL0/1/2/3
C0
UVSEL0/1/2
AGND
Figure 6. ESD Diode Diagram
Detailed Description
Figure 1 shows the functional diagram; Figure 2 shows
the application circuit diagram for a 12-cell system
while Figure 3 shows the application circuit design for a
10-cell system and Figure 4 for an 8-cell system. Figure
5 is the application schematic for the battery module
system with redundant fault detection and Figure 6 is
the ESD diode diagram.
Architectural Overview
The MAX11080/MAX11081 are battery-pack fault-monitor
ICs capable of monitoring up to 12 Li+ battery cells.
These devices are designed to provide an overvoltage or
undervoltage alarm indicator when any of the cells cross
the user-selectable threshold for longer than the configured decision delay interval. The MAX11080/MAX11081
also incorporates daisy-chain bus for use in high-voltage
stacked-battery operation. The daisy-chain bus relays
12
shutdown and alarm communication across up to 31
stacked modules without the need for isolation between
each module. This results in a simplified system with
reduced cost. The MAX11080/MAX11081 are ideal as an
ultra-low-power, redundant cell-fault monitor that is the
perfect complement to the MAX11068 high-voltage battery measurement IC. Both ICs in concert form a powerful
Li+ battery system monitor with redundant overvoltage
and undervoltage fault detection.
Overvoltage and Undervoltage
Fault Detection
Figure 7 summarizes the fault-detection mechanism for
a set of differential cell inputs in the MAX11080/
MAX11081.
First, the differential cell inputs are attenuated by a factor of four while being level shifted and converted to a
single-ended voltage referenced to AGND. The groundreferenced voltage is then connected to a set of over-
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
CD pin. If the voltage at the CD pin reaches VCD, the
ALRML line is set to VAA (+2.4V minimum as referred to
AGND). Normally, the ALRML line is a heartbeat signal
with pulses occurring every 250µs. If all cell voltages
transition from out-of-range to in-range before the voltage at pin CD reaches VCD, an internal switch clamps
the CD pin to GND. This action discharges CDLY and,
because the delay had not yet expired, no alarm
occurs. Discharging CDLY ensures that the full delay
time occurs for the next overvoltage or undervoltage
VOV/4
VCELL/(4 x RSHIFT)
HV
HYSTERESIS
CELL
OUT-OF-RANGE
Cn+1
+
RIN*
40MΩ
TYP
VCELL
RSHIFT
+
VCELL/4
-
-
OUT-OF-RANGE
HYSTERESIS
Cn
AGND
CELLS 2–12
VUV/4
C1
11
+
VCELL
6MΩ
TYP
2MΩ
TYP
VCELL/4
VSC/4
AGND
CELL 1
UNDERVOLTAGE
COMPARATOR
ENABLE
SHORT-CIRCUIT
DETECTOR
HYSTERESIS: MAX11080 = 75mV
MAX11081 = 9.375mV
Figure 7. Cell Differential Input and Comparator Block Diagram
VAA
6kΩ
CD
ICD
6.1µA
OUT-OF-RANGE
ALARM
CELL OUT-OF-RANGE
1 TO 12
11
VCD
THRESHOLD
CDLY
Figure 8. CDLY Circuit Block Diagram
______________________________________________________________________________________
13
MAX11080/MAX11081
voltage and undervoltage comparators. The threshold
references for the comparators are set by the UVSEL_
and OVSEL_ input pins. When one of the cell voltages
exceeds VOV or is below VUV when VUV is enabled, the
internal cell out-of-range signal for the given cell is set
and logically ORed with the same signal for the other
cell positions to create an overall out-of-range signal.
When any cells are out-of-range as indicated by the
internal out-of-range signal, an internal current source
begins to charge the capacitor CDLY connected to the
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
event. Figure 8 summarizes the CDLY circuit.
Once the ALRML pin is forced high due to an alarm
(+2.4V minimum as referred to AGND), it transitions
back to a heartbeat signal only after all battery cells
meet the following condition:
(VOV - VHYS) > VCELL(ALL) > (VUV + VHYS)
Examples of cell-voltage readings and their effect on
the alarm status are shown in Figures 9 and 10 for single- and multiple-cell systems. In the case where an
upper module is forwarding an active alarm condition
down the daisy-chain, that condition continues to be
propagated toward the host regardless of the alarm
state of any lower module. Furthermore, to circumvent
the possibility of a short-circuited capacitor connected
to CD preempting the fault-time validation process, a
redundant built-in delay of 4s nominal is asserted as a
backup. If the VCD threshold is not reached within 4s of
an out-of-range event, the alarm becomes active.
CDLY = (tDLY x ICD)/VCD
The effective ICD value of the current source is 6.1µA
typical and the threshold voltage, VCD, is 1.23V typical.
The VCD threshold is specified at an internal node prior
to the resistor in series with the CD pin as shown in
Figure 8. The threshold voltage seen at the pin is
approximately 1.18V due to the drop associated with
the typical I CD value and the 6kΩ resistor. The
MAX11080/MAX11081 can operate with capacitor values from 15nF (3.0ms) to 16.5µF (3.32s). Each capacitor should have a voltage tolerance of 5V minimum.
Cell-Voltage Threshold Selection
The overvoltage and undervoltage threshold selection
is configured through the OVSEL_ and UVSEL_ inputs.
The overvoltage selection can be configured from 3.3V
to 4.8V in 100mV increments. The undervoltage threshold can be configured from 1.6V to 2.8V in 200mV
increments. The undervoltage detection can also be
disabled. See Tables 1 and 2 for the proper configuration settings.
Programmable Delay Time
The alarm trigger delay time is calculated according to
the following equations:
tDLY = (VCD x CDLY)/ICD
Immunity to unintended changes in the threshold voltage setting (due to accidental pin-to-pin short circuits,
for example) is provided. The customer-programmed
Table 1. Overvoltage Threshold Selection
THRESHOLD (V)
14
OVERVOLTAGE SELECTION
OVSEL3
OVSEL2
OVSEL1
OVSEL0
3.3
0
0
0
0
3.4
0
0
0
1
3.5
0
0
1
0
3.6
0
0
1
1
3.7
0
1
0
0
3.8
0
1
0
1
3.9
0
1
1
0
4.0
0
1
1
1
4.1
1
0
0
0
4.2
1
0
0
1
4.3
1
0
1
0
4.4
1
0
1
1
4.5
1
1
0
0
4.6
1
1
0
1
4.7
1
1
1
0
4.8
1
1
1
1
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
MAX11080/MAX11081
VOV
VOV - VHYS
ANY
CELL
CELL
VOLTAGE
VCD
CD
ALRML
Figure 9. Single-Cell Overvoltage Detection Example
VOV
VOV - VHYS
CELL 12
CELL 11
CELL
VOLTAGE CELL N
CELL 1
VCD
CD
ALRML
Figure 10. Multiple-Cell Overvoltage Detection Example
______________________________________________________________________________________
15
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
Table 2. Undervoltage Threshold Selection
UNDERVOLTAGE SELECTION
THRESHOLD (V)
UVSEL2
UVSEL1
Disabled
0
0
0
1.6
0
0
1
1.8
0
1
0
2.0
0
1
1
2.2
1
0
0
2.4
1
0
1
2.6
1
1
0
2.8
1
1
1
selection is sensed and stored at power-up and any
subsequent change to the input pin status is ignored.
Internal Linear Regulator
The MAX11080/MAX11081 have an internal linear regulator for generating the internal supply from DCIN (Figure
11). The regulator can accept a supply voltage on the
DCIN pin from +6.0V to +72V, which it regulates to 3.3V
to run the voltage-detection system, control logic, and
low-side alarm-pulse interface. When the SHDN pin is not
active and a sufficient voltage is applied to DCIN, the output of the regulator becomes active. The regulator is
paired with a power-on-reset (POR) circuit that senses its
output voltage and holds the MAX11080/MAX11081 in a
reset state until the internal supply has reached a sustainable threshold of +3.0V (±5%). The internal comparators
have built-in hysteresis that can reject noise on the supply
DCIN
UVSEL0
+6.0V TO +72V
LINEAR
REGULATOR
line. Because secondary metal batteries are never fully
discharged to 0V, the MAX11080/MAX11081 are
designed for a hot-swap insertion of the battery cells.
Once the POR threshold is reached, approximately 1ms
later the internal reset signal disables, the internal oscillator starts, and the charge pump begins operating. The
charge pump reaches regulation in approximately 3ms.
The MAX11080/MAX11081 associated with the top module in the battery pack are identified as detailed in the
TOPSEL Function section. This is followed by a self-test of
the overvoltage comparators and detection of the number
of cells connected. At this time in the power-on
sequence, the MAX11080/MAX11081 are ready for operation. When the charge pump achieves regulation of 3.3V
between VDDU and GNDU, it switches to a standby mode
until the voltage drops by about 35mV. The specified
accuracy and full operation of the MAX11080/MAX11081
INTERNAL +3.3V
VAA
SHDN
GNDU
REGULATOR
ENABLE
CHARGE
PUMP
DIE OVERTEMPERATURE
DETECT
BANDGAP
REFERENCE
CHARGE-PUMP
ENABLE
35mV
HYSTERESIS
AGND
POR THRESHOLD
VDDU
2.6V
CP POR
COMPARATOR
+3.3V TO
GNDU
CP_POR/
+3.0V ±5%
POR
COMPARATOR
INTERNAL
POR/
VAA POR/
Figure 11. Internal Linear Regulator Block Diagram
16
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
16kHz OSCILLATOR
ENABLED
CHARGE-PUMP
INTERNAL RESET
ASSERTED
START CELL SHORTCIRCUIT TEST
FOR EACH CELL
INPUT N
(VDDU - GNDU) < 2.6V
1.1ms TYP
CHECK (VDDU GNDU)
VOLTAGE APPLIED
TO DCIN
NEXT INPUT N
(VDDU - GNDU) > 2.6V
1.0ms TYP
CHARGE-PUMP
INTERNAL RESET
DEASSERTED
SHDN ASSERTED
CHECK SHDN
OVSEL/UVSEL
INPUTS LATCHED
CHARGE-PUMP
ENABLED
INTERNAL POR
RESET ASSERTED
INTERNAL POR
RESET DEASSERTED
SHORT-CIRCUIT
COMPARATOR [N]
DETECTS SHORT?
YES
INPUT [N] UV
COMPARATOR
DISABLED
NO
0.7ms TYP
VDDU WITHIN
REGULATION
SHDN DEASSERTED
MAX11080/MAX11081
VAA POR RESET
ASSERTED
ALARM STATE
DISABLED
NEXT INPUT N
REGULATOR ENABLED
START OVERVOLTAGE
COMPARATOR TEST
VAA < 3.0V
0.2ms TYP
CELL SHORT-CIRCUIT
TEST DONE
NUMBER OF CELLS
DETECTED
CHECK VAA
CONNECT GROUND AS
OV THRESHOLD
1.0ms TYP
MAX11080/MAX11081
FULLY FUNCTIONAL
VAA > 3.0V
VAA POR RESET
DEASSERTED
FAULT: ALRML
ASSERTED UNTIL
NEXT ACTIVE POR
NO
ALL
OV COMPARATORS
OUTPUT HIGH?
YES
1.8ms TYP
REGULATOR IN
REGULATION
DISCONNECT GROUND
AS OV THRESHOLD
OVERVOLTAGE
COMPARATOR TEST
DONE
Figure 12. Linear Regulator Power-Up Sequence
are not guaranteed until a minimum of 6.0V is applied to
the DCIN pin.
The linear regulator also incorporates a thermal shutdown
feature. If the MAX11080/MAX11081 die temperature
rises above +145°C, the device shuts down. After a thermal shutdown, the die temperature must cool 15°C below
the shutdown temperature before the device restarts.
Figure 12 shows the linear regulator power-up sequence
and Figure 13 shows the low DCIN POR event.
VAA AND INTERNAL
POR INACTIVE
FALLING DCIN
VOLTAGE
VAA > 2.8V
CHECK VAA
VAA < 2.8V
DCIN and GNDU Supply Connections
VAA AND INTERNAL
POR ACTIVE
A surge voltage is produced by the electric motor
during regenerative braking conditions. The
MAX11080/MAX11081 are designed to tolerate an
absolute maximum of 80V under this condition. The
MAX11080/MAX11081 should be protected against higher voltages with an external voltage suppressor such as
OSCILLATOR,
CHARGE-PUMP,
DIGITAL LOGIC,
AND ALARM PULSE
DISABLED
Figure 13. Low DCIN POR Event
______________________________________________________________________________________
17
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
22Ω
TOP OF
CELL STACK
TO GNDU
INPUT
RLIMIT
22Ω
5kΩ
SEE THE APPLICATION CIRCUIT
DIAGRAM FOR PROPER
CONNECTION LOCATION
CDCIN
0.1µF
80V
100kΩ
TO DCIN
INPUT
SMCJ70
Figure 14. Battery Module Surge and Overvoltage Protection
Circuit
the SMCJ70 on the DCIN connection point. This protection circuit also helps to reduce power spikes that can
occur during the insertion of the battery cells. During
negative voltage excursions, the protection circuit stores
enough charge to power the regulator through the transient. Figure 14 shows the clamp configuration to protect
the DCIN supply input.
The DCIN input contains a comparator circuit to detect an
open circuit on this pin for fault-management purposes.
Whenever a nominal voltage of two silicon diode drops
appears between C12 and DCIN following the power-up
sequence, the ALRML output is asserted as a fault indication. This voltage drop must appear for at least the delay
time set by CDLY to result in a fault. The voltage drop from
C12 to DCIN during normal operation should be kept at
no more than 0.5V to prevent erroneous tripping of the
DCIN open-circuit comparator under worst-case circumstances (lowest silicon diode forward bias voltage). The
diode DDCIN is used to supply the transient current
demanded at startup by the decoupling circuit. In parallel
with this diode, RDCIN provides the supply path during
normal operation. It is selected to be 5kΩ so that the maximum voltage drop between C12 and DCIN is about
0.25V with nominal supply currents.
High-power batteries are often used in noisy environments subject to high dV/dt or dI/dt supply noise and
EMI noise. For example, the supply noise of a power
inverter driving a high horse-power motor produces a
large square wave at the battery terminals, even though
the battery is also a high-power battery. Typically, the
battery dominates the task of absorbing this noise, since
it is impractical to put hundreds of farads at the inverter.
The MAX11080/MAX11081 are designed with several
mechanisms to deal with extremely noisy environments.
First, the major power-supply inputs that see the full
battery-stack voltage are 80V tolerant. This is high
enough to handle the large voltage changes on the battery stack that can occur when the batteries transition
18
between charge and discharge conditions. Next, the
linear regulator has high PSRR to produce a clean lowvoltage power supply for the internal circuitry. This
allows DCIN to be connected directly to the stack voltage. Finally, GNDU serves two purposes. It supplies the
internal charge pump with its power and acts as the reference ground for the upper alarm communication port.
The charge pump creates a secondary low-voltage
supply that is referenced to GNDU. Because the levelshifted supply VDDU is referenced to GNDU, the entire
upper alarm communication port glides smoothly on
GNDU and it is effectively immune to noise on GNDU.
The upper alarm signal is internally shifted down to
AGND level where it is processed by the digital logic.
There are two connection methods that can be used for
GNDU depending on application requirements.
For the top module in a system, or where GNDU cannot
be DC-coupled to the next higher module for other reasons, GNDU should be connected to the same location
as DCIN. This connection is valid as long as the voltage
difference between the top of Stack(n) and the bottom
of Stack(n+1) during worst-case conditions does not
exceed the margin of the alarm pin signaling levels.
When GNDU is not DC-coupled to the far side of the
bus bar, it can be AC-coupled to the far side to maintain alarm communication when the bus bar is open-circuit. In that case, the two sides of the AC-coupling
capacitor can be at different DC potentials, but the
alarm communication signal continues to be passed
across the capacitor connection. It is recommended
that an AC- or DC-coupled version of GNDU is paired
with the alarm signal through the communication bus
wiring, possibly by twisted pair wire, for maximum noise
immunity and minimum emissions.
The preferred connection to reject noise between modules is when a DC connection can be made from GNDU
to AGND of the next module. It is again recommended
that the DC-coupled GNDU signal is routed adjacent to
the alarm signal as part of the communication bus for
maximum noise immunity and minimum emissions.
Shutdown Control
The SHDN pin connections of the MAX11080/MAX11081
operate in a manner that allows the shutdown/wake-up
command to trickle up through the series of daisychained packs. Because the internal linear regulator is
powered down during shutdown, the shutdown function
must operate when VAA is absent and, therefore, it cannot depend on a Schmitt trigger input. A special low-current, high-voltage circuit is used to detect the state of the
SHDN pin. The shutdown pin has a +2.1V minimum
threshold for the inactive state. When SHDN > 2.1V, the
MAX11080/MAX11081 turn on and begin regulating VAA,
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
MAX11080/MAX11081
MODULEN+1
MODULEN+1
DCIN
C12
DCIN
GNDU
C12
C11
C11
C2
ALRML
C2
ALRML
C1
SHDN
C1
SHDN
C0
AGND
OPTIONAL
TO MAINTAIN
ALARM
COMMUNICATION
MODULEN
BUS BAR
C0
BUS BAR
GNDU
AGND
MODULEN
DCIN
DCIN
DC
ISOLATOR
C12
GNDU
C11
CP+
C12
GNDU
C11
CP+
ALRMU
ALRMU
C2
C2
C1
C1
C0
C0
AGND
AGND
Figure 15. GNDU Connection: AC-Coupled to Next Module,
DC-Coupled to Present Module
Figure 16. GNDU Connection: DC-Coupled with the
Communication Bus
______________________________________________________________________________________
19
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
S1B
150I
1kI
CP+
DEVICE
(n)
SHDN
5.6V
100nF
5.6V
68nF
DEVICE
(n+1)
200kI
GNDU
AGND
Figure 17. Shutdown Circuit Interface
and then VDD U . If SHDN < 0.6V, the MAX11080/
MAX11081 shut down.
Figure 17 shows the shutdown circuit interface of two
daisy-chain devices.
When SHDN is high for device n, the charge pump is
enabled and begins to charge the capacitors in the
interface circuit. When the voltage of the SHDN pin for
device (n+1) rises above the VIH threshold, that device
begins its power-up sequence. This action propagates
up the daisy-chain until the last battery module is
enabled. Conversely, pulling SHDN to AGND powers
down a module and thus propagates the power-down
to all higher daisy-chained modules as the charge on
their SHDN capacitors is dissipated. The zener diodes
provide additional ESD protection. The filter capacitors
and resistors are sized to provide robust noise immunity. The diode from the CP+ pin should be S1B or a similar low-leakage type for high-temperature stability.
The SHDN pin has a weak internal pulldown resistor on
the order of 12MΩ. A 200kΩ or similar resistor from SHDN
to AGND should be installed to ensure that the SHDN pin
is pulled low when the active SHDN signal is propagated
up the daisy-chain bus. The resistor is not needed for
applications that tie SHDN high at all times. The typical
SHDN rising edge propagation time from one daisychained module to the next is 1.5ms.
For FMEA detectability, the SHDN pin is designed to
detect logic transitions that could be indicative of a
short circuit to the ALRML pin. The SHDN pin circuit
shown in Figure 18 provides some immunity for rare
glitches at the SHDN pin, such as those during powerup, that are not a result of a short to ALRML. The SHDN
pin signal is fed as a clock to a 5-bit counter. When the
counter reaches the maximum count of 32, the full flag
is set and acts as a clock to a D flip-flop. When the D
flip-flop is clocked, its output goes high to signal the
FMEA fault condition and trigger the alarm. In this way,
the device goes into the alarm state only after 32 pulses
20
ALRMU
VAA
D
Q
FMEA FLAG
ALRML
5 BIT UP
FULL FLAG
SHDN
COUNTER
CLK
INTERNAL ALARM
SIGNAL
RST
PORb
Figure 18. Internal FMEA SHDN Pin Functionality Circuit
on the SHDN pin have occurred. To clear the FMEA
fault state, a POR of the device must be activated. The
application circuit should ensure that the SHDN pin is
glitch free and only toggles when a shutdown or powerdown event is intended. This FMEA detection circuit
should not be considered as a provision to filter out
noise or glitches on the SHDN pin.
C1 Input Absolute Maximum Rating
The C1 input is limited to VDCIN - 0.6V above AGND or
a maximum of 20V if the SHDN pin is asserted. If an
application requires that the 20V restriction be removed
during active shutdown, then a 4.0V zener diode can
be added from VAA to AGND. This protects VAA and
allows the C1 input to go to VDCIN - 0.6V regardless of
the SHDN state. It also allows the differential C1 to C0
voltage to range from -0.3V to +80V.
Cell-Connection and Detection
An individual MAX11080/MAX11081 can be connected to
as many as 12 series-connected cells. To accommodate
configurations with fewer cells, unused cell inputs must be
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
Internal Self-Test
The MAX11080/MAX11081 perform an internal self-test
during power-up according to the linear regulator
power-up flowchart (Figure 12). Each overvoltage comparator is tested for the ability to detect an internally
generated overvoltage test condition. This is done by
using the ground voltage level as the threshold reference in place of the usual threshold level. Figure 8
shows the connection for this test-mode compare level.
If all comparators can detect the internally generated
overvoltage test event, part operation continues. If any
comparator fails to detect the internally generated overvoltage test event, a fault is signaled using the ALRML
pin. The device must be power cycled to retest the
comparators and attempt to clear this fault condition.
TOPSEL Function
Failure Mode and Effects Analysis
The TOPSEL pin is used to indicate to a device whether
it is the top device in the daisy-chain stack. The top
daisy-chain device is responsible for generating the
heartbeat signal at the top of the ALRM_ pin bus. This
heartbeat propagates along the chain toward the host.
To designate a device as the top device, the TOPSEL
pin should be connected to VAA. For all other devices
in a daisy-chain, this pin should be connected to
AGND. The TOPSEL pin has a weak internal pulldown
resistor, but this resistor should not be relied upon as
the sole means of setting the TOPSEL logic level. The
logic level of the TOPSEL pin is not latched internally at
startup and is continuously sampled during operation.
The ALRMU input should be connected to GNDU for the
top module as good design practice to prevent noise
pickup even though the input logic level is ignored.
For a single device or DC-coupled daisy-chain application, the device can be operated in an alarm level mode
instead of heartbeat mode by tying TOPSEL to AGND for
all devices. In this mode of operation, ALRML passes the
signal of ALRMU when the device is not in the alarm state.
ALRML drives high when the device is in the alarm state.
ALRMU must be tied to GNDU for the topmost device for
this application. The following table summarizes the
operation of TOPSEL and ALRML for level mode:
High-voltage battery-pack systems can be subjected to
severe stresses during in-service fault conditions and
could experience similar conditions during the manufacturing and assembly process. The MAX11080/MAX11081
are designed with high regard to these potential states.
Open and short circuits at the package level must be
readily detected for fault diagnosis and should be tolerated whenever possible. A number of circuits are
employed within the MAX11080/MAX11081 specifically
to detect such conditions and progress to a known
device state. Table 3 summarizes other conditions typical in a normal manufacturing process along with their
effect on the MAX11080/MAX11081 devices.
See Table 4 for the FMEA analysis of the MAX11080/
MAX11081. If the cell voltage is within the monitor
range, the heartbeat signal on ALRML resumes once
the fault condition (either open or short) is removed,
unless otherwise specified.
TOPSEL
ALRMU
0
1
ALRML
No alarm
Alarm
0
ALRMU
1
X
Heartbeat
1
______________________________________________________________________________________
21
MAX11080/MAX11081
shorted together, but Cell 1 must always be populated.
The designer can choose which cell inputs to leave
unused. The example application circuits recommended
are the most efficient configurations.
At power-up, the part compares the voltage applied to
each cell input with a nominal cell-detection threshold
voltage of 0.7V. If the cell voltage is less than the celldetection threshold, undervoltage detection is disabled
for that cell input. If the voltage at the input is 0.7V or
greater, undervoltage detection is specified by the state
of the UVSEL_ inputs. Overvoltage detection is always
enabled for all cell-voltage inputs. The cell-connection
detection occurs just before the MAX11080/MAX11081
are fully functional as shown in Figure 12 under NUMBER
OF CELLS DETECTED.
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
Table 3. System Fault Modes
CONDITION
EFFECT
DESIGN RECOMMENDATION
Refer to the pin-level FMEA analysis
spreadsheet available from the factory
The built-in features of the
MAX11080/MAX11081, should ensure low FMEA
risk in most cases.
Random connection of cells to IC—
no stack load
No effect
The series resistors on the cell inputs of the
MAX11080/MAX11081, as well as the internal
design, ensure protection against random
power-supply or ground connections.
Random connection of modules—
no stack load
No effect
Each module is referenced to its neighbor, so no
special connection order is necessary.
Random connect/disconnect of
communication bus—no stack load;
AC- or DC-coupled
Communication from host to the first
break in the daisy-chain bus
The level-shifted interface design of the
MAX11080/MAX11081 ensures that the SHDN,
GNDU, and ALRM_ communication bus can be
connected at any time with no load.
Random connect/disconnect of
communication bus—with stack load;
AC- or DC-coupled
Communication from host to the first
break in the daisy-chain bus
The level-shifted interface design of the
MAX11080/MAX11081 ensures that the SHDN,
GNDU, ALRM_ communication bus can be
connected at any time as long as the power
bus is properly connected.
Connect/disconnect module
interconnect (bus bar)—no stack load
No effect for DC- or AC-coupled
communication bus
A break in the power bus does not cause a
problem as long as there is no load on the
stack.
Removal/fault of module interconnect
(bus bar)—with stack load
No effect for AC-coupled
communication bus; device damage for
DC-coupled bus
An AC-coupled bus with isolation on the SHDN
pin or a redundant bus-bar connection should
be used to protect against this case.
Removal/fault of module interconnect
(bus bar)—with stack under charge
No effect for AC-coupled
communication bus; device damage for
DC-coupled bus
An AC-coupled bus with isolation on the SHDN
pin or a redundant bus-bar connection should
be used to protect against this case.
PCB or IC package open or short
circuit—no stack load
22
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
PIN
NUMBER
NAME
1
DCIN
2
HV
3
4
5
6
7
N.C.
ACTION
EFFECT
Open (or Disconnected)
ALRML goes high (see Note 7).
Short to Pin 2
ALRML goes high.
Open (or Disconnected)
ALRML goes high.
Short to Pin 3
No effect.
Open (or Disconnected)
No effect.
Short to Pin 4
No effect.
Open (or Disconnected)
• If open occurs before power-up, the part works as if C12 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C12 to C11 is disabled and is
not enabled even if the pin is reconnected.
• If open occurs after power-up, it is considered a zero voltage input. ALRML
goes high when the undervoltage is enabled.
Short to Pin 5
• If short occurs before power-up, the part works as if C12 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C12 to C11 is disabled and is
not enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C12 to C11. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high because it causes an overvoltage to the affected input pair
even if the overvoltage is set to the maximum.
Short to Pin 6
• If short occurs before power-up, the part works as if C11 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C11 to C10 is disabled and is
not enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C11 to C10. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 7
• If short occurs before power-up, the part works as if C10 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C10 to C9 is disabled and is
not enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C10 to C9. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 8
• If short occurs before power-up, the part works as if C9 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C9 to C8 is disabled and is not
enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C9 to C8. ALRML goes high when the undervoltage is enabled.
C12
C11
C10
C9
______________________________________________________________________________________
23
MAX11080/MAX11081
Table 4. FMEA Analysis (Note 6)
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
Table 4. FMEA Analysis (Note 6) (continued)
PIN
NUMBER
8
9
10
11
12
24
NAME
ACTION
EFFECT
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 9
• If short occurs before power-up, the part works as if C8 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C8 to C7 is disabled and is not
enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C8 to C7. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 10
• If short occurs before power-up, the part works as if C7 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C7 to C6 is disabled and is not
enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C7 to C6. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 11
• If short occurs before power-up, the part works as if C6 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C6 to C5 is disabled and is not
enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C6 to C5. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 12
• If short occurs before power-up, the part works as if C5 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C5 to C4 is disabled and is not
enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C5 to C4. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 13
• If short occurs before power-up, the part works as if C4 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C4 to C3 is disabled and is not
enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C4 to C3. ALRML goes high when the undervoltage is enabled.
C8
C7
C6
C5
C4
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
PIN
NUMBER
13
14
15
16
17
18
19
NAME
ACTION
EFFECT
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 14
• If short occurs before power-up, the part works as if C3 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C3 to C2 is disabled and is not
enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C5 to C4. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 15
• If short occurs before power-up, the part works as if C2 does not exist
because the internal circuit detects the situation and assumes it is what the
application intended to do. The monitoring of C2 to C1 is disabled and is not
enabled even if the short is removed.
• If short occurs after power-up, the situation is treated as a zero voltage input
for C2 to C1. ALRML goes high when the undervoltage is enabled.
Open (or Disconnected)
ALRML goes high as it causes an overvoltage to the affected input pair even if
the overvoltage is set to the maximum.
Short to Pin 16
ALRML goes high irrespective of whether undervoltage is enabled/disabled
and before and after power-up.
Open (or Disconnected)
No effect.
Short to Pin 17
• If pin 17 is tied to VAA, then VAA is shorted to AGND and ALRML goes low.
• If pin 17 is tied to AGND, there is no effect.
Open (or Disconnected)
The pin defaults to low due to the internal pulldown (see Note 8). The effect
depends on the intended undervoltage setting.
Short to Pin 18
• If pin 17 and pin 18 have the same intended value, there is no effect for the
short.
• If pin 17 and pin 18 have a different setting, the VAA is shorted to AGND.
ALRML goes low.
Open (or Disconnected)
The pin defaults to low due to the internal pulldown (see Note 8). The effect
depends on the intended undervoltage setting.
Short to Pin 19
• If pin 18 and pin 19 have the same intended value, there is no effect for the
short.
• If pin 18 and pin 19 have a different setting, the VAA is shorted to AGND.
ALRML goes low.
Open (or Disconnected)
The pin defaults to low due to the internal pulldown (see Note 8). The effect
depends on the intended undervoltage setting.
Short to Pin 20
• If pin 19 and pin 20 have the same intended value, there is no effect for the
short.
• If pin 19 and pin 20 have the different setting, the VAA is shorted to. AGND
ALRML goes low.
C3
C2
C1
C0
UVSEL0
UVSEL1
UVSEL2
______________________________________________________________________________________
25
MAX11080/MAX11081
Table 4. FMEA Analysis (Note 6) (continued)
MAX11080/MAX11081
12-Channel, High-Voltage
Battery-Pack Fault Monitors
Table 4. FMEA Analysis (Note 6) (continued)
PIN
NUMBER
20
21
22
23
Short to Pin 21
• If pin 20 and pin 21 have the same intended value, there is no effect for the
short.
• If pin 20 and pin 21 have a different setting, the VAA is shorted to AGND.
ALRML goes low.
Open (or Disconnected)
The pin defaults to low due to the internal pulldown (see Note 8). The effect
depends on the intended overvoltage setting.
Short to Pin 22
• If pin 21 and pin 22 have the same intended value, there is no effect for the
short.
• If pin 21 and pin 22 have a different setting, the VAA is shorted to AGND.
ALRML goes low.
Open (or Disconnected)
The pin defaults to low due to the internal pulldown (see Note 8). The effect
depends on the intended overvoltage setting.
Short to Pin 23
• If pin 22 and pin 23 have the same intended value, there is no effect for the
short.
• If pin 22 and pin 23 have a different setting, the VAA is shorted to AGND.
ALRML goes low.
Open (or Disconnected)
The pin defaults to low due to the internal pulldown (see Note 8). The effect
depends on the intended overvoltage setting.
Short to Pin 24
• If pin 23 is set high, there is no effect for the short.
• If pin 23 is set low, the VAA is shorted to AGND. ALRML goes low.
OVSEL3
AGND
28
The pin defaults to low due to the internal pulldown (see Note 8). The effect
depends on the intended overvoltage setting.
OVSEL2
25
Open (or Disconnected)
ALRML goes high.
Short to Pin 25
ALRML goes low.
Open (or Disconnected)
VAA goes to approximately 100mV and ALRML is approximately 0.5V. There is
no heartbeat if there is a one before the opening.
Short to Pin 26
The device is in shutdown mode. ALRML is low.
Open (or Disconnected)
The pin is internally pulled down and the device goes to the shutdown mode.
ALRML is low.
Short to Pin 27
ALRML goes high and stays high even if the short is removed. The internal
detect circuit considers this a major failure and the part has to be repowered
up to come out of this state.
Open (or Disconnected)
The signal at the ALRML cannot be seen by the host.
Short to Pin 28
ALRML goes high and stays high even if the short is removed. The internal
detect circuit considers this a major failure and the part has to be repowered
up to come out of this state.
Open (or Disconnected)
The delay between the fault condition and alarm setting (ALRML goes high)
goes to the minimum. This means there is almost no delay.
Short to Pin 29
The delay between the fault condition and alarm setting (ALRML goes high) is
approximately 4s, which is set by the internal watchdog.
SHDN
ALRML
EFFECT
Open (or Disconnected)
OVSEL1
VAA
27
ACTION
OVSEL0
24
26
26
NAME
CD
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
PIN
NUMBER
NAME
29
TST1
30
31
TST2
TST3
33
N.C.
Open (or Disconnected)
No effect.
Short to Pin 30
No effect.
Open (or Disconnected)
No effect.
Short to Pin 31
If pin TOPSEL is set high (VAA), it causes the short between VAA and AGND.
ALRML is low.
There is no effect if TOPSEL is set low.
Open (or Disconnected)
If the part is the topmost device in the daisy chain, the ALRML is set high as
the state of TOPSEL is low (internally pulled down).
There are no other effects as the state of the pin stays the same (both low).
Short to Pin 32
No effect if TOPSEL is set low.
If TOPSEL is set high, it causes the short between VAA and AGND and ALRML
is low.
Open (or Disconnected)
No effect.
Short to Pin 33
No effect.
Open (or Disconnected)
No effect.
Short to Pin 34
No effect.
Open (or Disconnected)
ALRMU is internally pulled up to VDDU. There is no effect to the topmost
device. Otherwise, the communication of the chain is broken and the alarm
signal from the parts close to the topmost device are not passed through.
Since ALRML is a reflection of ALRMU, the state of ALRML is high for the noalarm state.
Short to Pin 35
No effect for the topmost device. Otherwise, the communication of the chain is
broken and the alarm signal from the parts close to the topmost are not
passed through. Since ALRML is a reflection of ALRMU, the state of ALRML is
low for the no-alarm state.
Open (or Disconnected)
The ALRML goes high.
Short to Pin 36
The ALRML is high. (See Note 9.)
Open (or Disconnected)
ALRML goes high. HV is approximately 0.4V below DCIN. (See Note 9.)
Short to Pin 37
ALRML goes high. VDDU is approximately 0.5V lower than GNDU.
(See Note 9.)
ALRMU
35
GNDU
36
VDDU
37
CP-
38
CP+
Note 6:
Note 7:
Note 8:
Note 9:
EFFECT
TOPSEL
32
34
ACTION
Open (or Disconnected)
ALRML goes high. VDDU and HV collapse.
Short to Pin 38
ALRML goes high. VDDU is approximately 0.5V lower than GNDU.
(See Note 9.)
Open (or Disconnected)
ALRML goes high. VDDU and HV collapse. (See Note 9.)
If the cell voltage is within the monitor range, the heartbeat signal on ALRML resumes once the fault condition is removed.
The voltage level of high is equal to VAA and low is equal to AGND.
Even if the pin has internal pulldown, the pulldown is very weak and the pin should be tied to AGND for logic 0 setting.
VDDU - GNDU = 3.3V and HV - DCIN = 3.6V for the typical configuration. When VDDU and HV collapse, VDDU - GNDU ≈ 0V
and HV - DCIN ≈ -0.4V.
______________________________________________________________________________________
27
MAX11080/MAX11081
Table 4. FMEA Analysis (Note 6) (continued)
12-Channel, High-Voltage
Battery-Pack Fault Monitors
MAX11080/MAX11081
Pin Configuration
TOP VIEW
DCIN
1
+
38
CP+
HV
2
37
CP-
N.C.
3
36
VDDU
C12
4
35
GNDU
C11
5
34
ALRMU
C10
6
33
N.C.
C9
7
32
TST1
C8
8
31
TOPSEL
C7
9
30
TST2
C6
10
29
TST3
C5
11
28
CD
C4
12
27
ALRML
C3
13
26
SHDN
C2
14
25
AGND
C1
15
24
VAA
C0
16
23
OVSEL3
UVSEL0
17
22
OVSEL2
UVSEL1
18
21
OVSEL1
UVSEL2
19
20
OVSEL0
MAX11080
MAX11081
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
38 TSSOP
U38-1
21-0081
90-0140
TSSOP
28
______________________________________________________________________________________
12-Channel, High-Voltage
Battery-Pack Fault Monitors
REVISION
NUMBER
REVISION
DATE
0
4/09
Initial release
1
6/10
Added the MAX11081; corrected bugs found in application; new derivative of
C015 featuring timed fault hysteresis in the order of 50mV or less
DESCRIPTION
PAGES
CHANGED
—
1–29
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX11080/MAX11081
Revision History
工商网监
湘ICP备2023018690号
