19-3866; Rev 0; 4/06
KIT
ATION
EVALU
E
L
B
A
AVAIL
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
The MAX1214N is a monolithic, 12-bit, 210Msps analog-to-digital converter (ADC) optimized for outstanding
dynamic performance at high-IF frequencies beyond
300MHz. The product operates with conversion rates
up to 210Msps while consuming only 799mW.
At 210Msps and an input frequency up to 100MHz, the
MAX1214N achieves an 81.3dBc spurious-free dynamic range (SFDR) with excellent 67dB signal-to-noise
ratio (SNR) that remains flat (within 2dB) for input tones
up to 250MHz. This makes it ideal for wideband applications such as communications receivers, cable-head
end receivers, and power-amplifier predistortion in cellular base-station transceivers.
The MAX1214N operates from a single 1.8V power supply. The analog input is designed for AC-coupled differential or single-ended operation. The ADC also features
a selectable on-chip divide-by-2 clock circuit that
accepts clock frequencies as high as 420MHz. A lowvoltage differential signal (LVDS) sampling clock is recommended for best performance. The converter
provides LVDS-compatible digital outputs with data format selectable to be either two’s complement or offset
binary.
The MAX1214N is available in a 68-pin QFN package
with exposed paddle (EP) and is specified over the
industrial (-40°C to +85°C) temperature range.
See the Pin-Compatible Versions table for a complete
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in
this family.
Features
♦ 210Msps Conversion Rate
♦ Excellent Low-Noise Characteristics
SNR = 67dB at fIN = 100MHz
SNR = 65dB at fIN = 250MHz
♦ Excellent Dynamic Range
SFDR = 81.3dBc at fIN = 100MHz
SFDR = 84.9dBc at fIN = 250MHz
♦ Single 1.8V Supply
♦ 799mW Power Dissipation at fSAMPLE = 210Msps
and fIN = 100MHz
♦ On-Chip Track-and-Hold Amplifier
♦ Internal 1.24V-Bandgap Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ MAX1214NEVKIT Available
Ordering Information
PART
TEMP RANGE
MAX1214NEGK-D
-40°C to +85°C 68 QFN-EP*
G6800-4
G6800-4
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
Pin-Compatible Versions
Base-Station Power-Amplifier Linearization
RESOLUTION
(BITS)
SPEED
GRADE
(Msps)
ON-CHIP
BUFFER
MAX1121
8
250
Yes
MAX1122
10
170
Yes
MAX1123
10
210
Yes
MAX1124
10
250
Yes
MAX1213
12
170
Yes
MAX1214
12
210
Yes
MAX1215
12
250
Yes
MAX1213N
12
170
No
MAX1214N
12
210
No
MAX1215N
12
250
No
PART
Wireless and Wired Broadband Communications
Communications Test Equipment
Radar and Satellite Subsystems
PKG
CODE
MAX1214NEGK+D -40°C to +85°C 68 QFN-EP*
Applications
Cable-Head End Receivers
PINPACKAGE
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1214N
General Description
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
ABSOLUTE MAXIMUM RATINGS
AVCC to AGND ......................................................-0.3V to +2.1V
OVCC to OGND .....................................................-0.3V to +2.1V
AVCC to OVCC .......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
INP, INN to AGND ....................................-0.3V to (AVCC + 0.3V)
All Digital Inputs to AGND........................-0.3V to (AVCC + 0.3V)
REFIO, REFADJ to AGND ........................-0.3V to (AVCC + 0.3V)
All Digital Outputs to OGND ....................-0.3V to (OVCC + 0.3V)
Current into Any Pin..........................................................±50mA
Continuous Power Dissipation (TA = +70°C, multilayer board)
68-Pin QFN-EP (derate 41.7mW/°C above +70°C)....3333mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering,10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω. Limits are for TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
Bits
fIN = 10MHz (Note 2)
-2.1
±0.75
+2.1
LSB
DNL
No missing codes (Note 2)
-1.0
±0.3
+1.3
LSB
VOS
(Note 2)
Integral Nonlinearity
INL
Differential Nonlinearity
Transfer Curve Offset
-3
+3
Offset Temperature Drift
mV
±15
µV/°C
1390
mVP-P
±60
ppm/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
VFS
1150
Full-Scale Range Temperature
Drift
Common-Mode Input Voltage
VCM
Differential Input Capacitance
CIN
Differential Input Resistance
Full-Power Analog Bandwidth
Internally self-biased
0.7
V
2.5
pF
RIN
1.8
kΩ
FPBW
700
MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
VREFIO
REFADJ = AGND
1.18
1.24
Reference Temperature Drift
REFADJ Input High Voltage
90
VREFADJ
Used to disable the internal reference
AVCC - 0.3
1.30
V
ppm/°C
V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
fSAMPLE
Minimum Sampling Rate
fSAMPLE
Clock Duty Cycle
210
MHz
20
40 to 60
%
Aperture Delay
tAD
Figures 5, 11
620
ps
Aperture Jitter
tAJ
Figure 11
0.15
psRMS
2
Set by clock-management circuit
MHz
_______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω. Limits are for TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
200
500
mVP-P
1.15 ±0.25
V
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 3)
Clock Input Common-Mode
Voltage Range
Internally self-biased
Clock Differential Input
RCLK
11 ±25%
kΩ
Clock Differential Input
Capacitance
CCLK
5
pF
DYNAMIC CHARACTERISTICS (at AIN = -1dBFS)
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
SNR
SINAD
fIN = 10MHz
65.5
fIN = 100MHz
65.2
SFDR
Worst Harmonics
(HD2 or HD3)
Two-Tone Intermodulation
Distortion
TTIMD
67
fIN = 200MHz
65.3
fIN = 250MHz
65.0
fIN = 10MHz
65.3
67.2
fIN = 100MHz
64.9
66.6
fIN = 200MHz
dB
dB
65.2
fIN = 250MHz
Spurious-Free Dynamic Range
67.3
64.9
fIN = 10MHz
77.0
88.5
fIN = 100MHz
76.0
81.3
dBc
fIN = 200MHz
82.8
fIN = 250MHz
84.9
fIN = 10MHz
-88.5
-77.0
fIN = 100MHz
-81.3
-76.0
fIN = 200MHz
-82.8
fIN = 250MHz
-84.9
fIN1 = 97MHz at -7dBFS,
fIN2 = 100MHz at -7dBFS
-79
dBc
dBc
LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N)
Differential Output Voltage
|VOD|
RL = 100Ω
280
440
mV
Output Offset Voltage
OVOS
RL = 100Ω
1.110
1.370
V
_______________________________________________________________________________________
3
MAX1214N
ELECTRICAL CHARACTERISTICS (continued)
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100Ω. Limits are for TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input-Voltage Low
VIL
Digital Input-Voltage High
VIH
0.2 x AVCC
0.8 x AVCC
V
V
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay
CLK-to-DCLK Propagation Delay
DCLK-to-Data Propagation Delay
tPDL
Figure 5
tCPDL
Figure 5
tCPDL - tPDL Figure 5 (Note 3)
2.05
ns
3.95
1.8
1.9
ns
2.0
ns
LVDS Output Rise Time
tRISE
20% to 80%, CL = 5pF
450
ps
LVDS Output Fall Time
tFALL
20% to 80%, CL = 5pF
450
ps
Figure 5
11
Clock
cycles
Output Data Pipeline Delay
tLATENCY
POWER REQUIREMENTS
Analog Supply Voltage Range
AVCC
Digital Supply Voltage Range
OVCC
Analog Supply Current
IAVCC
fIN = 100MHz
Digital Supply Current
IOVCC
Analog Power Dissipation
PDISS
Power-Supply Rejection Ratio
(Note 4)
Note 1:
Note 2:
Note 3:
Note 4:
4
PSRR
1.70
1.80
1.90
V
1.70
1.80
1.90
V
379
410
mA
fIN = 100MHz
65
71
mA
fIN = 100MHz
799
866
Offset
1.8
mV/V
Gain
1.5
%FS/V
mW
Values at TA ≥ +25°C guaranteed by production test, values at TA < +25°C guaranteed by design and characterization.
Static linearity and offset parameters are computed from an end-point curve fit.
Parameter guaranteed by design and characterization: TA = -40°C to +85°C.
PSRR is measured with both analog and digital supplies connected to the same potential.
_______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
-60
-70
2
-80
-50
-60
-70
-80
5
3 4
-40
-90
MAX1214N toc02
5
-30
-40
-50
-60
-100
-100
-100
-110
-110
0
-40
-50
-60
-70
2
-80
3
fSAMPLE = 210MHz
fIN1 = 96.8737793MHz
fIN2 = 100.1550293MHz
IMD = -79dBc
-20
4
5
-30
-40
fIN1
fIN2
fIN2 + fIN1
-50
2fIN2 + fIN1
fIN2 - fIN1
-60
2fIN1 + fIN2
-70
-100
-100
-110
-110
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
2fIN2 - fIN1
HD2/HD3 (dBc)
80
75
-THD
65
60
55
50
45
fIN (MHz)
SINAD
60
55
200
250
45
300
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
-50
-55
-60
-65
85
150
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
65
50
100
150
200
250
300
fIN (MHz)
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 210MHz, fIN = 65.087MHz)
70
60
SNR
50
-70
-75
-80
-85
-90
-95
-100
-105
-110
SNR/SINAD (dB)
SFDR
100
10
SNR
MAX1214N toc08
95
50
8
70
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 210MHz, AIN = -1dBFS)
MAX1214N toc07
100
0
7
50
0
SFDR/(-THD) vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 210MHz, AIN = -1dBFS)
70
6
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 210MHz, AIN = -1dBFS)
-90
90
5
-80
-90
0
9
4
0
SNR/SINAD (dB)
-30
0
-10
AMPLITUDE (dBFS)
fSAMPLE = 210MHz
fIN = 249.913MHz
AIN = -0.994dBFS
SNR = 65dB
SINAD = 64.9dB
THD = -79.3dBc
SFDR = 85dBc
HD2 = -85dBc
HD3 = -86dBc
-20
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT
(8192-POINT DATA RECORD)
MAX1214N toc04
0
-10
3
-80
-110
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
2
-70
-90
FFT PLOT
(8192-POINT DATA RECORD)
AMPLITUDE (dBFS)
3
-90
0
SFDR/(-THD) (dBc)
-20
MAX1214N toc06
-50
-30
fSAMPLE = 210MHz
fIN = 199.771MHz
AIN = -0.961dBFS
SNR = 65.4dB
SINAD = 65.1dB
THD = -78.5dBc
SFDR = 82.8dBc
HD2 = -82.8dBc
HD3 = -84.6dBc
MAX1214N toc9
-40
-20
AMPLITUDE (dBFS)
-30
0
-10
MAX1214N toc05
AMPLITUDE (dBFS)
-20
fSAMPLE = 210MHz
fIN = 100.155MHz
AIN = -0.954dBFS
SNR = 67dB
SINAD = 66.6dB
THD = -76.8dBc
SFDR = 81.2dBc
HD2 = -81.2dBc
HD3 = -81.8dBc
2
4
-10
AMPLITUDE (dBFS)
fSAMPLE = 210MHz
fIN = 12.484MHz
AIN = -0.97dBFS
SNR = 67.3dB
SINAD = 67.2dB
THD = -83.4dBc
SFDR = 88.5dB
HD2 = -90.4dBc
HD3 = -96.7dBc
-10
FFT PLOT
(8192-POINT DATA RECORD)
0
MAX1214N toc01
0
FFT PLOT
(8192-POINT DATA RECORD)
MAX1214N toc03
FFT PLOT
(8192-POINT DATA RECORD)
HD2
40
SINAD
30
20
HD3
10
0
0
50
100
150
fIN (MHz)
200
250
300
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
0
ANALOG INPUT AMPLITUDE (dBFS)
_______________________________________________________________________________________
5
MAX1214N
Typical Operating Characteristics
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 210MHz, fIN = 65.087MHz)
SNR
70
65
SNR/SINAD (dB)
HD2/HD3 (dBc)
75
-60
-70
HD2
-80
SINAD
60
55
50
-90
45
-100
-110
40
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
0
MAX1214N toc12
-50
-THD
SNR/SINAD vs. SAMPLE FREQUENCY
(fIN = 65.087MHz, AIN = -1dBFS)
MAX1214N toc11
HD2
-40
SFDR
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
0
0
20 40 60 80 100 120 140 160 180 200 220
ANALOG INPUT AMPLITUDE (dBFS)
ANALOG INPUT AMPLITUDE (dBFS)
fSAMPLE (MHz)
SFDR/(-THD) vs. SAMPLE FREQUENCY
(fIN = 65.087MHz, AIN = -1dBFS)
HD2/HD3 vs. SAMPLE FREQUENCY
(fIN = 65.087MHz, AIN = -1dBFS)
TOTAL POWER DISSIPATION vs. SAMPLE
FREQUENCY (fIN = 65.087MHz, AIN = -1dBFS)
HD2/HD3 (dBc)
85
80
-THD
70
65
60
0.850
HD3
0.825
50
0.725
0.700
0
20 40 60 80 100 120 140 160 180 200 220
20 39 58 77 96 115 134 153 172 191 210
20 40 60 80 100 120 140 160 180 200 220
fSAMPLE (MHz)
fSAMPLE (MHz)
fSAMPLE (MHz)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
GAIN BANDWIDTH PLOT
(fSAMPLE = 210MHz, AIN = -1dBFS)
0.7
MAX1214N toc16
0.4
DNL (LSB)
0.5
0.2
-0.1
-0.4
-0.5
0
-1
0.1
-0.2
1
GAIN (dB)
0.8
MAX1214N toc17
0
0.775
0.750
HD2
-110
-115
-120
55
0.800
MAX1214N toc18
75
-75
-80
-85
-90
-95
-100
-105
MAX1214N toc15
SFDR
90
0.875
PDISS (W)
95
-60
-65
-70
MAX1214N toc14
100
SFDR/(-THD) (dBc)
-30
MAX1214N toc10
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
MAX1214N toc13
SFDR/(-THD) (dBc)
SFDR/(-THD) vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 210MHz, fIN = 65.087MHz)
INL (LSB)
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
-2
-3
-4
-5
-6
-0.8
-0.7
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
6
-7
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
1
10
100
ANALOG INPUT FREQUENCY (MHz)
______________________________________________________________________________________
1000
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
SFDR/(-THD) vs. TEMPERATURE
(fSAMPLE = 210MHz, fIN = 100MHz, AIN = -1dBFS)
66.5
65.5
SINAD
64.5
63.5
62.5
SFDR
95
HD2
90
85
80
75
HD2/HD3 (dBc)
SFDR/(-THD) (dBc)
67.5
-THD
70
80
75
HD3
70
65
60
65
55
61.5
50
60
60.5
10
35
60
-40
85
-15
10
35
60
-15
SNR/SINAD vs. SUPPLY VOLTAGE
(fIN = 65.087MHz, AIN = -1dBFS)
69
SNR
100
SINAD
65
97
94
SFDR/(-THD) (dBc)
67
66
35
60
85
SFDR/(-THD) vs. SUPPLY VOLTAGE
(fIN = 65.087MHz, AIN = -1dBFS)
MAX1214N toc22
70
10
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
68
-40
85
64
63
MAX1214N toc23
-15
SFDR
91
88
85
82
-THD
79
62
76
61
73
60
70
1.70
1.75
1.80
1.85
1.90
1.70
1.75
1.80
1.85
1.90
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
HD2/HD3 vs. SUPPLY VOLTAGE
(fIN = 65.087MHz, AIN = -1dBFS)
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(fIN = 65.087MHz, AIN = -1dBFS)
1.248
MAX1214N toc24
-70
-75
-80
1.247
1.246
HD3
VREFIO (V)
-85
-90
-95
-100
HD2
MAX1214N toc25
SNR/SINAD (dB)
-40
HD2/HD3 (dBc)
SNR/SINAD (dB)
SNR
85
100
MAX1214N toc20
69.5
68.5
90
MAX1214N toc19
70.5
HD2/HD3 vs. TEMPERATURE
(fSAMPLE = 210MHz, fIN = 100MHz, AIN = -1dBFS)
MAX1214N toc21
SNR/SINAD vs. TEMPERATURE
(fSAMPLE = 210MHz, fIN = 100MHz, AIN = -1dBFS)
1.245
1.244
1.243
-105
1.242
-110
1.241
-115
1.240
-120
1.70
1.75
1.80
1.85
SUPPLY VOLTAGE (V)
1.90
1.70
1.75
1.80
1.85
1.90
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
MAX1214N
Typical Operating Characteristics (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 210MHz, AIN = -1dBFS; see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Pin Description
PIN
NAME
FUNCTION
1, 6, 11–14, 20,
25, 62, 63, 65
AVCC
Analog Supply Voltage. Bypass AVCC to AGND with a parallel combination of 0.1µF and 0.22µF
capacitors for best decoupling results. Connect all AVCC inputs together. See the Grounding,
Bypassing, and Board Layout Considerations section.
2, 5, 7, 10, 15, 16,
18, 19, 21, 24,
64, 66, 67
AGND
Analog Converter Ground. Connect all AGND inputs together.
3
REFIO
Reference Input/Output. Pull REFADJ high to allow REFIO to accept an external reference. Pull
REFADJ low to activate the internal 1.24V-bandgap reference. Connect a 0.1µF capacitor from
REFIO to AGND for both internal and external reference.
4
REFADJ
8
INP
Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases
FSR). Connect REFADJ to AVCC to override the internal reference with an external source
connected to REFIO. Connect REFADJ to AGND to allow the internal reference to determine the
FSR of the data converter. See the FSR Adjustment Using the Internal Bandgap Reference
section.
Positive Analog Input Terminal. Internally self-biased to 0.7V.
9
INN
Negative Analog Input Terminal. Internally self-biased to 0.7V.
Clock Divider Input. CLKDIV controls the sampling frequency relative to the input clock
frequency. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: Sampling frequency is at one-half the input clock frequency.
CLKDIV = 1: Sampling frequency is equal to the input clock frequency.
17
CLKDIV
22
CLKP
True Clock Input. Apply an LVDS-compatible input level to CLKP. Internally self-biased to 1.15V.
23
CLKN
Complementary Clock Input. Apply an LVDS-compatible input level to CLKN. Internally selfbiased to 1.15V.
26, 45, 61
OGND
Digital Converter Ground. Ground connection for digital circuitry and output drivers. Connect all
OGND inputs together.
27, 28, 41, 44, 60
OVCC
Digital Supply Voltage. Bypass OVCC with a 0.1µF capacitor to OGND. Connect all OVCC inputs
together. See the Grounding, Bypassing, and Board Layout Considerations section.
29
D0N
Complementary Output Bit 0 (LSB)
30
D0P
True Output Bit 0 (LSB)
31
D1N
Complementary Output Bit 1
32
D1P
True Output Bit 1
33
D2N
Complementary Output Bit 2
34
D2P
True Output Bit 2
35
D3N
Complementary Output Bit 3
36
D3P
True Output Bit 3
8
_______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
PIN
NAME
FUNCTION
37
D4N
Complementary Output Bit 4
38
D4P
True Output Bit 4
39
D5N
Complementary Output Bit 5
40
D5P
True Output Bit 5
42
DCLKN
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock.
43
DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock.
46
D6N
Complementary Output Bit 6
47
D6P
True Output Bit 6
48
D7N
Complementary Output Bit 7
49
D7P
True Output Bit 7
50
D8N
Complementary Output Bit 8
51
D8P
True Output Bit 8
52
D9N
Complementary Output Bit 9
53
D9P
True Output Bit 9
54
D10N
Complementary Output Bit 10
55
D10P
True Output Bit 10
56
D11N
Complementary Output Bit 11 (MSB)
57
D11P
True Output Bit 11 (MSB)
58
ORN
Complementary Out-of-Range Control Bit Output. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
59
ORP
True Out-of-Range Control Bit Output. If an out-of-range condition is detected, bit ORP flags
this condition by transitioning high.
68
T/B
Output Format Select. This LVCMOS-compatible input controls the digital output format of the
MAX1214N. T/B has an internal pulldown resistor.
T/B = 0: Two’s-complement output format.
T/B = 1: Binary output format.
—
EP
Exposed Paddle. The exposed paddle is located on the backside of the chip and must be
connected to AGND.
_______________________________________________________________________________________
9
MAX1214N
Pin Description (continued)
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
OVCC
AVCC
INP
12-BIT PIPELINE
ADC
T/H
MAX1214N
INN
900Ω
900Ω
DCLKP
DCLKN
COMMONMODE BUFFER
REFIO
REFERENCE
REFADJ
DIV1/DIV2
D0P/N
CLOCK
MANAGEMENT
D1P/N
LVDS
DATA
PORT
D2P/N
D11P/N
CLKP
ORP/ORN
CLKN
CLKDIV
T/B
AGND
OGND
Figure 1. Block Diagram
Detailed Description—
Theory of Operation
The MAX1214N uses a fully differential pipelined architecture that allows for high-speed conversion, optimized accuracy, and linearity while minimizing power
consumption.
Both positive (INP) and negative/complementary analog input terminals (INN) are centered around a 0.7V
common-mode voltage, and accept a differential analog input voltage swing of ±VFS / 4 each, resulting in a
typical 1.39V P-P differential full-scale signal swing.
Inputs INP and INN are sampled when the differential
sampling clock signal transitions high. When using
the clock-divide mode, the analog inputs are sampled
at every other high transition of the differential sampling clock.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital output code is multiplied and passed along to the next
10
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in user-selectable two’s-complement
or offset binary output formats with LVDS-compatible
output levels. See Figure 1 for a more detailed view of
the MAX1214N architecture.
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1214N. Differential inputs usually feature good
rejection of even-order harmonics, which allows for
enhanced AC performance as the signals are progressing through the analog stages. The MAX1214N analog
inputs are self-biased at a 0.7V common-mode voltage
and allow a 1.39VP-P differential input voltage swing
(Figure 2). Both inputs are self-biased through 900Ω
resistors, resulting in a typical differential input resistance of 1.8kΩ. Drive the analog inputs of the
MAX1214N in AC-coupled configuration to achieve the
best dynamic performance. See the TransformerCoupled, Differential Analog Input Drive section.
______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
MAX1214N
AVCC
T/H
MAX1214N
INP
CP
900Ω
CS
12-BIT PIPELINE
ADC
900Ω
CS
INN
CP
FROM CLOCKMANAGEMENT BLOCK
TO COMMON MODE
CS IS THE SAMPLING CAPACITANCE.
CP IS THE PARASITIC CAPACITANCE ~ 1pF.
VCM + VFS / 4
INP
VCM
INN
VCM - VFS / 4
GND
+VFS / 2
GND
1.39V DIFFERENTIAL FSR
INP - INN
-VFS / 2
Figure 2. Simplified Analog Input Architecture and Allowable Input Voltage Range
______________________________________________________________________________________
11
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
The MAX1214N also features an internal clock-management circuit (duty-cycle equalizer) that ensures the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal
that desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum 20MHz
clock frequency to allow the device to meet data sheet
specifications.
On-Chip Reference Circuit
The MAX1214N features an internal 1.24V-bandgap reference circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the FSR
of the MAX1214N. Bypass REFIO with a 0.1µF capacitor
to AGND. To compensate for gain errors or increase/decrease the ADC’s FSR, the voltage of this bandgap reference can be indirectly adjusted by adding an external
resistor (e.g., 100kΩ trim potentiometer) between
REFADJ and AGND or REFADJ and REFIO. See the
Applications Information section for a detailed description
of this process.
To disable the internal reference, connect REFADJ to
AVCC. Apply an external, stable reference to set the
converter’s full scale. To enable the internal reference,
connect REFADJ to AGND.
Data Clock Outputs (DCLKP, DCLKN)
The MAX1214N features a differential clock output,
which can be used to latch the digital output data with
an external latch or receiver. Additionally, the clock output can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
3.95ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 5 for timing details.
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX1214N with an LVDS- or
LVPECL-compatible clock to achieve the best dynamic
performance. The clock signal source must be of high
quality and low phase noise to avoid any degradation in
the noise performance of the ADC. The clock inputs
(CLKP, CLKN) are internally biased to 1.15V and accept
a typical 0.5VP-P differential signal swing (Figure 4). See
the Differential, AC-Coupled LVPECL-Compatible Clock
Input section for more circuit details on how to drive
CLKP and CLKN appropriately. Although not recommended, the clock inputs also accept a single-ended
input signal.
Divide-by-2 Clock Control (CLKDIV)
The MAX1214N offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that require this divide-by-2 mode. Connecting CLKDIV
to OVCC disables the divide-by-2 mode.
REFT
ADC FULL SCALE = REFT - REFB
1V
G
REFERENCESCALING AMPLIFIER
REFB
REFERENCE
BUFFER
REFIO
0.1µF
REFADJ*
CONTROL LINE TO
DISABLE REFERENCE BUFFER
100Ω*
MAX1214N
AVCC
AVCC / 2
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
Figure 3. Simplified Reference Architecture
12
______________________________________________________________________________________
*REFADJ MAY
BE SHORTED TO
AGND DIRECTLY.
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N
are LVDS compatible, and data on D0P/N–D11P/N is
presented in either binary or two’s-complement format
(Table 1). The T/B control line is an LVCMOS-compatible input, which allows the user to select the desired
output format. Pulling T/B low outputs data in two’s
complement and pulling it high presents data in offset
binary format on the 12-bit parallel bus. T/B has an
internal pulldown resistor and may be left unconnected
in applications using only two’s-complement output format. All LVDS outputs provide a typical 0.325V voltage
swing around a 1.2V common-mode voltage, and must
be terminated at the far end of each transmission line pair
(true and complementary) with 100Ω. Apply a 1.7V to
1.9V voltage supply at OVCC to power the LVDS outputs.
The MAX1214N offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out-of-range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
2.89kΩ
CLKP
5.35kΩ
5.35kΩ
CLKN
5.35kΩ
AGND
Figure 4. Simplified Clock Input Architecture
System Timing Requirements
Figure 5 shows the relationship between the clock input
and output, analog input, sampling event, and data output. The MAX1214N samples on the rising (falling)
edge of CLKP (CLKN). Output data is valid on the next
rising (falling) edge of the DCLKP (DCLKN) clock, but
has an internal latency of 11 clock cycles.
SAMPLING EVENT
SAMPLING EVENT
Note: Although a differential LVDS output architecture
reduces single-ended transients to the supply and
ground planes, capacitive loading on the digital outputs should still be kept as low as possible. Using
LVDS buffers on the digital outputs of the ADC when
driving larger loads may improve overall performance
and reduce system-timing constraints.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
N + 11
N + 12
INP
INN
tAD
CLKN
N
N+1
N + 10
CLKP
tCH
tCL
tCPDL
DCLKN
N - 11
N - 10
N-1
N+1
N
DCLKP
tLATENCY
tPDL
D0P/D0N–
D11P/D11N
ORP/N
N - 11
N - 10
N-9
N-1
N
N+1
tCPDL - tPDL~ 0.4 x tSAMPLE WITH tSAMPLE = 1 / fSAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 5. System and Output Timing Diagram
______________________________________________________________________________________
13
MAX1214N
Digital Outputs (D0P/N–D11P/N, DCLKP/N,
ORP/N) and Control Input T/B
AVDD
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
Table 1. MAX1214N Digital Output Coding
INP ANALOG
INPUT VOLTAGE
LEVEL
INN ANALOG
INPUT VOLTAGE
LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY DIGITAL OUTPUT
CODE (D11P/N–D0P/N)
TWO’S-COMPLEMENT DIGITAL
OUTPUT CODE (D11P/N–D0P/N)
> VCM + VFS / 4
< VCM - VFS / 4
1 (0)
1111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111
(exceeds +FS, OR set)
VCM + VFS / 4
VCM - VFS / 4
0 (1)
1111 1111 1111 (+FS)
0111 1111 1111 (+FS)
VCM
VCM
0 (1)
1000 0000 0000 or
0111 1111 1111 (FS/2)
0000 0000 0000 or
1111 1111 1111 (FS/2)
VCM - VFS / 4
VCM + VFS / 4
0 (1)
0000 0000 0000 (-FS)
1000 0000 0000 (-FS)
1 (0)
0000 0000 0000
(exceeds -FS, OR set)
1000 0000 0000
(exceeds -FS, OR set)
< VCM + VFS / 4
> VCM - VFS / 4
CONFIGURATION TO INCREASE THE FSR OF THE MAX1214N
CONFIGURATION TO DECREASE THE FSR OF THE MAX1214N
REFERENCESCALING
AMPLIFIER
ADC FULL SCALE = REFT - REFB
REFT
REFERENCESCALING
AMPLIFIER
ADC FULL SCALE = REFT - REFB
REFT
G
G
REFERENCE REFB
BUFFER
REFERENCE REFB
BUFFER
1V
1V
REFIO
REFIO
0.1µF
REFADJ
0.1µF
13kΩ TO
1MΩ
REFADJ
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
MAX1214N
AVCC
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
MAX1214N
AVCC / 2
AVCC
13kΩ TO
1MΩ
AVCC / 2
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
Figure 6a. Circuit Suggestions to Adjust the ADC’s Full-Scale Range
Applications Information
FSR Adjustments Using the Internal
Bandgap Reference
The MAX1214N supports a 10% (±5%) full-scale
adjustment range. To decrease the full-scale signal
range, add an external resistor value ranging from
13kΩ to 1MΩ between REFADJ and AGND. Adding a
variable resistor, potentiometer, or predetermined resis14
tor value between REFADJ and REFIO increases the
FSR of the data converter. Figure 6a shows the two
possible configurations and their impact on the overall
full-scale range adjustment of the MAX1214N. Do not
use resistor values of less than 13kΩ to avoid instability
of the internal gain regulation loop for the bandgap reference. See Figure 6b for the resulting FSR for a series
of resistor values.
______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
The MAX1214N dynamic performance depends on the
use of a very clean clock source. The phase noise floor
of the clock source has a negative impact on the SNR
performance. Spurious signals on the clock signal
source also affect the ADC’s dynamic range. The preferred method of clocking the MAX1214N is differentially with LVDS- or LVPECL-compatible input levels. The
fast data transition rates of these logic families minimize
the clock-input circuitry’s transition uncertainty, thereby
improving the SNR performance. To accomplish this, a
50Ω reverse-terminated clock signal source with low
phase noise is AC-coupled into a fast differential
receiver such as the MC100LVEL16 (Figure 7). The
receiver produces the necessary LVPECL output levels
to drive the clock inputs of the data converter.
FS VOLTAGE
vs. ADJUST RESISTOR
MAX1214N fig06b
1.34
1.32
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND REFIO INCREASES VFS
1.30
VFS (V)
1.28
1.26
1.24
1.22
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND AGND DECREASES VFS
1.20
1.18
1.16
1.14
0 100 200 300 400 500 600 700 800 900 1000
FS ADJUST RESISTOR (kΩ)
Transformer-Coupled,
Differential Analog Input Drive
The MAX1214N provides the best SFDR and THD with
fully differential input signals and it is not recommended to drive the ADC inputs in single-ended configuration. In differential input mode, even-order harmonics
are usually lower since INP and INN are balanced, and
Figure 6b. FS Adjustment Range vs. FS Adjustment Resistor
VCLK
0.1µF
10kΩ
SINGLE-ENDED
INPUT TERMINAL
8
0.1µF
0.1µF
2
7
150Ω
50Ω
MC100LVEL16D
0.1µF
6
3
510Ω
150Ω
510Ω
AVCC OVCC
4
5
0.01µF
INP
CLKN CLKP
D0P/N–D11P/N, 0RP/N
MAX1214N
INN
12
AGND OGND
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
______________________________________________________________________________________
15
MAX1214N
Differential, AC-Coupled,
LVPECL-Compatible Clock Input
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
each of the ADC inputs only requires half the signal
swing compared to a single-ended configuration.
Wideband RF transformers provide an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1214N to reach its
optimum dynamic performance. Apply a secondaryside termination of a 1:1 transformer (e.g., Mini-Circuit’s
ADT1-1WT) into two separate 24.9Ω resistors. Higher
source impedance values can be used at the expense
of degradation in dynamic performance. This configuration optimizes THD and SFDR performance of the
ADC by reducing the effects of transformer parasitics.
However, the source impedance combined with the
shunt capacitance provided by a PC board and the
ADC’s parasitic capacitance limit the ADC’s full-power
input bandwidth.
To further enhance THD and SFDR performance at high
input frequencies (> 100MHz), a second transformer
(Figure 8) should be placed in series with the singleended-to-differential conversion transformer. This transformer reduces the increase of even-order harmonics
at high frequencies.
Single-Ended, AC-Coupled Analog Inputs
Although not recommended, the MAX1214N can be used
in single-ended mode (Figure 9). AC-couple the analog
signals to the positive input INP through a 0.1µF capacitor
terminated with a 49.9Ω resistor to AGND. Terminate the
negative input INN with a 49.9Ω resistor in series with a
0.1µF capacitor to AGND. In single-ended mode, the
input range is limited to approximately half of the FSR of
the device, and dynamic performance usually degrades.
AVCC
SINGLE-ENDED
INPUT TERMINAL
0.1µF
0.1µF
6
1 ADT1-1WT 4
OVCC
INP
3 ADT1-1WT
5
2
5
2
3
6
1
4
12
24.9Ω
D0P/N–D11P/N,
0RP/N
10Ω
MAX1214N
24.9Ω
10Ω
12
INN
0.1µF
AGND
OGND
Figure 8. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
AVCC
SINGLE-ENDED
INPUT TERMINAL
0.1µF
OVCC
INP
D0P/N–D11P/N, 0RP/N
49.9Ω
1%
0.1µF
MAX1214N
INN
12
49.9Ω
1%
AGND
OGND
Figure 9. Single-Ended, AC-Coupled Analog Input Configuration
16
______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
The MAX1214N requires board-layout design techniques suitable for high-speed data converters. This
ADC provides separate analog and digital power supplies. The analog and digital supply voltage pins
accept 1.7V to 1.9V input voltage ranges. Although
both supply types can be combined and supplied from
one source, it is recommended to use separate sources
to cut down on performance degradation caused by digital switching currents, which can couple into the analog
supply network. Isolate analog and digital supplies
(AVCC and OVCC) where they enter the PC board with
separate networks of ferrite beads and capacitors to
their corresponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor
and parallel combinations of 10µF and 1µF ceramic
capacitors. Additionally, the ADC requires each supply
pin to be bypassed with separate 0.1µF ceramic
capacitors (Figure 10). Locate these capacitors directly
at the ADC supply pins or as close as possible to the
MAX1214N. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PC board.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. The dynamic currents that may need to travel
long distances before they are recombined at a common source ground, resulting in large and undesirable
ground loops, are a major concern with this approach.
Ground loops can degrade the input noise by coupling
back to the analog front-end of the converter, resulting
in increased spurious activity, leading to decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
coupling of the digital output signals from the analog
input, segregate the digital output bus carefully from the
analog input circuitry. To further minimize the effects of
digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching
currents away from the sensitive analog sections of the
ADC. This approach does not require split ground
planes, but can be accomplished by placing substantial
ground connections between the analog front-end and
the digital outputs.
The MAX1214N is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The exposed
paddle (EP) must be soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
BYPASSING—ADC LEVEL
BYPASSING—BOARD LEVEL
OVCC
AVCC
0.1µF
AVCC
0.1µF
1µF
AGND
10µF
47µF
ANALOG POWERSUPPLY SOURCE
10µF
47µF
DIGITAL/OUTPUT
DRIVER POWERSUPPLY SOURCE
OGND
D0P/N–D11P/N, 0RP/N
OVCC
MAX1214N
12
1µF
AGND
OGND
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1214N
______________________________________________________________________________________
17
MAX1214N
Grounding, Bypassing, and
Board Layout Considerations
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the board with standard infrared (IR)
flow soldering techniques.
Thermal efficiency is one of the factors for selecting a
package with an exposed paddle for the MAX1214N.
The exposed paddle improves thermal and ensures a
solid ground connection between the ADC and the PC
board’s analog ground layer.
Considerable care must be taken when routing the digital output traces for a high-speed, high-resolution data
converter. Keep trace lengths at a minimum and place
minimal capacitive loading (less than 5pF) on any digital trace to prevent coupling to sensitive analog sections of the ADC. It is recommended running the LVDS
output traces as differential lines with 100Ω matched
impedance from the ADC to the LVDS load device.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity
parameters for the MAX1214N are measured using the
histogram method with a 10MHz input frequency.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1214N’s DNL specification is measured with the
histogram method based on a 10MHz input tone.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR[max] = 6.02 x N + 1.76
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities also contribute to the SNR calculation and
should be considered when determining the signal-tonoise ratio in ADC. The SNR for the MAX1214N is specified in decibels (dB), however, SNR can also be
specified in dBFS. To obtain the SNR in dBFS, simply
subtract the amplitude of the input tone (this number is
given in dBFS) at which the SNR is measured from the
SNR number in dB. For example, an ADC having an
SNR of 67dB resulting from an input tone with amplitude
-1dBFS will have an SNR of 67 - (-1) = 68dBFS.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In the case of the MAX1214N,
SINAD is computed from a curve fit.
CLKP
CLKN
ANALOG
INPUT
tAD
Dynamic Parameter Definitions
Aperture Jitter
tAJ
SAMPLED
DATA (T/H)
Figure 11 shows the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
18
T/H
TRACK
HOLD
TRACK
Figure 11. Aperture Jitter/Delay Specifications
______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
The fundamental input tone amplitudes (V1 and V2) are
at -7dBFS. The intermodulation products are the amplitudes of the output spectrum at the following frequencies:
• Second-order intermodulation products: fIN1 + fIN2,
fIN2 - fIN1
• Third-order intermodulation products: 2 x fIN1 - fIN2,
2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1
• Fourth-order intermodulation products: 3 x fIN1 - fIN2,
3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1
• Fifth-order intermodulation products: 3 x fIN1 - 2 x fIN2,
3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2, 3 x fIN2 + 2 x fIN1
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
VIM12 + VIM22 + ...... + VIM32 + VIMn2
IMD = 20 × log
V12 + V22
Full-Power Bandwidth
A large -1dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. The -3dB point is defined as
the full-power input bandwidth frequency of the ADC.
Pin Configuration
63 62 61 60 59 58
D9P
D9N
D10N
D10P
D11N
D11P
ORN
ORP
OVCC
OGND
AVCC
67 66 65 64
AVCC
AGND
68
AVCC
AGND
AGND
T/B
TOP VIEW
57 56 55 54 53 52
AVCC
1
51
D8P
AGND
2
50
D8N
REFIO
3
49
D7P
REFADJ
4
48
D7N
AGND
5
47
D6P
AVCC
6
46
D6N
AGND
7
45
OGND
INP
8
44
OVCC
INN
9
43
DCLKP
AGND 10
42
DCLKN
AVCC
11
41
OVCC
AVCC 12
40
D5P
AVCC 13
39
D5N
D4P
EP
MAX1214N
AVCC 14
38
AGND 15
37
D4N
AGND 16
36
D3P
35
D3N
CLKDIV 17
D2P
D2N
D1P
D1N
D0P
D0N
OVCC
OVCC
AVCC
OGND
AGND
CLKN
CLKP
AVCC
AGND
AGND
AGND
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
EP = EXPOSED PADDLE
______________________________________________________________________________________
19
MAX1214N
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the carrier
frequency (maximum signal component) to the RMS
value of the next-largest noise or harmonic distortion
component. SFDR is usually measured in dBc with
respect to the carrier frequency amplitude or in dBFS
with respect to the ADC’s full-scale range.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
For the MAX1214N, the package code is G6800-4.
68L QFN.EPS
MAX1214N
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
C
21-0122
2
20
______________________________________________________________________________________
1.8V, Low-Power, 12-Bit, 210Msps
ADC for Broadband Applications
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
C
21-0122
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2005 Maxim Integrated Products
Heaney
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX1214N
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
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