19-3157; Rev 4; 10/08
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Features
The MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–
MAX1326 14-bit, analog-to-digital converters (ADCs) offer
two, four, or eight independent input channels.
Independent track/hold (T/H) circuitry provides simultaneous sampling for each channel. The MAX1316/
MAX1317/MAX1318 have a 0 to +5V input range with
±6.0V fault-tolerant inputs. The MAX1320/MAX1321/
MAX1322 have a ±5V input range with ±16.5V fault-tolerant inputs. The MAX1324/MAX1325/MAX1326 have a
±10V input range with ±16.5V fault-tolerant inputs. These
ADCs convert two channels in 2µs, and up to eight channels in 3.8µs, and have an 8-channel throughput of
250ksps per channel. Other features include a 10MHz
T/H input bandwidth, internal clock, internal (+2.5V) or
external (+2.0V to +3.0V) reference, and powersaving modes.
A 16.6MHz, 14-bit, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs.
These devices operate from a +4.75V to +5.25V analog
supply and a separate +2.7V to +5.25V digital supply,
and consume less than 50mA total supply current.
These devices come in a 48-pin LQFP package and operate over the extended -40°C to +85°C temperature range.
♦ 8-/4-/2-Channel, 14-Bit ADCs
±1.5 LSB INL, ±1 LSB DNL, No Missing Codes
90dBc SFDR, -86dBc THD, 76.5dB SINAD, 77dB
SNR at 100kHz Input
Applications
♦ On-Chip T/H Circuit for Each Channel
10ns Aperture Delay
50ps Channel-to-Channel T/H Matching
♦ Fast Conversion Time
One Channel in 1.6µs
Two Channels in 1.9µs
Four Channels in 2.5µs
Eight Channels in 3.7µs
♦ High Throughput
526ksps/ch for One Channel
455ksps/ch for Two Channels
357ksps/ch for Four Channels
250ksps/ch for Eight Channels
♦ Flexible Input Ranges
0 to +5V (MAX1316/MAX1317/MAX1318)
±5V (MAX1320/MAX1321/MAX1322)
±10V (MAX1324/MAX1325/MAX1326)
♦ No Calibration Needed
♦ 14-Bit, High-Speed, Parallel Interface
♦ Internal or External Clock
♦ +2.5V Internal Reference or +2.0V to +3.0V
External Reference
Multiphase Motor Control
Power-Grid Synchronization
Power-Factor Monitoring and Correction
Vibration and Waveform Analysis
Selector Guide
♦ +5V Analog Supply, +3V to +5V Digital Supply
46mA Analog Supply Current (typ)
1.6mA Digital Supply Current (max)
Shutdown and Power-Saving Modes
♦ 48-Pin LQFP Package (7mm x 7mm Footprint)
Ordering Information
PART
INPUT RANGE (V)
CHANNEL COUNT
MAX1316ECM
0 to +5
8
MAX1317ECM
0 to +5
4
MAX1316ECM
-40°C to +85°C
48 LQFP
MAX1318ECM
0 to +5
2
MAX1317ECM
-40°C to +85°C
48 LQFP
MAX1320ECM
±5
8
MAX1318ECM
-40°C to +85°C
48 LQFP
MAX1321ECM
±5
4
MAX1320ECM
-40°C to +85°C
48 LQFP
MAX1322ECM
±5
2
MAX1321ECM
-40°C to +85°C
48 LQFP
MAX1324ECM
±10
8
MAX1322ECM
-40°C to +85°C
48 LQFP
MAX1325ECM
±10
4
MAX1324ECM
-40°C to +85°C
48 LQFP
MAX1326ECM
±10
2
MAX1325ECM
-40°C to +85°C
48 LQFP
MAX1326ECM
-40°C to +85°C
48 LQFP
PART
TEMP RANGE
PIN-PACKAGE
Pin Configurations and Typical Operating Circuits appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
General Description
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ABSOLUTE MAXIMUM RATINGS
REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V)
D0–D13 to DGND ....................................-0.3V to (DVDD + 0.3V)
Maximum Current into Any Pin Except AVDD, DVDD,
AGND, DGND...............................................................±50mA
Continuous Power Dissipation
LQFP (derate 22.7mW/°C above +70°C) ...................1818mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, I.C. to AGND (MAX1316/MAX1317/MAX1318)...±6.0V
CH0–CH7, I.C. to AGND (MAX1320/MAX1321/MAX1322).±16.5V
CH0–CH7, I.C. to AGND (MAX1324/MAX1325/MAX1326).±16.5V
INTCLK/EXTCLK to AGND .......................-0.3V to (AVDD + 0.3V)
EOC, EOLC, WR, RD, CS to DGND .........-0.3V to (DVDD + 0.3V)
CONVST, CLK, SHDN,
ALLON to DGND..................................-0.3V to (DVDD + 0.3V)
MSV, REFMS, REF to AGND.....................-0.3V to (AVDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, C COM = 2.2µF || 0.1µF, C MSV = 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±2.0
LSB
±1
LSB
STATIC PERFORMANCE (Note 1)
Resolution
N
14
Bits
Integral Nonlinearity
INL
(Note 2)
±0.8
Differential Nonlinearity
DNL
No missing codes (Note 2)
±0.5
Offset Error
Unipolar devices
±40
Bipolar devices
±40
LSB
Unipolar devices
-4
Bipolar devices
-4
Unipolar devices between all channels
35
80
Bipolar devices between all channels
25
60
Gain Error
(Note 3)
±8
±40
LSB
Channel Gain-Error Matching
Between all channels
25
LSB
Offset Drift
Channel Offset Matching
Gain Temperature Coefficient
ppm/°C
3
LSB
ppm/°C
DYNAMIC PERFORMANCE (at fIN = 100kHz, -0.4dB FS)
Signal-to-Noise Ratio
SNR
Signal-to-Noise and Distortion
Ratio
SINAD
Spurious-Free Dynamic Range
SFDR
Total Harmonic Distortion
THD
Unipolar
Bipolar
Unipolar
Bipolar
74.5
76
75
76.5
74.5
76
75
76.5
83
dB
93
-90
Channel-to-Channel Isolation
dB
dBc
-83
83
dBc
dB
ANALOG INPUTS (CH0–CH7)
MAX1316/MAX1317/MAX1318
Input Voltage Range
2
0
+5
MAX1320/MAX1321/MAX1322
-5
+5
MAX1324/MAX1325/MAX1326
-10
+10
_______________________________________________________________________________________
V
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, C COM = 2.2µF || 0.1µF, C MSV = 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MAX1316/MAX1317/MAX1318
Input Current (Note 4)
MAX1320/MAX1321/MAX1322
MAX1324/MAX1325/MAX1326
MIN
VIN = +5V
VIN = 0V
-1.16
-0.87
-1.13
-0.85
0.29
0.56
MAX1316/MAX1317/MAX1318
Input Resistance (Note 4)
0.72
-0.12
VIN = +10V
VIN = -10V
MAX
0.54
-0.157
VIN = +5V
VIN = -5V
TYP
0.39
UNITS
mA
0.74
7.58
MAX1320/MAX1321/MAX1322
8.66
MAX1324/MAX1325/MAX1326
14.26
Input Capacitance
kΩ
15
pF
TRACK/HOLD
One channel
External-Clock Throughput Rate
(Note 5)
Internal-Clock Throughput Rate
(Note 5)
526
Two channels
455
Four channels
357
Eight channels
250
One channel (INTCLK/EXTCLK = AVDD)
526
Two channels (INTCLK/EXTCLK = AVDD)
455
Four channels (INTCLK/EXTCLK = AVDD)
357
Eight channels (INTCLK/EXTCLK = AVDD)
250
ksps
ksps
Small-Signal Bandwidth
10
MHz
Full-Power Bandwidth
10
MHz
Aperture Delay
16
ns
Aperture Jitter
50
psRMS
Aperture-Delay Matching
100
ps
INTERNAL REFERENCE
REFMS Voltage
REF Voltage
VREFMS
2.475
2.500
2.525
V
VREF
2.475
2.500
2.525
V
REF Temperature Coefficient
30
ppm/°C
EXTERNAL REFERENCE (REFMS AND REF EXTERNALLY DRIVEN)
Input Current
-250
REFMS Input Voltage Range
REF Voltage Input Range
VREFMS
Unipolar devices
VREF
+250
µA
2.0
2.5
3.0
V
2.0
2.5
3.0
V
REF Input Capacitance
15
pF
REFMS Input Capacitance
DIGITAL INPUTS (D0–D7, RD, WR, CS, CLK, SHDN, ALLON, CONVST)
15
pF
Input-Voltage High
VIH
0.7 x
DVDD
V
_______________________________________________________________________________________
3
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
ELECTRICAL CHARACTERISTICS (continued)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, C COM = 2.2µF || 0.1µF, C MSV = 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Input-Voltage Low
SYMBOL
CONDITIONS
MIN
TYP
VIL
Input Hysteresis
Input Capacitance
CIN
Input Current
IIN
MAX
UNITS
0.3 x
DVDD
V
15
mV
15
pF
±1
VIN = 0V or DVDD
µA
CLOCK-SELECT INPUT (INTCLK/EXTCLK)
0.7 x
AVDD
Input-Voltage High
V
0.3 x
AVDD
Input-Voltage Low
V
DIGITAL OUTPUTS (D0–D13, EOC, EOLC)
DVDD 0.6
V
Output-Voltage High
VOH
ISOURCE = 0.8mA
Output-Voltage Low
VOL
Tri-State Leakage Current
ISINK = 1.6mA
RD ≥ VIH or CS ≥ VIH
0.06
Tri-State Output Capacitance
RD ≥ VIH or CS ≥ VIH
15
0.4
V
1
µA
pF
POWER SUPPLIES
Analog-Supply Voltage
AVDD
4.75
5.25
Digital-Supply Voltage
DVDD
5.25
V
Analog-Supply Current
IAVDD
All channels selected
46
56
mA
Digital-Supply Current
IDVDD
CLOAD = 100pF, all channels selected
(Note 6)
1
1.6
mA
Shutdown Current (Note 7)
Power-Supply Rejection Ratio
4
2.70
V
IAVDD
VSHDN = DVDD, VCH = float
IDVDD
V RD = V WR = DVDD, VSHDN = DVDD
0.1
10
PSRR
AVDD = +4.75V to +5.75V (Note 8)
50
_______________________________________________________________________________________
2
µA
dB
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
PARAMETER
SYMBOL
CONDITIONS
MIN
Internal clock
Time-to-First-Conversion Result
tCONV
Time-to-Next-Conversion Result
tNEXT
CONVST Pulse-Width Low
(Acquisition Time)
tACQ
TYP
MAX
1.6
1.8
External clock, Figure 6
16
Internal clock
0.3
External clock, Figure 6
(Note 9)
µs
Clock
cycles
0.36
µs
Clock
cycles
3
0.16
UNITS
100
µs
CS Pulse Width
t2
30
ns
RD Pulse-Width Low
t3
30
ns
RD Pulse-Width High
t4
30
ns
WR Pulse-Width Low
t5
30
CS to WR
t6
(Note 10)
ns
WR to CS
t7
(Note 10)
ns
CS to RD
t8
(Note 10)
ns
RD to CS
t9
(Note 10)
ns
Data-Access Time
(RD Low to Valid Data)
t10
30
ns
Bus-Relinquish Time (RD High)
t11
30
ns
EOC Pulse Width
t12
Input-Data Setup Time
t14
10
Input-Data Hold Time
t15
10
External-Clock Period
t16
0.08
External-Clock High Period
t17
Logic sensitive to rising edges
20
External-Clock Low Period
t18
Logic sensitive to rising edges
20
(Note 11)
0.1
Internal clock
External-Clock Frequency
80
External clock, Figure 6
ns
ns
10.00
t19
EOC Low to RD
t20
20
µs
ns
ns
12.5
10
CONVST High to CLK Edge
Note 2:
Note 3:
Note 4:
ns
Clock
cycles
1
Internal-Clock Frequency
Note 1:
ns
MHz
MHz
(Note 12)
ns
0
ns
For the MAX1316/MAX1317/MAX1318, VIN = 0 to +5V. For the MAX1320/MAX1321/MAX1322, VIN = -5V to +5V. For the
MAX1324/MAX1325/MAX1326, VIN = -10V to +10V.
All channel performance is guaranteed by correlation to a single channel test.
Offset nulled.
The analog input resistance is terminated to an internal bias point. Calculate the analog input current using:
ICH _ =
VCH _ − VBIAS
RCH _
for VCH within the input voltage range.
Note 5:
Note 6:
Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK = 10MHz). See the Data
Throughput section for more information.
All analog inputs are driven with an FS 100kHz sine wave.
_______________________________________________________________________________________
5
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3)
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3) (continued)
Shutdown current is measured with analog input floating. The large amplitude of the maximum shutdown current specification is due to automatic test equipment limitations.
Note 8: Defined as the change in positive full scale caused by ±5% variation in the nominal supply voltage.
Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor
droop.
Note 10: CS-to-WR and CS-to-RD pins are internally AND together. Setup and hold times do not apply.
Note 11: Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST
to the falling edge of EOLC to a maximum of 0.25ms.
Note 12: To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10µs of the rising edge of CONVST, and have a minimum clock frequency of 100kHz.
Note 7:
Typical Operating Characteristics
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits section, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
0.25
0.25
DNL (LSB)
0.50
0
-0.25
-0.50
-0.50
-0.75
-0.75
4096
8192
12288
16384
fSAMPLE = 250ksps
ALL 8 CHANNELS
DRIVEN WITH FULLSCALE SINE WAVES
30
0
4096
8192
12288
4.75
16384
4.87
5.00
5.12
DIGITAL OUTPUT CODE
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. TEMPERATURE
35
30
SHUTDOWN CURRENT (µA)
SHUTDOWN CURRENT (µA)
fSAMPLE = 250ksps
ALL 8 CHANNELS
DRIVEN WITH FULLSCALE SINE WAVES
ANALOG
SHUTDOWN
CURRENT
0.6
0.4
DIGITAL
SHUTDOWN
CURRENT
0.2
10
35
TEMPERATURE (°C)
60
85
MAX1316 toc06
ANALOG
SHUTDOWN
CURRENT
0.6
5.25
0.4
DIGITAL
SHUTDOWN
CURRENT
0.2
0
0
-15
0.8
MAX1316 toc05
0.8
MAX1316 toc04
45
-40
40
DIGITAL OUTPUT CODE
50
40
45
35
-1.00
0
6
0
-0.25
-1.00
SUPPLY CURRENT (mA)
0.75
0.50
50
MAX1316 toc02
0.75
INL (LSB)
1.00
MAX1316 toc01
1.00
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1316 toc03
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SUPPLY CURRENT (mA)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
2.5
3.5
4.5
SUPPLY VOLTAGE (V)
5.5
-40
-15
10
35
TEMPERATURE (°C)
_______________________________________________________________________________________
60
85
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.5001
2.501
VREF (V)
2.502
2.5000
2.500
0.5
0
-0.5
2.4999
2.499
2.4998
2.498
2.4997
2.497
-1.5
2.4996
2.496
-2.0
4.8
4.9
5.0
5.1
5.2
5.3
-40
-15
AVDD (V)
35
60
85
OFFSET ERROR vs. TEMPERATURE
-0.01
14
13
12
11
-0.02
NORMALIZED AT TA = +25°C
35
TEMPERATURE (°C)
85
5.25
0.07
0.06
0.05
0.04
0.02
0.01
9
60
5.15
0.03
10
-0.03
5.05
0.08
GAIN ERROR (%FSR)
0
4.95
0.09
MAX1316 toc11
15
GAIN ERROR (LSB)
0.01
10
4.85
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
0.02
-15
4.75
AVDD (V)
16
MAX1316 toc10
0.03
-40
NORMALIZED AT TA = +25°C
TEMPERATURE (°C)
0.04
-0.04
10
-1.0
MAX1316 toc12
4.7
OFFSET ERROR (%FSR)
1.0
OFFSET ERROR (LSB)
2.503
2.5002
OFFSET ERROR vs. SUPPLY VOLTAGE
1.5
MAX1316 toc08
2.5003
VREF (V)
2.504
MAX1316 toc07
2.5004
MAX1316 toc09
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
4.75
4.85
4.95
5.05
AVDD (V)
5.15
5.25
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits section, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits section, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
77
76
75
74
-100
-120
0.05
0.10
0.15
0.20
75
74
73
72
72
71
71
70
8
0.25
10
12
14
16
18
8
20
10
12
14
16
18
FREQUENCY (MHz)
fCLK (MHz)
fCLK (MHz)
EFFECTIVE NUMBER OF BITS
vs. CLOCK FREQUENCY
TOTAL HARMONIC DISTORTION
vs. CLOCK FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
-70
MAX1316 toc16
13.5
fIN = 100kHz
13.0
100
-75
20
MAX1316 toc17b
0
76
73
70
-140
MAX1316 toc15
78
77
-80
fIN = 100kHz
79
SINAD (dB)
-60
78
MAX1316 toc17
AMPLITUDE (dB)
-40
fIN = 100kHz
79
80
MAX1316 toc14
-20
80
SNR (dB)
fANALOG_IN = 103kHz
fSAMPLE = 490kHz
fCLK = 10MHz
SINAD = 76.7dB
SNR = 77.0dB
THD = -88.3dB
SFDR = 91.0dB
MAX1316 toc13
0
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. CLOCK FREQUENCY
FFT
95
90
12.0
SFDR (dB)
-80
12.5
THD (dB)
ENOB (BITS)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
-85
11.5
-90
11.0
-95
85
80
75
70
60
-100
10.5
8
10
12
14
fCLK (MHz)
8
65
16
18
20
8
10
12
14
fCLK (MHz)
16
18
20
8
10
12
14
fCLK (MHz)
_______________________________________________________________________________________
16
18
20
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
CONVERSION TIME
vs. TEMPERATURE
1.4
1.2
1.0
0.8
0.6
tNEXT
INTERNAL CLOCK
1.6
4500
4000
3000
1.2
1.0
0.8
0.4
1000
0.2
500
0
5.000
5.125
5.250
0
-40
-15
2306
2000
1562
1500
tNEXT
0.6
2500
0.2
4.875
3815
3500
1.4
0.4
0
4.750
MAX1316 toc20
tCONV
1.8
CONVERSION TIME (µs)
CONVERSION TIME (µs)
1.6
2.0
COUNTS
INTERNAL CLOCK
tCONV
1.8
MAX1316 toc18
2.0
OUTPUT HISTOGRAM
(DC INPUT)
MAX1316 toc19
CONVERSION TIME
vs. ANALOG SUPPLY VOLTAGE
10
35
60
85
341
0
13
1
0
8209 8210 8211 8212 8213 8214 8215 8216 8217
TEMPERATURE (°C)
ANALOG SUPPLY VOLTAGE (V)
154
DIGITAL OUTPUT CODE
Pin Description
PIN
MAX1316
MAX1320
MAX1324
1, 15, 17
MAX1317
MAX1321
MAX1325
1, 15, 17
MAX1318
MAX1322
MAX1326
1, 15, 17
2, 3, 14, 16, 23 2, 3, 14, 16, 23 2, 3, 14, 16, 23
NAME
FUNCTION
AVDD
Analog Supply Input. AVDD is the power input for the analog section
of the converter. Apply 4.75V to 5.25V to AVDD. Bypass AVDD to
AGND (pin 14 to pin 15, pin 16 to pin 17, pin 1 to pin 2) with a 0.1µF
capacitor at each AVDD input.
AGND
Analog Ground. AGND is the power return for AVDD. Connect all
AGNDs together.
4
4
4
CH0
Channel 0 Analog Input
5
5
5
CH1
Channel 1 Analog Input
6
6
6
MSV
Midscale Voltage Bypass. For the MAX1316/MAX1317/MAX1318,
connect a 2.2µF and a 0.1µF capacitor from MSV to AGND. For the
MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326,
connect MSV directly to AGND.
7
7
—
CH2
Channel 2 Analog Input
8
8
—
CH3
Channel 3 Analog Input
9
—
—
CH4
Channel 4 Analog Input
_______________________________________________________________________________________
9
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits section, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Pin Description (continued)
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAME
10
—
—
CH5
Channel 5 Analog Input
11
—
—
CH6
Channel 6 Analog Input
12
—
—
CH7
Channel 7 Analog Input
13
INTCLK/
EXTCLK
Clock-Mode Select Input. Use INTCLK/EXTCLK to select the internal
or external conversion clock. Connect INTCLK/EXTCLK to AVDD to
select the internal clock. Connect INTCLK/EXTCLK to AGND to use
an external clock connected to CLK.
REFMS
Midscale Reference Bypass or Input. REFMS is the bypass point for
an internally generated reference voltage. For the MAX1316/
MAX1317/MAX1318, connect a 0.1µF capacitor from REFMS to
AGND. For the MAX1320/MAX1321/MAX1322/MAX1324/
MAX1325/MAX1326, connect REFMS directly to REF and bypass
with a 0.1µF capacitor from REFMS to AGND.
13
18
19
10
13
18
19
18
19
FUNCTION
REF
ADC Reference Bypass or Input. REF is the bypass point for an
internally generated reference voltage. Bypass REF with a 0.01µF
capacitor to AGND. REF can be driven externally by a precision
external voltage reference.
20
20
20
REF+
Positive Reference Bypass. REF+ is the bypass point for an
internally generated reference voltage. Bypass REF+ with a 0.1µF
capacitor to AGND. Also bypass REF+ to REF- with a 2.2µF and a
0.1µF capacitor.
21
21
21
COM
Reference Common Bypass. COM is the bypass point for an
internally generated reference voltage. Bypass COM to AGND with
a 2.2µF and a 0.1µF capacitor.
22
22
22
REF-
Negative Reference Bypass. REF- is the bypass point for an
internally generated reference voltage. Bypass REF- with a 0.1µF
capacitor to AGND. Also bypass REF- to REF+ with a 2.2µF and a
0.1µF capacitor.
24
24
24
D0
Digital I/O Bit 0 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
25
25
25
D1
Digital I/O Bit 1 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
26
26
26
D2
Digital I/O Bit 2 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
______________________________________________________________________________________
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAME
27
27
27
D3
Digital I/O Bit 3 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
28
28
28
D4
Digital I/O Bit 4 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
29
29
29
D5
Digital I/O Bit 5 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
30
30
30
D6
Digital I/O Bit 6 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
31
31
31
D7
Digital I/O Bit 7 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
32
32
32
D8
Digital Out Bit 8 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
33
33
33
D9
Digital Out Bit 9 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
34
34
34
D10
Digital Out Bit 10 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
35
35
35
D11
Digital Out Bit 11 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
36
36
36
D12
Digital Out Bit 12 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
37
37
37
D13
Digital Out Bit 13 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
38
38
38
DVDD
Digital-Supply Input. Apply +2.7V to +5.25V to DVDD. Bypass DVDD
to DGND with a 0.1µF capacitor.
39
39
39
DGND
Digital-Supply GND. DGND is the power return for DVDD. Connect
DGND to AGND at only one point (see the Layout, Grounding, and
Bypassing section).
40
40
40
EOC
End-of-Conversion Output. EOC goes low to indicate the end of a
conversion. EOC returns high after one clock period.
FUNCTION
______________________________________________________________________________________
11
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Pin Description (continued)
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Pin Description (continued)
PIN
12
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAME
41
41
41
EOLC
42
42
42
RD
Read Input. When RD and CS go low, the device initiates a read
command of the parallel data buses, D0–D13. D0–D13 are high
impedance while either RD or CS is high.
43
43
43
WR
Write Input. The write command initiates when WR and CS go low. A
write command loads the configuration byte on D0–D7.
44
44
44
CS
Chip-Select Input. Pulling CS low activates the digital interface.
D0–D13 are high impedance while either CS or RD is high.
FUNCTION
End-of-Last-Conversion Output. EOLC goes low to indicate the end
of the last conversion. EOLC returns high when CONVST goes low
for the next conversion sequence.
Convert-Start Input. Driving CONVST high places the device in hold
mode and initiates the conversion process. The analog inputs are
sampled on the rising edge of CONVST. When CONVST is low, the
analog inputs are tracked.
45
45
45
CONVST
46
46
46
CLK
External-Clock Input. CLK accepts an external-clock signal up to
15MHz. Connect CLK to DGND for internally clocked conversions.
To select external-clock mode, set INTCLK/EXTCLK = 0.
47
47
47
SHDN
Shutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1
for shutdown mode.
Enable-All-Channels Input. Drive ALLON high to enable all input
channels. When ALLON is low, only input channels selected as
active are powered. Select channels as active using the
configuration register.
48
48
48
ALLON
—
9–12
7–12
I.C.
Internally Connected. Connect I.C. to AGND. For factory use only.
______________________________________________________________________________________
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
CH0
S/H
8 x 14
SRAM
14-BIT
ADC
8x1
MUX
CH7
DVDD
D13
OUTPUT
DRIVERS
S/H
D8
D7
D0
MSV
CONFIGURATION
REGISTER
REF+
COM
REF-
*
WR
CS
INTERFACE
AND
CONTROL
RD
CONVST
SHDN
5kΩ
CLK
REF
ALLON
5kΩ
EOC
REFMS
2.500V
EOLC
DGND
INTCLK/EXTCLK
AGND
*SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES
Figure 1. Functional Diagram
Detailed Description
Analog Inputs
The MAX1316–MAX1318/MAX1320–MAX1322/MAX1324MAX1326 are 14-bit ADCs. They offer two, four, or eight
(independently selectable) input channels, each with its
own T/H circuitry. Simultaneous sampling of all active
channels preserves relative phase information, making
these devices ideal for motor control and power monitoring. These devices are available with 0 to +5V, ±5V, and
±10V input ranges. The 0 to +5V devices feature ±6V
fault-tolerant inputs. The ±5V and ±10V devices feature
±16.5V fault-tolerant inputs. Two channels convert in 2µs;
all eight channels convert in 3.8µs, with a maximum 8channel throughput of 263ksps per channel. Internal or
external reference and internal- or external-clock capability offer great flexibility and ease of use. A write-only configuration register can mask out unused channels, and a
shutdown feature reduces power. A 16.6MHz, 14-bit, parallel data bus outputs the conversion result. Figure 1
shows the functional diagram of these devices.
T/H
To preserve phase information across these multichannel devices, each input channel has a dedicated
T/H amplifier.
Use a low-input source impedance to minimize gainerror harmonic distortion. The time required for the T/H
to acquire an input signal depends on the input source
impedance. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. The acquisition
time (t 1 ) is the maximum time the device takes to
acquire the signal. Use the following formula to calculate acquisition time:
t1 = 10 (RS + RIN) x 6pF
where R IN = 2.2kΩ, R S = the input signal’s source
impedance, and t1 is never less than 180ns. A source
impedance of less than 100Ω does not significantly
affect the ADC’s performance.
______________________________________________________________________________________
13
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
MAX1316–MAX1318
MAX1320–MAX1322
MAX1324–MAX1326
AVDD
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
To improve the input-signal bandwidth under AC conditions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance and settle
quickly. For example, the MAX4265 can be used for +5V
unipolar devices, or the MAX4350 can be used for ±5V
bipolar inputs.
The T/H aperture delay is typically 13ns. The aperturedelay mismatch between T/Hs of 50ps allows the relative
phase information of up to eight different inputs to be
preserved. Figure 2 shows a simplified equivalent input
circuit, illustrating the ADC’s sampling architecture.
Input Bandwidth
The input tracking circuitry has a 12MHz small-signal
bandwidth, making it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Input Range and Protection
These devices provide ±10V, ±5V, or 0 to +5V analog
input voltage ranges. Figure 2 shows the equivalent input
circuit. Overvoltage protection circuitry at the analog
input provides ±16.5V fault protection for the bipolar input
devices and ±6.0V fault protection for the unipolar input
devices. This fault-protection circuit limits the current
going into or out of the device to less than 50mA, providing an added layer of protection from momentary overvoltage or undervoltage conditions at the analog input.
MAX1316–MAX1318
MAX1320–MAX1322
MAX1324–MAX1326
R1
Shutdown Mode
During shutdown, the analog and digital circuits in the
device power down and the device draws less than
100µA from AVDD, and less than 100µA from DVDD.
Select shutdown mode using the SHDN input. Set SHDN
high to enter shutdown mode. After coming out of shutdown, allow a 1ms wake-up time before making the first
conversion. When using an external clock, apply at least
20 clock cycles with CONVST high before making the first
conversion. When using internal-clock mode, wait at least
2µs before making the first conversion.
ALLON
ALLON is useful when some of the analog input channels
are selected (see the Configuration Register section).
Drive ALLON high to power up all input channel circuits,
regardless of whether they are selected as active by the
configuration register. Drive ALLON low or connect to
ground to power only the input channels selected as
active by the configuration register, saving 2mA per
channel (typ). The wake-up time for any channel turned
on with the configuration register is 2µs (typ) when
ALLON is low. The wake-up time with ALLON high is
only 0.01µs. New configuration-register information
does not become active until the next CONVST falling
edge. Therefore, when using software to control power
states (ALLON = 0), pulse CONVST low once before
applying the actual CONVST signal (Figure 3). With an
external clock, apply at least 15 clock cycles before
the second CONVST. If using internal-clock mode, wait
at least 1.5µs or until the first EOC before generating
the second CONVST.
Table 1. Conversion Times Using the
Internal Clock
NUMBER OF CHANNELS
INTERNAL-CLOCK
CONVERSION TIME
1
1.6
2
1.9
3
2.2
4
2.5
5
2.8
5pF
CH_
R2
Power-Saving Modes
CPAR
1pF
VBIAS
INPUT RANGE (V) R1 (kΩ) R2 (kΩ) VBIAS (V)
6
3.1
0 TO +5
3.33
5.00
0.90
7
3.4
±5
6.67
2.86
2.50
8
3.7
±10
13.33
2.35
2.06
Figure 2. Typical Input Circuit
14
______________________________________________________________________________________
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
SAMPLE
CONVST
WR
DUMMY
CONVERSION
START
LATCH
ACTUAL
CONVERSION
START
DATA-IN CHANGES ONE OR MORE CHANNELS
FROM POWER-DOWN TO ACTIVE MODE
D0–D7
DATA-IN
1
2
3
4
5
14
15
1
CLK
>14 CYCLES
EOC
EOLC
Figure 3. Software Channel Wake-Up Timing (ALLON = 0)
Clock Modes
These devices provide an internal clock of 10MHz
(typ). Alternatively, an external clock can be used.
Internal Clock
Internal-clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For internalclock operation, connect INTCLK/EXTCLK to AVDD and
connect CLK to DGND. Table 1 illustrates the total conversion time using internal-clock mode.
External Clock
For external-clock operation, connect INTCLK/EXTCLK
to AGND and connect an external-clock source to CLK.
Note that INTCLK/EXTCLK is referenced to the analog
power supply, AVDD. The external-clock frequency can
be up to 15MHz, with a duty cycle between 30% and
70%. Clock frequencies of 100kHz and lower can be
used, but the droop in the T/H circuits reduce linearity.
MAX4265), which settles quickly and is stable with the
ADC’s capacitive load (in parallel with any bypass
capacitors on the analog inputs).
Applications Section
Digital Interface
The bidirectional, parallel, digital interface sets the 8-bit
configuration register (see the Configuration Register
section) and outputs the 14-bit conversion result. The
interface includes the following control signals: chip
select (CS), read (RD), write (WR), end of conversion
(EOC), end of last conversion (EOLC), convert start
(CONVST), shutdown (SHDN), all on (ALLON), internalclock select (INTCLK /EXTCLK), and external-clock input
(CLK). Figures 4, 5, 6, 7, Table 4, and the Timing
Characteristics section show the operation of the interface. D0–D7 are bidirectional, and D8–D13 are output
only. All bits are high impedance when RD = 1 or CS = 1.
Selecting an Input Buffer
Configuration Register
Most applications require an input buffer to achieve 14bit accuracy. Although slew-rate and bandwidth are
important, the most critical specification is settling time.
The sampling requires a relatively brief sampling interval of 150ns. At the beginning of the acquisition, the
internal sampling capacitor array connects to CH_ (the
amplifier output), causing some output disturbance.
Ensure the amplifier is capable of settling to at least 14bit accuracy during this interval. Use a low-noise, lowdistortion, wideband amplifier (such as the MAX4350 or
Enable channels as active by writing to the configuration
register through I/O lines D0–D7 (Table 2). The bits in the
configuration register map directly to the channels, with
D0 controlling channel zero, and D7 controlling channel
seven. Setting any bit high activates the corresponding
input channel, while resetting any bit low deactivates the
corresponding channel. Devices with fewer than eight
channels contain some bits that have no function.
______________________________________________________________________________________
15
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
tACQ
tACQ
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Table 2. Configuration Register
PART NO.
STATE
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
BIT/CHANNEL
D0/CH0
D1/CH1
D2/CH2
D3/CH3
D4/CH4
D5/CH5
D6/CH6
D7/CH7
ON
1
1
1
1
1
1
1
1
OFF
0
0
0
0
0
0
0
0
ON
1
1
1
1
NA
NA
NA
NA
OFF
0
0
0
0
NA
NA
NA
NA
ON
1
1
NA
NA
NA
NA
NA
NA
OFF
0
0
NA
NA
NA
NA
NA
NA
NA = Not applicable.
To write to the configuration register, pull CS and WR
low, load bits D0–D7 onto the parallel bus, and force
WR high. The data are latched on the rising edge of
WR (Figure 4). It is possible to write to the configuration
register at any point during the conversion sequence;
however, it is not active until the next convert-start signal. At power-up, write to the configuration register to
select the active channels before beginning a conversion. Shutdown does not change the configuration register. See the Shutdown Mode and the ALLON sections
for information about using the configuration register for
power saving.
RD
t2
CS
16
t7
WR
t14
Starting a Conversion
To start a conversion using internal-clock mode, pull
CONVST low for at least the acquisition time (t1). The
T/H acquires the signal while CONVST is low, and conversion begins on the rising edge of CONVST. An endof-conversion signal (EOC) pulses low when the first
result becomes available, and for each subsequent
result until the end of the conversion cycle. The end-oflast-conversion signal (EOLC) goes low when the last
conversion result is available (Figures 5, 6, and 7).
To start a conversion using external-clock mode, pull
CONVST low for at least the acquisition time (t1). The T/H
acquires the signal while CONVST is low, and conversion
begins on the rising edge of CONVST. Apply an external
clock to CLK. To avoid T/H droop degrading the sampled
analog input signals, the first clock pulse should occur
within 10µs from the rising edge of CONVST, and have a
minimum clock frequency of 100kHz. The first conversion
result is available for read on the rising edge of the 17th
clock cycle, and subsequent conversions after every third
clock cycle thereafter (Figures 5, 6, and 7).
t5
t6
D0–D7
t15
DATA-IN
Figure 4. Write Timing
In both internal- and external-clock modes, CONVST
must be held high until the last conversion result is
read. For best operation, the rising edge of CONVST
must be a clean, high-speed, low-jitter digital signal.
Table 3 shows the total throughput as a function of the
clock frequency and the number of channels selected
for conversion. The calculations use the nominal speed
of the internal clock (10MHz) and a 200ns CONVST
pulse width.
______________________________________________________________________________________
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Reading a Conversion Result
Reading During a Conversion
Figures 5 and 6 show the interface signals for initiating a
read operation during a conversion cycle. These figures
show two channels selected for conversion. If more channels are selected, the results are available successively
every third clock cycle. CS can be low at all times; it can
be low during the RD cycles, or it can be the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC to go low (about 1.6µs in internal-clock
mode or 17 clock cycles in external-clock mode) before
reading the first conversion result. Read the conversion
result by bringing RD low, thus latching the data to the
parallel digital-output bus. Bring RD high to release the
digital bus. Wait for the next falling edge of EOC (about
300ns in internal-clock mode or three clock cycles in
external-clock mode) before reading the next result.
When the last result is available, EOLC goes low.
where N is the number of active channels and tQUIET
includes acquistion time tACQ. tQUIET is the period of bus
inactivity before the rising edge of CONVST. Typically use
tQUIET = tACQ + 50ns, and prevent disturbance on the
output bus from corrupting signal acquistion. See the
Starting a Conversion section for more information.
Table 3. Throughput vs. Channels Sampled (tQUIET = tACQ = 200ns, fCLK = 10MHz)
CHANNELS
SAMPLED
(N)
CLOCK CYCLES
UNTIL LAST
RESULT
CLOCK CYCLE FOR
READING LAST
CONVERSION
TOTAL
CONVERSION
TIME (ns)
SAMPLES PER
SECOND
(ksps)
THROUGHPUT
PER CHANNEL
(ksps)
1
16
1
1900
526
526
2
19
1
2200
909
455
3
22
1
2500
1200
400
4
25
1
2800
1429
357
5
28
1
3100
1613
323
6
31
1
3400
1765
294
7
34
1
3700
1892
270
8
37
1
4000
2000
250
SAMPLE
t13
t1
CONVST
HOLD
TRACK
tCONV
TRACK
tNEXT
t12
EOC
t20
RD
t10
t3
D0–D13
CH0
CH1
t11
Figure 5. Read During Conversion—Two Channels Selected, Internal Clock
______________________________________________________________________________________
17
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Data Throughput
The data throughput (fTH) of the MAX1316–MAX1318/
MAX1320–MAX1322/MAX1324–MAX1326 is a function
of the clock speed (fCLK). In internal-clock mode, fCLK =
10MHz. In external-clock mode, 100kHz ≤ f CLK ≤
12.5MHz. When reading during conversion (Figures 5
and 6), calculate fTH as follows:
1
fTH =
16 + 3 x (N − 1) + 1
tQUIET +
fCLK
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
SAMPLE
t13
tACQ
CONVST
HOLD
TRACK
t19
TRACK
t16
1
CLK
2
3
t17
16
17
18
t18
19
20
21
22
23
EOC
t12
tQUIET
RD
t10
t3
D0–D13
CH0
CH1
t11
Figure 6. Read During Conversion—Two Channels Selected, External Clock
SAMPLE
tACQ
CONVST
t13
HOLD
TRACK
t19
CLK
1
t17
2
38
39
40
t16
EOC
41
42
43
t18
ONLY LAST PULSE SHOWN
t12
EOLC
CS
t9
t8
t3
t4
tQUIET
RD
D0–D13
CH0
t10
CH1
CH2
CH3
CH4
CH5
CH6
t11
Figure 7. Reading After Conversion—Eight Channels Selected, External Clock
18
______________________________________________________________________________________
CH7
1
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Power-Up Reset
At power-up, all channels are selected for conversion
(see the Configuration Register section). After applying
power, allow a 1.0ms wake-up time to elapse before initiating the first conversion. Then, hold CONVST high for
at least 2.0µs after the wake-up time is complete. If
using an external clock, apply 20 clock pulses to CLK
with CONVST high before initiating the first conversion.
Layout, Grounding, and Bypassing
For best performance use PC boards with ground
planes. Board layout should ensure that digital and
analog signal lines are separated from each other. Do
not run analog and digital lines parallel to one another
(especially clock lines), or do not run digital lines
underneath the ADC package. Figure 8 shows the recommended system ground connections when not using
a ground plane. A single-point analog ground (star
ground point) should be established at AGND, separate from the logic ground. All other analog grounds
and DGND should be connected to this ground.
SUPPLIES
Reference
+5V
Internal Reference
The internal-reference circuits provide for analog input
voltages of 0 to +5V unipolar (MAX1316/MAX1317/
MAX1318), ±5V bipolar (MAX1320/MAX1321/MAX1322),
or ±10V bipolar (MAX1324/MAX1325/MAX1326). Install
external capacitors for reference stability, as indicated in
Table 4, and as shown in the Typical Operating Circuits.
RETURN
+3V TO +5V
RETURN
VDD
GND
OPTIONAL
FERRITE
BEAD
External Reference
Connect a +2.0V to +3.0V external reference at REFMS
and/or REF. When connecting an external reference, the
input impedance is typically 5kΩ. The external reference
must be able to drive 200µA of current and have a low
output impedance. For more information about using
external references see the Transfer Functions section.
AVDD
AGND
DVDD
DGND
DIGITAL
CIRCUITRY
MAX1316–MAX1318
MAX1320–MAX1322
MAX1324–MAX1326
Figure 8. Power-Supply Grounding and Bypassing
Table 4. Reference Bypass Capacitors
LOCATION
MSV bypass capacitor to AGND
INPUT VOLTAGE RANGE
UNIPOLAR (µF)
BIPOLAR (µF)
2.2 || 0.1
NA
REFMS bypass capacitor to AGND
0.01
0.01 (connect REFMS to REF)
REF bypass capacitor to AGND
0.01
0.01 (connect REFMS to REF)
REF+ bypass capacitor to AGND
0.1
0.1
2.2 || 0.1
2.2 || 0.1
REF+ to REF- capacitor
REF- bypass capacitor to AGND
0.1
0.1
COM bypass capacitor to AGND
2.2 || 0.1
2.2 || 0.1
NA = Not applicable (connect MSV directly to AGND).
______________________________________________________________________________________
19
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Reading After Conversion
Figure 7 shows the interface signals for a read operation
after a conversion with all eight channels enabled. At the
falling edge of EOLC, on the 38th clock pulse after the initiation of a conversion, driving CS and RD low places the
first conversion result onto the parallel bus, which can be
latched on the rising edge of RD. Successive low pulses
of RD place the successive conversion results onto the
bus. Pulse CONVST low to initiate a new conversion.
No other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low impedance and as short as possible for noise-free operation.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with
0.1µF and 2.2µF bypass capacitors close to the device.
If the +5V power supply is very noisy, a ferrite bead can
be connected as a lowpass filter, as shown in Figure 8.
Transfer Functions
Bipolar ±10V Devices
Table 5 and Figure 9 show the two’s complement transfer function for the MAX1324/MAX1325/MAX1326 with a
±10V input range. The full-scale input range (FSR) is
eight times the voltage at REF. The internal +2.500V reference gives a +20V FSR, while an external +2V to +3V
reference allows an FSR of +16V to +24V, respectively.
Calculate the LSB size using the following equation:
LSB =
8 × VREF
214
This equals 1.2207mV with a +2.5V internal reference.
The input range is centered about V MSV. Normally,
MSV = AGND, and the input is symmetrical about zero.
For a custom midscale voltage, drive MSV with an
external voltage source. Noise present on MSV directly
couples into the ADC result. Use a precision, low-drift
voltage reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
FSR, be careful not to violate the absolute maximum
voltage ratings of the analog inputs when choosing
VMSV.
Determine the input voltage as a function of V REF ,
VMSV, and the output code in decimal using the following equation:
VCH _ = LSB × CODE10 + VMSV
Bipolar ±5V Devices
Table 6 and Figure 10 show the two’s complement
transfer function for the MAX1320/MAX1321/MAX1322
with a ±5V input range. The FSR is four times the voltage at REF. The internal +2.500V reference gives a
+10V FSR, while an external +2V to +3V reference
allows an FSR of +8V to +12V, respectively. Calculate
the LSB size using the following equation:
LSB =
4 × VREF
214
This equals 0.6104mV when using the internal reference.
Table 5. ±10V Bipolar Code Table
TWO’S COMPLEMENT
BINARY OUTPUT CODE
DECIMAL
EQUIVALENT
OUTPUT
(CODE10)
INPUT
VOLTAGE (V)
(VREF = 2.5V,
VMSV = 0V)
01 1111 1111 1111
0x1FFF
8191
9.9994
±0.5 LSB
01 1111 1111 1110
0x1FFE
8190
9.9982
±0.5 LSB
00 0000 0000 0001
0x0001
1
0.0018
±0.5 LSB
00 0000 0000 0000
0x0000
0
0.0006
±0.5 LSB
11 1111 1111 1111
0x3FFF
-1
-0.0006
±0.5 LSB
10 0000 0000 0001
0x2001
-8191
-9.9982
±0.5 LSB
-8192
-9.9994
±0.5 LSB
10 0000 0000 0000
0x2000
20
8 x VREF
TWO'S COMPLEMENT BINARY OUTPUT CODE
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
0x1FFF
0x1FFE
0x1FFD
0x1FFC
0x0001
0x0000
0x3FFF
8 x VREF
0x2003
0x2002
0x2001
0x2000
1 LSB =
-8192 -8190
-1 0 +1
(MSV)
______________________________________________________________________________________
214
+8189 +8191
INPUT VOLTAGE (VCH_ - VMSV IN LSBs)
Figure 9. ±10V Bipolar Transfer Function
8 x VREF
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
TWO'S COMPLEMENT BINARY OUTPUT CODE
4 x VREF
0x1FFF
0x1FFE
0x1FFD
0x1FFC
0x0001
0x0000
0x3FFF
4 x VREF
0x2003
0x2002
0x2001
0x2000
1 LSB =
4 x VREF
2
-8192 -8190
-1 0 +1
(MSV)
14
+8189 +8191
INPUT VOLTAGE (VCH_ - VMSV IN LSBs)
Figure 10. ±5V Bipolar Transfer Function
The input range is centered about V MSV. Normally,
MSV = AGND, and the input is symmetrical about zero.
For a custom midscale voltage, drive MSV with an
external voltage source. Noise present on MSV directly
couples into the ADC result. Use a precision, low-drift
voltage reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
FSR, be careful not to violate the absolute maximum
voltage ratings of the analog inputs when choosing
V MSV . Determine the input voltage as a function of
VREF, VMSV, and the output code in decimal using the
following equation:
TWO’S COMPLEMENT
BINARY OUTPUT CODE
DECIMAL
EQUIVALENT
OUTPUT
(CODE10)
INPUT
VOLTAGE (V)
(VREF = 2.5V,
VMSV = 0V)
01 1111 1111 1111
0x1FFF
8191
4.9997
±0.5 LSB
01 1111 1111 1110
0x1FFE
8190
4.9991
±0.5 LSB
00 0000 0000 0001
0x0001
1
0.0009
±0.5 LSB
00 0000 0000 0000
0x0000
0
0.0003
±0.5 LSB
11 1111 1111 1111
0x3FFF
-1
-0.0003
±0.5 LSB
10 0000 0000 0001
0x2001
-8191
-4.9991
±0.5 LSB
10 0000 0000 0000
0x2000
-8192
-4.9997
±0.5 LSB
Table 7. 0 to +5V Unipolar Code Table
BINARY OUTPUT CODE
DECIMAL
EQUIVALENT
OUTPUT
(CODE10)
INPUT
VOLTAGE (V)
(VREF = VREFMS
= 2.5V)
11 1111 1111 1111
0x3FFF
16383
4.9998
±0.5 LSB
11 1111 1111 1110
0x3FFE
16382
4.9995
±0.5 LSB
VCH _ = LSB × CODE10 + VMSV
10 0000 0000 0001
0x2001
8193
2.5005
±0.5 LSB
Unipolar 0 to +5V Devices
Table 7 and Figure 11 show the offset binary transfer
function for the MAX1316/MAX1317/MAX1318 with a 0
to +5V input range. The FSR is two times the voltage at
REF. The internal +2.500V reference gives a +5V FSR,
while an external +2V to +3V reference allows an FSR
of +4V to +6V, respectively. Calculate the LSB size
using the following equation:
10 0000 0000 0000
0x2000
8192
2.5002
±0.5 LSB
01 1111 1111 1111
0x1FFF
8191
2.4998
±0.5 LSB
00 0000 0000 0001
0x0001
1
0.0005
±0.5 LSB
00 0000 0000 0000
0x0000
0
0.0002
±0.5 LSB
LSB =
2 × VREF
214
This equals 0.3052mV when using the internal reference.
______________________________________________________________________________________
21
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Table 6. ±5V Bipolar Code Table
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification of less than ±1 LSB guarantees no missing codes
and a monotonic transfer function.
2 x VREF
0x3FFF
0x3FFE
0x3FFD
0x3FFC
BINARY OUTPUT CODE
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
0x2001
0x2000
0x1FFF
2 x VREF
0x0003
0x0002
0x0001
0x0000
1 LSB =
0
2
8192
8190 8194
(MSV)
2 x VREF
214
16,381 16,383
INPUT VOLTAGE (LSBs)
Figure 11. 0 to +5V Unipolar Transfer Function
Unipolar Offset Error
For the unipolar MAX1316/MAX1317/MAX1318, the ideal
zero-scale transition from 0x0000 to 0x0001 occurs at
1 LSB (see Figure 11). The unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point.
Bipolar Offset Error
For the bipolar MAX1320/MAX1321/MAX1322/
MAX1324/MAX1325/MAX1326, the ideal zero-point transition from 0x3FFF to 0x0000 occurs at MSV, which is
usually connected to ground (see Figures 9 and 10).
The bipolar offset error is the amount of deviation
between the measured zero-point transition and the
ideal zero-point transition.
Gain Error
The input range is centered about VMSV, which is internally set to +2.500V. For a custom midscale voltage,
drive REFMS with an external voltage source and MSV
will follow REF MS. Noise present on MSV or REFMS
directly couples into the ADC result. Use a precision,
low-drift voltage reference with adequate bypassing to
prevent MSV from degrading ADC performance. For
maximum FSR, be careful not to violate the absolute
maximum voltage ratings of the analog inputs when
choosing VMSV. Determine the input voltage as a function of VREF, VMSV, and the output code in decimal
using the following equation:
VCH _ = LSB × CODE10 + (VMSV - 2.500V)
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. For
these devices, this straight line is a line drawn between
the end points of the transfer function, once offset and
gain errors have been nullified.
22
The ideal full-scale transition from 0x1FFE to 0x1FFF
occurs at 1 LSB below full scale (see the Transfer
Functions section). The gain error is the amount of deviation between the measured full-scale transition point
and the ideal full-scale transition point, once offset error
has been nullified.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s resolution (N bits):
SNR = (6.02 × N + 1.76)dB
where N = 14 bits.
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
______________________________________________________________________________________
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Aperture Delay
Aperture delay (tAD) is the time delay from the sampling
clock edge to the instant when an actual sample is taken.
⎡
⎤
SignalRMS
SINAD(dB) = 20 × log ⎢
⎥
⎣ (Noise + Distortion)RMS ⎦
Aperture Jitter (tAJ) is the sample-to-sample variation in
aperture delay.
Effective Number of Bits
The effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:
ENOB =
SINAD - 1.76
6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
⎡
⎤
V22 + V32 + V4 2 + V52 ⎥
⎢
THD = 20 × log ⎢
⎥
V1
⎢⎣
⎥⎦
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest frequency component.
Aperture Jitter
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each
analog input is isolated from the other channels. Channelto-channel isolation is measured by applying DC to channels 1 to 7, while a -0.5dBFS sine wave is applied to
channel 0. A 100kHz FFT is taken for channel 0 and
channel 1. Channel-to-channel isolation is expressed in
dB as the power ratio of the two 100kHz magnitudes.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in a manner that ensures that the signal’s slew
rate does not limit the ADC’s performance. The input
frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased 3dB.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as fullpower input bandwidth frequency.
Chip Information
TRANSISTOR COUNT: 80,000
PROCESS: BiCMOS 0.6µm
______________________________________________________________________________________
23
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Typical Operating Circuits
13
DVDD
INTCLK/EXTCLK
38
+5V
0.1µF
0.1µF
1
AVDD
0.1µF
15
0.1µF
17
AVDD
MSV
18
REFMS
19
REF
20
REF+
22
REF0.1µF
CLK
EOLC
D13
D12
2.2µF
D11
21
COM
AGND
D8
CH7
D7
CH6
D6
CH5
D5
CH4
D4
12
11
9
8
7
MAX1317
5
MAX1318
4
D10
D9
2, 3, 14, 16, 23
10
24
39
GND
44
42
43
45
47
48
DIGITAL
INTERFACE
AND
CONTROL
46
40
41
0.1µF
2.2µF
MAX1316
ALLON
EOC
0.1µF
ANALOG
INPUTS
0 TO +5V
CONVST
SHDN
0.01µF
0.1µF
CS
WR
6
0.01µF
DGND
RD
0.1µF
UNIPOLAR
CONFIGURATION
MAX1316
MAX1317
MAX1318
AVDD
2.2µF
GND
+3V
CH3
D3
CH2
D2
CH1
D1
CH0
D0
37
36
35
34
PARALLEL
DIGITAL
OUTPUT
33
32
31
30
29
28
27
PARALLEL
DIGITAL
I/O
26
25
24
______________________________________________________________________________________
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
13
DVDD
INTCLK/EXTCLK
38
+5V
0.1µF
0.1µF
1
AVDD
0.1µF
15
0.1µF
17
AVDD
AVDD
MAX1320
MAX1321
MAX1322
MAX1324
MAX1325
MAX1326
DGND
CS
RD
WR
6
BIPOLAR
CONFIGURATION
0.01µF
18
19
MSV
REFMS
REF
CONVST
SHDN
ALLON
CLK
0.1µF
20
EOC
REF+
EOLC
22
REF0.1µF
BIPOLAR
ANALOG
INPUTS
D11
21
COM
AGND
12
11
9
8
7
MAX1320
MAX1325
5
MAX1321
MAX1326
4
D10
D9
2, 3, 14, 16, 23
10
MAX1322
MAX1324
D13
D12
2.2µF
0.1µF
39
GND
44
42
43
45
47
48
DIGITAL
INTERFACE
AND
CONTROL
46
40
41
0.1µF
2.2µF
GND
+3V
D8
CH7
D7
CH6
D6
CH5
D5
CH4
D4
CH3
D3
CH2
D2
CH1
D1
CH0
D0
37
36
35
34
PARALLEL
DIGITAL
OUTPUT
33
32
31
30
29
28
27
PARALLEL
DIGITAL
I/O
26
25
24
______________________________________________________________________________________
25
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Typical Operating Circuits (continued)
CH4
CH5
CH6
9
28
10
27
D5
D4
D3
11
26
CH7
12
25
DVDD
D13
10
27
D5
D4
D3
11
26
I.C.
12
25
13
DVDD
D13
3
34
CH0
CH1
MSV
4
33
5
32
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
7
31
MAX1318
MAX1322
MAX1326
30
29
24
D0
22
23
REFMS
REF
REF+
21
25
COM
REFAGND
26
12
20
27
11
19
28
10
18
9
17
4-CHANNEL LQFP
37
38
39
EOLC
EOC
DGND
40
41
42
CS
WR
RD
43
44
45
46
ALLON
SHDN
CLK
CONVST
48
35
16
37
38
28
36
15
39
EOLC
EOC
DGND
41
9
2
14
40
WR
RD
I.C.
I.C.
I.C.
1
13
42
43
D6
29
8
AVDD
INTCLK/EXTCLK
AGND
AVDD
AGND
AVDD
44
CLK
CONVST
CS
46
30
MAX1317
MAX1321
MAX1325
7
AGND
AGND
8
45
ALLON
SHDN
D8
D7
D2
D1
6
47
31
8-CHANNEL LQFP
47
48
6
24
23
22
21
20
19
18
17
16
15
MSV
CH2
CH3
AGND
AVDD
REFMS
REF
REF+
COM
REFAGND
D0
14
13
8
D9
32
24
D6
29
33
5
D0
30
MAX1316
MAX1320
MAX1324
7
4
CH1
23
31
D11
D10
22
6
34
21
MSV
CH2
CH3
D8
D7
3
20
D9
32
AGND
CH0
COM
REFAGND
33
5
D12
35
19
4
CH1
36
2
18
34
1
17
3
AVDD
AGND
REFMS
REF
REF+
AGND
CH0
D11
D10
16
D12
35
15
36
2
AVDD
AGND
AVDD
1
14
AVDD
AGND
INTCLK/EXTCLK
AGND
D13
37
38
39
40
41
42
43
44
45
46
ALLON
SHDN
CLK
CONVST
CS
WR
RD
EOLC
EOC
DGND
DVDD
47
TOP VIEW
48
Pin Configurations
INTCLK/EXTCLK
AGND
AVDD
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
2-CHANNEL LQFP
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
48 LQFP
C48-6
21-0054
26
______________________________________________________________________________________
D2
D1
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
3
2/07
Corrected units for input resistance in EC table
3
4
10/08
Changed specs for analog and digital supply current in EC table
4
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
Revision History
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