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MAX14917
Industrial Octal High-Side Switch
General Description
Benefits and Features
The MAX14917 has eight high-side switches specified to
deliver up to 700mA (min) continuous current per channel.
The high-side switches have on-resistance of 120mΩ (typ)
at 25°C ambient temperature.
● Robust Solutions
• 65V Absolute Maximum Supply Range
• CRC Error Checking on the SPI Interface
• Watchdog Timers for Monitoring SPI and SYNCH
• Per Channel Overload Diagnostic and Protection
• Loss of VDD or GND Protection
• Thermal Shutdown Protection
• Integrated ±1kV / 42Ω IEC 61000-4-5 Surge
Protection
• ±7kV / IEC 61000-4-2 Contact Discharge Method
• ±30kV / IEC 61000-4-2 Air Discharge Method
• -40°C to +125°C Operating Ambient Temperature
The device has an SPI interface that can be daisy
chained, allowing communication with multiple MAX14917
devices utilizing a common SPI chip select (CS). There
are also per-channel overload diagnostics provided
through the SPI interface. Two watchdog timers provide
an additional safety check of the master-to-device connectivity.
The MAX14917 features a 4 x 4 LED cross-bar matrix,
which provides a visual indication of channel status and
overload conditions for each channel, and an integrated
line-to-ground and line-to-line surge protection provides
robustness to the electrical stress as per IEC 61000-4-5
and requires only one TVS on VDD. The MAX14917 is
available in a compact 48-pin 6mm x 6mm FC2QFN package.
Applications
●
●
●
●
●
Industrial Digital Outputs
PLC Systems
Factory Automation
Building Automation
Industrial IoT
● Reduces Power and Heat Dissipation
• 120mΩ (typ) On-Resistance at TA = 25°C
• 2.5mA (typ) Supply Current
• Accurate Output Current Limiting
● Flexible
• SYNCH Input for Simultaneous Update of Switches
• LED Driver Matrix for 16 LEDs, Powered from 3.0V
to 36V
• Internal Clamps for Fast Inductive Load
Demagnetization
• Daisy Chainable SPI
• Flexible Logic Voltage Interface from 2.5V to 5.5V
• Pin Compatible with the MAX14915 and MAX14916
in Daisy-Chain Configuration
● Compact 6mm x 6mm FC2QFN Package
Ordering Information appears at end of datasheet.
19-100741; Rev 0; 2/20
MAX14917
Industrial Octal High-Side Switch
Simplified Block Diagram
VL
VDDOK
VA
REGEN
VDD
VDD
READY
SUPPLY
MONITOR
DRIVE +
MONITOR
VA
REGULATOR
OUT8
EN
VDD
DRIVE +
MONITOR
EN
SYNCH
CONTROL
OUT7
EN
CRCEN
VDD
DRIVE +
MONITOR
COMERR
OUT6
EN
SPIWD
VDD
WATCHDOGS
SYNCHWD
DRIVE +
MONITOR
MAX14917
OUT5
EN
VDD
DRIVE +
MONITOR
CS
CLK
SERIAL
INTERFACE
SDI
VDD
DRIVE +
MONITOR
SDO
FAULT
OUT3
EN
OVERLOAD
DIAGNOSTIC
VLED
VDD
DRIVE +
MONITOR
LHS1-4
LHS5-8
OUT2
EN
LED
DRIVERS
MATRIX
LHF1-4
VDD
DRIVE +
MONITOR
LHF5-8
LL48
LL37
LL26
LL15
EN
www.maximintegrated.com
OUT4
EN
OUT1
GND
19-100741
Maxim Integrated | 2
MAX14917
Industrial Octal High-Side Switch
Absolute Maximum Ratings
VDD......................................................................... -0.3V to +65V
OUT_ ................................................(VDD - 49V) to (VDD + 0.3V)
VA, VL ....................................................................... -0.3V to +6V
SDO, READY, COMERR ..............................-0.3V to (VL + 0.3V)
REGEN ..................................................................... -0.3V to +6V
FAULT ...................................................................... -0.3V to +6V
SDI, CS, CLK, EN, SYNCH, CRCEN, SPIWD, SYNCHWD .-0.3V
to +6V
VLED ....................................................................... -0.3V to +70V
LH_, LL_, VDDOK..................................... -0.3V to (VLED + 0.3V)
OUT_ Load Current ...........................................Internally Limited
Continuous Power Dissipation (Multilayer Board) (TA = +70°C,
derate 50mW/°C above +70°C) ......................................3900mW
Operating Temperature Range ...........................-40°C to +125°C
Junction Temperature ....................................................... +150°C
Storage Temperature Range ..............................-65°C to +150°C
Soldering Temperature (reflow) .......................................... 260°C
Note 1: All voltages relative to GND.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
48 F2CQFN
Package Code
F486A6F+1
Outline Number
21-100232
Land Pattern Number
90-100077
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
20.5°C/W
Junction to Case (θJC)
0.39°C/W (bottom)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VDD = +10V to +36V, VLED = +3.0V to 36V, VA = +3.0V to +5.5V, VL = +2.5V to +5.5V, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = VLED = 24V, VA = 3.3V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
36
V
DC Characteristics / SUPPLY
VDD Supply Voltage
VDD
VDD Supply Current
IDD
10
EN = high, OUT_ switches on, no load,
VA and VL supplied externally
3
EN = low
3
9.6
VDD UVLO Rise
Threshold
VDD_UVLO_R
VDD rising
VDD UVLO Fall
Threshold
VDD_UVLO_F
VDD falling, OUT_ disabled
VDD UVLO Hysteresis
VDD_UVLO_H
VDD Warn Fall
Threshold
VDD_WARN_F
VDD falling, VDDOK pin set Hi-Z
VDD Good Rise
Threshold
VDD_GOOD_R
VDD rising, VDDOK pin set low
www.maximintegrated.com
2
19-100741
7.9
12
mA
V
V
0.35
V
13
V
17
V
Maxim Integrated | 3
MAX14917
Industrial Octal High-Side Switch
Electrical Characteristics (continued)
(VDD = +10V to +36V, VLED = +3.0V to 36V, VA = +3.0V to +5.5V, VL = +2.5V to +5.5V, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = VLED = 24V, VA = 3.3V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
VDD Good Fall
Threshold
VDD_GOOD_F
VDD Good Hysteresis
VDD_GOOD_H
CONDITIONS
VDD falling
MIN
VDD rising
VDD POR Falling
Threshold
VDD_POR_F
VDD falling
5.6
3.0
VA
When VA is supplied externally; REGEN
= GND.
VA Supply Current
IVA
EN = high, OUT_ are turned on, no load,
no LEDs connected
VA Undervoltage
Lockout Threshold
VA_UV
VA Undervoltage
Lockout Hysteresis
VA_UVHYST
VL Supply Voltage
VL
IVL
VVL_POR
V
6.8
VA Supply Voltage
VDD = 24V, VA rising
2.45
5.5
V
0.85
mA
2.9
V
0.1
2.5
All logic inputs high or low
VL falling
0.87
V
V
0.5
VDD = 24V
UNITS
V
0.4
VDD_POR_R
VL POR Threshold
MAX
15
VDD POR Rise
Threshold
VL Supply Current
TYP
V
5.5
V
13
34
µA
1.32
1.5
V
120
250
mΩ
DC Characteristics / SWITCH OUTPUTs (OUT_)
On-Resistance
ROUT_HS
Current Limit
ILIM
Off Leakage Current
ILKG
IOUT_ = -600mA
0.7
Switch off, OUT_ = 0V
1
-10
1.3
A
+10
µA
3.6
V
DC Characteristics / LINEAR REGULATOR
Output Voltage
VA
Current Limit
ICL_VA
Short Current
ISHRT_VA
REGEN Threshold
VTREGEN
REGEN Leakage
Current
ILK_REGEN
REGEN open, CLOAD = 1μF, 0mA < IVA
< 20mA
3.0
REGEN open
25
3.3
mA
REGEN open, VA = 0V
REGEN = 0V
60
mA
0.2
V
-50
μA
DC Characteristics / LOGIC I/O
Input Voltage High
VIH
Input Voltage Low
VIL
Input Threshold
Hysteresis
VIHYS
Input Pulldown Resistor
RIN_PD
Input Pullup Resistor
RIN_PU
0.7 x VL
V
0.11 x
VL
V
All logic input pins except SYNCH and
CS
200
kΩ
SYNCH and CS
200
kΩ
Output Logic-High
(SDO)
VOH
ILOAD = -5mA
Output Logic-Low
VOL
ILOAD = +5mA
www.maximintegrated.com
V
0.3 x VL
VL - 0.6
V
0.33
19-100741
V
Maxim Integrated | 4
MAX14917
Industrial Octal High-Side Switch
Electrical Characteristics (continued)
(VDD = +10V to +36V, VLED = +3.0V to 36V, VA = +3.0V to +5.5V, VL = +2.5V to +5.5V, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = VLED = 24V, VA = 3.3V, TA = +25°C.) (Note 2)
PARAMETER
SDO Output Tristate
Leakage
SYMBOL
IL_SDO
CONDITIONS
CS = high
MIN
TYP
-1
MAX
UNITS
+1
µA
DC Characteristics / OPEN-DRAIN OUTPUT (FAULT, COMERR, READY, VDDOK)
READY Output LogicHigh
VODH
ILOAD = -5mA
Output Logic-Low
VODL
ILOAD = +5mA
Leakage
IODL
Open-drain output off, VOD = 5.5V
VL - 0.6
V
0.33
V
-1
+1
µA
VVLED
3.0
VDD
V
VOH_LH
VLED 0.3
DC Characteristics / LED Drivers (LH_, LL_)
LED Supply Voltage
LH Voltage High
LH = on, VLED = VDD, IVLED = -5mA
LH Off Leakage Current
IL_LH
LH_ = off, VLED = 0V
LL Output Voltage Low
VOH_LL
LL = on, IVLED = 5mA
LL Off Leakage Current
IL_LL
LL = off, VLED = VDD
-1
VCL = VDD - VOUT, IOUT_ = -500mA,
OUT_ is off
49
V
5
µA
0.3
V
+1
µA
DC Characteristics / PROTECTION
OUT_ Clamp Voltage
Channel Thermal
Shutdown Temperature
Channel Thermal
Shutdown Hysteresis
VCL
TJSHDN
Junction temperature rising. Per channel.
TJSHDN_HYST
Chip Thermal Shutdown
TCSHDN
Chip Thermal Shutdown
Hysteresis
TCSHDN_HYS
Temperature rising.
T
56
V
150
°C
15
°C
150
°C
10
°C
Timing Characteristics / OUT_
Prop Delay LH
tPD_LH
Delay from rising SYNCH edge to VOUT_
rising to 90%. RL = 48Ω. VDD = 24V.
Figure 2
11
30
µs
Prop Delay HL
tPD_HL
Delay from rising SYNCH edge to VOUT_
falling to 10% of VDD, VDD = 24V, RL =
48Ω, Figure 2
11
30
µs
Rise Time
tR
20% to 80% VDD, VDD = 24V, RL = 48Ω,
Figure 2
8
µs
Fall Time
tF
80% to 20% VDD, VDD = 24V, RL = 48Ω,
Figure 2
8
µs
Timing Characteristics / GLITCH FILTERS
Pulse Length of
Rejected Glitch
tFPL_GF
EN, SYNCH, SPIWD, SYNCHWD,
CRCEN
0
Passed Pulse Length
tFD_GF
EN, SYNCH, SPIWD, SYNCHWD,
CRCEN
300
www.maximintegrated.com
19-100741
80
ns
ns
Maxim Integrated | 5
MAX14917
Industrial Octal High-Side Switch
Electrical Characteristics (continued)
(VDD = +10V to +36V, VLED = +3.0V to 36V, VA = +3.0V to +5.5V, VL = +2.5V to +5.5V, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = VLED = 24V, VA = 3.3V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Glitch Filter Delay Time
TYP
MAX
tD_GF
EN, SYNCH
CONDITIONS
MIN
140
300
tD_GFL
SPIWD, SYNCHWD, CRCEN
290
600
UNITS
ns
Timing Characteristics / WATCHDOG
Watchdogs Timeout
Accuracy
tWD_ACC
SPIWD/SYNCHWD = 1
-30
+30
%
Timing Characteristics / LED Matrix
LED Driver Scan rate
FLED
Update rate for each LED
1
kHz
Timing Characteristics / SPI
CLK Clock Period
tCH+CL
100
ns
CLK Pulse Width High
tCH
40
ns
CLK Pulse Width Low
tCL
40
ns
CS Fall to CLK Rise
Time
tCSS
40
ns
SDI Hold Time
tDH
10
ns
SDI Setup Time
tDS
10
ns
SDO Propagation Delay
tDO
SDO Rise and Fall
Times
tFT
CS Hold Time
CS Pulse Width High
CLOAD = 10pF, CLK falling edge to SDO
stable
1
tCSH
tCSPW
30
(Note 3)
ns
ns
40
ns
40
ns
EMC
ESD
Surge Tolerance
Note 2:
Note 3:
Note 4:
Note 5:
VESD_C
OUT_ to GND, IEC 61000-4-2 Contact
Discharge
±7
VESD_A
OUT_ to GND, IEC 61000-4-2 Air
Discharge
±30
VESD
All other pins. Human Body Model (Note
4)
±2
VSURGE
OUT_ to GND, IEC 61000-4-5 with 42Ω,
TVS on VDD. (Note 5)
±1
kV
kV
All units are production tested at TA = +25°C. Specifications over temperature are guaranteed by characterization.
Specification is guaranteed by design; not production tested.
Bypass VDD pin to GND with 1μF capacitor as close as possible to the device for high ESD protection.
At typical application value of VDD = 24V with a TVS protection on VDD to GND.
www.maximintegrated.com
19-100741
Maxim Integrated | 6
MAX14917
Industrial Octal High-Side Switch
CS
tCLK
tCSS
tCL
tCSH
tCH
tCSPW
CLK
tDS
tDH
SDI
tDO
SDO
tFT
Figure 1. SPI TIming Diagram
SYNCH
SYNCH
tPD_LH
tPD_HL
0.9 VDD
OUT_
OUT_
0.1 VDD
ON_ = 1
ON_ = 0
Figure 2. SYNCH to OUT_ Propagation Delay
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19-100741
Maxim Integrated | 7
MAX14917
Industrial Octal High-Side Switch
Typical Operating Characteristics
(VDD = +24V, REGEN = open, VL = +3.3V, TA = +25°C, unless otherwise noted.)
www.maximintegrated.com
19-100741
Maxim Integrated | 8
MAX14917
Industrial Octal High-Side Switch
Pin Configuration
MAX14917
28
27
26 25
CRCEN
COMERR
30 29
SPIWD
CS
31
EN
CLK
33 32
VA
SDI
35 34
SYNCH
FAULT
36
SDO
READY
TOP VIEW
VL
37
24 I.C.
GND
38
23 GND
OUT8
39
22 OUT4
OUT8
40
21 OUT4
OUT7
41
20 OUT3
OUT7
42
OUT6
43
18 OUT2
OUT6
44
17 OUT2
OUT5
45
16 OUT1
OUT5
46
GND
47
LL48
48
19 OUT3
MA
MAX
X149
14917
17
15 OUT1
EP
14 GND
REGEN
8
9
10
11 12
LHF1-4
LL15
VDDOK
7
LHS5-8
LL26
6
LHF5-8
5
VDD
4
VLED
3
VL
2
SYNCHWD
1
LL37
13 LHS1-4
FC2
FC2QFN
QFN
6mm x 6mm
Pin Description
NAME
FUNCTION
REF
SUPPLY
TYPE
EP, 8
VDD
Supply Voltage, Nominally 24V. Connect all VDD together. Bypass
VDD to GND through a 1µF capacitor.
GND
Supply
29
VA
Analog Supply Input. Connect an external 3.0V to 5.5V supply to
VA or use the internal linear regulator by leaving REGEN open.
Bypass VA to GND through a 1µF ceramic capacitor.
GND
Supply
5
REGEN
VA Regulator Enable Input. Connect REGEN to GND to disable
VA regulator. Leave REGEN open to enable the VA regulator,
which internally supplies VA with 3.3V.
GND
Supply
14, 23, 38, 47
GND
Ground. Connect all GND pins together.
GND
GND
PIN
Power Supply
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19-100741
Maxim Integrated | 9
MAX14917
Industrial Octal High-Side Switch
Pin Description (continued)
PIN
NAME
6, 37
VL
4
VDDOK
REF
SUPPLY
TYPE
Logic Supply Input. VL defines the logic levels on all logic
interface pins. Bypass VL to GND through a 100nF ceramic
capacitor.
GND
Supply
Active-Low, Open-Drain Logic Output for the VDD Supply.
VDDOK turns on low when VDD rises above 16V (typ) and turns
off when VDD falls below 13V (typ). Connect a LED with a pullup
resistor to a voltage between 3.3V and VDD.
GND
Logic
FUNCTION
Switch Outputs
15, 16
OUT1
High-Side Switch Output 1
VDD
Power
17, 18
OUT2
High-Side Switch Output 2
VDD
Power
19, 20
OUT3
High-Side Switch Output 3
VDD
Power
21, 22
OUT4
High-Side Switch Output 4
VDD
Power
45, 46
OUT5
High-Side Switch Output 5
VDD
Power
43, 44
OUT6
High-Side Switch Output 6
VDD
Power
41, 42
OUT7
High-Side Switch Output 7
VDD
Power
39, 40
OUT8
High-Side Switch Output 8
VDD
Power
Control Interface
28
EN
Enable Logic Input. Drive EN high for normal operation. Drive EN
low to disable/three-state all OUT_ drivers. Internal weak
pulldown.
VL
Logic
35
FAULT
FAULT Global Diagnostics Open-Drain Output. The FAULT goes
low in case of overload or undervoltage conditions. Connect a
pullup resistor to VL.
VL
Logic
33
SYNCH
SYNCH Input. All eight output switches are updated
simultaneously on the rising edge of SYNCH, as determined by
the content of the SPI command. The OUT_ states do not change
when SYNCH is held low. When SYNCH is high, the output states
change immediately after a new SPI command. SYNCH has a
weak pullup.
VL
Logic
25
CRCEN
CRC Enable Select Input. Drive CRCEN high to enable CRC
generation and error detection on the serial data. CRC has a
weak pulldown.
VL
Logic
36
READY
Open-Drain Output. READY is passive low when the internal logic
chip supply and VL I/O supply are both higher than their
respective UVLO thresholds, indicating that the part is ready for
SPI communication. When the internal register supply falls below
the UVLO threshold the OUTs are off and READY transitions
active-high. Connect a pulldown resistor to READY.
VL
Logic
26
COMERR
SPI Error Open-Drain Output. The COMERR transistor turns on
low when an error occurs during a SPI transaction. Connect a
pullup resistor to VL.
VL
Logic
7
SYNCHWD
SYNCH Watchdog Enable Logic Input. Set SYNCHWD high to
enable the SYNCH watchdog.
VL
Logic
27
SPIWD
SPI Watchdog Enable Logic Input. Set SPIWD high to enable the
SPI watchdog.
VL
Logic
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19-100741
Maxim Integrated | 10
MAX14917
Industrial Octal High-Side Switch
Pin Description (continued)
NAME
FUNCTION
REF
SUPPLY
TYPE
32
SDI
Serial Data Input. SPI MOSI data from controller. SDI has a weak
pulldown.
VL
Logic
34
SDO
Serial Data Output. SPI MISO data output to controller.
VL
Logic
31
CLK
Serial Clock Input. CLK has a weak pulldown.
VL
Logic
30
CS
Chip Select Input. CS has a weak pullup.
VL
Logic
PIN
Serial Interface
LED DRIVER MATRIX
9
VLED
Supply for LED Drivers. Apply supply voltage of 3.0V to VDD.
3
LL15
OUTs 1, 5 Status/Fault LED Cathode Output (Open-drain LowSide). Connect a resistor in series to set the LED current.
2
LL26
OUTs 2, 6 Status/Fault LED Cathode Output (Open-Drain LowSide). Connect a resistor in series to set the LED current.
1
LL37
OUTs 3, 7 Status/Fault LED Cathode Output (Open-Drain LowSide). Connect a resistor in series to set the LED current.
48
LL48
OUTs 4, 8 Status/Fault LED Cathode Output (Open-Drain LowSide). Connect a resistor in series to set the LED current.
13
LHS1-4
OUTs 1-4 Status LED Anode Outputs (Open-Drain High-Side).
Connect a resistor in series to set the LED current.
12
LHS5-8
OUTs 5-8 Status LED Anode Outputs (Open-Drain High-Side).
Connect a resistor in series to set the LED current.
11
LHF1-4
OUTs 1-4 Fault LED Anode Connections (Open-Drain High-Side).
Connect a resistor in series to set the LED current
10
LHF5-8
OUTs 5-8 Fault LED Anode Connections (Open-Drain High-Side).
Connect a resistor in series to set the LED current.
NO CONNECT
24
I.C.
www.maximintegrated.com
Internally Connected. Do not connect.
19-100741
Maxim Integrated | 11
MAX14917
Industrial Octal High-Side Switch
Detailed Description
The MAX14917 is an octal high-side switch. The state of the high-side switches (OUT[1:8]) are set through the SPI
interface. The OUT_ high-side switches have an on-resistance of 120mΩ (typ) at 700mA and TA = 25°C, and 250mΩ
(max) on-resistance at 700mA and TA = 125°C. Watchdog timers (SPIWD and/or SYNCHWD) monitor SPI and/or
SYNCH activity, and automatically turn the OUT_ pins off in case of missing SPI/SYNCH activity when enabled.
Global OUT Disable
When the EN pin input is low, all OUT_ switches are off independent of the level of the SYNCH input or the ON_ bits in the
SPI command (Figure 6). Logic low on the EN pin also allows quick disable of all OUT_ switches in case of emergency.
Note: logic high on the EN pin is required for normal operation.
Power-Up and Undervoltage Lockout
When the VDD, VA, VL, or VINT supply voltages are under their respective UVLO thresholds, all OUT_ switches are off.
VINT is an internal supply for the registers and logic that is derived from the VA or VDD supply.
When the VDD supply or VA supply rises, the internal logic supply (VINT) rises. If VL and VINT are both above their UVLO
thresholds, the chip is ready for communication and the READY pin becomes passive low to indicate that the part is
ready to communicate through the SPI interface.
When VDD rises above VDD_GOOD_R the VDDOK pin is turned active-low, indicating that the VDD supply is high enough
so the OUT_ switches can be operated normally.
When VDD falls below 13V (typ) the VDDOK is turned high, but all the OUT_ switches continue operate normally until
VDD falls below the VDD_UVLO_F threshold. All OUT_ switches are off until VDD reaches the VDD_GOOD_R threshold
again as shown in Figure 3.
The READY and VDDOK pins are always active, but the FAULT pin does not signal supply conditions.
VDD
24V
VDD_GOOD_R
APPROXIMATELY 16V
VDD_WARN_F
APPROXIMATELY 13V
OUT_ TURNED ON IF ON_=1
VDD_UVLO_F
APPROXIMATELY 8V
All OUT_ TURNED OFF
t
VDDOK
Figure 3. VDD Supply Monitoring
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19-100741
Maxim Integrated | 12
MAX14917
Industrial Octal High-Side Switch
Watchdog
The MAX14917 provides two watchdog timers to monitor activity: one on the SPI interface and the other on the SYNCH
pin. SPIWD logic high input enables SPI watchdog functions and the SYNCHWD logic high input enables the SYNCH
watchdog function.
● The SPI watchdog timer monitors clock activity on the CLK and inputs. At least one valid SPI cycle must be detected
in the watchdog-timeout period. This means that the CLK input must have a multiple of 8 clock-cycles during a low
period.
● The SYNCH pin watchdog checks if SYNCH is stuck low. At least a 1µs SYNCH pin high level must be present in
the watchdog-timeout period. Driving the SYNCH pin high if SYNCH is not used ensures that the SYNCH watchdog
is disabled.
If either watchdog criteria is not met, all OUT_ switches are automatically turned off. The watchdog timeout is 1.2s (typ).
Note: the FAULT pin does not indicate the watchdog-timeout error. The CMERR bit is visible only on the second byte if
CRC is enabled (CRCEN pin is high). If CRC is not enabled, the second byte is not reported and CMERR is not signaled
through SPI, as shown in Figure 7 and Figure 9.
Chip Thermal Protection
When the chip temperature rises to above the thermal shutdown threshold of 150°C, the chip enters shutdown protection
and all overloaded OUT switches are kept off until chip temperature drops below 140°C.
If an overload occurs on the VA regulator or on the LED matrix, i.e., if the chip temperature rises above 165°C due to a
short, then the VA regulator and all OUT switches, as well as the LED matrix are shut down to prevent chip damage. In
this condition, the FAULT pin output is driven low. All F_ bits in the SPI SDO data stream are set to 1. When the chip
temperature then falls by the hysteresis amount, the VA regulator turns on, and the LED matrix and OUT switches are
restored to normal operation.
Channel Thermal Management
Every OUT switch temperature is constantly monitored. If the temperature of a switch rises above the thermal shutdown
threshold of 150°C (typ), that OUT_ is automatically turned off for protection. After the temperature drops by 15°C, the
OUT_ is turned on again. When an OUT_ turns off due to thermal shutdown, its associated F_ bit in the SDO stream and
the FAULT pin is driven low.
Current Limiting
Each high-side switch features active current limiting. When the load current exceeds 1A (typ), the load current is
limited by the high-side switch. If the load current exceeds the current limit, the voltage across the high-side FET switch
increases and the temperature of the FET increases in accordance with the FET power dissipation. Increase of the switch
temperature generally leads to thermal shutdown of that OUT switch.
Lamp Load Turn On
Incandescent lamps initially draw high currents while their filament is cold, then this turn-on current reduces as the
filament heats up. The MAX14917 automatically detects the presence of a lamps loads. When a lamp load is detected,
the overload signaling is masked for a duration of 200ms (typ).
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MAX14917
Industrial Octal High-Side Switch
LED Drivers
The 4x4 LED driver crossbar matrix offers an efficient configuration for driving up to 16 LEDs as shown in Figure 4.
The LEDs are controlled by the MAX14917 autonomously to indicate per-channel status and fault conditions. A channel
status LED (SLED) is automatically turned on when the corresponding OUT_ switch is on and there is no fault condition.
If a fault is detected, its associated fault LED (FLED) is turned on and its associated status LED (SLED) is automatically
turned off. For any OUT_ channel, its SLED and its FLED are never on simultaneously. The fault LEDs signal thermal
overload shutdown of the switches and they are stretched by 2s (typ). The LED matrix is powered through the VLED
supply input, which can be in the range of the 3.0V (min) up to the VDD field supply voltage.
For every current limiting resistor (R) each of the four LEDs in a column string is pulsed for a quarter of the time, so
that current only flows through one LED and resistor at any one time. Thus, the resistors (R) determine the LED current
through one LED during the pulse. Each LED is pulsed on at a rate of 1kHz (typ) and is on for 25% of the 1ms period.
Thus, the average current flowing through a LED that is turned on is about 0.25 x (VLED - VF)/R. VF is the forward voltage
of the LED. The resistor value should be chosen according to the LED current/light intensity requirements.
VLED
MAX14917
LHS1-4
LHS5-8
R
LHF1-4
R
LHF5-8
R
F1
R
S1
S5
F5
S2
S6
S3
S7
F3
F7
S4
S8
F4
F8
LL15
F2
F6
LL26
LL37
LL48
Figure 4. LED Matrix Scheme
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Maxim Integrated | 14
MAX14917
Industrial Octal High-Side Switch
Serial Interface
The MAX14917 communicates with the host controller through a high-speed SPI serial interface. The interface has three
logic inputs: clock (CLK), chip select (CS), serial data in (SDI), and one data out (SDO). The SDO is three-stated when
CS is high. The maximum SPI clock rate is 10MHz. The SPI interface logic complies with SPI clock polarity CPOL = 0
and clock phase CPHA = 0.
The basic SPI command is 8 clock cycles and is extended to 16 clocks when CRC is enabled (CRCEN = high).
Note: while Figure 1, Figure 6, and Figure 7 show CLK to be low at the beginning of the SPI cycle, on the falling CS edge,
the CLK can also be logic high. The MAX14917 ignores the initial CLK logic state and only acts on the first rising CLK
edge and samples the first SDI bit.
Daisy-Chained SPI
Daisy-chained SPI mode allows communication with multiple MAX14917 devices using a common CS signal in one SPI
cycle (refer to Figure 5). Figure 6 shows a single SPI cycle without CRC enabled (CRCEN = low) for one device.
If the ON_ bit is a 1 the high-side switch is turned on, and if it is 0, the high-side switch is turned off. The F_ bits are
per-channel faults. The F_ bits are latched and are, therefore, only cleared on the following SPI cycle if the fault has
disappeared before the following SPI cycle. The F_ bits do not go active when a lamp load is detected. In thermal chip
shutdown, all F_ bits are set to 1.
CRC error detection is supported if the CRCEN pin is high, which lengthens the minimum SPI cycle to 16 CLK clocks per
MAX14917. A single SPI command with CRC enabled is shown in Figure 7.
CLK
CLK
MOSI
SDI
CLK
D A T A -
I C 1
D A T A -
I C 1
D A T A -
I C 1
SDO
SDI
CLK
D A T A -
I C 2
D A T A -
I C 2
D A T A -
I C 2
SDO
SDI
D A T A -
I C 3
D A T A -
I C 3
D A T A -
I C 3
SDO
MCU
CS
CS
CS
CS
MAX14917
MAX14917
MAX14917
MISO
Figure 5. Diagram of Three MAX14917 Devices Daisy-Chained
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Maxim Integrated | 15
MAX14917
Industrial Octal High-Side Switch
CS
CLK
SDI
X
ON8
ON7
ON6
ON5
ON4
ON3
ON2
ON1
F8
F7
F6
F5
F4
F3
F2
F1
SDO
X
Figure 6. Single SPI Command
CS
CLK
SDI
X
SDO
ON8 ON7 ON6 ON5 ON4 ON3 ON2 ON1
F8
F7
F6
F5
F4
F3
F2
0
0
0
CRC4 CRC3 CRC2 CRC1 CRC0
F1 CMERR VERR THERR CRC4 CRC3 CRC2 CRC1 CRC0
X
HiZ
Figure 7. Single SPI Command with CRC
Checking of Clocks on the Serial Interface
The MAX14917 checks that the number of clock cycles in one SPI cycle (from falling edge of CS to rising edge of CS)
is a multiple of 8. The expected number of clocks is scaled according to CRCEN setting. If the number of clock cycles
differs from the expected, then the SPI command is not executed and an SPI error is signaled through the COMERR pin.
CRC Error Detection on the Serial Interface
CRC error detection of the serial data can be enabled to minimize incorrect operation/misinformation due to data
corruption of the SDI/SDO signals. If error detection is enabled, then the MAX14917:
1. Performs error detection on the SDI data that it receives from the controller, and
2. Calculates a CRC on the SDO data and appends a check byte to the SDO diagnostics/status data that it sends to the
controller.
This ensures that both the data that it receives from the controller (OUT_ setting) and the data that it sends to the
controller (F_ diagnostic) have a low likelihood of undetected errors.
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MAX14917
Industrial Octal High-Side Switch
Setting the CRCEN input high enables CRC error detection. A CRC frame check sequence (FCS) is then sent along with
each serial transaction. The 5-bit FCS is based on the generator polynomial X5 + X4 + X2 + 1 with CRC starting value =
11111. When CRC is enabled, the MAX14917 expects a check byte appended to the SDI program/configure data that it
receives. The check byte has the format shown in Figure 8. The five FCS bits (CR_) are calculated on all the data sent
in one SPI command including the three “0” in the MSBs of the check byte. Therefore, the CRC is calculated from 8 bits
+ 3 bits. CR0 is the LSB of the FCS.
The MAX14917 verifies the received FCS. If no error is detected, the MAX14917 sets the OUT_ output switches per the
SDI data. If a CRC error is detected, then the MAX14917 does not change the OUT_ outputs, but sets the COMERR
logic output low (i.e., the open-drain COMERR NMOS output transistor is turned on).
In Figure 9, the format of the check byte that the device appends to the SDO data is shown: the CMERR bit is set when
either an SPI or SYNCH watchdog event has occurred; the VERR bit is set if either of the VDD, VA, or internal voltages is
below its nominal operational thresholds; and, the THERR bit is set when a chip thermal shutdown event has occurred.
The CR_ are the CRC bits that the MAX14917 calculate on the SDO data, including the CMERR, VERR, and THERR
bits. This allows the controller to check for errors on the SDO data received from the MAX14917.
CS
CLK
SDI
0
0
0
CRC4
CRC3
CRC2
CRC1
CRC0
HiZ
CRC4
CRC3
CRC2
CRC1
CRC0
HiZ
Figure 8. FCS Byte Expected from the SPI Master
CS
CLK
SDO
CMERR
VERR
THERR
Figure 9. FCS Byte Sent by the MAX14917 to the SPI Master
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Maxim Integrated | 17
MAX14917
Industrial Octal High-Side Switch
Applications Information
Inductive Load Turn-Off Energy Clamping
During turn-off of inductive loads, the free-wheel energy is clamped by the internal VCL clamps. This energy must be
limited to 150mJ (max) at TJ = +125°C and IOUT_ = -600mA per channel, all channels switching simultaneously. Refer to
Figure 10.
VDD
VCL
OUT_
MAX14917
ZL
GND
Figure 10. Inductive Load Clamping Scheme
Surge Protection
The MAX14917 has internal protection against ±1kV 42Ω/0.5µF 1.2µs/50µs surges on the OUT_ pins to GND, if the VDD
pins are protected with one TVS. Ensure that the peak voltage of the VDD TVS is below 65V.
RF Conducted Immunity
To ensure that the OUT_ pins do not produce wrong logic conditions while being off, during IEC61000-4-6 RF immunity
testing, connect 10nF capacitors at each OUT_ to GND.
Reverse Currents into OUT_
If currents flow into the OUT_ pins, the device heats up due to internal currents that flow through the device from VDD
to GND. The internal currents are proportional to the reverse current into OUT_. The allowed reverse OUT_ current
depends on VDD, the ambient temperature and the thermal resistance. At 25°C ambient temperature, the reverse current
into one OUT should be limited to 1A at VDD = 36V and 1.5A at VDD = 24V. Driving higher currents into OUT_ can
destroy the device thermally.
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Maxim Integrated | 18
MAX14917
Industrial Octal High-Side Switch
Typical Application Circuits
16-Channel Isolated High-Side Switch
24V
3.3V
0.1μF
1μF
0.1μF
10k
GPIO
INT
MISO
MOSI
SAA
SCLK
GPIO
GND
VA REGEN VDDOK
VDDB
VDDA
MAX14483
OFAULT
IRDY
IFAULT
ISDO
OSDO
ISDI
OSDI
ICS
OCS
OSCLK
IAUX
OUT2
OUT3
OUT3
COMERR
10nF
FAULT
OUT4
SDO
OUT4
10nF
MAX14917
OUT5
OUT5
SDI
10nF
CS
OUT6
OUT6
10nF
OUT7
SYNCH
OUT7
10nF
OUT8
OUT8
LHS1-4 LHS5-8 LHF1-4 LHF5-8 LL15 LL48
GNDA
OUT2
10nF
READY
OAUX
GNDB
OUT1
10nF
CLK
ISCLK
36V
VLED VDD
OUT1
SPIWD
SYNCHWD
MCU
CS
VL
EN
10k
VDD
10μF
GND
10nF
24V
1μF
10μF
VL
VA REGEN VDDOK
EN
OUT1
OUT2
OUT3
COMERR
OUT4
MAX14917
SYNCH
OUT12
10nF
OUT5
OUT13
10nF
CS
CLK
OUT11
10nF
FAULT
SDI
OUT10
10nF
READY
SDO
OUT9
10nF
SPIWD
SYNCHWD
10k
36V
VLED VDD
OUT6
OUT14
10nF
OUT7
OUT15
10nF
OUT8
GND
LHS1-4 LHS5-8 LHF1-4 LHF5-8 LL15 LL48
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19-100741
OUT16
10nF
Maxim Integrated | 19
MAX14917
Industrial Octal High-Side Switch
Ordering Information
TEMP RANGE
PACKAGE
TOP MARKING
LEAD PITCH
MAX14917AFM+
PART
-40°C to +125°C
48-Pin F2CQFN (6mm x 6mm)
MAX14917AFM
0.4mm
MAX14917AFM+T
-40°C to +125°C
48-Pin F2CQFN (6mm x 6mm)
MAX14917AFM
0.4mm
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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Maxim Integrated | 20
MAX14917
Industrial Octal High-Side Switch
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/20
DESCRIPTION
Initial release
PAGES
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For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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