MAX19700ETM+T

19-3549; Rev 0; 2/05 KIT ATION EVALU E L B AVAILA 7.5Msps, Ultra-Low-Power Analog Front-End ♦ Excellent Gain/Phase Match ±0.22° Phase, ±0.02dB Gain (Rx ADC) at fIN = 1.87MHz at -0.5dBFS ♦ Three 12-Bit, 1µs Aux-DACs ♦ Single-Supply Operation ♦ Multiplexed Parallel Digital I/O ♦ Serial-Interface Control ♦ Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx-Rx Disable ♦ Miniature 48-Pin Thin QFN Package (7mm x 7mm x 0.8mm) VDD DAC1 DAC2 37 38 39 40 GND IDP IDN 41 42 43 QDP QDN VDD 45 44 COM REFIN 46 TOP VIEW REFN Pin Configuration 36 2 35 3 34 4 33 5 32 Ordering Information GND VDD 7 9 PIN-PACKAGE PKG CODE 10 48 Thin QFN-EP** T4877-4 QAN QAP VDD 11 26 GND 12 25 28 VDD GND VDD CS SCLK DIN T/R DR SHDN 24 23 22 21 27 DAC3 N.C. N.C. D7 D8 D9 20 OVDD D6 19 18 17 16 EXPOSED PADDLE (GND) 15 *All devices are specified over the -40°C to +85°C operating range. **EP = Exposed paddle. +Denotes lead-free package. 29 8 14 T4877-4 30 MAX19700 13 48 Thin QFN-EP** 31 6 D1 D2 D3 D4 D5 OGND Portable Communication Equipment D0 TD-SCDMA Data Cards MAX19700ETM+ ♦ Excellent Dynamic Performance SINAD = 54.9dB at fIN = 1.87MHz (Rx ADC) SFDR = 76.5dBc at fOUT = 620kHz (Tx DAC) 1 TD-SCDMA Handsets MAX19700ETM ♦ Integrated TD-SCDMA Filters with >55dB Stopband Rejection REFP VDD IAP IAN GND CLK Applications PART* ♦ Ultra-Low Power 36.3mW at fCLK = 5.12Msps, Fast Mode 19.8mW at fCLK = 5.12Msps, Slow Mode Low Standby and Shutdown Current 47 The MAX19700 operates on a single +2.7V to +3.3V analog supply and +1.8V to +3.3V digital I/O supply. The MAX19700 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin, thin QFN package. ♦ Dual 10-Bit Rx ADC and Dual 10-Bit Tx DAC 48 The MAX19700 is an ultra-low-power, mixed-signal analog front-end (AFE) designed for TD-SCDMA handsets and data cards. Optimized for high dynamic performance at ultra-low power, the MAX19700 integrates a dual 10-bit, 7.5Msps receive (Rx) ADC, dual 10-bit, 7.5Msps transmit (Tx) DAC with TD-SCDMA baseband filters, and three fast-settling 12-bit aux-DAC channels for ancillary RF front-end control. The typical operating power in Tx-Rx FAST mode is 36.3mW at a 5.12Msps clock frequency. The Rx ADCs feature 54.9dB SINAD and 78dBc SFDR at a 1.87MHz input frequency with a 7.5Msps sample frequency. The analog I/Q input amplifiers are fully differential and accept 1.024V P-P full-scale signals. Typical I/Q channel matching is ±0.22° phase and ±0.02dB gain. The Tx DACs with TD-SCDMA lowpass filters feature -3dB cutoff frequency of 1.27MHz and >55dB stopband rejection at fIMAGE = 4.32MHz. The analog I/Q full-scale output voltage range is selectable at ±410mV or ±500mV. The output common-mode voltage is selectable from 0.9V to 1.4V and the I/Q channel offset is adjustable. The typical I/Q channel matching is ±0.05dB gain and ±0.16° phase. The Rx ADC and Tx DAC share a single, 10-bit parallel, high-speed digital bus allowing half-duplex operation for time-division duplex (TDD) applications. A 3-wire serial interface controls power-management modes and the aux-DAC channels. Features THIN QFN Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX19700 General Description MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End ABSOLUTE MAXIMUM RATINGS VDD to GND, OVDD to OGND ..............................-0.3V to +3.4V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, REFP, REFN, REFIN, COM, DAC1, DAC2, DAC3 to GND .................-0.3V to (VDD + 0.3V) D0–D9, DR, T/R, SHDN, SCLK, DIN, CS, CLK to OGND .....................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin Thin QFN (derate 26.3mW/°C above +70°C) .......2.1W Thermal Resistance θJA ..................................................38°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP 3.0 MAX UNITS POWER REQUIREMENTS Analog Supply Voltage VDD 2.7 Output Supply Voltage OVDD 1.8 Ext1-Tx, Ext3-Tx, and SPI2-Tx states; transmit DAC operating mode (Tx), fCLK = 5.12MHz, fOUT = 620kHz on both channels; aux-DACs ON and at midscale 10.3 Ext2-Tx, Ext4-Tx, and SPI4-Tx states; transmit DAC operating mode (Tx), fCLK = 5.12MHz, fOUT = 620kHz on both channels; aux-DACs ON and at midscale 12.4 Ext1-Rx, Ext4-Rx, and SPI3-Rx states; receive ADC operating mode (Rx), fCLK = 5.12MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale 12.1 3.3 V VDD V VDD Supply Current 2 mA Ext2-Rx, Ext3-Rx, and SPI1-Rx modes; receive ADC operating mode (Rx), fCLK = 5.12MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale 6.6 Ext2-Tx, Ext4-Tx, and SPI4-Tx modes; transmit DAC operating mode (Tx), fCLK = 7.5MHz, fOUT = 620kHz on both channels; aux-DACs ON and at midscale 13.1 Ext1-Tx, Ext3-Tx, and SPI2-Tx modes; transmit DAC operating mode (Tx), fCLK = 7.5MHz, fOUT = 620kHz on both channels; aux-DACs ON and at midscale 10.4 _______________________________________________________________________________________ 16 7.5Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1) PARAMETER SYMBOL VDD Supply Current OVDD Supply Current CONDITIONS MIN TYP MAX Ext1-Rx, Ext4-Rx, and SPI3-Rx modes; receive ADC operating mode (Rx), fCLK = 7.5MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale 12.8 16 Ext2-Rx, Ext3-Rx, and SPI1-Rx modes; receive ADC operating mode (Rx), fCLK = 7.5MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale 7 UNITS mA Standby mode, CLK = 0 or OVDD; aux-DACs ON and at midscale 2.7 4 Idle mode, fCLK = 7.5MHz; aux-DACs ON and at midscale 4.7 6 Shutdown mode, CLK = 0 or OVDD 0.7 µA Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx, SPI1-Rx, SPI3-Rx modes; receive ADC operating mode (Rx), fCLK = 7.5MHz, fIN = 1.87MHz on both channels; aux-DACs ON and at midscale 1.38 mA Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx, SPI2-Tx, SPI4-Tx modes; transmit DAC operating mode (Tx), fCLK = 7.5MHz, fOUT = 620kHz; aux-DACs ON and at midscale 72.9 Idle mode, fCLK = 7.5MHz; aux-DACs ON and at midscale 10.9 Shutdown mode, CLK = 0 or OVDD 0.01 Standby mode, CLK = 0 or OVDD; aux-DACs ON and at midscale 0.03 µA Rx ADC DC ACCURACY Resolution 10 Bits Integral Nonlinearity INL ±0.85 Differential Nonlinearity DNL ±0.55 Offset Error Residual DC offset error Gain Error Include reference error ±0.5 LSB LSB ±5 %FS %FS ±1.1 ±5 DC Gain Matching ±0.01 ±0.25 Offset Matching ±4.5 LSB ±15.7 ppm/°C Gain Temperature Coefficient Power-Supply Rejection PSRR dB Offset error (VDD ±5%) ±0.2 LSB Gain error (VDD ±5%) ±0.04 %FS _______________________________________________________________________________________ 3 MAX19700 ELECTRICAL CHARACTERISTICS (continued) MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rx ADC ANALOG INPUT Input Differential Range VID Input Common-Mode Voltage Range VCM Input Impedance RIN Differential or single-ended inputs Switched capacitor load CIN ±0.512 V VDD / 2 V 720 kΩ 5 pF Rx ADC CONVERSION RATE Maximum Clock Frequency fCLK Data Latency (Figure 3) (Note 2) 7.5 Channel I 5 Channel Q 5.5 MHz Clock Cycles Rx ADC DYNAMIC CHARACTERISTICS (Note 3) Signal-to-Noise Ratio SNR Signal-to-Noise Plus Distortion SINAD Spurious-Free Dynamic Range SFDR Third-Harmonic Distortion HD3 Intermodulation Distortion fIN = 1.875MHz, fCLK = 7.5MHz 53.7 fIN = 3.5MHz, fCLK = 7.5MHz fIN = 1.875MHz, fCLK = 7.5MHz 53.6 fIN = 3.5MHz, fCLK = 7.5MHz fIN = 1.875MHz, fCLK = 7.5MHz 55 dB 54.8 54.9 dB 54.7 66 78 fIN = 3.5MHz, fCLK = 7.5MHz 70.1 fIN = 1.875MHz, fCLK = 7.5MHz -84 dBc dBc fIN = 3.5MHz, fCLK = 7.5MHz -72.1 IMD f1 = 1.8MHz, -7dBFS; f2 = 1MHz, -7dBFS -75.6 dBc Third-Order Intermodulation Distortion IM3 f1 = 1.8MHz, -7dBFS; f2 = 1MHz, -7dBFS -78 dBc Total Harmonic Distortion THD fIN = 1.875MHz, fCLK = 7.5MHz fIN = 3.5MHz, fCLK = 7.5MHz Aperture Delay Overdrive Recovery Time 1.5x full-scale input -77.9 -71 -64 dBc 3.5 ns 2 ns -85 dB Rx ADC INTERCHANNEL CHARACTERISTICS Crosstalk Rejection fINX,Y = 1.875MHz at -0.5dBFS, fINX,Y = 1MHz at -0.5dBFS (Note 4) Amplitude Matching fIN = 1.875MHz at -0.5dBFS (Note 5) ±0.02 dB Phase Matching fIN = 1.875MHz at -0.5dBFS (Note 5) ±0.22 Degrees 4 _______________________________________________________________________________________ 7.5Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Tx DAC DC ACCURACY Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Residual DC Offset VOS 10 Guaranteed monotonic (Note 6) Bits ±0.45 LSB ±0.26 LSB TA > +25°C -4 ±1 +4 TA < +25°C -6.5 ±1 +6.5 Include reference error (peak-to-peak error) -50 Corner Frequency 3dB corner 1.1 Passband Ripple DC to 640kHz (Note 6) Group Delay Variation in Passband DC to 640kHz, guaranteed by design DC to 700kHz 2 Full-Scale Gain Error mV +50 mV 1.5 MHz 0.28 0.5 dBP-P 50 100 ns TRANSMIT-PATH DYNAMIC PERFORMANCE Error-Vector Magnitude EVM fIMAGE = 4.32MHz, fOUT = 800kHz, fCLK = 5.12MHz Stopband Rejection Spot relative to 100kHz Baseband Attenuation 1.27 55 dBc 2MHz 20 4MHz 46.5 5MHz 54.7 10MHz 81 20MHz 88 DAC Conversion Rate fCLK In-Band Noise Density ND fOUT = 620kHz, fCLK = 5.12MHz, offset = 500kHz Third-Order Intermodulation Distortion IM3 f1 = 620kHz, f2 = 640kHz % (Note 2) dB 7.5 Glitch Impulse -121.7 dBc/Hz 76 dBc 10 pV•s 76.5 dBc Spurious-Free Dynamic Range to Nyquist SFDR fCLK = 7.5MHz, fOUT = 620kHz Total Harmonic Distortion to Nyquist THD fCLK = 7.5MHz, fOUT = 620kHz -74.8 Signal-to-Noise Ratio to Nyquist SNR fCLK = 7.5MHz, fOUT = 620kHz 57.1 60 MHz -59 dB dB _______________________________________________________________________________________ 5 MAX19700 ELECTRICAL CHARACTERISTICS (continued) MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRANSMIT-PATH INTERCHANNEL CHARACTERISTICS I-to-Q Output Isolation fOUTx,Y = 500kHz, fOUTx,Y = 620kHz Gain Mismatch Between DAC Outputs Measured at DC Phase Mismatch Between DAC Outputs fOUT = 620kHz, fCLK = 7.5MHz 85 -0.3 Differential Output Impedance ±0.05 dB +0.3 dB ±0.16 Degrees 800 Ω TRANSMIT-PATH ANALOG OUTPUT Full-Scale Output Voltage (Table 6) VFS Bit E7 = 0 (default) ±410 Bit E7 = 1 ±500 Bits CM1 = 0, CM0 = 0 (default) Output Common-Mode Voltage (Table 8) 1.32 1.4 Bits CM1 = 0, CM0 = 1 1.25 Bits CM1 = 1, CM0 = 0 1.1 Bits CM1 = 1, CM0 = 1 0.9 mV 1.48 V RECEIVE TRANSMIT-PATH INTERCHANNEL CHARACTERISTICS ADC fINI = fINQ = 1.875MHz, DAC fOUTI = fOUTQ = 620kHz, fCLK = 7.5MHz Receive Transmit Isolation 85 dB ±1.25 LSB Guaranteed monotonic over codes 100 to 4000 (Note 6) ±0.65 LSB RL > 200kΩ ±0.7 %FS ±0.6 %FS AUXILIARY DACs (DAC1, DAC2, DAC3) Resolution (Note 6) Integral Nonlinearity INL Differential Nonlinearity DNL Gain Error GE 12 Zero-Code Error Output-Voltage Low VOL RL > 200kΩ Output-Voltage High VOH RL > 200kΩ Bits 0.1 2.56 V V Ω DC Output Impedance DC output at midscale 4 Settling Time From 1/4 FS to 3/4 FS 1 µs Glitch Impulse From 0 to FS transition 24 nV•s Rx ADC-Tx DAC TIMING CHARACTERISTICS CLK Rise to Channel-I Output Data Valid tDOI Figure 3 (Note 6) 6.9 10 ns CLK Fall to Channel-Q Output Data Valid tDOQ Figure 3 (Note 6) 9.3 13 ns CLK Rise/Fall to DR Rise/Fall Time tDR Figure 3 (Note 6) 8.5 12 ns I-DAC DATA to CLK Fall Setup Time tDSI Figure 5 (Note 6) 6 10 _______________________________________________________________________________________ ns 7.5Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q-DAC DATA to CLK Rise Setup Time tDSQ Figure 5 (Note 6) 10 ns CLK Fall to I-DAC Data Hold Time tDHI Figure 5 (Note 6) 0 ns CLK Rise to Q-DAC Data Hold Time tDHQ Figure 5 (Note 6) 0 ns CLK Duty Cycle CLK Duty-Cycle Variation Digital Output Rise/Fall Time 20% to 80% 50 % ±15 % 2.3 ns SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6) Falling Edge of CS to Rising Edge of First SCLK Time tCSS 10 DIN to SCLK Setup Time tDS 10 ns DIN to SCLK Hold Time tDH 0 ns SCLK Pulse-Width High tCH 25 ns SCLK Pulse-Width Low tCL 25 ns SCLK Period tCP 50 ns tCS 10 ns tCSW 80 ns SCLK to CS Setup Time CS High Pulse Width ns MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7) Shutdown Wake-Up Time Idle Wake-Up Time (With CLK) Standby Wake-Up Time tWAKE,SD tWAKE,ST0 tWAKE,ST1 From shutdown to Rx mode, ADC settles to within 1dB SINAD 75 From shutdown to Tx mode, DAC settles to within 10 LSB error 25 From idle to Rx mode with CLK present during idle, ADC settles to within 1dB SINAD 7.3 µs µs From idle to Tx mode with CLK present during idle, DAC settles to 10 LSB error 5 From standby to Rx mode, ADC settles to within 1dB SINAD 7.3 From standby to Tx mode, DAC settles to 10 LSB error 25 µs Enable Time from Tx to Rx, (Ext2Tx to Ext2-Rx, Ext4-Tx to Ext4-Rx, and SPI4-Tx to SPI3-Rx Modes) tENABLE, RX ADC settles to within 1dB SINAD 500 ns Enable Time from Rx to Tx, (Ext1Rx to Ext1-Tx, Ext4-Rx to Ext4-Tx, and SPI3-Rx to SPI4-Tx Modes) tENABLE, TX DAC settles to within 10 LSB error 1 µs _______________________________________________________________________________________ 7 MAX19700 ELECTRICAL CHARACTERISTICS (continued) MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1) PARAMETER SYMBOL CONDITIONS Enable Time from Tx to Rx, (Ext1Tx to Ext1-Rx, Ext3-Tx to Ext3-Rx, and SPI2-Tx to SPI1-Rx Modes) tENABLE, RX ADC settles to within 1dB SINAD Enable Time from Rx to Tx, (Ext2Rx to Ext2-Tx, Ext3-Rx to Ext3-Tx, and SPI1-Rx to SPI2-Tx Modes) tENABLE,TX MIN DAC settles to within 10 LSB error TYP MAX UNITS 7.3 µs 5 µs INTERNAL REFERENCE (REFIN = VDD; VREFP, VREFN, VCOM levels are generated internally) Positive Reference VREFP - VCOM 0.256 V Negative Reference VREFN - VCOM -0.256 V VCOM VDD / 2 VDD / 2 VDD / 2 - 0.15 + 0.15 V Maximum REFP/REFN/COM Source Current ISOURCE 2 mA Maximum REFP/REFN/COM Sink Current ISINK 2 mA Differential Reference Output VREF Common-Mode Output Voltage Differential Reference Temperature Coefficient VREFP - VREFN +0.490 REFTC +0.512 +0.534 ±10 V ppm/°C BUFFERED EXTERNAL REFERENCE (external REFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally) Reference Input Voltage VREFIN VREFP - VREFN 1.024 V Differential Reference Output VDIFF 0.512 V Common-Mode Output Voltage VCOM VDD / 2 V Maximum REFP/REFN/COM Source Current ISOURCE 2 mA Maximum REFP/REFN/COM Sink Current ISINK 2 mA REFIN Input Current -0.7 µA REFIN Input Resistance 500 kΩ DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0–D9, T/R, SHDN) Input High Threshold VINH D0–D9, CLK, SCLK, DIN, CS, T/R, SHDN Input Low Threshold VINL D0–D9, CLK, SCLK, DIN, CS, T/R, SHDN Input Leakage DIIN D0–D9, CLK, SCLK, DIN, CS, T/R, SHDN = OGND or OVDD Input Capacitance DCIN 8 0.7 x OVDD V -1 5 _______________________________________________________________________________________ 0.3 x OVDD V +1 µA pF 7.5Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF. Typical values are at TA = +25°C, unless otherwise noted. CL < 5pF on all aux-DAC outputs.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.2 x OVDD V DIGITAL OUTPUTS (D0–D9, DR) Output-Voltage Low VOL ISINK = 200µA Output-Voltage High VOH ISOURCE = 200µA Tri-State Leakage Current ILEAK Tri-State Output Capacitance COUT 0.8 x OVDD V -1 +1 µA 5 pF Note 1: Specifications from TA = +25°C to +85°C are guaranteed by production tests. Specifications from TA = +25°C to -40°C are guaranteed by design and characterization. Note 2: The minimum clock frequency for the MAX19700 is 2MHz. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tone. Note 5: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. Note 6: Guaranteed by design and characterization. Typical Operating Characteristics (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) -30 -40 -50 -60 HD3 HD2 -70 fCLK = 7.5MHz fQA = 2MHz AQA = -0.5dBFS 8192-POINT DATA RECORD -20 -30 QA -40 -50 -60 HD3 HD2 -70 0 -20 -30 -40 -50 -70 -80 -80 -90 -90 -100 -100 -100 1.0 1.5 2.0 2.5 FREQUENCY (MHz) 3.0 3.5 f2 f1 -60 -90 0.5 fCLK = 7.5MHz f1 = 2.0MHz f2 = 2.1MHz AIA = -7dBFS PER TONE 8192-POINT DATA RECORD -10 -80 0 MAX19700 toc03 IA AMPLITUDE (dBFS) AMPLITUDE (dBFS) -20 0 -10 AMPLITUDE (dBFS) fCLK = 7.5MHz fIA = 2MHz AIA = -0.5dBFS 8192-POINT DATA RECORD MAX19700 toc01 0 -10 Rx ADC CHANNEL-IA TWO-TONE FFT PLOT Rx ADC CHANNEL-QA FFT PLOT MAX19700 toc02 Rx ADC CHANNEL-IA FFT PLOT 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (MHz) 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (MHz) _______________________________________________________________________________________ 9 MAX19700 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) -50 55 53 f2 f1 -60 57 -70 -80 QA 53 SINAD (dB) -40 SNR (dB) AMPLITUDE (dBFS) -30 QA 55 Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT FREQUENCY MAX19700 toc05 fCLK = 7.5MHz f1 = 2.0MHz f2 = 2.1MHz AQA = -7dBFS PER TONE 8192-POINT DATA RECORD -20 57 MAX19700 toc04 0 -10 Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY MAX19700 toc06 Rx ADC CHANNEL-QA TWO-TONE FFT PLOT IA 51 IA 51 49 49 47 47 -90 45 -100 0 0.5 1.0 1.5 2.0 2.5 3.0 10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT AMPLITUDE IA 77 fIN = 1.9980913MHz 50 IA -74 40 SNR (dB) SFDR (dBc) 75 -72 MAX19700 toc09 60 MAX19700 toc08 MAX19700 toc07 79 -70 73 QA 71 QA 30 20 -76 69 -78 67 -80 10 0 65 0 10 20 30 40 50 60 70 80 90 100 0 -23 10 20 30 40 50 60 70 80 90 100 -18 -13 -8 -3 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT AMPLITUDE (dBFS) Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT AMPLITUDE Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT AMPLITUDE Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE IA fIN = 1.9980913MHz 75 70 SFDR (dBc) 40 30 QA 0 -23 -18 -13 -8 -3 ANALOG INPUT AMPLITUDE (dBFS) QA 54.4 65 60 QA 54.2 54.0 53.8 53.6 50 10 54.6 IA 55 20 IA 54.8 SNR (dB) 50 55.0 MAX19700 toc11 80 MAX19700 toc10 fIN = 1.9980913MHz MAX19700 toc12 ANALOG INPUT FREQUENCY (MHz) 60 10 0 FREQUENCY (MHz) -68 THD (dB) 45 0 3.5 -66 SINAD (dB) MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End 53.4 45 53.2 40 53.0 -23 -18 -13 -8 -3 ANALOG INPUT AMPLITUDE (dBFS) fIN = 1.9980913MHz 2 3 4 5 6 SAMPLING RATE (MHz) ______________________________________________________________________________________ 7 7.5Msps, Ultra-Low-Power Analog Front-End 54.6 IA 56.0 53.8 SNR (dB) 54.0 75 QA 70 54.5 QA 53.5 65 53.4 53.2 2 3 53.0 52.5 fIN = 1.9980913MHz 53.0 60 4 5 6 52.0 2 7 3 4 5 6 7 35 40 45 50 55 SAMPLING RATE (MHz) CLOCK DUTY CYCLE (%) Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. CLOCK DUTY CYCLE Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE Rx ADC OFFSET ERROR vs. TEMPERATURE 77 IA 54.5 54.0 QA 53.5 76 75 IA 74 73 53.0 72 52.5 71 52.0 1.0 45 50 55 60 65 40 45 50 55 60 65 -40 0 20 40 60 80 CLOCK DUTY CYCLE (%) TEMPERATURE (°C) Rx ADC GAIN ERROR vs. TEMPERATURE Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY 77 MAX19700 toc19 0.9 0.8 76 fOUT = fCLK / 10 75 78 77 76 0.6 0.5 0.4 73 72 71 0.3 70 0.2 69 0.1 68 0 SFDR (dBc) 74 SFDR (dBc) 0.7 0 20 40 TEMPERATURE (°C) 60 80 75 74 73 72 71 70 67 -20 -20 CLOCK DUTY CYCLE (%) 1.0 -40 0.4 0 35 MAX19700 toc20 40 0.6 0.2 70 35 0.8 MAX19700 toc21 55.0 SFDR (dBc) 55.5 QA MAX19700 toc18 78 OFFSET ERROR (%FS) 56.0 fIN = 1.9980913MHz 79 1.2 MAX19700 toc17 80 MAX19700 toc16 fIN = 1.9980913MHz 56.5 65 60 SAMPLING RATE (MHz) 57.0 SINAD (dB) IA 55.0 54.0 53.6 GAIN ERROR (%FS) fIN = 1.9980913MHz 56.5 55.5 IA 54.2 80 SFDR (dBc) SINAD (dB) 54.4 fIN = 1.9980913MHz MAX19700 toc15 QA 57.0 MAX19700 toc14 54.8 85 MAX19700 toc13 55.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 SAMPLING RATE (MHz) 200 300 400 500 600 700 800 OUTPUT FREQUENCY (kHz) ______________________________________________________________________________________ 11 MAX19700 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) Rx ADC SPURIOUS-FREE DYNAMIC RANGE Rx ADC SIGNAL-TO-NOISE AND DISTORTION Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE RATIO vs. SAMPLING RATE vs. CLOCK DUTY CYCLE Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) -20 AMPLITUDE (dBFS) 65 60 55 50 45 -30 -40 -50 -60 -30 -40 -50 -60 35 -80 -80 30 -90 -25 -20 -15 -10 -5 1.2 2.2 3.2 0.5 1.5 2.5 3.5 4.5 OUTPUT AMPLITUDE (dBFS) FREQUENCY (MHz) FREQUENCY (MHz) Tx PATH CHANNEL-QD SPECTRAL PLOT Tx PATH CHANNEL-ID TWO-TONE SPECTRAL PLOT Tx PATH CHANNEL-QD TWO-TONE SPECTRAL PLOT -50 -60 f2 -20 -70 -30 -40 -50 -60 -70 -40 -50 -60 -70 -80 -90 -90 -90 -100 -100 2.2 3.2 0.2 1.2 2.2 FREQUENCY (MHz) SUPPLY CURRENT vs. SAMPLING RATE Rx ADC INTEGRAL NONLINEARITY 0.8 0.6 12.2 0.2 0 -0.2 -0.6 11.2 3.2 -20 -0.4 11.4 0 AMPLITUDE (dB) 11.6 INL (LSB) IVDD 2.2 TRANSMIT FILTER FREQUENCY RESPONSE 0.4 12.0 1.2 FREQUENCY (MHz) MAX19700 toc29 12.4 1.0 MAX19700 toc28 Ext4-Rx MODE 0.2 3.2 FREQUENCY (MHz) 12.6 f2 -30 -80 1.2 f1 -20 -80 0.2 f1 = 600kHz, f2 = 800kHz -10 MAX19700toc30 -40 f1 0 AMPLITUDE (dBFS) -30 f1 = 600kHz, f2 = 800kHz -10 AMPLITUDE (dBFS) -20 0 MAX19700 toc26 fQD = 620kHz MAX19700 toc25 0 -10 11.8 IMAGE REJECTION -90 0.2 0 fID = 800kHz, fCLK = 5.12Msps -20 -70 -30 AMPLITUDE (dBFS) 0 -10 -70 40 -40 -60 -80 -0.8 11.0 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 SAMPLING RATE (MHz) 12 fID = 620kHz MAX19700 toc24 70 SFDR (dBc) 0 -10 AMPLITUDE (dBFS) fOUT = 620kHz MAX19700 toc23 75 MAX19700 toc22 80 Tx PATH CHANNEL-ID SPECTRAL PLOT WITH IMAGE REJECTION Tx PATH CHANNEL-ID SPECTRAL PLOT MAX19700 toc27 Tx PATH SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT AMPLITUDE SUPPLY CURRENT (mA) MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End -100 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE 0.1 1 FREQUENCY (MHz) ______________________________________________________________________________________ 10 7.5Msps, Ultra-Low-Power Analog Front-End 0.8 0.6 0.2 0.515 0.4 0.2 0 -0.2 VREFP - VREFN (V) 0.1 DNL (LSB) INL (LSB) 0.520 MAX19700 toc32 0.3 MAX19700 toc31 1.0 REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE Tx PATH DIFFERENTIAL NONLINEARITY MAX19700 toc33 Tx PATH INTEGRAL NONLINEARITY 0 -0.1 -0.4 0.510 0.505 -0.6 -0.2 -0.8 -1.0 -0.3 128 256 384 512 640 768 896 1024 0.500 0 DIGITAL OUTPUT CODE -40 DIGITAL OUTPUT CODE TRANSMIT FILTER PASSBAND RIPPLE 1.5 INL (LSB) -0.02 -0.04 -0.06 1.0 0.4 0.5 0.2 0 -0.2 -0.10 -0.4 -0.12 -1.5 -0.6 -2.0 0 0.3 0.6 0.9 FREQUENCY (MHz) 1.2 60 80 0 -1.0 -0.14 40 0.6 -0.5 -0.08 20 AUX-DAC DIFFERENTIAL NONLINEARITY DNL (LSB) 0 0 0.8 MAX19700 toc35 0.02 -20 TEMPERATURE (°C) AUX-DAC INTEGRAL NONLINEARITY 2.0 MAX19700 toc34 0.04 AMPLITUDE (dB) 128 256 384 512 640 768 896 1024 MAX19700 toc36 0 -0.8 0 1024 2048 3072 DIGITAL INPUT CODE 4096 0 1024 2048 3072 4096 DIGITAL INPUT CODE ______________________________________________________________________________________ 13 MAX19700 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 7.5MHz 50% duty cycle, ADC input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End Pin Description PIN NAME 1 REFP FUNCTION 2, 8, 11, 31, 33, 39 43 VDD Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 3 IAP Channel IA Positive Analog Input. For single-ended operation, connect signal source to IAP. 4 IAN Channel IA Negative Analog Input. For single-ended operation, connect IAN to COM. 5, 7, 12, 32, 42 GND Analog Ground. Connect all GND pins to ground plane. 6 CLK Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs. 9 QAN Channel QA Negative Analog Input. For single-ended operation, connect QAN to COM. 10 QAP Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. Channel QA Positive Analog Input. For single-ended operation, connect signal source to QAP. 13–18, 21–24 D0–D9 Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most significant bit (MSB) and D0 is the least significant bit (LSB). 19 OGND Output-Driver Ground 20 OVDD Output-Driver Power Supply. Supply range from +1.8V to VDD to accommodate most logic levels. Bypass OVDD to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 25 SHDN Active-Low Shutdown Input. Apply logic-low to place the MAX19700 in shutdown. 26 DR Data-Ready Indicator. This digital output indicates channel I data (DR = 1) or channel Q data (DR = 0) is present on the output. 27 T/R Transmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A logic-high input sets the device in transmit mode. 28 DIN 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK. 29 SCLK 30 CS 3-Wire Serial-Interface Clock Input 3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface. 34, 35 N.C. 36 DAC3 No Connection Analog Output for Auxiliary DAC3 37 DAC2 Analog Output for Auxiliary DAC2 Analog Output for Auxiliary DAC1 (AFC DAC, VOUT = 1.1V During Power-Up) 38 DAC1 40, 41 IDN, IDP DAC Channel-ID Differential Voltage Output 44, 45 QDN, QDP DAC Channel-QD Differential Voltage Output 46 REFIN Reference Input. Connect to VDD for internal reference. 47 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor. 48 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF capacitor. — EP Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane. Detailed Description The MAX19700 integrates a dual 10-bit Rx ADC and a dual 10-bit Tx DAC with TD-SCDMA baseband filters while providing ultra-low power and high dynamic performance at a 7.5Msps conversion rate. The Rx ADC analog input amplifiers are fully differential and accept 1VP-P full-scale signals. The Tx DAC analog outputs are fully differential with ±410mV full-scale output, selectable common-mode range and offset adjust. 14 The MAX19700 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPI™ and MICROWIRE™ compatible. The MAX19700 serial interface selects shutdown, idle, standby, transmit (Tx), and receive (Rx) modes. SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ______________________________________________________________________________________ 7.5Msps, Ultra-Low-Power Analog Front-End MAX19700 INTERNAL BIAS COM S5a S2a C1a S3a S4a IAP OUT C2a S4c S1 OUT IAN S4b C1b C2b S3b S5b S2b INTERNAL BIAS COM INTERNAL BIAS COM HOLD CLK HOLD TRACK TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a QAP OUT C2a S4c S1 MAX19700 OUT QAN S4b C1b C2b S3b S2b INTERNAL BIAS S5b COM Figure 1. MAX19700 Rx ADC Internal T/H Circuits To operate the device in TDD applications, configure the MAX19700 for Tx or Rx mode with the 3-wire serial interface. The Rx ADC and Tx DAC share a common digital bus to reduce the digital I/O to a single 10-bit parallel multiplexed bus. Dual 10-Bit Rx ADC The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA. The ADC full-scale analog input range is ±VREF with a VDD / 2 ±0.2V common-mode input range. VREF is the difference between VREFP and VREFN. See the Reference Configurations section for details. Input Track-and-Hold (T/H) Circuits Figure 1 displays a simplified diagram of the Rx ADC input track-and-hold (T/H) circuitry. Both ADC inputs (IAP, QAP, IAN, and QAN) can be driven either differentially or single-ended. Match the impedance of IAP ______________________________________________________________________________________ 15 Table 1. Output Codes vs. Input Voltage DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT (LSB) OFFSET BINARY (D0–D9) VREF x 512/512 511 (+Full Scale – 1 LSB) 11 1111 1111 1023 VREF x 511/512 510 (+Full Scale – 2 LSB) 11 1111 1110 1022 VREF x 1/512 +1 10 0000 0001 513 VREF x 0/512 0 (Bipolar Zero) 10 0000 0000 512 -VREF x 1/512 -1 01 1111 1111 511 -VREF x 511/512 -511 (-Full Scale +1 LSB) 00 0000 0001 1 -VREF x 512/512 -512 (-Full Scale) 00 0000 0000 0 and IAN, as well as QAP and QAN, and set the input signal common-mode voltage within the ADC range of VDD / 2 (±200mV) for optimum performance. ADC System Timing Requirements Figure 3 shows the relationship between the clock, analog inputs, DR indicator, and the resulting output data. Channel I (CHI) and channel Q (CHQ) are sampled on the rising edge of the clock signal (CLK) and the resulting data is multiplexed at the D0–D9 outputs. CHI data is updated on the rising edge and CHQ data is updated on the falling edge of the CLK. The DR indicator follows CLK with a typical delay time of 8.5ns and remains high when CHI data is updated and low when CHQ data is updated. Including the delay through the output 1 LSB = 2 x VREF 1024 VREF VREF = VREFP - VREFN VREF VREF 11 1111 1111 11 1111 1110 11 1111 1101 10 0000 0001 10 0000 0000 01 1111 1111 (COM) VREF OFFSET BINARY OUTPUT CODE (LSB) MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 -1 0+ 1 (COM) -512 -511 -510 -509 INPUT VOLTAGE (LSB) Figure 2. ADC Transfer Function 16 +509 +510 +511 +512 OUTPUT DECIMAL CODE latch, the total clock-cycle latency is 5 clock cycles for CHI and 5.5 clock cycles for CHQ. Digital Input/Output Data (D0–D9) D0–D9 are the Rx ADC digital logic outputs when the MAX19700 is in receive mode. This bus is shared with the Tx DAC digital logic inputs and operates in halfduplex mode. D0–D9 are the Tx DAC digital logic inputs when the MAX19700 is in transmit mode. The logic level is set by OVDD from 1.8V to VDD. The digital output coding is offset binary (Table 1). Keep the capacitive load on the digital outputs D0–D9 as low as possible (55dB image rejection at fIMAGE = 4.32MHz, fOUT = 800kHz, and fCLK = 5.12MHz. See Figure 4 for an illustration of the filter frequency response. ______________________________________________________________________________________ 7.5Msps, Ultra-Low-Power Analog Front-End MAX19700 5.5 CLOCK-CYCLE LATENCY (CHQ) 5 CLOCK-CYCLE LATENCY (CHI) CHI CHQ tCLK tCL tCH CLK tDR DR CHQ CHI tDOQ CHQ CHI CHQ CHI CHQ CHI CHQ CHI CHQ CHI CHQ D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q tDOI D0–D9 D0Q D1I D1Q Figure 3. Rx ADC System Timing Diagram AMPLITUDE DAC sin(x)/x RESPONSE OCCUPIED CHANNEL TD-SCDMA FILTER RESPONSE 0dB -3dB Tx PATH: SFDR = 76.5dBc THD = -74.8dBc SINAD = 57.1dB -15dB -49.3dB -55dB (min) -57.1dB FREQ (MHz) 0.8 CHANNEL EDGE 1.27 fC 4.32 IMAGE 5.12 fCLK NOT TO SCALE Figure 4. TD-SCDMA Filter Frequency Response Buffer amplifiers follow the TD-SCDMA filters. The amplifier outputs are biased at an adjustable commonmode DC level and designed to drive a differential input stage with input impedance ≥70kΩ. This simplifies the analog interface between RF quadrature upconverters and the MAX19700. Many RF upconverters require a 0.9V to 1.5V common-mode bias. The SPI-controlled DC common-mode bias eliminates discrete level-setting resistors and code-generated level shifting while preserving the full dynamic range of each Tx DAC. Table 2 shows the Tx path output voltage vs. input codes. Table 10 shows the selection of DC common-mode levels. The buffer amplifiers also feature a programmable fullscale output level of ±410mV or ±500mV and independent DC offset correction of each I/Q channel. Both features are configured through the SPI interface. The DC offset correction is used to optimize sideband and carrier suppression in the Tx signal path (see Tables 8 and 9). ______________________________________________________________________________________ 17 MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End Table 2. Tx Path Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN; VFS = 410mV for 820mVP-P Full Scale and VFS = 500mV for 1VP-P Full Scale) DIFFERENTIAL OUTPUT VOLTAGE (V) OFFSET BINARY (D0–D9) INPUT DECIMAL CODE 1023 × (VFS ) VREFDAC 1024 1023 11 1111 1111 1023 1021 × (VFS ) VREFDAC 1024 1023 11 1111 1110 1022 3 × (VFS ) VREFDAC 1024 1023 10 0000 0001 513 1 × (VFS ) VREFDAC 1024 1023 10 0000 0000 512 1 × (VFS ) −VREFDAC 1024 1023 01 1111 1111 511 1021 × (VFS ) −VREFDAC 1024 1023 00 0000 0001 1 1023 × (VFS ) −VREFDAC 1024 1023 00 0000 0000 0 CLK tDHQ tDSQ D0–D9 Q: N - 2 I: N - 1 Q: N - 1 tDSI Q: N I: N I: N + 1 tDHI ID N-2 N-1 N QD N-2 N-1 N Figure 5. Tx DAC System Timing Diagram Tx DAC Timing Figure 5 shows the relationship between the clock, input data, and analog outputs. Data for the I-channel (ID) is latched on the falling edge of the clock signal, and Qchannel (QD) data is latched on the rising edge of the clock signal. Both I and Q outputs are simultaneously updated on the next rising edge of the clock signal. 18 3-Wire Serial Interface and Operation Modes The 3-wire serial interface controls the MAX19700 operation modes as well as the three 12-bit aux-DACs. Upon power-up, program the MAX19700 to operate in the desired mode. Use the 3-wire serial interface to program the device for shutdown, idle, standby, Rx, Tx, or aux-DAC modes. A 16-bit data register sets the mode control. The 16-bit word is comprised of A3–A0 control bits and D11–D0 data bits. Tables 4, 5, and 6 show the MAX19700 operating modes and SPI commands. The serial interface remains active in all modes. ______________________________________________________________________________________ 7.5Msps, Ultra-Low-Power Analog Front-End Modes Aux-DAC1, Aux-DAC2, and Aux-DAC3 select the aux-DAC channels named DAC1, DAC2, and DAC3 and hold the data inputs for each DAC. Bits _D11–_D0 are the data inputs for each aux-DAC and can be programmed through SPI. The MAX19700 also includes two 6-bit registers that can be programmed to correct the offsets for the Tx-path I and Q channels independently (see Table 9). Use the COMSEL mode to select the output common-mode voltage with bits CM1 and CM0 (see Table 10). Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX19700 and placing the Rx ADC digital outputs in tri-state mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital outputs. The Tx DAC previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 75µs to enter Rx mode and 25µs to enter Tx mode. In idle mode, the reference and clock distribution circuits are powered, but all other functions are off. The Rx ADC outputs are forced to tri-state. The wake-up time is 7.3µs to enter Rx mode and 5µs to enter Tx mode. When the Rx ADC outputs transition from tristate to active, the last converted word is placed on the digital outputs. In standby mode, the reference is powered, but the rest of the device functions are off. The wake-up time from standby mode is 7.3µs to enter Rx mode and 25µs to enter Tx mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital outputs. FAST and SLOW Rx and Tx Modes In addition to the external Tx-Rx control, the MAX19700 also features SLOW and FAST modes for switching between Rx and Tx operation. In FAST Tx mode, the Rx ADC core is powered on but the ADC core digital outputs are tri-stated on the D0–D9 bus; likewise, in FAST Rx mode the transmit path (DAC core and Tx filter) is powered on but the DAC core digital inputs are tri-stated on the D0–D9 bus. The switching time between Tx to Rx or Rx to Tx is FAST because the converters are on and do not have to recover from a power-down state. In FAST mode, the switching time between Rx to Tx and Tx to Rx is 1µs. However, power consumption is higher in this mode because both the Tx and Rx cores are always on. To prevent bus contention in these states, the Rx ADC output buffers are tri-stated during Tx and the Tx DAC input bus is tri-stated during Rx. In SLOW mode, the Rx ADC core is off during Tx; likewise the Tx DAC and filters are turned off during Rx to yield lower power consumption in these modes. For example, the power in SLOW Tx mode is 31.2mW. The power consumption during Rx is 21mW compared to power consumption in FAST mode of 38.4mW. However, the recovery time between states is increased. The switching time in SLOW mode between Rx to Tx is 5µs and Tx to Rx is 7.3µs. R Switching Control vs. External T/R Serial-Interface Control Bit E3 in the ENABLE-16 register determines whether the device Tx-Rx mode is controlled externally through the T/R input (E3 = low) or through the SPI command (E3 = high). By default, the MAX19700 is in the external Tx-Rx control mode. In the external control mode, use the T/R input (pin 27) to switch between Rx and Tx modes. Using the T/R pin provides faster switching between Rx and Tx modes. To override the external TxRx control, program the MAX19700 through the serial interface. During SHDN, IDLE, or STBY modes, the T/R input is overridden. To restore external Tx-Rx control, program bit E3 low and exit the SHDN, IDLE, or STBY modes through the serial interface. ______________________________________________________________________________________ 19 MAX19700 SPI Register Description The operating modes can be selected by programming the control bits, A3–A0, in the register as shown in Table 3. Modifying A3–A0 bits will select from ENABLE-16, Aux-DAC1, Aux-DAC2, Aux-DAC3, IOFFSET, QOFFSET, and COMSEL modes. ENABLE-16 is the default operating mode. This mode allows for shutdown, idle, and standby states as well as switching between FAST, SLOW, Rx, and Tx modes. Table 4 shows the MAX19700 power-management modes. Table 5 shows the T/R pin-controlled external Tx-Rx switching modes. Table 6 shows the SPI-controlled Tx-Rx switching modes. In ENABLE-16 mode, the aux-DACs have independent control bits E6, E5, and E4, and the Tx-path full-scale output can be set with bit E7. Table 7 shows the auxiliary DAC enable codes and Table 8 shows the fullscale output selection. Bits E11 and E10 are reserved and need to be programmed to logic-low. Bits E9 and E8 are not used. MAX19700 7.5Msps, Ultra-Low-Power Analog Front-End SPI Timing The serial digital interface is a standard 3-wire connection compatible with SPI/QSPI™/MICROWIRE/DSP interfaces. Set CS low to enable the serial data loading at DIN. Following a CS high-to-low transition, data is shifted synchronously, most significant bit first, on the rising edge of the serial clock (SCLK). After 16 bits are loaded into the serial input register, data is transferred to the latch when CS transitions high. CS must transition high for a minimum of 80ns before the next write sequence. The SCLK can idle either high or low between transitions. Figure 6 shows the detailed timing diagram of the 3-wire serial interface. Mode-Recovery Timing Figure 7 shows the mode-recovery timing diagram. tWAKE is the wakeup time when exiting shutdown, idle, or standby mode and entering Rx or Tx mode. tENABLE is the recovery time when switching between either Rx or Tx mode. tWAKE or tENABLE is the time for the Rx ADC to settle within 1dB of specified SINAD performance and Tx DAC settling to 10 LSB error. tWAKE and tENABLE times are measured after either the 16-bit serial command is latched into the MAX19700 by a CS transition high (SPI controlled) or a T/R logic transition (external Tx-Rx control). In FAST mode, the recovery time is 1µs to switch between Tx or Rx modes. QSPI is a trademark of Motorola, Inc. Table 3. MAX19700 Mode Control D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ENABLE-16 E11 = 0 Reserved E10 = 0 Reserved — — E7 E6 E5 E4 E3 E2 E1 E0 0 0 0 0 Aux-DAC1 1D11 1D10 1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0 0 0 0 1 Aux-DAC2 2D11 2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 0 0 1 0 Aux-DAC3 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0 0 0 1 1 IOFFSET — — — — — — IO5 IO4 IO3 IO2 IO1 IO0 0 1 0 0 QOFFSET — — — — — — QO5 QO4 QO3 QO2 QO1 QO0 0 1 0 1 COMSEL — — — — — — 0 1 1 0 REGISTER NAME — — — — CM1 CM0 Table 4. Power-Management Modes ADDRESS DATA BITS A3 A2 A1 A0 E3 E2 E1 E0 X000 0000 X001 X010 T/R MODE PIN 27 X X X SHDN IDLE STBY FUNCTION (POWER MANAGEMENT) DESCRIPTION COMMENT Rx ADC = OFF Tx DAC = OFF Aux-DAC = OFF REF = OFF Device is in complete shutdown Overrides T/R pin IDLE Rx ADC = OFF Tx DAC = OFF Aux-DAC = Last State CLK = ON REF = ON Fast turn-on time Moderate idle power Overrides T/R pin STANDBY Rx ADC = OFF Tx DAC = OFF Aux-DAC = Last State CLK = OFF REF = ON Slow turn-on time Low standby power Overrides T/R pin SHUTDOWN X = Don't care. 20 ______________________________________________________________________________________ 7.5Msps, Ultra-Low-Power Analog Front-End ADDRESS DATA BITS A3 A2 A1 A0 E3 E2 E1 E0 T/R STATE PIN 27 FUNCTION Rx TO Tx-Tx TO Rx SWITCHING SPEED DESCRIPTION COMMENT Rx Mode 0 Ext1-Rx 0011 FAST-SLOW 1 Ext1-Tx 0 Ext2-Rx (Default) 0100 Rx ADC = ON Tx DAC = ON Rx Bus = Enable Tx Mode Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Rx Mode SLOW-FAST Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Tx Mode 1 Ext2-Tx Rx ADC = ON Tx DAC = ON Tx Bus = Enable Rx Mode 0 Ext3-Rx Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Tx Mode 0000 0101 SLOW-SLOW 1 Ext3-Tx Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Rx Mode 0 Ext4-Rx Rx ADC = ON Tx DAC = ON Rx Bus = Enable Tx Mode FAST-FAST 0110 1 Ext4-Tx System Clock Input (CLK) Both the Rx ADC and Tx DAC share the CLK input. The CLK input accepts a CMOS-compatible signal level set by OVDD from 1.8V to VDD. Since the interstage conversion of the device depends on the repeatability of Rx ADC = ON Tx DAC = ON Tx Bus = Enable Moderate Power Fast Rx to Tx when T/R transitions 0 to 1 Low Power Slow Tx to Rx when T/R transitions 1 to 0 Low Power Slow Rx to Tx when T/R transitions 0 to 1 Moderate Power Fast Tx to Rx when T/R transitions 1 to 0 Low Power Slow Rx to Tx when T/R transitions 0 to 1 Low Power Slow Tx to Rx when T/R transitions 1 to 0 Moderate Power Fast Rx to Tx when T/R transitions 0 to 1 Moderate Power Fast Tx to Rx when T/R transitions 1 to 0 the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (