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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
General Description
The MAX19777 is a 12-bit, compact, high-speed,
lowpower, successive approximation analog-to-digital
converter (ADC). This high-performance ADC includes a
high dynamic range sample-and-hold, as well as a highspeed serial interface.
The MAX19777 features dual, single-ended analog inputs
connected to the ADC core using a 2:1 MUX.
This ADC operates from a 2.2V to 3.3V supply and
consumes only 6.2mW at 3Msps. The device includes
a full power-down mode and fast wake up for optimal
power management and a high-speed 3-wire serial
interface. The 3-wire serial interface directly connects to
SPI, QSPI™, and MICROWIRE® devices without external
logic.
Excellent dynamic performance, low voltage, low power,
ease-of-use, and small package size make this converter
ideal for portable, battery-powered data-acquisition
applications, as well as for other applications that demand
low power consumption and minimal space.
This ADC is available in an 8-pin wafer-level package
(WLP). This device operates over the -40°C to +125°C
temperature range.
Benefits and Features
●● 3Msps Conversion Rate, No Pipeline Delay
●● 12-Bit Resolution
●● 2-Channel, Single-Ended Analog Inputs
●● Low-Noise 72.5dB SNR
●● 2.2V to 3.3V Supply Voltage
●● Low Power
• 6.2mW at 3Msps
• Very Low Power Consumption at 2.5μA/ksps
●● 2μA Power-Down Current
●● SPI/QSPI/MICROWIRE-Compatible Serial Interface
●● 8-Pin, 0.857mm x 1.431mm WLP Package
●● Wide -40°C to +125°C Operation
Applications
●●
●●
●●
●●
●●
●●
Data Acquisition
Portable Data Logging
Medical Instrumentation
Battery-Operated Systems
Communication Systems
Automotive Systems
Ordering Information continued at end of data sheet.
Typical Operating Circuit
VDD
+3V
ANALOG
INPUTS
AIN1
MAX19777
SCLK
GND
CPU
DOUT
CS
CHSEL
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
19-100204; Rev 0; 11/17
SCK
AIN2
MISO
SS
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Absolute Maximum Ratings
VDD to GND..........................................................-0.3V to +3.6V
AIN1, AIN2, CS, SCLK, CHSEL, DOUT TO GND
..........................-0.3V to the lower of (VDD + 0.3V) and +3.6V
Input/Output Current (all pins).............................................50mA
Continuous Power Dissipation (TA = +70°C)
8-pin WLP (derate 11.6mW/°C above +70°C)..............872mW
Operating Temperature Range.......................... -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = 2.2V to 3.3V. fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
Integral Nonlinearity
12
INL
2Msps, VDD MAX
-1.5
+1.5
2Msps, VDD MIN
-2
+2
3Msps
Differential Nonlinearity
DNL
Offset Error
OE
Gain Error
GE
Total Unadjusted Error
TUE
Bits
LSB
±3
2Msps, VDD MAX
-1
+1.2
1Msps, VDD MAX
-0.95
+1.2
VDD MAX
-4
+10
LSB
VDD MAX
-7
+7
LSB
LSB
4
LSB
Channel-to-Channel Offset
Matching
±0.4
LSB
Channel-to-Channel Gain
Matching
±0.05
LSB
DYNAMIC PERFORMANCE (fAIN_ = 10kHz)
Signal-to-Noise and Distortion
SINAD
2Msps
70
3Msps
2Msps
72
69
71
72.5
dB
Signal-to-Noise Ratio
SNR
Total Harmonic Distortion
THD
-83
dB
SFDR
83
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
69
dB
f1 = 1.0003MHz, f2 = 0.99955MHz
-84
dB
Full-Power Bandwidth
-3dB point
40
MHz
Full-Linear Bandwidth
SINAD > 68dB
2.5
MHz
45
MHz
Small-Signal Bandwidth
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IMD
3Msps
Maxim Integrated │ 2
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Electrical Characteristics (continued)
(VDD = 2.2V to 3.3V. fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at TA = +25°C.)
Crosstalk
-90
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
dB
MAX
UNITS
3
Msps
CONVERSION RATE
Throughput
0.03
Conversion Time
260
Acquisition Time
tACQ
Aperture Delay
52
From CS falling edge
ns
4
Aperture Jitter
Serial-Clock Frequency
ns
ns
15
fCLK
0.48
VAIN_
0
ps
48
MHz
ANALOG INPUT (AIN1, AIN2)
Input Voltage Range
Input Leakage Current
Input Capacitance
IILA
CAIN_
DIGITAL INPUTS (SCLK, CS, CHSEL)
Digital Input High Voltage
VIH
Digital Input Low Voltage
VIL
Digital Input Hysteresis
Digital Input Leakage Current
Digital Input Capacitance
0.002
Track
20
Hold
4
V
±1
µA
pF
0.75 x
VDD
V
0.25 x
VDD
0.15 x
VDD
VHYST
IIL
VDD
Inputs at GND or VDD
0.001
CIN
V
V
±1
2
µA
pF
DIGITAL OUTPUT (DOUT)
Output High Voltage
VOH
ISOURCE = 200µA
Output Low Voltage
VOL
ISINK = 200µA
High-Impedance Leakage
Current
IOL
High-Impedance Output
Capacitance
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COUT
0.85 x
VDD
V
4
0.15 x
VDD
V
±1.0
µA
pF
Maxim Integrated │ 3
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Electrical Characteristics (continued)
(VDD = 2.2V to 3.3V. fSCLK = 48MHz, 50% duty cycle, 3Msps. CDOUT = 10pF, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.3
V
POWER SUPPLY
Positive Supply Voltage
VDD
Positive Supply Current
(Full-Power Mode)
IVDD
Full-Power Mode, 2Msps
2.8
3.6
mA
Positive Supply Current (FullPower Mode), No Clock
IVDD
Full-Power Mode, No Clock
2.0
2.8
mA
Leakage only
1.3
10
µA
VDD = +2.2V to +3.3V
0.7
Power-Down Current
IPD
Line Rejection
2.2
LSB/V
TIMING CHARACTERISTICS (Note 1)
Quiet Time
tQ
(Note 2)
4
ns
CS Pulse Width
t1
(Note 2)
10
ns
CS Fall to SCLK Setup
t2
(Note 2)
5
ns
t3
(Note 2)
1
ns
Data Access Time After SCLK
Falling Edge
t4
Figure 2
SCLK Pulse Width Low
t5
Percentage of clock period (Note 2)
SCLK Pulse Width High
t6
Percentage of clock period (Note 2)
t7
Figure 3
5
t8
Figure 4 (Note 2)
CS Falling Until DOUT HighImpedance Disabled
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT HighImpedance
Power-Up Time
Conversion cycle (Note 2)
23
ns
40
60
%
40
60
%
2.5
ns
14
ns
1
Cycle
Note 1: All timing specifications given are with a 10pF capacitor.
Note 2: Guaranteed by design in characterization; not production tested.
Note 3: Limits are 100% tested at TA=25°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization.
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Maxim Integrated │ 4
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
SAMPLE
SAMPLE
t6
CS
t1
t5
t2
SCLK
DOUT
16
1
2
0
HIGH
IMPEDANCE
3
D11
4
D10
5
D9
6
D8
7
D7
8
D6
9
10
D5
D4
11
D3
12
D2
13
D1
14
D0
15
0
0
(MSB)
t3
t4
16
t7
1
HIGH
IMPEDANCE
t8 tQUIET
tCONVERT
tACQ
1/fSAMPLE
Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices
t7
t4
SCLK
DOUT
SCLK
OLD DATA
VIH
NEW DATA
VIL
Figure 2. Setup Time After SCLK Falling Edge
DOUT
VIH
VIL
OLD DATA
NEW DATA
Figure 3. Hold Time After SCLK Falling Edge
t8
SCLK
DOUT
HIGH IMPEDANCE
Figure 4. SCLK Falling Edge DOUT Three-State
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Maxim Integrated │ 5
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Typical Operating Characteristics
(MAX19777AZA+, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs.
DIGITAL OUTPUT CODE toc 01
1
1
-0.5
0
-0.5
-1
2000
3000
4000
DIGITAL OUTPUT CODE)
GAIN ERROR
vs. TEMPERATURE
2000
3000
-40 -25 -10 5
4000
SNR, SINAD vs. INPUT FREQUENCY
3
2
toc 05
35000
1
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
HISTOGRAM FOR 30,000 CONVERSIONS
toc 04
4
OFFSET ERROR (LSB)
1000
DIGITAL OUTPUT CODE)
NUMBER OF OCCURRENCES
5
2
0
0
toc 06
72
SNR
30000
25000
SNR, SINAD (dB)
1000
3
1
-1
0
toc 03
4
ODDSET ERROR (LSB)
0
OFFSET ERROR
vs. TEMPERATURE
5
0.5
INL (LSB)
INL (LSB)
0.5
DIFFERENTIAL NONLINEARITY vs.
DIGITAL OUTPUT CODE toc 02
20000
15000
10000
71
70
SINAD
69
5000
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
68
2048
0
0
0
THD vs. INPUT FREQUENCY
60
80 100 120 140 160 180 200
toc 08
-75
-80
SFDR (dB)
-80
THD (dB)
40
SFDR vs. INPUT FREQUENCY
toc 07
-75
20
INPUT FREQUENCY (kHz)
OUTPUT CODE
-85
-90
-85
-90
-95
-95
-100
0
20
40
60
80 100 120 140 160 180 200
INPUT FREQUENCY (kHz)
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0
20
40
60
80 100 120 140 160 180 200
INPUT FREQUENCY (kHz)
Maxim Integrated │ 6
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Typical Operating Characteristics (continued)
(MAX19777AZA+, TA = +25°C, unless otherwise noted.)
THD vs.
INPUT RESISTANCE
-75
10kHz SINE WAVE INPUT
(16,384-POINT FFT PLOT)
toc 09
0
toc 10
fS = 2Msps
fIN = 9.886kHz
-20
-80
SNR (dB)
THD (dB)
-40
-85
-60
-90
-80
-95
-100
-100
-120
0
20
40
60
0
500
1000
1500
FREQUENCY (kHz)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
SNR vs.
SUPPLY VOLTAGE (REFERENCE)
toc 11
toc 12
73
72
VDD = 3.0V
71
70
2.3
SNR (dB)
SUPPLY CURRENT (mA)
100
INPUT RESISTANCE (Ω)
2.5
2.4
80
2.2
VDD = 2.2V
69
68
67
66
2.1
65
2
64
-40 -25 -10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
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2.2
2.4
2.6
2.8
3
3.2
SUPPLY VOLTAGE (V)
Maxim Integrated │ 7
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Bump Configuration
TOP VIEW
MAX19777
2
3
4
A
AIN1
AIN2
GND
VDD
B
SCLK
CS
CHSEL
DOUT
+
1
8 WLP
Bump Descriptions
PIN
NAME
FUNCTION
A1
AIN1
Analog Input Channel 1. Single-ended analog input with respect to GND with range of 0V to VDD.
A2
AIN2
Analog Input Channel 2. Single-ended analog input with respect to GND with range of 0V to VDD.
A3
GND
Ground. Connect GND directly the GND ground plane.
A4
VDD
Positive Supply Voltage. Bypass VDD with a 10µF || 0.1µF capacitor to GND. VDD range is 2.2V to 3.3V. For
the WLP, VDD also defines the signal range of the input signal AIN: 0V to VDD.
B1
SCLK
Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of SCLK. See
Figure 2 and Figure 3.
B2
CS
B3
CHSEL
Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for conversion.
B4
DOUT
Three-State Serial Data Output. ADC conversion results are clocked out on the falling edge of SCLK, MSB
first. See Figure 1.
Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a conversion,
and frames the serial data transfer.
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Maxim Integrated │ 8
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Functional Diagrams
VDD
CS
SCLK
CONTROL
LOGIC
SAR
MAX19777
OUTPUT
BUFFER
DOUT
CHSEL
AIN1
AIN2
MUX
CDAC
GND
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Maxim Integrated │ 9
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Detailed Description
Serial Interface
The MAX19777 is a fast, 12-bit, low-power, single-supply
ADC. The device operates from a 2.2V to 3.3V supply and
consume only 8.4mW (VDD = 3V)/6.2mW (VDD = 2.2V) at
3Msps. The 3Msps device is capable of sampling at full
rate when driven by a 48MHz clock.
The device features a 3-wire serial interface that directly
connects to SPI, QSPI, and MICROWIRE device without
external logic. Figure 1 and Figure 5 show the interface
signals for a single conversion frame to achieve maximum
throughput.
The conversion result appears at DOUT, MSB first, with a
leading zero followed by the 12-bit result. A 12-bit result is
followed by two trailing zeros. See Figure 1 and Figure 5.
The falling-edge of CS defines the sampling instant.
Once CS transitions low, the external clock signal (SCLK)
controls the conversion.
The input signal range for AIN1/AIN2 is defined as 0V to
VDD with respect to GND.
The SAR core successively extracts binary-weighted
bits in every clock cycle. The MSB appears on the data
bus during the 2nd clock cycle with a delay outlined in
the timing specifications. All extracted data bits appear
successively on the data bus with the LSB appearing
during the 13th clock cycle for 12-bit operation. The serial
data stream of conversion bits is preceded by a leading
“zero” and succeeded by trailing “zeros.” The data output
(DOUT) goes into high-impedance state during the 16th
clock cycle.
This ADC includes a power-down feature allowing
minimized power consumption at 2.5µA/ksps for lower
throughput rates. The wake up and power-down feature
is controlled by using the SPI interface as described in the
Operating Modes section.
To sustain the maximum sample rate, the device has to be
resampled immediately after the 16th clock cycle. For lower
sample rates, the CS falling edge can be delayed leaving
DOUT in a high-impedance condition. Pull CS high after the
10th SCLK falling edge (see the Operating Modes section).
SAMPLE
SAMPLE
CS
SCLK
DOUT
16
HIGH
IMPEDANCE
1
2
0
3
D11
4
D10
5
D9
6
D8
7
D7
8
D6
9
D5
10
D4
11
D3
12
D2
13
D1
14
D0
15
0
16
1
0
HIGH
IMPEDANCE
Figure 5. 12-Bit Timing Diagrams
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Maxim Integrated │ 10
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Analog Input
amp, such as the MAX4430, to drive the analog input,
thereby decoupling the signal source and the ADC.
The devices produce a digital output that corresponds to
the analog input voltage within the specified operating
range of 0 to VDD for the dual-channel device.
While the ADC is in conversion mode, the sampling switch
is open presenting a pin capacitance, CP (CP = 5pF),
to the driving stage. See the Applications Information
section for information on choosing an appropriate buffer
for the ADC.
Figure 6 shows an equivalent circuit for the analog input
AIN1/AIN2. Internal protection diodes D1/D2 confine the
analog input voltage within the power rails (VDD, GND).
The analog input voltage can swing from GND - 0.3V to
VDD + 0.3V without damaging the device.
ADC Transfer Function
The output format is straight binary. The code transitions
midway between successive integer LSB values such
as 0.5 LSB, 1.5 LSB, etc. The LSB size for dual-channel
devices is VDD/2n, where n is the resolution. The ideal
transfer characteristic is shown in Figure 10.
The electric load presented to the external stage driving the analog input varies depending on which mode
the ADC is in: track mode vs. conversion mode. In track
mode, the internal sampling capacitor CS (16pF) has to
be charged through the resistor R (R = 50Ω) to the input
voltage. For faithful sampling of the input, the capacitor
voltage on CS has to settle to the required accuracy
during the track time.
Operating Modes
The ICs offer two modes of operation: normal mode and
power-down mode. The logic state of the CS signal during
a conversion activates these modes. The power-down
mode can be used to optimize power dissipation with
respect to sample rate.
The source impedance of the external driving stage in
conjunction with the sampling switch resistance affects
the settling performance. The THD vs. Input Resistance
graph in the Typical Operating Characteristics shows THD
sensitivity as a function of the signal source impedance. Keep
the source impedance at a minimum for high dynamic
performance applications. Use a high-performance op
VDD
In normal mode, the devices are powered up at all times,
thereby achieving their maximum throughput rates. Figure
7 shows the timing diagram of these devices in normal
mode. The falling edge of CS samples the analog input signal,
starts a conversion, and frames the serial data transfer.
SWITCH CLOSED IN TRACK MODE
SWITCH OPEN IN CONVERSION MODE
D1
To remain in normal mode, keep CS low until the falling
edge of the 10th SCLK cycle. Pulling CS high after the
10th SCLK falling edge keeps the part in normal mode.
However, pulling CS high before the 10th SCLK falling
edge terminates the conversion, DOUT goes into highimpedance mode, and the device enters power-down
mode. See Figure 8.
CS
R
AIN1/AIN2
AIN
CP
Normal Mode
D2
Figure 6. Analog Input Circuit
KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE
PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE
CS
SCLK
DOUT
1
2
HIGH
IMPEDANCE
3
4
5
6
7
8
VALID DATA
9
10
11
12
13
14
15
16
HIGH
IMPEDANCE
Figure 7. Normal Mode
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Maxim Integrated │ 11
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
HIGH
IMPEDANCE
INVALID
DATA
INVALID DATA OR HIGH IMPEDANCE
HIGH IMPEDANCE
Figure 8. Entering Power-Down Mode
CS
1
SCLK
2
3
4
5
DOUT
6
7
8
9
10
11
12
13
14
15
INVALID DATA (DUMMY CONVERSION)
HIGH
IMPEDANCE
16
N
1
2
3
4
5
6
HIGH
IMPEDANCE
7
8
9
10
VALID DATA
11
12
13
14
15
16
HIGH
IMPEDANCE
Figure 9. Exiting Power-Down Mode
Power-Down Mode
OUTPUT CODE
In power-down mode, all bias circuitry is shut down drawing typically only 1.3µA of leakage current. To save power,
put the device in power-down mode between conversions. Using the power-down mode between conversions
is ideal for saving power when sampling the analog input
infrequently.
FS - 1.5 x LSB
111...111
111...110
111...101
Entering Power-Down Mode
To enter power-down mode, drive CS high between the
2nd and 10th falling edges of SCLK (see Figure 8). By
pulling CS high, the current conversion terminates and
DOUT enters high impedance.
000...010
000...001
000...000
0
1
2
3
2n-2 2n-1 2n
ANALOG
INPUT (LSB)
FULL SCALE (FS):
AIN1/AIN2 = VDD (WLP)
n = RESOLUTION
Figure 10. ADC Transfer Function
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Exiting Power-Down Mode
To exit power-down mode, implement one dummy
conversion by driving CS low for at least 10 clock cycles
(see Figure 9). The data on DOUT is invalid during this
dummy conversion. The first conversion following the
dummy cycle contains a valid conversion result.
The power-up time equals the duration of the dummy
cycle, and is dependent on the clock frequency. The powerup time for 3Msps operation (48MHz SCLK) is 333ns.
Maxim Integrated │ 12
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Supply Current vs. Sampling Rate
For applications requiring lower throughput rates, the
user can reduce the clock frequency (fSCLK) to lower the
sample rate. Figure 11 shows the typical supply current
(IVDD) as a function of sample rate (fS) for the 3Msps
devices. The part operates in normal mode and is never
powered down.
5
5
VDD=3V
fSCLK= VARIABLE
16 CYCLES/CONVERSION
4
VDD=3V
fSCLK= VARIABLE
16 CYCLE/CONVERSION
4
3
IVDD (mA)
IVDD (mA)
The user can also power down the ADC between conversions
by using the power-down mode. Figure 12 shows for the
3Msps device that as the sample rate is reduced, the
device remains in the power-down state longer and the
average supply current (IVDD) drops accordingly.
2
1
3
2
1
0
0
0
500
1000
1500 2000
fS (ksps)
2500
3000
Figure 11. Supply Current vs. Sample Rate (Normal Operating
Mode, 3Msps Devices)
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0
300
600
900
fS (ksps)
1200
1500
Figure 12. Supply Current vs. Sample Rate (Device Powered
Down Between Conversions, 3Msps Devices)
Maxim Integrated │ 13
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Applications Information
Dual-Channel Operation
The MAX19777 features dual-input channels. This device
uses a channel-select (CHSEL) input to select between
analog input AIN1 (CHSEL = 0) or AIN2 (CHSEL = 1).
As shown in Figure 13, the CHSEL signal is required
to change between the 2nd and 12th clock cycle within
a regular conversion to guarantee proper switching
between channels.
Layout, Grounding, and Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the VDD
power supply affects the ADC’s performance. Bypass
VDD to ground with 0.1µF and 10µF bypass capacitors.
Minimize capacitor lead and trace lengths for best supplynoise rejection.
14-Cycle Conversion Mode
The ICs can operate with 14 cycles per conversion.
Figure 14 shows the corresponding timing diagram.
Observe that DOUT does not go into high-impedance
mode. Also, observe that tACQ needs to be sufficiently
long to guarantee proper settling of the analog input
voltage. See the Electrical Characteristics table for tACQ
requirements and the Analog Input section for a description
of the analog inputs.
Choosing an Input Amplifier
It is important to match the settling time of the input amplifier
to the acquisition time of the ADC. The conversion results
are accurate when the ADC samples the input signal
for an interval longer than the input signal’s worst-case
settling time. By definition, settling time is the interval
between the application of an input voltage step and the
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CHSEL
DOUT
DATA CHANNEL AIN1
DATA CHANNEL AIN2
Figure 13. Channel Select Timing Diagram
SAMPLE
SAMPLE
CS
SCLK
DOUT
2
1
3
D11
0
4
D10
5
D9
6
D8
7
D7
8
D6
(MSB)
9
D5
10
D4
11
D3
12
D2
13
D1
14
D0
1
0
0
tACQ
1/fSAMPLE
tCONVERT
Figure 14. 14-Clock Cycle Operation
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Maxim Integrated │ 14
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
point at which the output signal reaches and stays within
a given error band centered on the resulting steady-state
amplifier output level. The ADC input sampling capacitor
charges during the sampling cycle, referred to as the
acquisition period. During this acquisition period, the
settling time is affected by the input resistance and the
input sampling capacitance. This error can be estimated
by looking at the settling of an RC time constant using
the input capacitance and the source impedance over the
acquisition time period.
Figure 15 shows a typical application circuit. The
MAX4430, offering a settling time of 37ns at 16 bits, is
an excellent choice for this application. See the THD
vs. Input Resistance graph in the Typical Operating
Characteristics.
+5V
0.1µF
10µF
3V
100pF COG
VDD
500Ω
AIN1
500Ω
MAX4430
VDC
0.1µF
10µF
5
4
10Ω
1
AIN1
470pF
COG CAPACITOR
-5V
3
GND
2
AIN2
0.1µF
470pF
COG CAPACITOR
10µF
MAX19777
SCLK
SCK
DOUT
MISO
CS
SS
CPU
CHSEL
+5V
0.1µF
10µF
100pF COG
500Ω
AIN2
500Ω
5
4
MAX4430
VDC
3
0.1µF
10Ω
1
-5V
2
10µF
Figure 15. Typical Application Circuit
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Maxim Integrated │ 15
MAX19777
Definitions
For the MAX19777, VREF is internally tied to VDD.
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. For this
device, the straight line is a line drawn between the end
points of the transfer function after offset and gain errors
are nulled.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of ±1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Offset Error
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
3Msps, Low-Power, Serial 12-Bit ADC
Signal-to-Noise Ratio and
Distortion (SINAD)
SINAD is a dynamic figure of merit that indicates the
converter’s noise and distortion performance. SINAD is
computed by taking the ratio of the RMS signal to the
RMS noise plus distortion. RMS noise plus distortion
includes all spectral components to the Nyquist frequency
excluding the fundamental and the DC offset:
SIGNAL RMS
SINAD(dB) = 20 × log
(NOISE + DISTORTION) RMS
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
V 22 + V32 + V 42 + V52
= 20 × log
THD
V1
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal after adjusting for the offset
error, that is, VREF - 1.5 LSB.
where V1 is the fundamental amplitude and V2–V5 are
the amplitudes of the 2nd- through 5th-order harmonics.
Aperture Jitter
Spurious-Free Dynamic Range (SFDR)
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
SFDR is a dynamic figure of merit that indicates the lowest usable input signal amplitude. SFDR is the ratio of
the RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest spurious
component, excluding DC offset. SFDR is specified in
decibels with respect to the carrier (dBc).
Signal-to-Noise Ratio (SNR)
Full-Power Bandwidth
Aperture delay (tAD) is the time between the falling edge
of sampling clock and the instant when an actual sample
is taken.
SNR is a dynamic figure of merit that indicates the
converter’s noise performance. For a waveform
perfectly reconstructed from digital samples, the theoretical
maximum SNR is the ratio of the full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization error only and results
directly from the ADC’s resolution (N bits):
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
SNR (dB) (MAX) = (6.02 x N + 1.76) (dB)
Any device with nonlinearities creates distortion products
when two sine waves at two different frequencies (f1 and
f2) are applied into the device. Intermodulation distortion
(IMD) is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones, f1 and f2. The
individual input tone levels are at -6dBFS.
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter that also degrade
SNR. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
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Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the signalto-noise ratio and distortion (SINAD) is equal to a specified
value.
Intermodulation Distortion
Maxim Integrated │ 16
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 WLP
Z80B1+1
21-100166
Refer to Application Note 1891
COMMON DIMENSIONS
Pin 1
Indicator
E
1
see Note 7
Marking
A
A1
A
0.27 REF
A2
AAAA
D
0.040 BASIC
0.21 0.03
A3
b
TOP VIEW
E
D1
A3
A
0.857
1.432
D
SIDE VIEW
E1
A1
A2
0.025
0.025
0.35 BASIC
1.05 BASIC
0.35 BASIC
e
S
0.35 0.02
0.08 0.01
0.175 BASIC
SD
SE
0.175 BASIC
DEPOPULATED BUMPS:
NONE
0.05 S
FRONT VIEW
E1
e
SE
B
SD
B
D1
A
1
2
3
4
A
BOTTOM VIEW
- DRAWING NOT TO SCALE -
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NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
b
0.05 M
maxim
integrated
S AB
TM
TITLE
PACKAGE OUTLINE 8 BUMPS
ULTRA THIN WLP PKG. 0.35 mm PITCH, Z80B1+1
APPROVAL
DOCUMENT CONTROL NO.
21-100166
REV.
A
1
1
Maxim Integrated │ 17
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Ordering Information
PART
PIN-PACKAGE
BITS
SPEED (Msps)
NO. OF CHANNELS
TOP MARK
MAX19777AZA+
8 WLP
12
MAX19777AZA+T
8 WLP
12
3
2
AAAH
3
2
AAAH
Note: Devices specified over the -40°C to +125°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T= Tape and reel.
Chip Information
PROCESS: CMOS
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Maxim Integrated │ 18
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/17
DESCRIPTION
Initial release
PAGES
CHANGED
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2017 Maxim Integrated Products, Inc. │ 19
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