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MAX20340
General Description
The MAX20340 is a universal bidirectional DC
powerline communication (PLC) management IC
with a 166.7kbps maximum bit rate. The device is
capable of a maximum of 1.2A charge current.
The MAX20340 features a slave detection circuit
that flags an interrupt to the system when the PLC
master detects
the presence of a PLC slave on the powerline.
This function allows the system to remain in a lowpower state until a slave device is connected.
Bidirectional DC Powerline
Communication Management IC
Benefits and Features
•
•
•
The device is available in a 9-bump, 0.4mm pitch,
1.358mm x 1.358mm wafer-level package (WLP).
Truly Wireless Earbuds
Tethered Wireless Headphones
Hearing Aids
Wearables
Game Controllers
Handheld Radios
Point of Sales Devices
19-100706; Rev 0; 11/19
Up to 166.7kbps Bit Rate
-
Many of the features of the MAX20340, such as master/
slave mode, I2C address, dual/single PLC slave
mode, and PLC slave address, are pin configurable.
Applications
Compact, Simple Solution for PLC
•
5.7kbps Data Throughput in Automatic
Mode
•
1.2A Charge Current
•
Automatic
Presence
Detection
of
PLC
Slave
Flexible Configuration
•
Single Resistor to Program
•
PLC Master or Slave
•
Dual or Single Slave Mode (Master Only)
•
PLC Slave Address (Slave Only)
•
I2C Address
Small Solution Size
•
Space-Saving 0.4mm Pitch, 9-Bump,
1.358mm x 1.358mm WLP
MAX20340
Bidirectional DC Powerline
Communication Management IC
Functional Diagram
VCC
LDO
(ONLY IN SLAVE MODE,
BYPASSED OTHERWISE)
RON_Q2
Q2
RON_Q1
Q1
MAX20340
PLC
BAT
VCCINT
SELECTOR
VBAT_RECHG
VCCINT
HIGH PSRR
INTERNAL SUPPLY
IPLC_SNK
VOLTAGE
CLAMP
SDA
SCL
I2C
MASTER/SLAVE
PLC CONFIG AND
CONTROL
PEAK
DETECTOR
BAT
GND
DAC
REF
RSEL
Absolute Maximum Ratings
VCC, PLC, SCL, SDA,
BAT,
, RSEL to GND…. ................................................................................................... -0.3V to +6V
Continuous Current VCC, Q1, Q2 closed, PLC ...............................................................................................................-1.2A to +1.2A
Continuous
Current
into
Any
Other
Terminal
...................................................................................................................................................................................-20mA to +20mA
Continuous Power Dissipation (Multilayer Board) (TA = 70°C, derate 11.91mW/°C above +70°C) ........................................ 952.8mW
Operating Temperature Range ..................................................................................................................................... -40°C to +85°C
Junction Temperature............................................................................................................................................................... +150°C
Storage Temperature Range ...................................................................................................................................... -40°C to +150°C
Soldering Temperature (reflow) ................................................................................................................................................ +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Information
9 WLP
Package Code
W91R1+1
Outline Number
21-100389
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θJA)
83.98°C/W
Junction-to-Case Thermal Resistance (θJC)
N/A
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layerboard. For
detailed information on package thermal considerations see www.maxim-ic.com/thermal-tutorial.
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Maxim Integrated | 2
MAX20340
Bidirectional DC Powerline
Communication Management IC
Electrical Characteristics
(TA = -40C to +85C, VCC = +3.4V to +5.5V, unless otherwise noted. Typical values are at T A = +25°C. (Note 1))
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.4
V
VCCINT (VCCINT_MASTER = BAT, VCCINT_SLAVE = PLC if VPLC > VPLC_DET, otherwise VCCINT = BAT)
VCCINT POR Threshold
VCCINT_POR
VCCINT POR Threshold
Hysteresis
VCCINT_PORH
Rising and falling
1.7
2.15
166
mV
VCC
Input Supply Voltage
Range
VCC Shutdown Current
VCC Supply Current
VCC
ICC_SHDN
ICC
Supply range to operate PLC
5.5
V
1
μA
50
μA
5.5
V
0.8
2.1
μA
4
9
0.7
2
VCC = +5.0V, VBAT = +3.6V,
=
0, master only, slave found charging state,
PLC unconnected
75
115
VPLC = +5.0V,
= 0, slave in master
found PLC communication enabled state,
LDO enabled
1
2
Slave in idle state, VPLC = +3.6V, VBAT =
+4.2V, VCC unconnected
0.6
1.4
Programmable in 200mV steps through
bits BAT_RECHG[2:0] of register 0x03; if
VBAT < VBAT_RECHG, a device in slave
idle state automatically transitions to
master detection state
3 to 4.4
VCC = +5.0V,
3.4
=1
VCC = +5.0V,
= 0, VBAT = +3.6V,
master in slave found charging state, PLC
unconnected
28.5
BAT
Input Supply Voltage
Range
BAT Shutdown Current
VBAT
IBAT_SHDN
Master/slave mode
2.8
VCC/VPLC = 0, VBAT = +3.6V,
Device in Low Power Shutdown
= 1,
VBAT = +3.6V,
= 0, PLC unconnected,
master in slave detection state
PLC = 0, VBAT = +3.6V,
master detection state
BAT Supply Current
IBAT
Recharge Voltage
Threshold Range
VBAT_RECHG
Recharge Threshold
Voltage Accuracy
VRECHG_ACC
= 0, slave in
μA
V
-8
+8
%
3.4
5.5
V
PLC
Input Supply Voltage
Range
PLC Shutdown Current
PLC Supply Current
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VPLC
Supply range to operate PLC
IPLC_SHDN
Slave only,
= 1, VPLC = +3.6V, VBAT =
+3.4V, VCC unconnected
3
6.5
μA
IPLC
VPLC = +5.0V,
= 0, slave only, LDO
enabled, master found communication
160
270
μA
Maxim Integrated | 3
MAX20340
Bidirectional DC Powerline
Communication Management IC
(TA = -40C to +85C, VCC = +3.4V to +5.5V, unless otherwise noted. Typical values are at T A = +25°C. (Note 1))
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Slave in slave idle state,
= 0, VPLC =
+3.6V, VBAT = +4.2V, VCC unconnected
3.4
7
μA
enabled state, PLC communication not
ongoing
PLC Supply Current
IPLC
PLC Detection
Threshold
VPLC_DET
Slave only, VPLC rising
2.5
V
Short-Circuit Detection
Threshold
VPLC_SHT
Master only, VPLC falling
2.4
V
Short Detection
Blanking Time
tSHT_BLK
2.5
ms
VCC – PLC
PLC Logic Threshold
(|VPLC_PEAK – VPLC|)
VCOM_DET
COM_THRS [1:0] = 00
38
50
62
COM_THRS [1:0] = 01
53
65
77
COM_THRS [1:0] = 10
68
80
92
COM_THRS [1:0] = 11
88
100
112
72
110
mΩ
0.53
0.65
Ω
+2%
V
mV
Q1, Q2 SWITCH
Q1, Q2 RON
Q2 RON
RON_Q1Q2
RON_Q2
VCC = 5V
450mA
0.46
VLDO
Slave Only, VPLC = 5V, MAX[VBAT + DV,
VMIN], (DV = 100mV .. 400mV, 50mV
step; VMIN = 2.8V…3.5V, 100mV step),
VBAT = 3.4V, ILOAD = 200mA
-2%
PSRRLDO
Ripple induced by a PLC square wave
current, minimum LDO drop = 200mV,
LDO load current = 200mA, ripple
frequency 1/TU min, rising and falling
edge at 200ns
-20
dB
Q1 LDO
LDO Output Voltage
LDO PSRR
LDO Load Regulation
LOADRLDO
Load from 0mA to 200mA
100
μV
LDO Input Line
Regulation
LINERLDO
VPLC from 3.4V to 5.5V, load = 200mA
620
μV
DEVICE CONFIGURATION (RSEL)
RSEL Config 1
Threshold
RSEL1
RSEL Config 2
Threshold
RSEL2
5.864
RSEL Config 3
Threshold
RSEL3
RSEL Config 4
Threshold
RSEL Config 5
Threshold
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4.581
kΩ
6.65
7.677
kΩ
9.289
10.2
11.347
kΩ
RSEL4
13.301
14.3
15.613
kΩ
RSEL5
17.966
19.1
20.667
kΩ
Maxim Integrated | 4
MAX20340
Bidirectional DC Powerline
Communication Management IC
(TA = -40C to +85C, VCC = +3.4V to +5.5V, unless otherwise noted. Typical values are at T A = +25°C. (Note 1))
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RSEL Config 6
Threshold
RSEL6
23.491
24.9
26.662
kΩ
RSEL Config 7
Threshold
RSEL7
30.046
31.6
33.599
kΩ
RSEL Config 8
Threshold
RSEL8
37.631
kΩ
POWERLINE COMMUNICATION
Time Unit
PLC Current Sink
tUNIT
IPLC_SNK
I2C programmable
24
PLC_SINK = 00
200
PLC_SINK = 01
244
PLC_SINK = 10
288
PLC_SINK = 11
355
s
mA
DYNAMIC
Device Identification
Ready Time
General Timing
Accuracy
tACC
DIGITAL SIGNALS (SDA, SCL,
Input Logic-High
Input Logic-Low
From BAT (master) or PLC (slave) above
POR threshold to RSEL_DONEi (0x07[4])
bit set
tID
,
-16
Output Logic-High
Leakage Current (Open
Drain)
IOH_LKG
VOL
ms
+16
%
1.4
V
VIL
IIN_LKG
3.48
)
VIH
Input Leakage Current
Output Logic-Low
3
, SCL
-1
VIO = 5.5V, SDA and
ISINK = 20mA
0.4
V
+1
μA
1
μA
0.4
V
I2C TIMING (Figure 4)
I2C Serial Clock
Frequency
fSCL
Bus Free Time Between
a STOP and START
Condition
tBUF
1.3
µs
tHD:STA
0.6
µs
Low Period of SCL
Clock
tLOW
1.3
µs
High Period of SCL
Clock
tHIGH
0.6
µs
tSU:STA
0.6
µs
START Condition
(Repeated) Hold Time
Setup Time for a
Repeated START
Condition
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400
kHz
Maxim Integrated | 5
MAX20340
Bidirectional DC Powerline
Communication Management IC
(TA = -40C to +85C, VCC = +3.4V to +5.5V, unless otherwise noted. Typical values are at T A = +25°C. (Note 1))
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.9
µs
Data Hold Time
tHD:DAT
0
Data Setup Time
tSU:DAT
100
ns
Setup Time for STOP
Condition
tSU:STO
0.6
µs
Spike Pulse Widths
Suppressed by Input
Filter
tSP
50
ns
ESD PROTECTION
PLC
All Other Pins
Human Body Model
±30
IEC 61000-4-2 Air-Gap
±3
IEC 61000-4-2 Contact Discharge
±10
Human Body Model
±2
kV
kV
THERMAL PROTECTION
Thermal Shutdown
TSHDN
Low to high
130
°C
Thermal Hysteresis
THYS
High to low
20
°C
Note 1: All devices are production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Typical Operating Characteristics
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toc03
CURRENT (µA)
toc02
CURRENT (µA)
CURRENT (A)
toc01
Maxim Integrated | 6
MAX20340
Bidirectional DC Powerline
Communication Management IC
toc09
CURRENT (µA)
CURRENT (µA)
toc12
CURRENT (µA)
toc11
CURRENT (µA)
CURRENT (µA)
toc10
CURRENT (µA)
CURRENT (µA)
toc08
toc07
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toc06
toc05
CURRENT (A)
CURRENT (µA)
toc04
Maxim Integrated | 7
MAX20340
Bidirectional DC Powerline
Communication Management IC
toc13
toc14
toc15
toc17
toc18
RON (W)
RON (W)
toc20
RON (W)
toc19
toc21
VOLTAGE (V)
CURRENT (µA)
toc16
RON (W)
CURRENT (µA)
CURRENT (µA)
CURRENT (µA)
V_LDO_MIN[2:0] = 000
D_LDO_BAT[2:0] = 001
°
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Maxim Integrated | 8
MAX20340
Bidirectional DC Powerline
Communication Management IC
toc22
toc24
toc23
µ
400µs
µ
toc26
toc25
toc27
µ
Pin Configuration
MAX20340
TOP VIEW (BUMP SIDE DOWN)
1
2
3
A
VCC
PLC
RSEL
B
BAT
+
C
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GND
SCL
SDA
Maxim Integrated | 9
MAX20340
Bidirectional DC Powerline
Communication Management IC
Pin Descriptions
PIN
NAME
FUNCTION
A1
VCC
Supply Voltage Input (Master). LDO output, bypass VCC to ground with a 10F capacitor (Slave).
A2
PLC
PLC Master Output or PLC Slave Input
A3
RSEL
B1
BAT
Resistor Programming Input. Connect a resistor of desired value based on Table 1 to configure I2C address,
master/slave mode, PLC mode (master only) and PLC slave address (slave only).
Battery Connection. Connect to system battery and bypass with a 1µF capacitor to GND.
Active-Low Enable Input. Drive
pin high to place the MAX20340 in a low-power shutdown mode. Note
that the EN bit of register 0x01[0] can still be used to exit the low-power shutdown mode even if the
pin
is high.
B2
B3
GND
C1
Ground
Active-Low Open-Drain Interrupt Output. Connect
C2
SCL
I2C Clock Input
C3
SDA
I2C Data Input/Output
to IO supply through a pullup resistor.
Detailed Description
The MAX20340 is a universal bidirectional DC powerline (PLC) communication management IC with a 166.7kbps
maximum bit rate. The device is capable of a maximum of 1.2A charge current.
The MAX20340 features a slave detection circuit that flags an interrupt to the system when the PLC master detects the
presence of a PLC slave on the power line. This function allows the system to remain in a low power state until a slave
device is connected. Many of the features of the MAX20340, such as master/slave mode, I 2C address, dual/single PLC
slave mode, and PLC slave address, are pin configurable.
Device Configuration
After power-on reset (POR), the master/slave mode, PLC slave address (slave only), PLC slave address mode (master
only) and I2C address are configured based on the value of the RSEL resistor. The configuration status can be queried
by reading I2C_ADD and PS_ADD bits of the register 0x05.
Table 1. RSEL Configuration
RESISTOR VALUE
(kΩ)
DEVICE MODE
PLC SLAVE
ADDRESSING MODE
PLC SLAVE
ADDRESS (PS_ADD)
I2C ADDRESS
< 4.581
Master
Single
X
0010101
6.65
Master
Single
X
1101010
10.2
Master
Dual
X
0010101
14.3
Master
Dual
X
1101010
19.1
Slave
X
0
0010101
24.9
Slave
X
0
1101010
31.6
Slave
X
1
0010101
> 37.631
Slave
X
1
1101010
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Maxim Integrated | 10
MAX20340
Bidirectional DC Powerline
Communication Management IC
Device Initialization
After POR, the device starts by checking the resistor present on the RSEL pin. It is recommended to have the OTP bit
RSEL_DONEm (0x08[4]) default high so that an interrupt occurs at the end of this RSEL identification phase. As an
alternative to detecting the interrupt, the user can also choose to wait 3ms or more after POR to give enough time for
RSEL to be properly identified. The I2C interface cannot be used until RSEL identification is complete because RSEL
defines also the I2C slave address. With RSEL identified, the PLC master/slave mode, the I 2C slave address, the number
of PLC slaves (master mode), and the PLC slave address (slave mode) are automatically configured. The configuration
result can be determined through bit PS_ADD (0x05[0]). The user can also read bits FSM_STAT[2:0] (0x05[4:2]) to
determine whether the MAX20340 is configured as a master or a slave. If the MAX20340 is configured as a PLC master,
see the Master Mode Operation section for more details. Otherwise, see the Slave Mode Operation section for PLC slave
operation details. Figure 1 shows the flow chart for transmitting 3 bytes from the PLC master and receiving the response
from the PLC slave. It assumes that all relevant interrupts have been unmasked.
SLAVE FOUND
MASTER FOUND
WRITE TX DATA REGISTERS
WRITE TX_DATA0 (0x0D)
WRITE TX_DATA1 (0x0E)
WRITE TX_DATA2 (0x0F)
PLC_RX_DET = 1
WRITE PLC_COM_CTRL (0x09)
SET PLC_SINK[1:0], FREQ[1:0],
PARITY[1:0] AS DESIRED, AND
SET TX[1:0] = 11
PLC_TX_P = 1
CHECK
PLC_STATUS (0x0A)
FROM INTERRUPT
OR POLLING
NEW_DATA1 = 0 AND
NEW_DATA2 = 0 AND
PLC_TMR_ERR = 0
PLC_RX_ERR = 1
PLC_RX_DET = 0 AND
(NEW_DATA1 = 1 AND
NEW_DATA2 = 1)
READ RX DATA REGISTERS
READ RX_DATA0 (0x10)
READ RX_DATA1 (0x11)
READ RX_DATA2 (0x12)
PROCESS DATA
PLC_TX_ERR = 1
PLC_TX_OK = 1
CHECK
PLC_STATUS (0x0A)
FROM INTERRUPT
OR POLLING
CHECK
PLC_STATUS (0x0A)
FROM INTERRUPT
OR POLLING
PLC_TMR_ERR = 1
WRITE TX DATA REGISTERS
WRITE TX_DATA0 (0x0D)
WRITE TX_DATA1 (0x0E)
WRITE TX_DATA2 (0x0F)
WRITE PLC_COM_CTRL (0x09)
SET PLC_SINK[1:0], FREQ[1:0],
PARITY[1:0] AS DESIRED, AND
SET TX[1:0] = 11
NEW_DATA1 = 1 AND
NEW_DATA2 = 1
READ RX DATA REGISTERS
READ RX_DATA0 (0x10)
READ RX_DATA1 (0x11)
READ RX_DATA2 (0x12)
PLC_TX_P = 1
CHECK
PLC_STATUS (0x0A)
FROM INTERRUPT
OR POLLING
PLC_TX_ERR = 1
PLC_TX_OK = 1
Figure 1.
Flow Chart for Transmitting 3 Bytes
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Maxim Integrated | 11
MAX20340
Bidirectional DC Powerline
Communication Management IC
Master Mode Operation
After the RSEL and master mode identifications, the MAX20340 stays in the master low-power shutdown mode as long
as
input is high (assuming EN bit of register 0x01[0] is left at 0). When
is set low or 0x01[0] = 1, the device
transitions to the slave detection state. The user can unmask the FSM_STATi interrupt (0x08[0]) to be notified of any
change of master FSM state through the
pin. When a slave is detected, the state machine transitions to the slave
found state. In this state, both the Q1 and Q2 switches are on to provide a low-resistance charging path between VCC
and PLC pins with a 1.2A maximum charge current on the PLC line. In the slave found state, PLC communication can be
initiated by the PLC master using the following procedure:
•
Set PLC_STATm bit of the DEV_STATUS_MASK (0x08) register to 1 to unmask the PLC_STAT
interrupts. Then unmask the PLC interrupts in the PLC_IRQ register (0x0B) and the PLC_MASK (0x0C)
register.
•
Load the bytes to be transmitted into TX_DATAx registers (0x0D, 0x0E, and 0x0F).
•
Select the desired slave response time through the TWAIT_TMR (0x02[1:0]) bit or leave it at the default
setting.
•
Choose the desired PLC speed through the FREQ[1:0] (0x09[5:4]) bit, the parity through the
PARITY[1:0] (0x09[3:2]) bit, and the PLC sink current through the PLC_SINK[1:0] (0x09[7:6]) bit. Write
01 into TX[1:0] (0x09[1:0]) to send one byte, 10 to send two bytes, or 11 to send three bytes. The
checksum is automatically calculated by the MAX20340 and appended after the actual data bytes.
•
The master state machine transitions automatically to PLC mode and starts sending data.
•
If the transmission is completed without errors, PLC_TX_OKi (0x0B[5]) goes high. Otherwise,
PLC_TX_ERRi (0x0B[6]) goes high instead.
•
If the PLC slave responds within the time specified by the Rx wait timer bits 0x02[1:0], the received data
are available in the RX_DATAx registers (0x10, 0x11, and 0x12). The response includes one, two, or
three bytes plus the checksum. If the response is received without errors, NEW_DATA2i (0x0B[1]) or
NEW_DATA1i (0x0B[2]) bits (or both at the same time) are high. In case of parity, checksum or any
other error, PLC_RX_ERRi (0x0B[3]) goes high and the new data is not be updated in RX_DATAx.
The master state machine switches automatically between PLC mode and slave found states based on the PLC
communication requirements.
Slave Mode Operation
After RSEL and slave mode identification, the MAX20340 stays in the slave low-power shutdown mode as long as
input is high (assuming EN bit of register 0x01[0] is left at 0). When
is set low or 0x01[0] = 1, the device transitions to
master detection state. The user can unmask the FSM_STATi interrupt using FSM_STATm (0x08[0]) to notify through
the
pin when any change of state occurs. When a master is detected, the state machine switches to master found
state. In this state, PLC communication is enabled. The detected PLC master is always the one that initiates the
communication by sending one, two or three data bytes. When the PLC slave detects the beginning of a valid PLC
communication, PLC_RX_DETi (0x0B[0]) becomes high. If the packet is received without errors, NEW_DATA2i (0x0B[1])
or NEW_DATA1i (0x0B[2]) bits (or both at the same time) becomes high and the received data are available in the
RX_DATAx registers (0x10, 0x11, and 0x12). The PLC slave can be switched from master found state to slave idle state
by setting SLAVE_TO_IDLE (0x04[3]) to 1.
In the master found state, use the following procedure to control the PLC slave for PLC communication:
•
Set PLC_STATm bit of the DEV_STATUS_MASK (0x08) register to 1 to unmask PLC_STAT interrupts.
Then unmask the PLC interrupts in the PLC_IRQ register (0x0B) through the PLC_MASK (0x0C)
register.
•
Configure the slave to match the PLC speed (FREQ[1:0]) and parity (PARITY[1:0]) of the master through
the PLC_COM_CTRL register (0x09).
•
When ongoing PLC communication is detected, the PLC slave indicates that by setting PLC_RX_DETi
(0x0B[0]) to high. After that, wait for the assertion of interrupts NEW_DATA2i (0x0B[1]) or NEW_DATA1i
(0x0B[2]) indicating that the received data is available in the RX_DATAx registers. In case of parity,
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Maxim Integrated | 12
MAX20340
Bidirectional DC Powerline
Communication Management IC
checksum or any other error, PLC_RX_ERRi (0x0B[3]) is high and the new data is not updated in the
RX_DATAx registers.
•
To respond to the PLC master after processing the received data, load the bytes to be transmitted into
the slave’s TX_DATAx registers (0x0D, 0x0E, and 0x0F).
Write 01 into TX[1:0] bits (0x09[1:0]) to send just one byte, 10 to send two bytes, or 11 to send three bytes. The checksum
is automatically calculated by the MAX20340 and appended after the actual data bytes.
Dual Slave Configuration
When an MAX20340 PLC master interfaces with two MAX20340 PLC slaves in the dual slave configuration, both PLC
slaves should be configured to have a different PLC slave address using different RSEL values according to Table 1. The
configured PLC slave address can be determined by reading bit PS_ADD (0x05[0]). When the PLC master intends to
send a packet to one of the PLC slaves, the PLC slave address of the intended recipient should be embedded in the data
bytes. The user has the flexibility to assign the PLC slave address to any bit of the data bytes. Since both PLC slaves
receive the same data, each slave’s application processor is expected to extract the PLC slave address from the userdefined bit location in the PLC frame and compare it with the PLC slave address indicated by PS_ADD bit to determine
which slave is the intended recipient. The intended slave then processes the data accordingly while the other slave simply
discards the data.
LDO Operation
When the device is in slave mode (powered from the PLC pin), the V CC pin becomes the LDO output. In this mode, the
output voltage on VCC follows the battery voltage plus a voltage difference programmable by the D_LDO_BAT[2:0] bits
(register 0x02[4:2]) until VCC drops to a threshold programmable by V_LDO_MIN[2:0] bits (register 0x02[7:5]), in which
case the MAX20340 keeps VCC regulated at the voltage set by V_LDO_MIN[2:0]. In slave mode, the LDO can also be
bypassed by setting D_LDO_BAT[2:0] to 000.
Charge Timer
When the MAX20340 is configured as a PLC master. The charge timer starts when the master state machine switches
from the slave detection state to the slave found state. It continues counting without being interrupted or reset when the
state machine switches back and forth between the slave found state and the PLC mode state. The charge timer is reset
and stopped in the slave detection state and the master low-power shutdown state. The charge timer setting can be
changed by CHG_TMR_SET[1:0] bits (0x03[5:4]). The charge timer status is reflected by CHG_TMRS[1:0] bits
(0x05[7:6]).
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Maxim Integrated | 13
MAX20340
Bidirectional DC Powerline
Communication Management IC
VCCINT < VPOR
UVLO
ANY STATE
PLC CLAMP ENABLED
MASTER MODE
INITIALIZATION
CHECK RSEL VALUE,
I2C ADDRESS,
SET MASTER/SLAVE MODE ,
SINGLE/DUAL PLC (MASTER
ONLY), PLC SLAVE ADDRESS
MASTER LOW
POWER SHUTDOWN
PLC CLAMP DISABLED
PLC PULL-UP DISABLED
Q1, Q2 OPEN
=0
SLAVE LOW
POWER SHUTDOWN
PLC CLAMP DISABLED
PLC PULL-UP DISABLED
Q1, Q2 OPEN
=1
=0
=1
SLAVE DETECTION
MASTER DETECTION
PLC CLAMP DISABLED
PLC PULL-UP ENABLED
Q1, Q2 OPEN
PLC CLAMP ENABLED
PLC PULL-UP DISABLED
Q1, Q2 OPEN
DET_RST = 1 or
CHARGE TIMER
EXPIRED
CLAMP
DETECTED ON
PLC
SLAVE FOUND
CHARGING
PLC CLAMP DISABLED
=1
PLC PULL-UP DISABLED
Q1, Q2 CLOSED
SEND PLC DATA
RESPONSE RECEIVED
(TX[1:0] = 01, 10
FROM SLAVE OR RX
or 11)
WAIT TIMER EXPIRED
SHORT CIRCUIT
DETECTED ON
PLC
SLAVE MODE
PLC MODE
PLC CLAMP DISABLED
PLC PULL-UP DISABLED
Q1 OPEN, Q2 CLOSED
RX WAIT TIMER STARTS
VPLC > VPLC_DET
VPLC < VPLC_DET
MASTER FOUND
COMMUNICATION ENABLED
PLC CLAMP DISABLED
PLC PULL-UP DISABLED
Q1, Q2 IN LDO MODE
I2C COMMAND
TO ENTER IDLE
SLAVE IDLE
VPLC < VPLC_DET OR
VBAT < VBAT_RECHG OR
DET_RST = 1
SHORT CIRCUIT
DETECTED ON
PLC
=1
PLC CLAMP DISABLED
PLC PULL-UP DISABLED
Q1 Q2 OPEN
=1
SAFE
PLC CLAMP DISABLED
PLC PULL-UP DISABLED
Q1, Q2 OPEN
Figure 2.
DET_RST =1
Master and Slave Mode Operation State Diagram
Thermal Shutdown
When the MAX20340 enters thermal shutdown, the Q1/Q2 switches are open and the THM_SHDNi interrupt bit (0x07[5])
becomes high while the master/slave state machines are not affected.
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Maxim Integrated | 14
MAX20340
Bidirectional DC Powerline
Communication Management IC
INT Interrupt Output
The MAX20340 interrupts can be unmasked to indicate to the application processor (AP) that the status of the MAX20340
has changed. The
pin asserts low whenever one or more unmasked interrupts are toggled. The device has two readonly interrupt registers: DEV_STATUS_IRQ and PLC_IRQ. The DEV_STATUS_IRQ register indicates that the top-level
block has an interrupt generated. PLC_IRQ is an additional interrupt register dedicated to the PLC block for indicating
any change of the PLC communication status. The PLC_STATi bit in the DEV_STATUS_IRQ register goes high if any bit
of the register PLC_IRQ is asserted.
goes high (cleared) after the last interrupt register that contains an active interrupt is read. All interrupts can be
masked to prevent
from being asserted through the DEV_STATUS_MASK and PLC_MASK registers. The
DEV_STATUS1, DEV_STATUS2, and PLC_STATUS registers can still provide the actual interrupt status of the masked
interrupts, but
is not asserted. The interrupt structure is depicted in Figure 3.
VPLC_SHORTi
PLC_TIMER_ERRi
VPLC_SHORTm
PLC_TIMER_ERRm
THM_SHDNi
PLC_TX_ERRi
THM_SHDNm
PLC_TX_ERRm
RSEL_DONEi
PLC_TX_OKi
RSEL_DONEm
PLC_TX_OKm
LDO_DROP_ERRi
PLC_TX_Pi
LDO_DROP_ERRm
PLC_TX_Pm
CHG_TMRi
PLC_RX_ERRi
CHG_TMRm
PLC_RX_ERRm
PLC_STATi
NEW_DATA1i
PLC_STATm
NEW_DATA1m
FSM_STATi
NEW_DATA2i
FSM_STATm
NEW_DATA2m
PLC_RX_DETi
PLC_RX_DETm
Figure 3.
Interrupt Structure
I2C Interface
The device contains an I2C-compatible interface for data communication with a host controller (SCL and SDA). The
interface supports a clock frequency of up to 400kHz. SCL and SDA require pullup resistors that are connected to a
positive supply.
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Maxim Integrated | 15
MAX20340
Bidirectional DC Powerline
Communication Management IC
tSU:STA
tSU:STO
SDA
tSU:DAT
tR
tHU:DAT
tLOW
tBUF
tHD:STA
tR
SCL
tHD:STA
tHIGH
START
REPEATED START
STOP
START
Figure 4. I2C Interface Timing
START, STOP, and REPEATED START Conditions
When writing to the device using I2C, the master sends a START condition (S) followed by the device I2C address. After
the address, the master sends the register address of the register that is to be programmed. The master then ends
communication by issuing a STOP condition (P) to relinquish control of the bus, or a REPEATED START condition (Sr)
to communicate to another I2C slave. See Figure 5.
S
Sr
P
SCL
SDA
Figure 5.
I2C START, STOP, and REPEATED START Conditions
Slave Address
Set the R/ bit high to configure the device to read mode. Set the R/ bit low to configure the device to write mode. The
address is the first byte of information sent to the device after the START condition.
Bit Transfer
One data bit is transferred on the rising edge of each SCL clock cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals. See the
START, STOP, and REPEATED START Conditions. Both SDA and SCL remain high when the bus is not active.
Single-Byte Write
In this operation, the master sends an address and two data bytes to the slave device (Figure 6). The following procedure
describes the single byte write operation:
1) The master sends a START condition.
2) The master sends the 7-bit slave address plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The slave asserts an ACK on the data line only if the address is valid (NAK if not).
6) The master sends 8 data bits.
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Maxim Integrated | 16
MAX20340
Bidirectional DC Powerline
Communication Management IC
7)
The slave asserts an ACK on the data line.
8)
The master generates a STOP condition.
WRITE SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
8 DATA BITS
A
FROM MASTER TO SLAVE
Figure 6.
REGISTER ADDRESS
A
P
FROM SLAVE TO MASTER
Write Byte Sequence
Burst Write
In this operation, the master sends an address and multiple data bytes to the slave device (Figure 7). The slave device
automatically increments the register address after each data byte is sent. The following procedure describes the burst
write operation:
1) The master sends a START condition.
2) The master sends the 7-bit slave address plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The slave asserts an ACK on the data line only if the address is valid (NAK if not).
6) The master sends eight data bits.
7) The slave asserts an ACK on the data line.
8) Repeat steps 6 and 7 N - 1 times.
9) The master generates a STOP condition.
BURST WRITE
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
8 DATA BITS - 1
A
8 DATA BITS - 2
A
8 DATA BITS - N
A
FROM MASTER TO SLAVE
Figure 7.
P
FROM SLAVE TO MASTER
Burst Write Sequence
Single-Byte Read
In this operation, the master sends an address plus two data bytes and receives one data byte from the slave device
(Figure 8). The following procedure describes the single-byte read operation:
The master sends a START condition.
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Maxim Integrated | 17
MAX20340
Bidirectional DC Powerline
Communication Management IC
1)
The master sends the 7-bit slave address plus a write bit (low).
2)
The addressed slave asserts an ACK on the data line.
3)
The master sends the 8-bit register address.
4)
The slave asserts an ACK on the data line only if the address is valid (NAK if not).
5)
The master sends a REPEATED START condition.
6)
The master sends the 7-bit slave address plus a read bit (high).
7)
The addressed slave asserts an ACK on the data line.
8)
The slave sends eight data bits.
9)
The master asserts a NACK on the data line.
10) The master generates a STOP condition.
READ SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
Sr
DEVICE SLAVE ADDRESS - R
A
8 DATA BITS
NA
FROM MASTER TO SLAVE
P
FROM SLAVE TO MASTER
Figure 8. Read Byte Sequence
Burst Read
In this operation, the master sends an address plus two data bytes and receives multiple data bytes from the slave device
(Figure 9). The following procedure describes the burst-byte read operation:
1) The master sends a START condition.
2) The master sends the 7-bit slave address plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The slave asserts an ACK on the data line only if the address is valid (NAK if not).
6) The master sends a REPEATED START condition.
7) The master sends the 7-bit slave address plus a read bit (high).
8) The slave asserts an ACK on the data line.
9) The slave sends eight data bits.
10) The master asserts an ACK on the data line.
11) Repeat steps 9 and 10 N - 2 times.
12) The slave sends the last eight data bits.
13) The master asserts a NACK on the data line.
14) The master generates a STOP condition.
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Maxim Integrated | 18
MAX20340
Bidirectional DC Powerline
Communication Management IC
BURST READ
S
DEVICE SLAVE ADDRESS - W
A
REGISTER ADDRESS
A
Sr
DEVICE SLAVE ADDRESS - R
A
8 DATA BITS - 1
A
8 DATA BITS - 2
A
8 DATA BITS - 3
A
8 DATA BITS - N
NA
FROM MASTER TO SLAVE
Figure 9.
P
FROM SLAVE TO MASTER
Burst Read Sequence
Acknowledge Bits
Data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and
the device generate ACK bits. To generate an ACK, pull SDA low before the rising edge of the ninth clock pulse and hold
it low during the high period of the ninth clock pulse (Figure 10). To generate a NACK, leave SDA high before the rising
edge of the ninth clock pulse and leave it high for the duration of the ninth clock pulse. Monitoring for NACK bits allows
for detection of unsuccessful data transfers.
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
SCL
Figure 10. Acknowledge
Applications Information
Powerline Communication (PLC)
To communicate reliably over the PLC line, it is critical to keep VCC of the master stable by minimizing the trace between
VCC and its voltage source. A voltage source with a good load transient, load regulation, and output ripple performance
is recommended.
In addition, the capacitance present on the PLC can distort the PLC transmission waveform and therefore should be
minimized. This is an important consideration when the LDO of the slave is in the dropout state (LDO_DROP = 1) or when
the LDO is bypassed. In both cases, the output capacitance on the LDO output (V CC of the PLC slave) is effectively
affecting the PLC line and should therefore be minimized as well. Figure 11 illustrates the voltage waveform on the PLC
line during a PLC transmission.
The time unit (tUNIT) determines the PLC transmission speed. A time unit longer than 24µs can be selected in case the
slave device, such as a battery charger in a wireless earbud, has poor PSRR performance.
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Maxim Integrated | 19
MAX20340
Bidirectional DC Powerline
Communication Management IC
VCC
VPLC_PEAK
VCOM_DET
VPLC_DROP
tUNIT
DIGITIZED
PLC VALUE
VPLC_DROP = VCC – RON_Q2 * (IPLC_SNK + Charge Current during PLC)
Figure 11. Powerline Communication Signal Waveform
High-ESD Protection
Electrostatic discharge (ESD)-protection structures are incorporated on all pins to protect against electrostatic discharges
up to ±2kV Human Body Model (HBM) encountered during handling and assembly. PLC pin is further protected against
ESD up to ±30kV (HBM), ±3kV (Air-Gap Discharge), and ±10kV (Contact Discharge) without damage. The ESD structures
withstand high ESD in both normal operation and when the device is powered down. After an ESD event, the MAX20340
continues to function without latchup.
ESD Test Conditions
ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup,
test methodology, and test results.
Human Body Model
Figure 12 shows the Human Body Model. Figure 13 shows the current waveform it generates when discharged into a low
impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest that is then discharged into
the device through a 1.5kΩ resistor.
RC
1MW
HIGHVOLTAGE
DC
SOURCE
RD
1.5kW
CHARGE-CURRENTLIMIT RESISTOR
CS
100pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 12. Human Body ESD Test Model
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Maxim Integrated | 20
MAX20340
Bidirectional DC Powerline
Communication Management IC
IPEAK (AMPS)
100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
36.8%
10%
00
TIME
tRL
tDL
Figure 13. Human Body Current Waveform
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. It does not specifically refer to
integrated circuits. The MAX20340 is specified for ±3kV Air-Gap and ±10kV Contact Discharge IEC 61000-4-2 on the
PLC pin.
The main difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC
61000-4-2. Because series resistance is lower in the IEC 61000-4-2 ESD test model (Figure 14), the ESD-withstand
voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 15 shows
the current waveform for the ±6kV IEC 61000-4-2 Level 4 ESD Contact Discharge test. The Contact Discharge method
connects the probe to the device before the probe is energized.
RC
50MW to 100MW
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
150pF
RD
330W
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 14. IEC61000-4-2 ESD Test Model
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Maxim Integrated | 21
MAX20340
Bidirectional DC Powerline
Communication Management IC
IPEAK (AMPS)
100%
90%
10%
tR = 0.7ns TO 1ns
TIME
30ns
60ns
Figure 15. IEC61000-4-2 ESD Generator Current Waveform
Register Map
MAX20340
ADDRESS
NAME
MSB
LSB
I2C MAP
0x00
DEVICE_ID[7:0]
0x01
CONTROL1[7:0]
0x02
CONTROL2[7:0]
0x03
CONTROL3[7:0]
0x04
CONTROL4[7:0]
0x05
DEV_STATUS1[7:0]
CHG_TMR_STAT[1:0]
0x06
DEV_STATUS2[7:0]
LDO_DR
OP
ENb
—
—
—
0x07
DEV_STATUS_IRQ[7:0]
—
VPLC_SH
ORTi
THM_SH
DNi
RSEL_DO
NEi
0x08
DEV_STATUS_MASK[7:0]
—
VPLC_SH
ORTm
THM_SH
DNm
RSEL_DO
NEm
0x09
PLC_COM_CTRL[7:0]
PLC_SINK[1:0]
0x0A
PLC_STATUS[7:0]
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CHIP_ID[3:0]
—
—
CHIP_REV[3:0]
—
V_LDO_MIN[2:0]
COM_THRS[1:0]
—
PLC_TMR
_ERR
—
PLC_TX_
ERR
—
—
DET_RST
D_LDO_BAT[2:0]
TXRX_RE
SET
—
PLC_STA
T
SLAVE_T
O_IDLE
BAT_RECHG[2:0]
—
TXFILT_E
NB
I2C_ADD
PS_ADD
—
THM_SH
DN
PLC_CMP
_OUT
LDO_DR
OP_ERRi
CHG_TM
R_STATi
PLC_STA
Ti
FSM_STA
Ti
LDO_DR
OP_ERR
m
CHG_TM
Rm
PLC_STA
Tm
FSM_STA
Tm
—
FSM_STAT[2:0]
FREQ[1:0]
PLC_TX_
OK
TWAIT_TMR[1:0]
—
CHG_TMR_SET[1:0]
PLC_TX_
P
EN
PARITY[1:0]
PLC_RX_
ERR
NEW_DA
TA1
TX[1:0]
NEW_DA
TA2
PLC_RX_
DET
Maxim Integrated | 22
MAX20340
ADDRESS
Bidirectional DC Powerline
Communication Management IC
NAME
MSB
LSB
0x0B
PLC_IRQ[7:0]
PLC_TMR
i
PLC_TX_
ERRi
PLC_TX_
OKI
PLC_TX_
Pi
PLC_RX_
ERRi
NEW_DA
TA1i
NEW_DA
TA2i
PLC_RX_
DETi
0x0C
PLC_MASK[7:0]
PLC_TMR
m
PLC_TX_
ERRm
PLC_TX_
OKm
PLC_TX_
Pm
PLC_RX_
ERRm
NEW_DA
TA1m
NEW_DA
TA2m
PLC_RX_
DETm
0x0D
TX_DATA0[7:0]
TXDATA0[7:0]
0x0E
TX_DATA1[7:0]
TXDATA1[7:0]
0x0F
TX_DATA2[7:0]
TXDATA2[7:0]
0x10
RX_DATA0[7:0]
RXDATA0[7:0]
0x11
RX_DATA1[7:0]
RXDATA1[7:0]
0x12
RX_DATA2[7:0]
RXDATA2[7:0]
Register Details DEVICE_ID (0x0)
BIT
7
6
5
4
3
2
1
Field
CHIP_ID[3:0]
CHIP_REV[3:0]
Reset
0x1
0x0
Read Only
Read Only
Access Type
BITFIELD
BITS
0
DESCRIPTION
CHIP_ID
7:4
CHIP_ID[3:0] shows information about the version of the MAX20340.
CHIP_REV
3:0
CHIP_REV[3:0} shows information about the revision of the MAX20340 silicon.
CONTROL1 (0x1)
BIT
7
6
5
Field
—
—
—
Reset
0x0
0x0
Write, Read
Write, Read
Access Type
BITFIELD
BITS
2
1
0
—
—
DET_RST
EN
0x0
0x0
0x0
0x0
0x1
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
DESCRIPTION
—
7
Reserved. Used internally.
—
6
Reserved. Used internally.
—
5
Reserved. Used internally.
—
4:3
Reserved. Used internally.
—
2
Reserved. Used internally.
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4
3
DECODE
Maxim Integrated | 23
MAX20340
BITFIELD
Bidirectional DC Powerline
Communication Management IC
BITS
DESCRIPTION
DECODE
DET_RST
1
Master/Slave Detection Reset
Writing a 1 to this bit will reset the FSM to the master/slave
detection state.
EN
0
Device Enable. If the external pin EN is low, this bit
is ignored. If the external pin EN is high, this bit can
be used to enter or exit low-power shutdown mode
by software rather than by driving EN.
0x0: Device enters low-power shutdown mode (both
master and slave).
0x1: Device exits low-power shutdown mode.
CONTROL2 (0x2)
BIT
7
6
5
4
3
2
1
0
Field
V_LDO_MIN[2:0]
D_LDO_BAT[2:0]
TWAIT_TMR[1:0]
Reset
0x0
0x6
0x1
Write, Read
Write, Read
Write, Read
Access Type
BITFIELD
V_LDO_MIN
BITS
DESCRIPTION
7:5
DECODE
LDO Voltage Select. In slave mode, except when
D_LDO_BAT[2:0] = 000, this sets the minimum
allowed LDO output voltage, overriding
D_LDO_BAT[2:0].
0x0: 2.8V
0x1: 2.9V
0x2: 3.0V
0x3: 3.1V
0x4: 3.2V
0x5: 3.3V
0x6: 3.4V
0x7: 3.5V
D_LDO_BAT
4:2
Regulated LDO-BAT Difference. In slave mode, this
sets the regulated difference between the voltages
of LDO output and BAT.
0x0: LDO Bypassed
0x1: 100mV
0x2: 150mV
0x3: 200mV
0x4: 250mV
0x5: 300mV
0x6: 350mV
0x7: 400mV
TWAIT_TMR
1:0
PLC Master's Rx Wait Time After Transmission
0x0: 2ms
0x1: 10ms (default)
0x2: 100ms
0x3: 800ms
CONTROL3 (0x3)
BIT
7
6
5
4
Field
COM_THRS[1:0]
CHG_TMR_SET[1:0]
Reset
0x0
0x0
Write, Read
Write, Read
Access Type
BITFIELD
BITS
COM_THRS
7:6
CHG_TMR_SE
T
5:4
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3
—
1
0
BAT_RECHG[2:0]
0x1
Write, Read
DESCRIPTION
Communication Detection Threshold
2
Write, Read
DECODE
0x0: 50mV
0x1: 65mV
0x2: 80mV
0x3: 100mV
Charge Timer Setting (Master Only
and Master/Slave State Machine
Active).
Maxim Integrated | 24
MAX20340
BITFIELD
Bidirectional DC Powerline
Communication Management IC
BITS
DESCRIPTION
DECODE
0x0:
0x1:
0x2:
0x3:
—
3
BAT_RECHG
2:0
Charge timer disabled
60min
120min
240min
Reserved
Battery Recharge Threshold. Programmable in
200mV steps (slave mode only and master/slave
state machine active). When the voltage on BAT
drops below this level, the device automatically
transitions from slave idle state to master detection
state and applies the clamp on PLC.
0x0: 3V
0x1: 3.2V
...
0x7: 4.4V
CONTROL4 (0x4)
BIT
7
6
5
4
3
2
1
0
Field
—
—
—
TXRX_RESE
T
SLAVE_TO_I
DLE
—
—
TXFILT_ENB
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
—
7
Reserved. Do not change the default value.
—
6
Reserved. Do not change the default value.
—
5
Reserved. Do not change the default value.
TXRX_RESET
4
When high, this bit clears asynchronously the PLC
transmitter, receiver, and tracking state machines.
The I2C map and master/slave state machines are
not affected.
SLAVE_TO_ID
LE
3
When high, this bit causes the transition from the
master found communication enabled state to slave
idle state. It is ignored in the other states or if the
MAX20340 is configured as a master. This bit
autoclears.
—
2
Reserved. Do not change the default value.
—
1
Reserved. Do not change the default value.
TXFILT_ENB
0
0x0: Filter that compares transmitted PLC data to realtime received data is enabled. In case of a mismatch, a
counter is incremented. When this counter reaches 15,
the PLC_TX_ERR flag is generated and the transmission
is interrupted.
0x1: Filter disabled.
Tx Filter Active-Low Enable.
DEV_STATUS1 (0x5)
BIT
Field
7
6
CHG_TMR_STAT[1:0]
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5
PLC_STAT
4
3
FSM_STAT[2:0]
2
1
0
I2C_ADD
PS_ADD
Maxim Integrated | 25
MAX20340
Bidirectional DC Powerline
Communication Management IC
Reset
Access Type
0x0
0x0
0x0
0x0
0x0
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
BITS
CHG_TMR_ST
AT
7:6
PLC_STAT
FSM_STAT
5
4:2
DESCRIPTION
DECODE
Charge Timer Status
0x0: Timer inactive
0x1: Timer running
0x2: Timer expired
0x3: Reserved
This bit is set high if one or more bits of the readonly register PLC_STATUS are high.
0x0: PLC_STATUS register has zero value.
0x1: PLC_STATUS register has nonzero value.
FSM State Status
0x0: Initialization (master/slave)/safe state (master)
0x1: Slave low power shutdown
0x2: Master low power shutdown
0x3: Master detection
0x4: Slave detection
0x5: Master found communication enabled
0x6: Slave found charging
0x7: PLC mode (master)/slave idle (slave)
I2C_ADD
1
Configured I2C Slave Address
0x0: 7-bit I2C slave address = 0010101b
0x1: 7-bit I2C slave address = 1101010b
PS_ADD
0
Configured PLC Slave Address
0x0: Slave mode: PLC slave address is 0b0.
Master mode: PLC master in single slave mode.
0x1: Slave mode: PLC slave address is 0b1.
Master mode: PLC master in dual slave mode.
DEV_STATUS2 (0x6)
BIT
7
6
5
4
3
2
1
0
Field
LDO_DROP
ENb
—
—
—
—
THM_SHDN
PLC_CMP_O
UT
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
LDO_DROP
7
Output Status of LDO_DROP Comparator
0x0: LDO_DROP comparator output is low.
0x1: LDO_DROP comparator output is high.
ENb
6
Status of EN input pin
0x0: EN input pin is low.
0x1: EN input pin is high.
—
5
Reserved. Used internally.
—
4
Reserved. Used internally.
—
3
Reserved. Used internally.
—
2
Reserved. Used internally.
THM_SHDN
1
Temperature Status Indicator
0x0: Device not in thermal shutdown.
0x1: Device in thermal shutdown.
PLC_CMP_OU
T
0
In slave mode, this bit indicates if VPLC is greater
than the PLC detection threshold (VPLC_DET). In
master mode, this bit indicates whether VPLC is less
than the short-circuit detection threshold (VPLC_SHT).
0x0: VPLC ≤ VPLC_DET.
0x1: VPLC > VPLC_DET.
DEV_STATUS_IRQ (0x7)
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Maxim Integrated | 26
MAX20340
BIT
Bidirectional DC Powerline
Communication Management IC
7
6
5
4
3
2
1
0
Field
—
VPLC_SHOR
Ti
THM_SHDNi
RSEL_DONEi
LDO_DROP_
ERRi
CHG_TMR_S
TATi
PLC_STATi
FSM_STATi
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
—
7
Reserved
VPLC_SHORTi
6
PLC Short Circuit Indicator
0x0: No short circuit detected on the PLC line.
0x1: Short circuit detected on the PLC line.
THM_SHDNi
5
Thermal Shutdown Status Indicator
0x0: Temperature below the thermal shutdown threshold.
0x1: Temperature above the thermal shutdown threshold.
RSEL_DONEi
4
RSEL Measurement Status Indicator
0x0: RSEL measurement not yet completed.
0x1: RSEL measurement completed.
LDO_DROP_E
RRi
3
LDO Drop Error Status Change Indicator
0x0: LDO is not in dropout condition.
0x1: LDO is in dropout condition.
CHG_TMR_ST
ATi
2
CHG_TMR_STAT Status Change Interrupt
0x0: No change in CHG_TMR_STAT since last read.
0x1: Change in CHG_TMR_STAT (from running to
expired).
PLC_STATi
1
PLC_STAT Status Change Interrupt
0x0: No change in PLC_STAT since last read.
0x1: Change in PLC_STAT since last read.
FSM_STATi
0
FSM_STAT Status Change Interrupt
0x0: No change in FSM_STAT since last read.
0x1: Change in FSM_STAT since last read.
DEV_STATUS_MASK (0x8)
BIT
7
6
5
4
3
2
1
0
Field
—
VPLC_SHOR
Tm
THM_SHDN
m
RSEL_DONE
m
LDO_DROP_
ERRm
CHG_TMRm
PLC_STATm
FSM_STATm
Reset
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
—
7
Reserved. Do not change the default value.
VPLC_SHORT
m
6
VPLC_SHORTi Interrupt Mask
0x0: Interrupt masked
0x1: Interrupt not masked
THM_SHDNm
5
THM_SHDNi Interrupt Mask
0x0: Interrupt masked
0x1: Interrupt not masked
RSEL_DONEm
4
RSEL_DONEi Interrupt Mask
0x0: Interrupt masked
0x1: Interrupt not masked
LDO_DROP_E
RRm
3
LDO_DROP_ERRi Interrupt Mask
0x0: Interrupt masked
0x1: Interrupt not masked
CHG_TMRm
2
CHG_TMR_STATi Interrupt Mask
0x0: Interrupt masked
0x1: Interrupt not masked
PLC_STATm
1
PLC_STATi Interrupt Mask
0x0: Interrupt masked
0x1: Interrupt not masked
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Maxim Integrated | 27
MAX20340
BITFIELD
Bidirectional DC Powerline
Communication Management IC
BITS
FSM_STATm
DESCRIPTION
0
DECODE
0x0: Interrupt masked
0x1: Interrupt not masked
FSM_STATi Interrupt Mask
PLC_COM_CTRL (0x9)
BIT
7
6
5
4
3
2
1
0
Field
PLC_SINK[1:0]
FREQ[1:0]
PARITY[1:0]
TX[1:0]
Reset
0x2
0x1
0x1
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
PLC_SINK
7:6
PLC Sink Current
0x0: 206mA
0x1: 252mA
0x2: 298mA (default)
0x3: 366mA
FREQ
5:4
Communication Frequency, Unit Time
0x0: 6µs
0x1: 24µs (default)
0x2: 192µs
0x3: 1536µs
PARITY
3:2
Parity bit
0x0: No parity (parity bit is ignored)
0x1: Odd
0x2: Even
0x3: No parity (parity bit is ignored)
1:0
PLC Transmit. Autoclears to 0b00 at the end of
transmission.
0x0: No action.
0x1: Send one byte stored in register 0x0D.
0x2: Send two bytes stored in registers 0x0E and 0x0F.
0x3: Send three bytes stored in registers 0x0D, 0x0E and
0x0F.
TX
PLC_STATUS (0xA)
BIT
7
6
5
4
3
2
1
0
Field
PLC_TMR_E
RR
PLC_TX_ER
R
PLC_TX_OK
PLC_TX_P
PLC_RX_ER
R
NEW_DATA1
NEW_DATA2
PLC_RX_DE
T
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Access Type
BITFIELD
BITS
PLC_TMR_ER
R
7
PLC Rx Timer Status. Master mode only.
0x0: Rx wait timer running or in idle.
0x1: Rx wait timer expired.
PLC_TX_ERR
6
PLC Transmission Error Indicator. This bit is cleared
when a new PLC send command is issued.
0x0: No Tx error
0x1: Tx error
PLC_TX_OK
5
PLC Transmission Success Indicator. This bit is
cleared when a new PLC send command is issued.
0x0: Not successful
0x1: Successful
PLC_TX_P
4
PLC Transmission Status Indicator
0x0: Not transmitting
0x1: PLC transmission in progress
PLC_RX_ERR
3
PLC Rx Error Status
0x0: No error
0x1: Error (start bit, parity, checksum, or stalled line)
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DESCRIPTION
DECODE
Maxim Integrated | 28
MAX20340
BITFIELD
Bidirectional DC Powerline
Communication Management IC
BITS
DESCRIPTION
DECODE
NEW_DATA1
2
When a new data byte is available in register
RX_DATA0 (reg 0x10), this bit is set. Once the
RX_DATA0 register is read, this bit is cleared.
0x0: No new data byte
0x1: One new data byte arrived
NEW_DATA2
1
When two new data bytes are available in the
RX_DATA1 and RX_DATA2 registers (0x11 and
0x12), this bit is set.
0x0: No new data bytes
0x1: Two new data bytes arrived
PLC_RX_DET
0
PLC Receiving Detection. Only during preamble
and data.
0x0: No PLC (within 4-bit length of no or invalid signal)
0x1: PLC is ongoing (within 4 bits of preamble signal)
PLC_IRQ (0xB)
BIT
7
6
5
4
3
2
1
0
Field
PLC_TMRi
PLC_TX_ER
Ri
PLC_TX_OKI
PLC_TX_Pi
PLC_RX_ER
Ri
NEW_DATA1i
NEW_DATA2i
PLC_RX_DE
Ti
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Read Clears
All
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
PLC_TMRi
7
PLC Rx Wait Timer Expiration Interrupt
0x0: Interrupt has not occurred
0x1: Interrupt occurred
PLC_TX_ERRi
6
PLC Transmission ERROR Interrupt
0x0: Interrupt Not occurred
0x1: Interrupt occurred
PLC_TX_OKI
5
PLC Transmission Success Interrupt
0x0: Interrupt not occurred
0x1: Interrupt occurred
PLC_TX_Pi
4
PLC Transmission in Progress Interrupt
0x0: Interrupt not occurred
0x1: Interrupt occurred
PLC_RX_ERRi
3
PLC Rx Error Interrupt
0x0: Interrupt not occurred
0x1: Interrupt occurred
NEW_DATA1i
2
NEW_DATA1 Interrupt
0x0: Interrupt not occurred
0x1: Interrupt occurred
NEW_DATA2i
1
NEW_DATA2 Interrupt
0x0: Interrupt not occurred
0x1: Interrupt occurred
PLC_RX_DETi
0
PLC Receiving Detection Interrupt
0x0: Interrupt not occurred
0x1: Interrupt occurred
PLC_MASK (0xC)
BIT
7
6
5
4
3
2
1
0
Field
PLC_TMRm
PLC_TX_ER
Rm
PLC_TX_OK
m
PLC_TX_Pm
PLC_RX_ER
Rm
NEW_DATA1
m
NEW_DATA2
m
PLC_RX_DE
Tm
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
Access Type
BITFIELD
PLC_TMRm
BITS
7
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DESCRIPTION
PLC_TMRi Interrupt Mask
DECODE
0x0: Masked
0x1: Not masked
Maxim Integrated | 29
MAX20340
Bidirectional DC Powerline
Communication Management IC
BITFIELD
BITS
DESCRIPTION
DECODE
PLC_TX_ERR
m
6
PLC_TX_ERRi Interrupt Mask
0x0: Masked
0x1: Not masked
PLC_TX_OKm
5
PLC_TX_OKi Interrupt Mask
0x0: Masked
0x1: Not masked
PLC_TX_Pm
4
PLC_TX_Pi Interrupt Mask
0x0: Masked
0x1: Not masked
PLC_RX_ERR
m
3
PLC_RX_ERRi Interrupt Mask
0x0: Masked
0x1: Not masked
NEW_DATA1m
2
NEW_DATA1i Interrupt Mask
0x0: Masked
0x1: Not masked
NEW_DATA2m
1
NEW_DATA2i Interrupt Mask
0x0: Masked
0x1: Not masked
PLC_RX_DET
m
0
PLC_RX_DETi Interrupt Mask
0x0: Masked
0x1: Not masked
TX_DATA0 (0xD)
BIT
7
6
5
4
3
Field
TXDATA0[7:0]
Reset
0x0
Access Type
2
1
0
1
0
1
0
Write, Read
BITFIELD
BITS
TXDATA0
DESCRIPTION
7:0
Transmit Data Byte 0
TX_DATA1 (0xE)
BIT
7
6
5
4
3
Field
TXDATA1[7:0]
Reset
0x0
Access Type
2
Write, Read
BITFIELD
BITS
TXDATA1
DESCRIPTION
7:0
Transmit Data Byte 1
TX_DATA2 (0xF)
BIT
7
6
5
4
3
Field
TXDATA2[7:0]
Reset
0x0
Access Type
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2
Write, Read
Maxim Integrated | 30
MAX20340
Bidirectional DC Powerline
Communication Management IC
BITFIELD
BITS
TXDATA2
DESCRIPTION
7:0
Transmit Data Byte 2
RX_DATA0 (0x10)
BIT
7
6
5
4
3
Field
RXDATA0[7:0]
Reset
0x0
Access Type
2
1
0
1
0
1
0
Read Only
BITFIELD
BITS
RXDATA0
DESCRIPTION
7:0
Receive Data Byte 0
RX_DATA1 (0x11)
BIT
7
6
5
4
3
Field
RXDATA1[7:0]
Reset
0x0
Access Type
2
Read Only
BITFIELD
BITS
RXDATA1
DESCRIPTION
7:0
Receive Data Byte 1
RX_DATA2 (0x12)
BIT
7
6
5
4
3
Field
RXDATA2[7:0]
Reset
0x0
Access Type
BITFIELD
RXDATA2
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2
Read Only
BITS
7:0
DESCRIPTION
Receive Data Byte 2
Maxim Integrated | 31
MAX20340
Bidirectional DC Powerline
Communication Management IC
Typical Application Circuits
Wireless Earbud Charging with Cradle
EARBUD1
BLUETOOTH AUDIO
HA+
HAMIC
BATTERY CHARGER
CHARGING CASE
CHRGIN
VSYS
USB
CONNECTOR
POWER PATH
CHARGER
BUCK-BOOST
CONVERTER
VIO
BAT
VCC
PLC
MAX20340
GND
VIO
SCL
SDA
PLC SLAVE
BAT
MICRO
GND
BAT
SCL
SDA
RSEL
VCC
MAX20340
PLC
PLC MASTER
GND
EARBUD2
RSEL
BLUETOOTH AUDIO
HA+
HAMIC
BATTERY CHARGER
CHRGIN
GND
BAT
VIO
BAT
VCC
PLC
GND
MAX20340
SCL
SDA
PLC SLAVE
RSEL
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Maxim Integrated | 32
MAX20340
Bidirectional DC Powerline
Communication Management IC
Ordering Information
PART NUMBER
PIN-PACKAGE
TOP MARKING
PACKAGE CODE
PACKAGE OUTLINE
MAX20340EWL+
9 WLP
ALT
W91R1+1
21-100389
MAX20340EWL+T
9 WLP
ALT
W91R1+1
21-100389
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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Maxim Integrated | 33
MAX20340
Bidirectional DC Powerline
Communication Management IC
Revision History
REVISION
REVISION
NUMBER
0
DATE
11/19
www.maximintegrated.com
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim Integrated | 34
Click here for production status of specific part numbers.
MAX20340
Bidirectional DC Powerline
Communication Management IC
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
c 2019 Maxim Integrated Products, Inc.
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