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MAX22700D–MAX22702D
MAX22700E–MAX22702E
General Description
The MAX22700–MAX22702 are a family of single-channel isolated gate drivers with ultra-high common-mode
transient immunity (CMTI) of 300kV/µs (typ). The devices
are designed to drive silicon-carbide (SiC) or galliumnitride (GaN) transistors in various inverter or motor
control applications. All devices have integrated digital
galvanic isolation using Maxim’s proprietary process technology. The devices feature variants with output options
for gate driver common pin GNDB (MAX22700), Miller
clamp (MAX22701), and adjustable undervoltage-lockout
UVLO (MAX22702). In addition, variants are offered as
differential (D versions) or single-ended (E versions)
inputs. These devices transfer digital signals between
circuits with different power domains. All of the devices in
the family feature isolation for a withstand voltage rating
of 3kVRMS for 60 seconds.
All devices support a minimum pulse width of 20ns with a
maximum pulse width distortion of 2ns. The part-to-part
propagation delay is matched within 2ns (max) at +25°C
ambient temperature, and 5ns (max) over the -40°C
to +125°C operating temperature range. This feature
reduces the power transistor’s dead time, thus improving
overall efficiency.
The MAX22700 and the MAX22702 have a maximum
RDSON of 1.25Ω for the low-side driver, and the MAX22701
has an RDSON of 2.5Ω for the low-side driver. All devices
have a maximum RDSON of 4.5Ω for the high-side driver.
See the Ordering Information for suffixes associated with
each option.
The MAX22700–MAX22702 can be used to drive SiC or
GaN FETs with different output gate drive circuitry and
B-side supply voltages. See the Typical Operating Circuits
for details.
All of the devices in the MAX22700–MAX22702 family
are available in an 8-pin, narrow-body SOIC package with
4mm of creepage and clearance. The package material
has a minimum comparative tracking index (CTI) of 600V,
which gives it a group I rat
ing in creepage tables. All
devices are rated for operation at ambient temperatures
of -40°C to +125°C.
19-100581; Rev 2; 9/19
Ultra-High CMTI
Isolated Gate Drivers
Benefits and Features
●● Matching Propagation Delay
• 20ns Minimum Pulse Width
• 35ns Propagation Delay at Room Temperature
• 2ns Part-to-Part Propagation Delay Matching at
Room Temperature
• 5ns Part-to-Part Propagation Delay Matching over
-40°C to +125°C Temperature Range
●● High CMTI (300kV/µs, typ)
●● Robust Galvanic Isolation
• Withstands 3kVRMS for 60s (VISO)
• Continuously Withstands 848VRMS (VIOWM)
• Withstands ±5kV Surge Between GNDA and VSSB
with 1.2/50μs Waveform
●● Precision UVLO
●● Options to Support a Broad Range of Applications
• 3 Output Options: GNDB, Miller Clamp, or
Adjustable UVLO
• 2 Input Configurations: Single-Ended with Enable
(E versions) or Differential (D versions)
Applications
●● Isolated Gate Driver for Inverters
●● Motor Drives
●● UPS and PV Inverters
Safety Regulatory Approvals
●● UL According to UL1577
●● cUL According to CSA Bulletin 5A
Ordering Information appears at end of data sheet.
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Absolute Maximum Ratings
VDDA to GNDA.........................................................-0.3V to +6V
VDDB to GNDB.......................................................-0.3V to +40V
GNDB to VSSB.......................................................-0.3V to +40V
VDDB to VSSB........................................................-0.3V to +40V
INP, INN, IN, EN to GNDA.......................................-0.3V to +6V
VDDB to ADJ.............................................................-0.3V to +6V
CLAMP to VSSB...................................... -0.3V to (VDDB + 0.3V)
OUT to VSSB........................................... -0.3V to (VDDB + 0.3V)
Continuous Power Dissipation (TA = +70°C)
Narrow SOIC (derate 9.39mW/°C above +70°C).......750.89mW
Operating Temperature Range.......................... -40°C to +125°C
Maximum Junction Temperature......................................+150°C
Storage Temperature Range............................. -60°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 8 NARROW SOIC
Package Code
S8MS+23
Outline Number
21-0041
Land Pattern Number
90-0096
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
106.54°C/W
Junction to Case (θJC)
44.91°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
VDDA
Supply Voltage
Differential Supply
Relative to GNDA
3
5.5
Relative to GNDB, MAX22700
13
36
Relative to VSSB, MAX22701
13
36
Relative to VSSB, MAX22702
6
36
VSSB
Relative to GNDB, MAX22700
-16
0
VDIFF
VDDB - VSSB, MAX22700
VDDB
13
V
36
Undervoltage-Lockout
Threshold
VUVLOAP
VDDA rising
2.69
2.82
2.95
V
VUVLOAN
VDDA falling
2.59
2.72
2.85
V
Undervoltage-Lockout
Threshold Hysteresis
VUVLOA_HYST
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100
mV
Maxim Integrated │ 2
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
DC Electrical Characteristics (continued)
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Undervoltage-Lockout
Threshold
Undervoltage-Lockout
Threshold Hysteresis
SYMBOL
CONDITIONS
VUVLOBP
VDDB rising, relative to GNDB, MAX22700
VUVLOBN
VDDB falling, relative to GNDB, MAX22700
VUVLOBP
VDDB rising, relative to VSSB, MAX22701
VUVLOBN
VDDB falling, relative to VSSB, MAX22701
VUVLOBP
VDDB rising, relative to ADJ, MAX22702
VUVLOBN
VDDB falling, relative to ADJ, MAX22702
VUVLOB_HYST
MIN
11.6
TYP
MAX
13
13.3
12
13
11.6
13.3
12
2
1.79
MAX22700, MAX22701
V
2.05
1.84
1
MAX22702
UNITS
V
0.16
SUPPLY CURRENT
VDDA = 5V, INN/EN = VDDA
5
6.5
VDDA = 3.3V, INN/EN = VDDA
3
4
VDDA = 5V, fPWM = 1MHz
5
6.5
VDDA = 3.3V, fPWM = 1MHz
3
4
3.5
6
mA
6
10
mA
A-Side Quiescent
Supply Current
IDDA
A-Side Active Supply Current
IDDA
B-Side Quiescent
Positive Supply Current
IDDB
INN/EN = VDDA
B-Side Active
Positive Supply Current
IDDB
fPWM = 1MHz (Note 2)
B-Side Ground Current
IGNDB
LOGIC INTERFACE (INP, INN, IN, EN)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
MAX22700
mA
mA
-25
µA
0.7 x
VDDA
V
0.3 x
VDDA
0.1 x
VDDA
VHYS
V
mV
Input Pullup Current (Note 3)
IPU
INN, EN
-10
-5
-1.5
µA
Input Pulldown Current (Note 3)
IPD
INP, IN
1.5
5
10
µA
Input Capacitance
CIN
fPWM = 1MHz
IADJ
VDDB - VADJ = 3V
2
pF
ADJ (MAX22702 ONLY)
Input Leakage Current
-100
100
nA
4.7
Ω
MAX22700/MAX22702
1.25
Ω
MAX22701
2.5
Ω
GATE DRIVER
High-Side Transistor
On-Resistance
RDSON_H
IOUT = -100mA (Note 3)
Low-Side Transistor
On-Resistance
RDSON_L
IOUT = 100mA
(Note 3)
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Maxim Integrated │ 3
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
DC Electrical Characteristics (continued)
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output-Voltage High
VOH
IOUT = -10mA (Note 3)
Output-Voltage Low
VOL
IOUT = 10mA
(Note 3)
High-Side Transistor
Peak Output Current
IOH
CL = 10nF, fPWM = 1kHz (Note 2)
2.35
4
Low-Side Transistor
Peak Output Current
IOL
CL = 10nF,
fPWM = 1kHz
(Note 2)
MAX22700/MAX22702
3.7
5.7
MAX22701
1.9
2.85
Active Pulldown Voltage
VOUTSD
MAX
19.95
MAX22700/MAX22702
0.01
MAX22701
0.02
UNITS
V
V
A
A
IOUT = 150mA (Note 3)
2.2
V
ICLAMP = 100mA (Note 3)
2.5
Ω
2.3
V
MILLER CLAMP (MAX22701 ONLY)
Miller Clamp Transistor
On-Resistance
RDSON_CLMP
Miller Clamp Threshold
VTH_CLMP
Miller Clamp Turn-On Time
tON
1.7
See Figure 4
2
20
ns
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
TSHDN
160
°C
Thermal-Shutdown Hysteresis
TSHDN_HYS
25
°C
Dynamic Characteristics
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Common-Mode Transient Immunity
CMTI
Minimum Pulse Width
Maximum PWM Frequency
PWMIN
Propagation Delay
(Figure 3)
tPHL
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tPM
MIN
TYP
MAX
300
CL = 200pF
1
CL = 200pF,
output is not
connected to
CLAMP pin
(MAX22701)
(Note 4)
CL = 200pF
(Note 4)
UNITS
kV/µs
20
fPWM
tPLH
Part-to-Part Propagation Delay
Matching (Figure 3)
CONDITIONS
(Note 5)
ns
MHz
TA = +25°C to +125°C
34
39
TA = +25°C
34
TA = -40°C to +25°C
31
36
TA = +25°C to +125°C
34
39
TA = +25°C
34
TA = -40°C to +25°C
31
35
35
36
ns
36
36
TA = +25°C
2
TA = -40°C to +125°C,
parts at the same
temperature
5
ns
Maxim Integrated │ 4
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Dynamic Characteristics (continued)
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB = 0V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
Pulse Width Distortion
Peak Eye Diagram Jitter
Rise Time
(Figure 3)
Fall Time
(Figure 3)
SYMBOL
PWD
TJIT(PK)
CONDITIONS
MIN
TYP
CL = 200pF, |tPLH - tPHL|
1MHz square wave, CL = 200pF
tR
CL = 200pF, 20% to 80% (Note 2)
tF
CL = 200pF,
80% to 20%
(Note 2)
MAX
UNITS
2
ns
60
ps
3.6
ns
MAX22700/
MAX22702
1.8
ns
MAX22701
2.5
ns
Note 1: All devices are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design and characterization.
Note 2: Not production tested. Guaranteed by design and characterization.
Note 3: All currents into the device are positive. All currents out of the device are negative. All voltages are referenced to their
respective ground (GNDA or VSSB), unless otherwise noted.
Note 4: Propagation delay is measured from 50% of the input to 2V at the output.
Note 5: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to
both rising and falling common-mode voltage edges. CMTI is tested with the transient generator connected between GNDA
and VSSB (VCM = 1000V).
ESD Protection
PARAMETER
ESD
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SYMBOL
CONDITIONS
Human Body Model, All Pins
MIN
TYP
±4
MAX
UNITS
kV
Maxim Integrated │ 5
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Table 1. Insulation Characteristics
PARAMETER
Partial Discharge Test Voltage
SYMBOL
VPR
CONDITIONS
VALUE
UNITS
Method B1 = VIORM x 1.875
(t = 1s, partial discharge < 5pC)
2250
VP
Maximum Repetitive Peak Isolation Voltage
VIORM
(Note 6)
1200
VP
Maximum Working Isolation Voltage
VIOWM
Continuous RMS voltage (Note 6)
848
VRMS
Maximum Transient Isolation Voltage
VIOTM
t = 1s (Note 6)
4242
VP
Maximum Withstand Isolation Voltage
VISO
fSW = 60Hz, duration = 60s (Note 6, 7)
3000
VRMS
5
kV
Maximum Surge Isolation Voltage
Insulation Resistance
VIOSM
RIO
Basic insulation, 1.2/50µs pulse per
IEC 61000-4-5 (Note 6)
VIO = 500V, TA = 25°C
>1012
VIO = 500V, 100°C ≤ TA ≤ 125°C
>1011
VIO = 500V at TS = 150°C
>109
Ω
Barrier Capacitance Side A to Side B
CIO
fSW = 1MHz (Note 8)
1
pF
Minimum Creepage Distance
CPG
Narrow SOIC
4
mm
Minimum Clearance Distance
CLR
Narrow SOIC
4
mm
Distance through insulation
0.015
mm
Material Group I (IEC 60112)
>600
Internal Clearance
Comparative Tracking Index
CTI
Climate Category
Pollution Degree
(DIN VDE 0110, Table 1)
40/125/21
2
Note 6: VISO, VIOTM, VIOSM, VIOWM, and VIORM are defined by the IEC 60747-5-5 standard.
Note 7: Product is qualified at VISO for 60s and 100% production tested at 120% of VISO for 1s.
Note 8: Capacitance is measured with all pins on side A and side B tied together.
Safety Regulatory Approvals
UL
The MAX22700–MAX22702 are certified under UL1577. For more details, refer to file E351759.
Rated up to 3000VRMS isolation voltage for single protection.
cUL (Equivalent to CSA notice 5A)
The MAX22700–MAX22702 are certified up to 3000VRMS for single protection. For more details, refer to file E351759.
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Maxim Integrated │ 6
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Safety Limits
Damage to the IC can result in a low-resistance path
to ground or to the supply and, without current limiting,
the MAX22700–MAX22702 could dissipate excessive
amounts of power. Excessive power dissipation can damage the die and result in damage to the isolation barrier,
potentially causing long-term reliability issues. Table 2
shows the safety limits for the MAX22700–MAX22702.
The maximum safety temperature (TS) for the device is
the +150°C maximum junction temperature specified in
the Absolute Maximum Ratings. The power dissipation
(PD) and junction-to-ambient thermal impedance (θJA)
THERMAL DERATING CURVE
FOR SAFETY POWER LIMITING
1400
determine the junction temperature. Thermal impedance values (θJA and θJC) are available in the Package
Information section of the data sheet and power dissipation calculations are discussed in the Calculating Power
Dissipation section. Calculate the junction temperature
(TJ) as:
TJ = TA + (PD × θJA)
Figure 1 and Figure 2 show the thermal derating curve
for safety limiting the power and the current of the device.
Ensure that the junction temperature does not exceed
+150°C.
THERMAL DERATING CURVE
FOR SAFETY CURRENT LIMITING
fig01
350
MULTILAYER BOARD
300
SAFE CURRENT LIMIT (mA)
1200
SAFE POWER LIMIT (mW)
1000
800
600
400
200
0
fig02
MULTILAYER BOARD
250
200
150
100
50
0
25
50
75
100
125
150
175
0
200
0
25
50
75
100
125
150
175
200
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 1. Thermal Derating Curve for Safety Power Limiting
Figure 2. Thermal Derating Curve for Safety Current Limiting
Table 2. Safety Limiting Values for the MAX22700–MAX22702
PARAMETER
Safety Operating Current on
B-Side Pins
SYMBOL
IOUT
TEST CONDITIONS
TJ = 150°C, TA = 25°C, IN = Low,
OUT = VDDB, OUT = Low during
thermal shutdown
MAX
UNIT
VDDB = 36V
32
mA
VDDB = 20V
57
mA
Safety Current on Any Pins (No
Damage to Isolation Barrier)
IS
TJ = 150°C, TA = 25°C
300
mA
Total Safety Power Dissipation
PS
TJ = 150°C, TA = 25°C
1173
mW
Maximum Safety Temperature
TS
150
°C
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Maxim Integrated │ 7
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Test Circuits and Timing Diagrams
VDDA
VDDA
IN
MAX2270_E
IN
TEST
SOURCE
VDDB
VDDB
VDDA
OUT
EN
GNDA
OUT1
IN
CL
200pF
50%
GNDA
VSSB
50%
tPLH
tPHL
VDDB
OUT1
VSSB
2V
2V
tPM
tPM
VDDB
VDDA
OUT2
MAX2270_E
IN
OUT
OUT2
EN
GNDA
VDDB
VSSB
CL
200pF
80%
20%
2V
2V
tR
tF
VSSB
(A)
(B)
Figure 3. Test Circuit (A) and Timing Diagram (B)
VDDA
INPUT
SOURCE
VDDA
VDDA
MAX22701E
IN
INPUT
SOURCE
CLAMP
EN
GNDA
GNDA
VDDB
VDDB
VDDB
TEST
SOURCE
50Ω
CL
200pF
VSSB
TEST
SOURCE
VDDB
VSSB
VTH_CLMP = 2V
CLAMP
VSSB
tON = 20ns
(A)
(B)
Figure 4. MAX22701 Miller Clamp Test Circuit (A) and Timing Diagram (B)
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Maxim Integrated │ 8
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Characteristics
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB, TA = +25°C, unless otherwise noted.)
HIGH-SIDE PEAK OUTPUT CURRENT
vs. VDDB SUPPLY VOLTAGE
6.0
8
CL = 0.1µF, SERIES RESISTOR RS = 0.5Ω
5.5
5
4.0
3.5
3.0
5
2.0
1
20
24
28
32
36
3
2
3
2
16
MAX22700/2
4
2.5
12
4
6
RDSON (Ω)
4.5
VDDB
VDDB == 13V
13V
VDDB
VDDB = 20V
VDDB = 36V
VDDB
1
MAX22701
6
12
18
24
30
0
36
-50
-25
0
5
LOW-SIDE TRANSISTOR RDSON
vs. TEMPERATURE
toc04
3.0
3
75
1
2.5
0.9
2.0
0.8
1.5
0
-50
-25
0
25
50
75
100
VDDB
VDDB==13V
13V
VDDB
VDDB==20V
20V
VDDB
VDDB==36V
36V
0.0
125
-50
-25
0
25
50
75
100
5.5
MAX22700/MAX22701
INP/IN = GNDA, INN/EN = VDDA, CL = 0pF
SUPPLY CURRENT (mA)
3.6
3.4
VDDB
VDDB ==13V
13V
VDDB
VDDB ==20V
20V
VDDB
VDDB ==25V
25V
VDDB ==36V
36V
VDDB
3.2
25
50
75
TEMPERATURE (°C)
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25
50
100
100
125
toc08
4.0
3.5
VDDB==6V
6V
VDDB
VDDB==13V
13V
VDDB
VDDB==20V
20V
VDDB
VDDB==36V
36V
VDDB
3.0
125
75
4.5
2.5
0
0
MAX22702
INP/IN = GNDA, INN/EN = VDDA, CL = 0pF
5.0
3.8
-25
-25
TEMPERATURE (°C)
toc07
4.0
-50
-50
VDDB SUPPLY CURRENT
vs. TEMPERATURE
VDDB SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT (mA)
0.4
TEMPERATURE (°C)
TEMPERATURE (°C)
3.0
VDDB
VDDB ==6V
6V
VDDB
VDDB ==13V
13V
VDDB
VDDB ==20V
20V
VDDB
VDDB ==36V
36V
0.5
125
toc06
0.7
0.6
1.0
0.5
125
MAX22700/MAX22702, IOUT = 100mA
VDDB = 6V ONLY APPLIES TO MAX22702
2
VDDB
6V
VDDB == 6V
VDDB
VDDB = 13V
VDDB
VDDB = 20V
VDDB
VDDB = 36V
100
1.0
RDSON (Ω)
RDSON (Ω)
4
50
LOW-SIDE TRANSISTOR RDSON
vs. TEMPERATURE
toc05
MAX22701, IOUT = 100mA
MAX22702, IOUT = 100mA
25
TEMPERATURE (°C)
VDDB SUPPLY VOLTAGE (V)
HIGH-SIDE TRANSISTOR RDSON
vs. TEMPERATURE
toc03
MAX22700/MAX22701, IOUT = 100mA
7
5.0
VDDB SUPPLY VOLTAGE (V)
RDSON (Ω)
HIGH-SIDE TRANSISTOR RDSON
vs. TEMPERATURE
toc02
CL = 0.1µF, SERIES RESISTOR RS = 0.5Ω
PEAK OUTPUT CURRENT (A)
PEAK OUTPUT CURRENT (A)
LOW-SIDE PEAK OUTPUT CURRENT
vs. VDDB SUPPLY VOLTAGE
toc01
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Maxim Integrated │ 9
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Characteristics (continued)
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB, TA = +25°C, unless otherwise noted.)
VDDB SUPPLY CURRENT
vs. PWM FREQUENCY
10
5.0
CL = 200pF, VDDB = 20V
VDDA SUPPLY CURRENT
vs. TEMPERATURE
toc10
7
6
5
4.0
3.5
3.0
4
2
6
5
4
3
2.5
3
0
200
400
600
800
2.0
1000
2
0
40
PWM FREQUENCY (kHz)
VDDA SUPPLY CURRENT
vs. PWM FREQUENCY
6.0
80
120
160
1
200
-50
RISE TIME AND FALL TIME
vs. LOAD CAPACITANCE
25
5.0
4.5
4.0
20
15
0
200
400
600
800
1000
tR
4
38
34
0
25
50
75
TEMPERATURE (°C)
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1
2
3
100
5
toc16
35
VDDB
6V
VDDB ==6V
VDDB
15V
VDDB ==15V
VDDB
20V
VDDB ==20V
VDDB ==36V
VDDB
36V
34
125
4
36
33
-25
0
SERIES RESISTOR RS = 0Ω,
CL = 200pF, tPHL
VDDB = 6V ONLY APPLIES TO MAX22702
37
VDDB
VDDB = 6V
VDDB
VDDB = 15V
VDDB = 20V
VDDB
VDDB = 36V
VDDB
-50
tF
LOAD CAPACITANCE (nF)
SERIES RESISTOR RS = 0Ω,
CL = 200pF, tPLH
VDDB = 6V ONLY APPLIES TO MAX22702
35
toc14
20
0
5
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
3
toc15
36
33
2
125
tR
PROPAGATION DELAY
vs. TEMPERATURE
PROPAGATION DELAY
vs. TEMPERATURE
37
30
LOAD CAPACITANCE (nF)
PWM FREQUENCY (kHz)
38
1
100
40
10
0
75
SERIES RESISTOR RS = 5Ω
5
3.5
50
50
tF
10
25
RISE TIME AND FALL TIME
vs. LOAD CAPACITANCE
toc13
RISE AND FALL TIME (ns)
RISE AND FALL TIME (ns)
SUPPLY CURRENT (mA)
5.5
0
0
TEMPERATURE (°C)
SERIES RESISTOR RS = 0Ω
3.0
-25
LOAD CAPACITANCE (pF)
toc12
VDDA
VDDB == 3V
3V
VDDA
VDDB = 3.3V
VDDA
VDDB = 5V
VDDA
VDDB = 5.5V
INP/IN = GNDA,
INN/EN = VDDA,
CL = 0pF
7
4.5
SUPPLY CURRENT (mA)
8
toc11
8
INPUT = 100kHz SQUARE WAVE, VDDB = 20V
SUPPLY CURRENT (mA)
9
SUPPLY CURRENT (mA)
VDDB SUPPLY CURRENT
vs. LOAD CAPACITANCE
toc09
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C)
Maxim Integrated │ 10
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Characteristics (continued)
(VDDA - VGNDA = 5V, VDDB - VSSB = 20V, VGNDA = VSSB, TA = +25°C, unless otherwise noted.)
toc17
1.0
SERIES RESISTOR RS = 0Ω, CL = 200pF
VDDB = 20V
PROPAGATION DELAY MATCHING (ns)
PROPAGATION DELAY MATCHING (ns)
1.0
PART-TO-PART
PROPAGATION DELAY MATCHING
vs. VDDB SUPPLY VOLTAGE
0.6
RISING EDGE
0.2
-0.2
FALLING EDGE
-0.6
-1.0
-50
-25
0
25
50
75
100
1.0
FALLING EDGE
0.2
-0.2
RISING EDGE
-0.6
6
12
TEMPERATURE (°C)
18
24
30
1.0
0.6
FALLING EDGE
0.2
-0.2
RISING EDGE
-0.6
-1.0
36
3.0
3.5
4.0
4.5
5.0
5.5
VDDA SUPPLY VOLTAGE (V)
VDDB UVLO vs. R2
toc20
toc21
15
MAX22702, R1 = 20kΩ (SEE FIGURE 13)
SERIES RESISTOR RS = 0Ω
VDDB SUPPLY VOLTAGE (V)
0.6
RISING EDGE
0.2
-0.2
FALLING EDGE
12
VDDB RISING
9
6
VDDB FALLING
3
-0.6
-1.0
toc19
SERIES RESISTOR RS = 0Ω, CL = 200pF
VDDB SUPPLY VOLTAGE (V)
PART-TO-PART
PROPAGATION DELAY MATCHING
vs. LOAD CAPACITANCE
PROPAGATION DELAY MATCHING (ns)
toc18
SERIES RESISTOR RS = 0Ω, CL = 200pF,
VDDB < 13V ONLY APPLIES TO MAX22702
0.6
-1.0
125
PART-TO-PART
PROPAGATION DELAY MATCHING
vs. VDDA SUPPLY VOLTAGE
PROPAGATION DELAY MATCHING (ns)
PART-TO-PART
PROPAGATION DELAY MATCHING
vs. TEMPERATURE
0
0
40
80
120
160
200
PART-TO-PART
PROPAGATION DELAY MATCHING
RISING EDGE
20
40
60
toc22
120
toc23
SERIES RESISTOR RS = 10Ω, CL = 200pF
5V/div
5V/div
VOUT1
VOUT1
VOUT2
VOUT2
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100
PART-TO-PART
PROPAGATION DELAY MATCHING
FALLING EDGE
SERIES RESISTOR RS = 10Ω, CL = 200pF
10ps/div
80
R2 RESISTANCE (kΩ)
LOAD CAPACITANCE (pF)
10ps/div
Maxim Integrated │ 11
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Pin Configurations
TOP VIEW
VDDA
1
INP
+
8
VSSB
2
7
GNDB
INN
3
6
GNDA
4
5
MAX22700D
VDDA
1
IN
OUT
VDDB
+
8
VSSB
2
7
GNDB
EN
3
6
OUT
GNDA
4
5
VDDB
8
VSSB
MAX22700E
NARROW SOIC
NARROW SOIC
TOP VIEW
VDDA
1
INP
+
+
VDDA
1
IN
2
7
CLAMP
OUT
EN
3
6
OUT
VDDB
GNDA
4
5
VDDB
8
VSSB
2
7
CLAMP
INN
3
6
GNDA
4
5
MAX22701D
MAX22701E
NARROW SOIC
NARROW SOIC
TOP VIEW
VDDA
1
INP
+
8
VSSB
2
7
INN
3
GNDA
4
MAX22702D
NARROW SOIC
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VDDA
1
ADJ
IN
6
OUT
5
VDDB
+
8
VSSB
2
7
ADJ
EN
3
6
OUT
GNDA
4
5
VDDB
MAX22702E
NARROW SOIC
Maxim Integrated │ 12
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Pin Description
NAME
PIN
MAX22700D MAX22700E MAX22701D MAX22701E MAX22702D MAX22702E
REF
SUPPLY
REF
GROUND
VDDA
1
1
1
1
1
1
VDDA
GNDA
INP
2
—
2
—
2
—
VDDA
GNDA
INN
3
—
3
—
3
—
VDDA
GNDA
IN
—
2
—
2
—
2
VDDA
GNDA
EN
—
3
—
3
—
3
VDDA
GNDA
GNDA
4
4
4
4
4
4
VDDA
GNDA
VDDB
5
5
5
5
5
5
VDDB
VSSB
OUT
6
6
6
6
6
6
VDDB
VSSB
GNDB
7
7
—
—
—
—
VDDB
VSSB
CLAMP
—
—
7
7
—
—
VDDB
VSSB
ADJ
—
—
—
—
7
7
VDDB
VSSB
VSSB
8
8
8
8
8
8
VDDB
VSSB
NAME
FUNCTION
POWER
VDDA
Power Supply Input for Side A (Transmitter Side). Bypass VDDA to GNDA with 1nF || 0.1µF || 1µF ceramic
capacitors as close as possible to the pin.
GNDA
Ground Reference for Side A (Transmitter Side).
VDDB
Positive Power Supply Input for Side B (Driver Side). Bypass VDDB to VSSB with 1nF || 0.1µF || 1µF ceramic
capacitors as close as possible to the pin. Place an additional 22µF capacitor between VDDB and VSSB.
VSSB
Negative Power Supply Input for Side B (Driver Side).
GNDB
(MAX22700) Gate Driver Common Pin. Connect to the power transistor’s source pin. The B-side UVLO is
referenced to GNDB in the MAX22700 versions.
INPUTS
INP
Non-Inverting PWM Input on Side A (D Versions). Has a weak internal pulldown. Connect the differential PWM
control inputs to INP and INN. Refer to Table 3 for Inputs vs. Output Truth table.
INN
Inverting PWM Input on Side A (D Versions). Has a weak internal pullup to VDDA. Connect the differential PWM
control inputs to INP and INN. Refer to Table 3 for Inputs vs. Output Truth table.
IN
Single-Ended PWM Input on Side A (E Versions). Has a weak internal pulldown. Refer to Table 4 for Inputs vs.
Output Truth table.
EN
Active-Low Enable on Side A (E Versions). Has a weak internal pullup to VDDA.
ADJ
(MAX22702) Adjustable UVLO Input on Side B. Connect external resistors between VDDB and ADJ and between ADJ and the power transistor’s source pin to adjust the B-side UVLO.
INPUT/OUTPUT
CLAMP
(MAX22701) Active Miller Clamp Input/Output on Side B. Prevents false turn-on of the power transistor.
OUTPUT
OUT
Gate Driver Output on Side B.
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Maxim Integrated │ 13
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Functional Diagrams
VDDA
IN
VDDA
VDDB
MAX22701D
INP
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
EN
VDDB
MAX22701E
OUT
INN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
VSSB
GNDA
CLAMP
CLAMP
2V
VSSB
VSSB
IN
EN
VDDB
MAX22700E
MAX22702E
UVLO
AND
LOGIC
INPUTS
GNDA
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
VDDA
INN
VSSB
GNDB/ADJ
The MAX22700–MAX22702 are a family of single-channel isolated gate drivers with an ultra-high CMTI of
300kV/µs (typ). All devices have integrated digital galvanic isolation with an isolation rating of 3kVRMS in an 8-pin,
narrow-body SOIC package. This family of devices offers
high common-mode transient immunity, high electromagnetic interference (EMI) immunity, and stable temperature
performance through Maxim’s proprietary process technology. The devices feature variants with output options
for gate driver common pin GNDB (MAX22700), Miller
clamp (MAX22701), and adjustable UVLO (MAX22702).
In addition, variants are offered as differential inputs INP
and INN (D versions) or single-ended input IN with enable
EN (E versions). Refer to the Ordering Information for details.
The MAX22700 has a gate driver common pin (GNDB)
that is a reference ground for VDDB and VSSB. VSSB
has a voltage range between -16V and 0V with reference
to GNDB. The MAX22701 has an active Miller clamp
pin, CLAMP, which prevents false turn-on of the external power transistor caused by the Miller current. The
VDDB
MAX22700D
MAX22702D
INP
OUT
Detailed Description
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VSSB
GNDA
2V
VDDA
OUT
UVLO
AND
LOGIC
INPUTS
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
GNDA
OUT
VSSB
GNDB/ADJ
MAX22702 provides an adjustable B-side UVLO, offering
design flexibility with different types of external power
transistors.
All devices support a minimum pulse width of 20ns with
maximum pulse-width distortion of 2ns. The part-to-part
propagation delay is matched within 2ns maximum at
+25°C ambient temperature, and is guaranteed to be
within 5ns maximum over the temperature range of -40°C
to +125°C.
All MAX22700–MAX22702 have a default-low output. The
default is the state the output assumes when the input is
either not powered or is open-circuit. The output is set to
logic-low when side A or side B supply is in UVLO, the
device is in thermal shutdown, or EN is high (E versions).
Output Driver Stage
The output driver stage of the MAX22700-MAX22702 features a pullup structure and a pulldown structure. The pullup structure consists of a PMOS transistor and a NMOS
transistor in parallel (see the Functional Diagrams). The
PMOS transistor has a maximum RDSON of 4.5Ω. The
Maxim Integrated │ 14
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
NMOS transistor only turns on for a short period of time
during the output low-to-high transition and provides a
boost current to enable the fast turn-on of the device. The
NMOS transistor has a much lower on-resistance than
the PMOS transistor; thus the parallel combination of the
NMOS and the PMOS enables a faster turn-on during the
output low-to-high transition.
The pulldown structure of the MAX22700–MAX22702
consists of a NMOS transistor. The NMOS transistor
in the MAX22700 and the MAX22702 has a maximum
RDSON of 1.25Ω, while the NMOS in the MAX22701 has
an RDSON of 2.5Ω. For the MAX22701, when both OUT
and CLAMP pins are connected to the gate of the external power transistor, an additional NMOS is connected
in parallel to the pulldown NMOS transistor to prevent
false turn-on of the external power transistor by providing an additional low-impedance path to VSSB. Refer to
Active Miller Clamp (MAX22701 Only) section and the
Functional Diagrams for details.
Digital Isolation
The MAX22700–MAX22702 provide basic galvanic isolation for digital signals transmitted between two ground
domains, and block high-voltage/high-current transients.
The devices withstand differences of up to 3kVRMS for up to
60 seconds, and up to 1200VPEAK of continuous isolation.
The devices have two supply inputs (VDDA and VDDB)
that independently set the logic levels on either side of
the device. VDDA and VDDB are referenced to GNDA and
VSSB, respectively. Logic input and output levels match
the supply voltages used in the associated power domain.
The difference in ground potential between the two power
domains may be as large as VIOWM for extended periods
of time and will withstand surge voltages up to 5kV. Data
transfer integrity is maintained for a differential ground
potential change up to 300kV/µs (typ).
Unidirectional Channel and Active Pulldown
The MAX22700–MAX22702 have an unidirectional channel that passes data in one direction, as indicated in the
Table 3. MAX2270_D Inputs vs. Output
Truth Table
Functional Diagrams. The two internal transistors in the
output driver are configured for push-pull operation and
feature an active pulldown function to turn off the external
power transistor when either side of the power supply is
in UVLO. This prevents the external power transistor from
falsely turning on during startup or UVLO.
INN vs. EN Function
The MAX2270_D features differential PWM inputs (INP
and INN). The differential inputs reject input glitches and
prevent false turn-on of the output. The output will hold
the previous value when a glitch is detected on either
input (Figure 5). The MAX2270_E features a single-ended
input (IN) and an active-low input enable (EN). The EN
pin allows the output (OUT) to be quickly set to logiclow, turning off the external power transistor. The output
remains at logic-low until the PWM input (IN) receives a
logic-high signal (Figure 6).
Current sources are used at both A-side inputs to prevent
the output from falsely turning on by input glitches or
noise. The INN pin has a weak pullup and the INP has a
weak pulldown in the MAX2270_D devices. The EN pin
has a weak pullup and the IN pin has a weak pulldown in
the MAX2270_E devices. Refer to Table 3 and Table 4 for
the Inputs vs. Output Truth Tables.
Undervoltage-Lockout (UVLO)
The VDDA and VDDB supplies are both internally monitored for undervoltage conditions. Undervoltage events
can occur during power-up, power-down, or during normal operation due to a sagging supply voltage. When
an undervoltage condition is detected on either supply,
the output is set to logic-low (default state) to turn off the
external power transistor, regardless of the state of the
MAX22700–MAX22702 inputs. The B-side UVLO has an
internal filter to reject any VDDB glitches less than 32µs
(typ) (see Figure 11 and Figure 12). Figure 7 through
Figure 10 show the behavior of the outputs during powerup and power-down.
Table 4. MAX2270_E Inputs vs. Output
Truth Table
INP
INN
OUT
IN
EN
OUT
Low
Low
Hold
Low
Low
Low
Low
High
Low
Low
High
Low (Default)
High
Low
High
High
Low
High
High
High
Hold
High
High
Low (Default)
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Maxim Integrated │ 15
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
H
INP
INN
LOGIC OUTPUT
L
L
HOLD
L
H
L
H
L
H
H
H
HOLD
INP
GLITCH
INP
GLITCH
INN
INN
L
H
OUT
FILTERED
L
H
FILTERED
L
OUT
(b)
(a)
H
INP
S
LOGIC
OUTPUT
R
INN
POR
INP
INP
GLITCH
INN
OUT
L
H
FILTERED
INN
L
H
GLITCH
FILTERED
L
OUT
(d)
(c)
Figure 5. MAX2270_D Differential Inputs
H
IN
EN
LOGIC OUTPUT
L
L
L
L
H
L
H
L
H
H
H
L
IN
EN
OUT
GLITCH
GLITCH
IN
EN
L
H
OUTPUT TURNS OFF
OUT
L
H
(b)
(a)
IN
EN
LOGIC
OUTPUT
FILTERED
L
H
IN
IN
EN
OUT
GLITCH
L
H
EN
OUT
L
H
GLITCH
FILTERED
L
OUTPUT TURNS OFF
(c)
(d)
Figure 6. MAX2270_E Single-Ended Input with Enable
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Maxim Integrated │ 16
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
VDDB POWER-UP AND POWER-DOWN
INPUT SET TO HIGH
VDDA POWER-UP AND POWER-DOWN
INPUT SET TO HIGH
EN OR INN = LOW
EN OR INN = LOW
fig08
fig07
VDDA
5V/div
VDDB
10V/div
VIN
5V/div
VOUT
10V/div
VDDA
5V/div
VDDB
10V/div
VIN
5V/div
VOUT
10V/div
400µs/div
400µs/div
Figure 7. VDDB Undervoltage Lockout Behavior (Input High)
Figure 8. VDDA Undervoltage Lockout Behavior (Input High)
VDDB POWER-UP AND POWER-DOWN
INPUT SET TO LOW
VDDA POWER-UP AND POWER-DOWN
INPUT SET TO LOW
EN OR INN = LOW
EN OR INN = LOW
fig09
fig10
VDDA
5V/div
VDDB
10V/div
VIN
5V/div
VOUT
10V/div
VDDA
5V/div
VDDB
10V/div
VIN
VOUT
400µs/div
10V/div
400µs/div
Figure 9. VDDB Undervoltage Lockout Behavior (Input Low)
VDDB GLITCH FILTER
5V/div
Figure 10. VDDA Undervoltage Lockout Behavior (Input Low)
VDDB GLITCH FILTER
fig11
fig12
EN OR INN = LOW, VDDB GLITCH 32µs
EN OR INN = LOW, VDDB GLITCH 28µs
VDDA
5V/div
VDDA
5V/div
VDDB
10V/div
VDDB
10V/div
VIN
VOUT
5V/div
VDDB UVLO IS NOT
TRIGGERED
10V/div
400µs/div
Figure 11. VDDB Undervoltage Lockout Glitch Filter,
UVLO Not Triggered
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VIN
5V/div
VDDB UVLO IS
TRIGGERED
VOUT
10V/div
400µs/div
Figure 12. VDDB Undervoltage Lockout Glitch Filter,
UVLO Triggered
Maxim Integrated │ 17
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Thermal Shutdown
The MAX22700–MAX22702 operate at an ambient temperature up to +125°C on a properly designed multilayer
PCB. Operating at higher voltages or with heavy output
loads will increase the junction temperature and power
dissipation, and also reduce the maximum allowable
operating temperature. See the Package Information,
Absolute Maximum Ratings and Safety Limits sections
for details.
The MAX22700–MAX22702 will be in thermal shutdown
when the junction temperature of the device exceeds
+160°C (typ). During thermal shutdown, the output is set to
logic-low to turn off the external power transistor regardless
of the state of the MAX22700–MAX22702 inputs.
Active Miller Clamp (MAX22701 Only)
The MAX22701 features an active Miller clamp to prevent
false turn-on of the external power transistor caused by
the Miller current. When the external high-side transistor
is turned on after the external low-side transistor is turned
off, the internal Miller clamp transistor starts to engage
when the Miller clamp pin voltage drops below the 2V
threshold, and it provides a low-impedance path to direct
the Miller current to VSSB. Refer to Figure 4 for a Miller
clamp timing diagram.
Adjustable UVLO (MAX22702 Only)
The MAX22702 features an adjustable B-side UVLO to
accommodate UVLO requirements of different types of
external power transistors. To set a user-defined B-side
UVLO, connect external resistors between VDDB and ADJ,
and between ADJ and the external power transistor ground
so that:
VADJ_UVLO = 2 × (1 + R2 ÷ R1)
where R1 is placed between VDDB and ADJ, and R2 is
placed between ADJ and the external power transistor
ground (see Figure 13).
For example, to set the B-side UVLO to 13V, connect
20kΩ (R1) between VDDB and ADJ. R2 will be:
(13 ÷ 2 - 1) × 20 = 110kΩ
Applications Information
Power-Supply Sequencing
The MAX22700–MAX22702 do not require special powersupply sequencing. The logic levels are set independently
on either side by VDDA and VDDB. Each supply can be
present over the entire specified range regardless of the
level or presence of the other supply.
VDDB
VDDA
1nF 0.1µF 22µF
1nF 0.1µF 1µF
HIGH VOLTAGE
VSSB VSSB VSSB
VDDA
INP/IN
UVLO
AND
LOGIC
INN/EN INPUTS
VDDB
MAX22702
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
GNDA
OUT
VDDB
VSSB
ADJ
R1
VSSB
R2
GNDB
NOTE: VDDB AND VSSB ARE REFERENCED TO GNDB. VDDB - VADJ < 5V (TYP)
Figure 13. Example Circuit for MAX22702 Adjustable UVLO
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Maxim Integrated │ 18
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass VDDA and VDDB with 1nF, 0.1µF, and 1µF
low-ESR and low-ESL ceramic capacitors with sufficient
voltage rating in parallel to GNDA and VSSB, respectively.
To ensure the best performance, place the decoupling
capacitors as close to the power-supply pins as possible.
On the B side, it is recommended to place the 1nF and
1µF capacitors close to the VSSB pin, and place the 0.1µF
capacitor close to the VDDB pin. It is also recommended
to include a 22µF reservoir capacitor (tantalum or electrolytic type) between VDDB and VSSB in case the VDDB
power supply is located far away from the VDDB pin. All
bypass capacitors on VDDB are required to have at least
a 50V voltage rating.
Layout Considerations
The PCB designer should follow some critical recommendations in order to get the best performance from the
design.
●● Keep the input/output traces as short as possible.
To maintain low signal-path inductance, avoid using
vias.
●● Place the gate driver as close to the external power
transistor as possible to decrease the trace inductance and avoid output ringing.
●● Have a solid ground plane underneath the highspeed signal layer.
●● Keep the area underneath the MAX22700–
MAX22702 free from ground and signal planes. Any
galvanic or metallic connection between side A and
side B defeats the isolation.
●● Have a solid ground plane next to VSSB pin with
multiple VSSB vias to reduce the parasitic inductance
and minimize the ringing on the output signal.
Calculating Power Dissipation
The required current for the A side of the MAX22700–
MAX22702 depends on the VDDA supply voltage and
the data rate. The required current for the B side of the
MAX22700–MAX22702 depends on the VDDB supply
voltage, the data rate, and the load condition. The typical
current for different VDDA and VDDB supply voltages at any
data rate without external load can be estimated from the
graphs in Figure 14 and Figure 15. Please note that the
data in Figure 14 and Figure 15 are extrapolated from supply current measurements in a typical operating condition.
The total current for the B side is the sum of the “no load”
current (shown in Figure 15) which is a function of the
www.maximintegrated.com
Ultra-High CMTI
Isolated Gate Drivers
voltage and the data rate, and the “load current”, which
depends on the load impedance. Current into a capacitive
load is a function of the load capacitance, the switching
frequency, and the supply voltage.
ICL = CL × fSW × VDDB
where:
ICL is the current required to drive the capacitive load.
CL is the load capacitance on the output pin.
fSW is the switching frequency in Hz.
VDDB is the B-side supply voltage.
The total power dissipation (PD) can be calculated as:
PD = VDDA × IDDA + VDDB × IDDB
where IDDA is the A-side supply current and IDDB is the
B-side supply current.
Example: A MAX22701 is operating with VDDA = 5V,
VDDB = 20V. The output is operating at 10kHz with 1nF
capacitive load. VDDA must supply about 4.56mA with
a 10kHz data rate and a 5V supply voltage according
to Figure 14. VDDB must supply the sum of the no load
current and the load current. The no load current is about
3.77mA with a 10kHz data rate and a 20V supply voltage
according to Figure 15. The load current is equal to 1nF ×
10kHz × 20V = 0.2mA. VDDB must therefore supply about
3.97mA. The total power dissipation is 5V × 4.56mA +
20V × 3.97mA = 102.2mW.
Gate Driver Output Resistors
External series resistors (RON and ROFF) between the
MAX22700–MAX22702 output and the gate of the power
transistor are required in gate driver applications. These
resistors control the turn-on and turn-off time of the power
transistor to optimize switching efficiency and EMI performance.
The RON resistance and external FET’s gate capacitance
determine the turn-on time. The parallel combination of
both RON and ROFF resistance and the external FET’s
gate capacitance determine the turn-off time. Turn-off
time is usually much faster than turn-on time to avoid
shoot-through. Figure 16 shows a typical RON and ROFF
network for the MAX22700–MAX22702. RON and ROFF
values should be adjusted based on the required slew
rate and the external FET’s gate capacitance.
The gate driver output resistors also help limit ringing caused
by parasitic inductances and capacitances due to PCB layout and device package leads. Output ringing can happen
during high voltage dV/dt and high current di/dt switching.
Increasing RON and ROFF can help reduce the ringing.
Maxim Integrated │ 19
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Driving GaN Transistors
The high CMTI rating of 300kV/µs (typ) and the propagation delay matching of 5ns (max) between the high-side
and low-side drivers make the MAX22701 and MAX22702
ideal to drive GaN devices. The MAX22702 also features
an adjustable B-side UVLO to accommodate the low gate
drive voltage of GaN devices.
As shown in the Typical Operating Circuits, a positive
supply (VDDB) and a negative supply (VSSB) with reference to GNDB are required to meet the gate voltage
requirement of GaN devices when using the MAX22701
VDDA SUPPLY CURRENT
vs. DATA RATE
6
and MAX22702 as GaN gate drivers. A boost current is
required during the GaN device’s turn-on period; hence
a capacitor is placed in series with one of the resistors at
the output. This capacitor needs to be discharged during
the turn-off period. Therefore, a diode is placed in parallel
to the resistor to provide a discharge path. On the layout,
it is recommended to place the gate driver very close to
the GaN device to minimize series inductance and reduce
gate drive loop area. To prevent ringing and support high
peak currents when turning on GaN devices, good decoupling is required on the VDDB and VSSB pins.
VDDB SUPPLY CURRENT
vs. DATA RATE
fig14
10
9
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
5
4
3
VDDA
VDDA==3.3V
3.3V
VDDA
VDDA==3.6V
3.6V
VDDA
VDDA==5V
5V
VDDA
VDDA==5.5V
5.5V
2
1
0
VDDB
VDDB == 6V
6V
VDDB
VDDB = 13V
VDDB
VDDB = 20V
VDDB
VDDB = 30V
VDDB
VDDB = 36V
8
7
CL = 0pF
6
5
4
3
0
200
400
600
800
fig15
VDDB = 6V ONLY
APPLIES TO MAX22702
1000
0
200
400
600
800
1000
DATA RATE (kHz)
DATA RATE (kHz)
Figure 14. VDDA Supply Current vs. Data Rate (typ)
Figure 15. VDDB Supply Current vs. Data Rate (typ)
VDDB
VDDA
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
VDDA
MAX22700 – MAX22702
INP/IN
UVLO
AND
LOGIC
INN/EN INPUTS
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
VDDB
VSSB VSSB VSSB
RON
OUT
ROFF
VSSB
GNDA
GNDB/CLAMP/ADJ
VSSB
GNDB
Figure 16. Typical Gate Driver Output Network with RON and ROFF
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Maxim Integrated │ 20
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits
HIGH-SIDE POSITIVE SUPPLY
VDDB1
5V
1nF 0.1µF 22µF
1nF 0.1µF 1µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VDDA
PWMH
PWML
GNDA
VSSB1 VSSB1 VSSB1
VDDA
VDDB
MAX22700E
IN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
EN INPUTS
OUT
VSSB
GNDA
GNDB
SiC
HIGH-SIDE
VSSB1 NEGATIVE SUPPLY
HIGH-SIDE SUPPLY GROUND
OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 0.1µF 22µF
VDDA
VDDB
MAX22700E
VSSB2 VSSB2 VSSB2
IN
UVLO
AND
LOGIC
EN INPUTS
GNDA
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
OUT
VSSB
GNDB
SiC
LOW-SIDE
VSSB2 NEGATIVE SUPPLY
LOW-SIDE SUPPLY GROUND
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Maxim Integrated │ 21
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
VDDB1
5V
1nF 0.1µF 22µF
1nF 0.1µF 1µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1
VDDA
VDDA
INP
PWMH
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INN INPUTS
PWMH
VDDB
MAX22700D
VSSB
GNDA
GNDA
OUT
GNDB
SiC
HIGH-SIDE
VSSB1 NEGATIVE SUPPLY
HIGH-SIDE SUPPLY GROUND
OUTPUT
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 0.1µF 22µF
VDDA
VDDB
MAX22700D
VSSB2 VSSB2 VSSB2
INP
PWML
UVLO
AND
LOGIC
INN INPUTS
PWML
GNDA
GNDA
www.maximintegrated.com
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
OUT
VSSB
GNDB
SiC
LOW-SIDE
VSSB2 NEGATIVE SUPPLY
LOW-SIDE SUPPLY GROUND
Maxim Integrated │ 22
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
VDDB1
5V
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1
VDDA
VDDA
IN
PWMH
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
EN INPUTS
PWML
VDDB
MAX22701E
OUT
VSSB
GNDA
GNDA
SiC
2V
CLAMP
VSSB
HIGH-SIDE
VSSB1 NEGATIVE SUPPLY
1nF 0.1µF 1µF
OUTPUT
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 0.1µF 22µF
VDDA
IN
UVLO
AND
LOGIC
EN INPUTS
VDDB
MAX22701E
VSSB2 VSSB2 VSSB2
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
OUT
VSSB
GNDA
2V
GNDA
SiC
CLAMP
VSSB
LOW-SIDE
VSSB2 NEGATIVE SUPPLY
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Maxim Integrated │ 23
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
VDDB1
5V
1nF 0.1µF 22µF
1nF 0.1µF 1µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1
VDDA
VDDA
INP
PWMH
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INN INPUTS
PWMH
VDDB
MAX22701D
OUT
VSSB
GNDA
GNDA
SiC
2V
CLAMP
VSSB
HIGH-SIDE
VSSB1 NEGATIVE SUPPLY
1nF 0.1µF 1µF
OUTPUT
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 0.1µF 22µF
VDDA
INP
PWML
UVLO
AND
LOGIC
INN INPUTS
PWML
VDDB
MAX22701D
VSSB2 VSSB2 VSSB2
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
OUT
VSSB
GNDA
2V
GNDA
SiC
CLAMP
VSSB
LOW-SIDE
VSSB2 NEGATIVE SUPPLY
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Maxim Integrated │ 24
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
5V
VDDB1
1nF 0.1µF 22µF
1nF 0.1µF 1µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1
VDDA
VDDA
IN
PWMH
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INPUTS
EN
PWML
VDDB
MAX22702E
GNDA
GNDA
OUT
SiC
VDDB1
VSSB
ADJ
VSSB1
HIGH-SIDE
NEGATIVE
SUPPLY
R2
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 0.1µF 22µF
VDDA
IN
UVLO
AND
LOGIC
EN INPUTS
GNDA
GNDA
R1
OUTPUT
GNDB1
VDDB
MAX22702E
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
VSSB2 VSSB2 VSSB2
OUT
SiC
VDDB2
VSSB
ADJ
VSSB2
LOW-SIDE
NEGATIVE
SUPPLY
R1
R2
GNDB2
NOTE: VDDB AND VSSB ARE REFERENCED TO GNDB. VDDB - VADJ < 5V (TYP)
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Maxim Integrated │ 25
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
VDDB1
5V
1nF 0.1µF 1µF
1nF 0.1µF 22µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1
VDDA
VDDA
MAX22702D
INP
PWMH
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INN INPUTS
PWMH
VDDB
GNDA
GNDA
OUT
SiC
VDDB1
VSSB
ADJ
VSSB1
HIGH-SIDE
NEGATIVE
SUPPLY
R2
1nF 0.1µF 1µF
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 0.1µF 22µF
VDDA
INP
PWML
UVLO
AND
LOGIC
INN INPUTS
PWML
GNDA
GNDA
R1
OUTPUT
GNDB1
VDDB
MAX22702D
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
VSSB2 VSSB2 VSSB2
OUT
SiC
VDDB2
VSSB
ADJ
VSSB2
LOW-SIDE
NEGATIVE
SUPPLY
R1
R2
GNDB2
NOTE: VDDB AND VSSB ARE REFERENCED TO GNDB. VDDB - VADJ < 5V (TYP)
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Maxim Integrated │ 26
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
VDDB1
5V
1nF 0.1µF 1µF
1nF 0.1µF 1µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1
VDDA
VDDA
MAX22701D
INP
PWMH
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
INN INPUTS
PWMH
VDDB
OUT
GNDB1
HIGH-SIDE
COMMON
GROUND
VSSB
GNDA
GNDA
GaN
(PANASONIC)
2V
CLAMP
VSSB
1nF 0.1µF 1µF
HIGH-SIDE
VSSB1 NEGATIVE SUPPLY
OUTPUT
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 0.1µF 1µF
VDDA
INP
PWML
UVLO
AND
LOGIC
INN INPUTS
PWML
GNDA
VDDB
MAX22701D
VSSB2 VSSB2 VSSB2
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
OUT
GaN
(PANASONIC)
GNDB2
LOW-SIDE
COMMON
GROUND
VSSB
GNDA
2V
CLAMP
VSSB
LOW-SIDE
VSSB2 NEGATIVE SUPPLY
MAX22701D AS GaN GATE DRIVER
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Maxim Integrated │ 27
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Typical Operating Circuits (continued)
HIGH-SIDE POSITIVE SUPPLY
VDDB1
5V
1nF 0.1µF 1µF
1nF 0.1µF 1µF
HIGH VOLTAGE
MICROCONTROLLER/
FPGA
VSSB1 VSSB1 VSSB1
VDDA
VDDA
IN
PWMH
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
UVLO
AND
LOGIC
EN INPUTS
PWML
VDDB
MAX22702E
GNDA
GNDA
OUT
VSSB
ADJ
GaN
HIGH-SIDE
NEGATIVE
VSSB1 SUPPLY
LOW-SIDE POSITIVE SUPPLY
VDDB2
1nF 0.1µF 1µF
1nF 0.1µF 1µF
VDDA
VDDB
MAX22702E
IN
UVLO
AND
LOGIC
INPUTS
EN
UVLO,
CONTROL
LOGIC,
AND
OUTPUT
DRIVER
GNDA
VDDB1
GNDB1
HIGH-SIDE
COMMON
GROUND
OUTPUT
GNDB1
VSSB2 VSSB2 VSSB2
OUT
VSSB
ADJ
GaN
LOW-SIDE
NEGATIVE
VSSB2 SUPPLY
VDDB2
GNDB2
LOW-SIDE
COMMON
GROUND
GNDA
MAX22702E AS GaN GATE DRIVER
GNDB2
NOTE: VDDB AND VSSB ARE REFERENCED TO GNDB. VDDB - VADJ < 5V (TYP)
www.maximintegrated.com
Maxim Integrated │ 28
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Ordering Information
PART NUMBER
INPUTS
PIN 7
UVLO
LOW-SIDE
R DSON (Ω)
ISOLATION
VOLTAGE
(kV RMS)
TEMP
RANGE
(°C)
PIN-PACKAGE
MAX22700DASA+*
Differential,
INP and INN
GNDB
13V to GNDB
1.25
3
-40 to +125
8 Narrow SOIC
MAX22700EASA+*
Single ended,
IN and EN
GNDB
13V to GNDB
1.25
3
-40 to +125
8 Narrow SOIC
MAX22701DASA+*
Differential,
INP and INN
CLAMP
13V to VSSB
2.5
3
-40 to +125
8 Narrow SOIC
MAX22701EASA+
Single ended,
IN and EN
CLAMP
13V to VSSB
2.5
3
-40 to +125
8 Narrow SOIC
MAX22702DASA+*
Differential,
INP and INN
ADJ
Adjustable
1.25
3
-40 to +125
8 Narrow SOIC
MAX22702EASA+*
Single ended,
IN and EN
ADJ
Adjustable
1.25
3
-40 to +125
8 Narrow SOIC
*Future product—contact factory for availability.
+Denotes a lead (Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: BiCMOS
www.maximintegrated.com
Maxim Integrated │ 29
MAX22700D–MAX22702D
MAX22700E–MAX22702E
Ultra-High CMTI
Isolated Gate Drivers
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
7/19
Initial release
1
8/19
Updated the Absolute Maximum Ratings and Package Information sections, Table
2, and Figure 1
2, 7
2
9/19
Updated the General Description, Benefits and Features, DC Electrical Characteristics, and Dynamic Characteristics sections
1, 4
DESCRIPTION
—
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2019 Maxim Integrated Products, Inc. │ 30
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