MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Benefits and Features
●● G3-PLC™ Compliant
●● Prestandard Conformance: IEEE® P1901.2, ITU
G.9903
●● Frequency-Band Compliant with CENELEC, FCC,
and ARIB
●● Operating Frequency from 10kHz to 490kHz
●● Single-Chip Solution Integrating Physical Layer
(PHY) and Media Access Controller (MAC)
●● Two UART and Two SPI™ Interfaces
●● Supports IPV6-Compatible Networking Layer
• 6LoWPAN IPV6 Header Compression Maximizes
Payload Size
• Dynamic Routing Mechanism Supports Mesh
Networking
• CSMA/CA (Carrier Sense Multiple Access with
Collision Avoidance/Channel Access)
●● High-Speed, Reliable Communication
• Data Rate of up to 300kbps
• Two Layers of Forward Error Correction (FEC) and
Cyclic Redundancy Check (CRC16)
• Enhanced FEC with Reed-Solomon and Viterbi
• CCM* Authentication Coprocessor featuring
AES-128 Encryption/Decryption
• Automatic Repeat Request (ARQ) Enhances Error
Detection and Data Reliability
• Dynamic Link Adaptation to Select Optimum Data
Rate Based on Channel Condition
• Programmable Tone Notching
●● AEC-Q100 Automotive Qualified
Applications
●●
●●
●●
●●
●●
●●
●●
●●
●●
Smart Grid Communications
Advanced Metering Infrastructure (AMI)
Smart Meters
AMI Concentrators
Electronic Vehicle Charging
Street Lighting Automation
Home Energy Monitoring
Building Automation
Solar and Renewable Energy Management
19-5812; Rev 1; 4/14
General Description
The MAX2992 powerline communication (PLC) baseband
modem delivers half-duplex, asynchronous data communication over AC power lines at speeds up to 300kbps (full
FCC band data rate). The MAX2992 is a system-on-chip
(SoC) that combines the physical (PHY) and media access
control (MAC) layers using Maxim’s 32-bit MAXQ30 microcontroller core. The MAX2991 integrated analog front-end
transceiver interfaces seamlessly with the MAX2992, and
together with the MAX2992 G3-PLC firmware, forms a
complete G3-PLC-compliant modem solution.
The MAX2992 utilizes OFDM techniques with DBPSK,
DQPSK, D8PSK modulation and forward error correction (FEC) to enable robust data communication using
the electrical power grid. The design provides inherent
adaptability to frequency selective channels, robustness
in the presence of group delay, and immunity to impulsive
noise. To allow for regulatory compliance, the MAX2992
incorporates a programmable tone notching mechanism.
This allows the notching of certain frequency bands in the
transmit spectrum of the modem. This feature also provides an alternative method to address coexistence with
other narrowband transmitters such as legacy FSK-based
PLC systems.
The MAX2992 MAC incorporates a 6LoWPAN adaptation
layer to support IPv6 packets. An enhanced CSMA/CA
and ARQ, together with the mesh routing protocol, supports all common MAC layer services for various network
topologies. Intelligent communication mechanisms adapt
and enhance system performance over a range of channel
conditions. These mechanisms include channel estimation,
adaptive tone mapping, and routing protocols. An on-chip
CCM (an extension of CCM specified in IEEE 802.15.4)
authentication coprocessor with AES-128 encryption/
decryption provides security and authentication.
Ordering Information
PART
MAX2992ECB+
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
64 LQFP
+Denotes lead(Pb)-free/RoHS-compliant package.
Ordering Information continued at end of data sheet.
G3-PLC is a trademark of Maxim Integrated Products, Inc. SPI
is a trademark of Motorola, Inc.
IEEE is registered service mark of the Institute of Electrical and
Electronics Engineers, Inc.
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Typical Application Circuit
MAX2991
MAX2992
HOST
APPLICATION
µC
MCU
INTERFACE
Tx BLOCK
PHY
AFE
LINE
DRIVER
LINE
COUPLER
AC POWER
LINE
Rx BLOCK
FLASH
(G3-PLC FIRMWARE)
www.maximintegrated.com
Maxim Integrated │ 2
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
TABLE OF CONTENTS
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clocks, PLL, and Power-on-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AFE Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Automatic Bootstrap from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bootstrap Using the UART0 Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bootstrap Using the JTAG Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CSMA/CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Automatic Repeat Request (ARQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PHY Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical Characteristics Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External Crystal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External Flash Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
www.maximintegrated.com
Maxim Integrated │ 3
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
TABLE OF CONTENTS (CONTINUED)
Network Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MAX2992 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LIST OF FIGURES
Figure 1. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. MAX2992 to MAX2991 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. MAX2992 Boot Sequence Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. Zero-Crossing AC Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Transmitter/Receiver Block Diagram of the Baseband Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. AFE Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. Star Network Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. Tree Network Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Peer-to-Peer Network Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Route Request Message Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Route Reply Message Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LIST OF TABLES
Table 1. Frequency Bands Supported by the MAX2992 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2. Frame Error Rate Requirements in AWGN Channels (100 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. Receiver Specification with MAX2991 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
www.maximintegrated.com
Maxim Integrated │ 4
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Device Details
Functional Diagram
SCK SO SI CS
FSH_SCK
SERIAL
FLASH
FSH_SO
FSH_SI
FSH_CS
MULTIPLIER
SPI0
(BOOT LOADER) PERIPHERAL BUS
TXD1
UART0
(BOOT LOADER)
SPI1
SECURITY KEYS
PROG TXDO RXDO
AES CCM
128/256 BIT
RXD1
UART1
CRC32
TIMERS (7)
BOOT ROM
TCK
TMS
TDI
TDO
JTAG
BOOT LOADER
AND
ICE DEBUGGER
WATCH
DOG
INTERRUPT
CONTROL
GND
MULT M
PLLS
XTALS
DIV N
DIV O
PLLS1
PLLS2
XTALS
MULT M
PLLA
www.maximintegrated.com
REED SOLOMON
DEINTERLEAVER
FFT
SYNC
DETECTOR
DIV N
DIV O
PLLA1
PLLA2
ENRX
RXDATA
DEMODULATOR
RXCLK
AFE
INTERFACE
TXCONV
ENTX
SCRAMBLER
REED SOLOMON
CONVOLUTION
ENCODER
INTERLEAVER
MODULATION
MAPPER
FIR
NOTCHING
IFFT
SHAPER
TXDATA
TXCLK
AFE_RST
XTALS
PLLS1
CLK_CPU
PLLS2
PLLA2
MAX2992
PLLS2
XTALA
XTAL1A
XTAL2A
DESCRAMBLER
VETERBI
DECODER
PHY TX PATH
POWER MONITOR
&
RESET CONTROL
XTAL2S
DATA
MEMORY
CHANNEL
ESTIMATOR
RST
GND
RXCONV
PHY RX PATH
VDD
XTAL1S
CRC16 (2)
CLOCK DOMAIN BOUNDARY
MAXQ30
32-BIT
CPU
DATA LINE
INSTRUCTION
MEMORY
INTRODUCTION BUS
PACKET MEMORY
DIV P
CLK_PHY
PLLA2
XTALS
PLLS2
XTALA
DIV P
CLK_AFE
PLLA1
Maxim Integrated │ 5
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
XTAL1A
TCK
TMS
TDI
P2.0/SCK
P2.1/SI
P2.2/AGC_FRZ
P2.3/SO
VDDIO
P2.4/AFE_SHDN
P2.5/CS
P2.6
P2.7
VDDC
VSS
TOP VIEW
XTAL2A
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSS
49
32
TDO
VDD
50
31
PROG
P3.0/TXCONV
51
30
VSS
P3.1/TXDATA
52
29
P1.7/FSH_CS
VSS
53
28
P1.6/FSH_SO
VDDC
54
27
P1.5/FSH_SI
P3.2/TXCLK
55
26
P1.4/FSH_SCK
MAX2992
P1.0/TXD0
P3.5/RXCONV
61
20
VDDC
P3.6/AFE_RST
62
19
VSS
P3.7/ENRX
63
18
XTAL2S
P3.8/ENTX
64
17
XTAL1S
www.maximintegrated.com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
21
VDD
60
RST
P3.4/RXDATA
P0.7/PULSE
P1.1/RXD0
P0.6/RDY
22
P0.5/ACT
59
P0.4/COL
VDDC
VSS
P1.2
VDDC
23
VDDC
58
VDDIO
VSS
VSS
P1.3
P0.3/AFE_SCLK
VDDIO
24
P0.2/AFE_SDOUT
25
57
P0.1/AFE_SDIN
56
P0.0/AFE_CS
VDDIO
P3.3/RXCLK
LQFP
Maxim Integrated │ 6
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Pin Description
PIN
NAME
TYPE
5, 9, 16,
19, 30,
33, 49,
53, 58
VSS
P
Ground
VDDC
P
+1.2V Digital Power Supply. Bypass VDDC to VSS with a 100nF capacitor as close as
possible to the device.
VDDIO
P
+3.3V I/O Power Supply. Bypass VDDIO to VSS with a 100nF capacitor as close as
possible to the device.
6, 8, 20,
34, 54,
59,
7, 25,
39, 56
FUNCTION
14
RST
I/O
Reset. The RST input/output recognizes external active-low reset inputs and employs
an internal pullup resistor to allow for a combination of wired-OR external reset
sources. Bypass with a 220nF capacitor to VSS and use a 10kΩ pullup resistor to
VDDIO.
15, 50
VDD
P
+1.2V Analog Power Supply. Bypass VDD to VSS with a 100nF capacitor as close as
possible to the device.
17
XTAL1S
I
18
XTAL2S
O
Crystal Oscillator Input/Output. The crystal oscillator input/output provide support
for parallel resonant, AT cut crystals. XTAL1S also acts as an input when there is
an external clock source in place of a crystal. XTAL2S is the output of the crystal
amplifier. Signal XTALS provides the clock base for the system clock.
31
PROG
I
PROG. PROG serves to initiate the UART boot loader. To activate the UART boot
loader, PROG must be held low for at least 3 system clock cycles. The host must
then send the autobaud character (0x0D) at a baud rate of 57,600 baud or less. The
MAX2992 detects the serial baud rate and reply with the prompt character (0x3E). At
this time, the bootloader protocol can be used to program the device.
32
TDO
O
JTAG Data Output
44
TDI
I
JTAG Data Input
45
TMS
I
JTAG Mode Select Input
46
TCK
I
JTAG Clock Input
47
XTAL1A
I
48
XTAL2A
O
Crystal Oscillator Input/Output. The crystal oscillator input/output provides support
for parallel resonant, AT cut crystals. XTAL1A also acts as an input when there is
an external clock source in place of a crystal. XTAL2A is the output of the crystal
amplifier. Signal XTALA provides the clock base for the AFE interface.
PORT 0
1
P0.0/AFE_CS
www.maximintegrated.com
I/O
O
P0.0/AFE_CS. P0.0/AFE_CS is used by the MAX2992 G3-PLC firmware to
implement an SPI command bus to the MAX2991 AFE. P0.0/AFE_CS is the chipselect line to the MAX2991. This is the general-purpose I/O hardware and part of the
8-bit I/O port P0.
P0.0/AFE_CS provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 0, In/Out A (Note 1).
Maxim Integrated │ 7
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Pin Description (continued)
PIN
2
3
4
10
11
NAME
P0.1/AFE_SDIN
P0.2/AFE_SDOUT
P0.3/AFE_SCLK
P0.4/COL
P0.5/ACT
www.maximintegrated.com
TYPE
FUNCTION
I/O
O
P0.1/AFE_SDIN. P0.1/AFE_SDIN is used by MAX2992 G3-PLC firmware to
implement an SPI command bus to the MAX2991 AFE. P0.1/AFE_SDIN is the serial
data to the MAX2991. This is general-purpose I/O hardware and part of the 8-bit I/O
port P0.
P0.1/AFE_SDIN provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 0, In/Out B (Note 1).
I/O
O
P0.2/AFE_SDOUT. P0.2/AFE_SDOUT is used by the MAX2992 G3-PLC firmware
to implement an SPI command bus to the MAX2991 AFE. P0.2/AFE_SDOUT is the
serial data returned from the MAX2991. This is the general-purpose I/O hardware and
part of the 8-bit I/O port P0.
P0.2/AFE_SDOUT provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 1, In/Out A (Note 1).
I/O
O
P0.3/AFE_SCLK. P0.3/AFE_SCLK is used by MAX2992 G3-PLC firmware to
implement an SPI command bus to the MAX2991 AFE. P0.3/AFE_SCLK is the serial
clock to the MAX2991.This is the general-purpose I/O hardware and part of the 8-bit
I/O port P0.
P0.3/AFE_SCLK provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 1, In/Out B (Note 1).
I/O
O
P0.4/COL. P0.4/COL is used by the MAX2992 G3-PLC firmware to indicate modem
status. P0.4/COL is the collision/packet error indicator, and can be used to drive a
COL LED. This is the general-purpose I/O hardware and part of the 8-bit I/O port P0.
P0.4/COL provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 2, In/Out A (Note 1).
I/O
O
P0.5/ACT. P0.5/ACT is used by the MAX2992 G3-PLC firmware to indicate modem
status. P0.5/ACT is the activity indicator and can be used to drive an ACT LED. This
is general-purpose I/O hardware and part of the 8-bit I/O port P0.
P0.5/ACT provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 2, In/Out B (Note 1).
Maxim Integrated │ 8
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Pin Description (continued)
PIN
TYPE
FUNCTION
I/O
P0.6/RDY. P0.6/RDY is used by the MAX2992 G3-PLC firmware to indicate modem
status. PO.6/RDY is the modem-ready indicator and is used to drive a RDY LED. This
is the general-purpose I/O hardware and part of the 8-bit I/O port P0.
P0.6/RDY provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 3, In/Out A (Note 1).
I/O
P0.7/PULSE. P0.7/PULSE is used by the MAX2992 G3-PLC firmware to input pulses
from an external zero-crossing detector. This is general-purpose I/O hardware and
part of the 8-bit I/O port P0.
P0.7/PULSE provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware.
● Interrupt input/stop mode wake-up.
● Timer I/O to Timer 3, In/Out B (Note 1).
P1.0/TXD0
I/O
O
P1.0/TXD0. P1.0/TXD0 provides connections to dedicated UART hardware. This is
used by the MAX2992 G3-PLC firmware to implement the UART host interface. P1.0/
TXD0 is the transmit data from the MAX2992 to the host. This is the general-purpose
I/O hardware and part of the 8-bit I/O port P1.
Connect P1.0/TXD0 with a 5kΩ resistor to VDDIO (Note 1).
22
P1.1/RXD0
I/O
I
P1.1/RXD0. P1.1/RXD0 provides connections to dedicated UART hardware. This is
used by the MAX2992 G3-PLC firmware to implement the UART host interface. P1.1/
RXD0 is the receive data from the host to the MAX2992. This is the general-purpose
I/O hardware and part of the 8-bit I/O port P1 (Note 1).
23
P1.2
I/O
O
P1.2. P1.2 provides connections to dedicated UART hardware used by the MAX2992
G3-PLC firmware for reserved function. Leave unconnected. This is the generalpurpose I/O hardware and part of the 8-bit I/O port P1 (Note 1).
24
P1.3
I/O
I
P1.3. P1.3 provides connections to dedicated UART hardware used by the MAX2992
G3-PLC firmware for reserved function. This is the general-purpose I/O hardware and
part of the 8-bit I/O port P1 (Note 1).
I/O
O
P1.4/FSH_SCK. P1.4/FSH_SCK provides dedicated connections to the SPI hardware,
and after power-on reset, the MAX2992 attempts to bootstrap code from an external
flash if it is present. P1.4/FSH_SCK is the serial clock from the MAX2992 to the flash.
This is the general-purpose I/O hardware and part of the 8-bit I/O port P1.
After boot, the SPI hardware can be used by the MAX2992 G3-PLC firmware. This
is not utilized by the MAX2992 G3-PLC firmware, but P1.4/FSH_SCK provides the
capability of:
● SPI master clock output.
● SPI slave clock input (Note 1).
12
13
NAME
P0.6/RDY
P0.7/PULSE
PORT 1
21
26
P1.4/FSH_SCK
www.maximintegrated.com
Maxim Integrated │ 9
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Pin Description (continued)
PIN
27
28
29
NAME
P1.5/FSH_SI
P1.6/FSH_SO
P1.7/FSH_CS
TYPE
FUNCTION
I/O
O
P1.5/FSH_SI. P1.5/FSH_SI provides dedicated connections to the SPI hardware, and
after power-on reset, the MAX2992 attempts to bootstrap code from an external flash
if it is present. P1.5/FSH_SI is the serial data from the MAX2992 to the flash. This is
the general-purpose I/O hardware and part of the 8-bit I/O port P1.
After boot, the SPI hardware can be used by the MAX2992 G3-PLC firmware. This
is not utilized by the MAX2992 G3-PLC firmware, but P1.4/FSH_SI provides the
capability of:
● SPI master output data.
● SPI slave input data (Note 1).
I/O
O
P1.6/FSH_SO. P1.6/FSH_SO provides dedicated connections to the SPI hardware,
and after power-on reset, the MAX2992 attempts to bootstrap code from an external
flash if it is present. P1.6/FSH_SO is the serial data return to the MAX2992 from the
flash. This is the general-purpose I/O hardware and part of the 8-bit I/O port P1.
After boot, the SPI hardware can be used by the MAX2992 G3-PLC firmware. This
is not utilized by the MAX2992 G3-PLC firmware, but P1.6/FSH_SO provides the
capability of:
● SPI master data input.
● SPI slave data output (Note 1).
I/O
O
P1.7/FSH_CS. P1.7/FSH_CS provides dedicated connections to the SPI hardware,
and after power-on reset, the MAX2992 attempts to bootstrap code from an external
flash if it is present. P1.7/FSH_CS is the serial chip select from the MAX2992 to the
flash. This is the general-purpose I/O hardware and part of the 8-bit I/O port P1.
After boot, the SPI hardware can be used by the MAX2992 G3-PLC firmware. This
is not utilized by the MAX2992 G3-PLC firmware, but P1.7/FSH_CS provides the
capability of:
● SPI slave chip select (Note 1).
I/O
P2.7. P2.7 is not used by the MAX2992 G3-PLC firmware. It is configured as an
unused input with the internal pullup enabled. It can be left unconnected. This is the
general-purpose I/O hardware and part of the 8-bit I/O port P2.
P2.7 provides hardware support that is available, but not utilized by the MAX2992
G3-PLC firmware:
● Hardware flow control line CTS for UART0.
● Timer I/O to Timer 4, In/Out A.
● Timer I/O to Timer 6, In/Out A (Note 1).
PORT 2
35
P2.7
www.maximintegrated.com
Maxim Integrated │ 10
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Pin Description (continued)
PIN
36
37
38
40
41
42
43
NAME
TYPE
FUNCTION
I/O
P2.6. P2.6 is not used by the MAX2992 G3-PLC firmware. It is configured as an
unused input with the internal pullup enabled. It can be left unconnected. This is the
general-purpose I/O hardware and part of the 8-bit I/O port P2.
P2.6 provides hardware support that is available, but not utilized by the MAX2992
G3-PLC firmware
● Hardware flow control line RTS for UART0.
● Timer I/O to Timer 4, In/Out A.
● Timer I/O to Timer 6, In/Out A (Note 1).
I/O
O
P2.5/CS. P2.5/CS provides dedicated connections to SPI hardware. This is used by
the MAX2992 G3-PLC firmware to implement the SPI host interface. P2.5/CS is the
active-low, chip select from the host to the MAX2992. This is general-purpose I/O
hardware and part of the 8-bit I/O port P2.
P2.5/CS provides hardware support that is available, but not utilized by the MAX2992
G3-PLC firmware.
● Timer I/O to Timer 5, In/Out B (Note 1).
P2.4/AFE_SHDN
I/O
P2.4/AFE_SHDN. P2.4/AFE_SHDN is used by the MAX2992 G3-PLC firmware to
place the MAX2991 AFE into shutdown mode for lowest power consumption. P2.4/
AFE_SHDN provides hardware support that is available, but not utilized by the
MAX2992 G3-PLC firmware. This is general-purpose I/O hardware and part of the
8-bit I/O port P2.
● Timer I/O to Timer 5, In/Out A (Note 1).
P2.3/SO
I/O
O
P2.3/SO. P2.3/SO provides dedicated connections to SPI hardware. This is used by
the MAX2992 G3-PLC firmware to implement the SPI host interface. P2.3/SO is the
serial data to the host from the MAX2992. This is general-purpose I/O hardware and
part of the 8-bit I/O port P2 (Note 1).
P2.2/AGC_FRZ
I/O
O
P2.2/AGC_FRZ. P2.2/AGC_FRZ provides dedicated connections to the PHY
hardware. This is used by the MAX2992 G3-PLC firmware to signal the MAX2991
AFE to freeze its automatic gain control (AGC) setting. This is general-purpose I/O
hardware and part of the 8-bit I/O port P2 (Note 1).
P2.1/SI
I/O
O
P2.1/SI. P2.1/SI provides dedicated connections to SPI hardware. This is used by the
MAX2992 G3-PLC firmware to implement the SPI host interface. P2.1/SI is the serial
data from the host to the MAX2992. This is general-purpose I/O hardware and part of
the 8-bit I/O port P2 (Note 1).
P2.0/SCK
I/O
I
P2.0/SCK. P2.0/SCK provides dedicated connections to SPI hardware. This is used
by the MAX2992 G3-PLC firmware to implement the SPI host interface. P2.0/SCK is
the serial clock from the host to the MAX2992. This is general-purpose I/O hardware
and part of the 8-bit I/O port P2 (Note 1).
P2.6
P2.5/CS
www.maximintegrated.com
Maxim Integrated │ 11
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Pin Description (continued)
PIN
NAME
TYPE
FUNCTION
P3.0/TXCONV
I/O
O
P3.0/TXCONV. P3.0/TXCONV provides dedicated connections to AFE interface
hardware. This is used by the MAX2992 G3-PLC firmware to implement the AFE
interface to the MAX2991. P3.0/TXCONV is the TX enable line to the MAX2991. This
is general-purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
P3.1/TXDATA
I/O
O
P3.1/TXDATA. P3.1/TXDATA provides dedicated connections to AFE interface hardware.
This is used by the MAX2992 G3-PLC firmware to implement the AFE interface to the
MAX2991. P3.1/TXDATA is the TX serial data output to the MAX2991. This is generalpurpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
P3.2/TXCLK
I/O
O
P3.2/TXCLK. P3.2/TXCLK provides dedicated connections to AFE interface
hardware. This is used by the MAX2992 G3-PLC firmware to implement the AFE
interface to the MAX2991. P3.2/TXCLK is the TX serial clock to the MAX2991. This is
general-purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
P3.3/RXCLK
I/O
O
P3.3/RXCLK. P3.3/RXCLK provides dedicated connections to AFE interface
hardware. This is used by the MAX2992 G3-PLC firmware to implement the AFE
interface to the MAX2991. P3.3/RXCLK is the RX serial clock to the MAX2991. This
is general-purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
P3.4/RXDATA
I/O
I
P3.4/RXDATA. P3.4/RXDATA provides dedicated connections to AFE interface
hardware. This is used by the MAX2992 G3-PLC firmware to implement the AFE
interface to the MAX2991. P3.4/AFE_SDI is the RX serial data from the MAX2991.
This is general-purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
61
P3.5/RXCONV
I/O
O
P3.5/RXCONV. P3.5/RXCONV provides dedicated connections to AFE interface
hardware. This is used by the MAX2992 G3-PLC firmware to implement the AFE
interface to the MAX2991. P3.5/RXCONV is the RX Enable line to the MAX2991. This
is general-purpose I/O hardware and part of the 8-bit I/O port P3 (Note 1).
62
P3.6/AFE_RST
I/O
O
P3.6/AFE_RST. P3.6/AFE_RST is used by the MAX2992 G3-PLC firmware to reset the
MAX2991. This is general-purpose I/O hardware and part of the 8-bit I/O port P3
(Note 1).
63
P3.7/ENRX
I/O
O
P3.7/ENRX. P3.7/ENRX is used by the MAX2992 G3-PLC firmware to enable the RX
channel in the MAX2991. This is general-purpose I/O hardware and part of the 8-bit
I/O port P3 (Note 1).
64
P3.8/ENTX
I/O
O
P3.8/ENTX. P3.8/ENTX is used by the MAX2992 G3-PLC firmware to enable the TX
channel in the MAX2991. This is general-purpose I/O hardware and part of the 8-bit
I/O port P3 (Note 1).
PORT 3
51
52
55
57
60
Note 1: Refer to the MAX2992 G3-PLC Firmware Release Note for updates to the function implemented.
www.maximintegrated.com
Maxim Integrated │ 12
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX2992 toc02
MAX2992 toc01
D8PSK (MAX)
G3-PLC DATA RATE*
FCC (10kHz TO 487.5kHz)
D8PSK (MAX)
D8PSK (MAX)
D8PSK (TYP)
D8PSK (TYP)
D8PSK (TYP)
DQPSK (TYP)
DQPSK (TYP)
DQPSK (TYP)
DBPSK (TYP)
DBPSK (TYP)
DBPSK (TYP)
ROBO (TYP)
ROBO (TYP)
ROBO (TYP)
0
10
20
30
40
*POINT-TO-POINT DATA RATE (kbps)
Detailed Description
50
0
50
150
200
250
300
*POINT-TO-POINT DATA RATE (kbps)
The MAX2992 integrates a high-performance Maxim
MAXQ30 32-bit RISC core with optimized OFDM PHY,
128/256-bit AES and CRC hardware and peripherals
including UART serial communication, SPI interface,
serial AFE interface, watchdog/countdown timers, GPIO,
and external interrupts. The MAX2992 G3-PLC modem
is based on Orthogonal Frequency Division Multiplexing
(OFDM) that places multiple evenly spaced carriers within
the available frequency band. Data is modulated onto
these carriers and three modulation methods are supported: DBPSK, DQPSK, and D8PSK. Special data interleaving and forward error correction techniques enhance the
robustness of communication that is immune to impulsive
noise, adaptable to frequency selective channels, and
robust in the presence of group delay. Additional performance is obtained by adaptive tone mapping, a process
by which the MAX2992 automatically detects carriers with
poor SNR, redistributing data onto better performing carriers. These features allow the MAX2992 to adapt to channel conditions to provide superior data rates for a given
channel condition. External flash stores the complete
G3-PLC application firmware supplied by Maxim, which
executes from the on-chip SRAM memory. G3-PLC data
and control is accomplished using the G3-PLC modem
interface over the UART or SPI port. A full description
of this interface is provided in the MAX2992 G3-PLC
Interface Guide. The MAC, implemented on the MAXQ30,
www.maximintegrated.com
100
MAX2992 toc03
G3-PLC DATA RATE*
FCC (150kHz TO 487.5kHz)
G3-PLC DATA RATE*
CENELEC A (36kHz to 91kHz)
0
50
100
150
200
250
300
*POINT-TO-POINT DATA RATE (kbps)
provides advanced CSMA/CA and ARQ functions and
supports all common MAC layer services.
Power Management
The MAX2992 power-management features minimize
power consumption by clock gating and by adjusting the
operating frequency. Clock gating is used to eliminate
active power of on-chip functional units when not in use.
A clock divider of up to 256 is set by software to reduce
the operating frequency to the required performance level
per single application.
Normal Operating Mode
In normal operating mode, the MAX2992’s powermanagement features minimize power consumption by
adjusting the frequency of CPU and PHY operation to
match the dynamic load on the device.
Idle Mode
In idle mode, the MAX2992 lowers power consumption
by shutting down the MAXQ30 processor, but keeps the
PHY’s receive circuitry active so that it can detect a powerline packet. At least one clock must be running during
idle mode. The processor awakes on the detection of a
line SYNC at the beginning of a packet and returns to
normal operating mode to receive the powerline packet.
Stop Mode
Stop mode disables all clocks and circuits within the
MAX2992. All modem functions are disabled. This is
Maxim Integrated │ 13
MAX2992
the lowest power state for the device where only leakage power is consumed. An external interrupt causes
the MAX2992 to exit from the stop mode. Stop mode is
controlled by the MAX2992 G3-PLC firmware. Refer to
the MAX2992 G3-PLC Interface Guide and MAX2992
G3-PLC Firmware Release Note for details on the use of
stop mode.
UART Interface
The MAX2992 features two hardware UARTs (UART0
and UART1). UART0 has a 16-byte deep receive and
transmit FIFO with configurable interrupt thresholds and
it supports hardware flow control. Additionally, UART0
provides a hardware function for booting the device. The
MAX2992 G3-PLC firmware dedicates UART0 to the host
interface with a baud rate of 115,200bps without flow control. See the MAX2992 G3-PLC Firmware Release Note
for additional information on the UART0 host interface
settings.
Data transfer for communication on the power line and
status and control commands are passed between host
and the MAX2992 G3-PLC modem over UART0. A simple
frame format is used to define data and management
primitives. A complete description of the frame format and
command primitives is provided in the MAX2992 G3-PLC
Interface Guide.
G3-PLC MAC/PHY Powerline Transceiver
Refer to the MAX2992 G3-PLC Interface Guide and
MAX2992 G3-PLC Firmware Release Note for details on
the use of the SPI1 port.
GPIO
The MAX2992 features 5V tolerant, 3.3V I/O. Each I/O
can be either an input or output. The MAX2992 G3-PLC
firmware configures each I/O as described in the Pin
Configuration section. Refer to the MAX2992 G3-PLC
Firmware Release Note for additional GPIO assignments.
When in input mode, a weak pullup resistance is enabled
pulling the I/O high. A series NFET provides the I/O’s
high voltage tolerance (Figure 1). This degrades the
VOH observed and an external resistive pullup is recommended when the I/O is not actively driven (such as RST
or PROG, see the Pin Description).
VDDIO
DEVICE
CLOAD
The MAX2992 G3-PLC firmware utilizes UART1 for a
reserved function. Do not connect in user designs.
Serial Peripheral Interface (SPI)
The MAX2992 includes two serial peripheral interface
modules (SPI0 and SPI1). The MAX2992 SPI hardware can operate in slave or master modes. This is a
common, high-speed, synchronous peripheral interface
that shifts a bit stream of variable length and data rate
between the microcontroller and other peripheral devices.
Programmable clock frequency, character lengths, polarity, and error handling enhance the usefulness of the
peripheral. The maximum baud rate of the SPI interface is
half the system clock for master mode operation and 1/8th
the system clock for slave mode operation.
SPI0 features a boot loading function that is the primary
method for initializing the MAXQ30 memory after reset.
SPI0 boot loading is described in the Boot Options section.
SPI1 is assigned by the MAX2992 G3-PLC firmware to
implement an alternative host interface to UART0. When
used as a host interface, four MAX2992 signals, P2.0/
SCK, P2.5/CS, P2.1/SI, and P2.3/SO must be connected
to the host processor.
www.maximintegrated.com
I/O
REN
WEAK PULLUP
Figure 1. GPIO
Timers
The MAX2992 incorporates seven 16-bit programmable
timers to allow precise control of internal and external
events. Each timer can operate in two modes: count-stop
or wrap-round. The timers can be configured so that the
timers generate interrupts upon reaching the extreme
value. The timers also feature output modes suitable for
synthesizing PWM. The MAX2992 G3-PLC firmware uses
these timers within its operating system, and to implement
CSMA and AC phase detection. Refer to the MAX2992
G3-PLC Interface Guide and MAX2992 G3-PLC Firmware
Release Note for information on timer use.
Clocks, PLL, and Power-on-Reset
The MAX2992 provides two built-in oscillators each with
an associated PLL. The device can function in a one or a
two crystal configuration, either reducing system components or maximizing flexibility of the operating frequencies
in the system. The one crystal configuration requires a
Maxim Integrated │ 14
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
crystal connected between XTAL1S and XTAL2S. Drive
XTAL1A low, have XTAL2A unconnected, and connect
VDD (Pin 50) to VSS in one crystal mode.
The MAX2992 G3-PLC firmware uses the one crystal configuration with a 19.2MHz crystal connected to
XTAL1S and XTAL2S. This crystal is used to generate
both CPU and AFE clocks. For this configuration, the CPU
clock is set to 76.8MHz and AFE clock is 6.4MHz for the
CENELEC frequency band with a 400kHz sample rate.
For FCC and ARIB bands, the AFE clock is 19.2MHz with
a 1.2MHz sample rate.
The two crystal configuration requires that a crystal be
connected between XTAL1S and XTAL2S, and XTAL1A
and XTAL2A. Refer to the MAX2992 G3-PLC Firmware
Release Note for information on the crystal configuration
used.
External Reset
During normal operation, the MAX2992 can be placed
into external reset mode by holding RST low for a minimum of eight clock cycles. After RST returns high, the
MAXQ30 processor exits the reset state within eight clock
cycles and begins program execution.
Watchdog Timer
ENTX
MAX2991
AFE
P3.8/ENTX
TXDATA
P3.1/TXDATA
TXCONV
P3.0/TXCONV
TXCLK
P3.2/TXCLK
ENRX
P3.7/ENRX
RXDATA
P3.4/RXDATA
RXCONV
P3.5/RXCONV
RXCLK
AGC_CS
RESET
MAX2992
P3.3/RXCLK
P2.2/AGC_FRZ
P3.6AFE_RST
Figure 2. MAX2992 to MAX2991 Interface
● At any time, the PROG can be used to initiate a
UART0 boot load cycle.
● From POR, if the JTAG interface and PROG are not
active, the MAX2992 boots load from external flash
using the SPI0 interface.
The watchdog timer is a programmable hardware timer
that can be used to reset the processor in case of a software lockup or other unrecoverable error. The MAX2992
G3-PLC firmware uses the watchdog timer to enhance
system reliability.
● Once a program is loaded (by any means) and the
program valid bit is set, successive resets causes
reexecution of the loaded code. An additional boot
load cycle is not required.
AFE Serial Interface
● When the JTAG and UART0 bootstrap are not selected, the MAX2992 boots from an external flash device
over SPI0. The flash must be preprogrammed with
the MAX2992 G3-PLC firmware. AES encryption of
the flash image is supported to protect any deployed
application. Refer to the MAX2992 Evaluation Kit for
details on programming the flash.
The MAX2992 AFE interface is designed to support the
MAX2991. The interface includes separate receive and
transmit serial interfaces. Connect the MAX2992 to the
MAX2991 as shown in Figure 2. Refer to the MAX2991
data sheet for a description of the serial interface timing.
Boot Options
The MAX2992 executes program code from internal
SRAM. This SRAM is volatile and must be loaded with
application code after a power-cycle event. There are
three options for loading the SRAM:
Automatic Bootstrap from Flash
Bootstrap Using the UART0 Loader
The MAX2992 can be booted over the UART0 host interface to avoid the need for a dedicated flash device. The
UART0 boot load procedure is:
● Bootstrap through the JTAG loader
1. Pull PROG low for a minimum of 8 clock cycles. If
automatic boot after power-up is desired, place an RC
on PROG so that PROG rises at least 8 clock cycles
after RST.
Figure 3 shows the flow diagram for MAX2992 booting.
The flowchart illustrates:
2. Send the MAX2992 the character 0x0D (8-bit, no parity) at a rate of 57,600 baud or less.
● Automatic bootstrap from external flash
● Bootstrap through the UART0 loader
www.maximintegrated.com
Maxim Integrated │ 15
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
PROG INPUT
RESET
SET PSPE
EXECUTE ROM
0x800000h
SPE?
SPE = SYSTEM PROGRAM ENABLE BIT WITHIN THE JTAG SPR REGISTER.
PSPE = PROG SYSTEM PROGRAM ENABLE BIT, SET BY THE PROG INPUT
AND CLEARED BY OTHER FORMS OF RESET.
PV = PROGRAM VALID BIT, SET AT THE COMPLETION OF LOADING CODE
INTO INSTRUCTION RAM AND CLEARED BY POWER-ON RESET.
YES
JTAG BOOTLOADER
NO
PSPE?
YES
NO
RUN APPLICATION JUMP TO
0x000000h
YES
PV?
NO
BOOTSTRAP FROM FLASH
PASS
NO
UART0 AUTOBAUD
UART0 BOOTLOADER
YES
SET PV
SET PV ON SUCCESSFUL
CODE LOAD
RESET
RESET
Figure 3. MAX2992 Boot Sequence Flow Chart
3. The MAX2992 measures the timing and autocalibrates
to the baud rate.
4. The MAX2992 acknowledges entry to the serial loader
by transmitting a prompt character (0x3E).
Details of using the serial boot-loader commands to implement a UART0 bootstrap are provided in the MAX2992
Evaluation Kit. The serial bootloader does not utilize the
hardware flow control feature of UART0. The loader manages flow control using the communication protocol.
www.maximintegrated.com
Toggling RST exits the serial boot loader whereby the
MAX2992 follows the boot sequence described by Figure 3.
Details of using the serial boot loader commands to implement a UART0 boot strap are provided in the MAX2992
Evaluation Kit.
Maxim Integrated │ 16
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
PULSE WIDTH
HALF CYCLE
=10ms/8.3ms
50Hz/60Hz
ZERO-CROSSING DETECTOR
Figure 4. Zero-Crossing AC Detector
Bootstrap Using the JTAG Loader
The JTAG bootstrap loader mode initializes the nonvolatile memory of the internal MAXQ30 microcontroller. The
JTAG loader is used by Maxim as a development interface and should not be utilized in user systems.
AC Phase Detector
To know the phases of each meter, the MAX2992 features internal timers to measure time intervals of pulses
resulted from zero-crossing of AC 50Hz/60Hz as shown
in Figure 4. P0.7/PULSE is used to input pulses received
from an external zero-crossing detector to reset an 8-bit
counter. The minimum required pulse width is 1% of the
cycle.
CSMA/CA
Concurrent transmission by multiple nodes can result in
frame collisions that occur when multiple transmissions
interfere with each other, distorting the signal sufficiently
to cause communication to fail. Carrier Sense Multiple
Access/Collision Avoidance (CSMA/CA) is a mechanism
to reduce the probability of collisions. When using CSMA
as soon as a node is ready to transmit a packet, the
device checks the channel for activity. If no other node
is transmitting the node transmits its packet. If another
transmitter is detected, the device waits for that transmission to end and then waits for a randomly selected period
of time for another device to start transmitting on the
channel. This wait time is called a random back-off time.
If no other device has started transmitting at the end of
the back-off time, the device starts its transmission. This
process is repeated until the device gets access to the
channel. All the devices in the system randomly choose
their back-off time from one of a limited number of predefined time slots after the end of the prior transmission.
www.maximintegrated.com
Automatic Repeat Request (ARQ)
To enhance error detection and improve data reliability,
the MAX2992 utilizes an automatic repeat request protocol. Since PLC communication is a half-duplex connection, the transmitter waits for an acknowledgment (ACK)
of each transmission before it proceeds with the next
transmission. If the transmitter does not receive an ACK
packet, the transmitter resends the packet.
PHY Overview
The MAX2992 powerline modem is designed to overcome the challenges associated with the harsh powerline
environment for data communications. Some of the challenges are noted below:
● Channel variability with frequency, location, and time
● Narrowband, wideband, and impulsive noise commonly present on the power line
● Presence of narrowband interference and multipath
signal propagation
● Low and time varying network impedance (3Ω to 30Ω)
● Propagation through transformers that subject the
channel to severe group delay and attenuation
The MAX2992 modem solution is based on orthogonal
frequency division multiplexing (OFDM) to overcome the
powerline channel impairment, providing high reliability
in data transmission. This method combines good bandwidth efficiency (high data rate) with the possibility of a
very flexible bandwidth allocation. In combination with
error correction coding, the MAX2992 is robust in the
presence of frequency selective channels and resilient to
jammer signals and impulsive noise.
Maxim Integrated │ 17
MAX2992
The OFDM technique places evenly spaced carriers into
the available frequency band. The MAX2992 can be configured to operate in a subset of frequencies in the range
10kHz to 490kHz, encompassing CENELEC, ARIB, and
FCC frequency bands. Three modulation methods are
supported; DBPSK, DQPSK, and D8PSK. This allows
the MAX2992 to trade off channel condition and data rate
to achieve the highest possible data through for a given
channel condition. Additional performance is obtained by
adaptive tone mapping, a process by which the MAX2992
automatically detects carriers with poor SNR, redistributing data onto better performing channels.
There are several advantages of the MAX2992 OFDM
scheme as compared to traditional single carrier FSK or
spread-spectrum systems:
● The MAX2992 OFDM allows an extremely flexible
allocation and use of a given channel bandwidth. As
an example, the lower and the upper limit of the used
frequency band can easily be configured. It is also
possible to use two or more noncontiguous sub-bands
for the transmission of a single data stream.
● It is considerably more robust against intersymbol interference (ISI) or group delay distortion caused by the
transmission channel than narrowband systems. This
is mainly due to the fact that the parallel transmission
on several carriers leads to longer symbol duration.
Furthermore, ISI is simply removed by inserting guard
intervals and cyclic prefixes between the symbols.
The MAX2992 is robust in presence of narrowband interference because such jammers typically destroy a single
carrier only. Through the use of forward error correction
coding—the erroneous data is detected and corrected
using the received coded information.
On the transmitter side, the PLC modem layer receives
input data from the UART and passes the data through
the FEC, modulator, and IFFT. On the receiver side, the
PLC modem layer receives inputs from the AFE and
hands the data over to the application layer (Figure 5).
Two separate signal paths are shown for the receiver.
The first path is dedicated to the detection of narrow
band interference, and the second path processes the
preamble for symbol and frame synchronization followed
by the FEC decoding block. After descrambling the output
of the FEC decoder data are available for the MAC layer.
www.maximintegrated.com
G3-PLC MAC/PHY Powerline Transceiver
Table 1 shows the frequency bands with which the
MAX2992 modem complies.
Table 1. Frequency Bands Supported by
the MAX2992
NUMBER
OF
CARRIERS
FIRST
CARRIER
(kHz)
CENELEC A
36
35.93
90.62
CENELEC B
16
98.43
121.87
CENELEC C
7
128.12
137.50
CENELEC BC
26
98.43
137.50
CENELEC D
4
142.18
146.87
FCC1
72
154.6875
487.5
FCC2
97
37.5
487.5
FCC3
24
154.6875
262.5
FCC4
40
304.6875
487.5
ARIB1
54
154.6875
403.125
ARIB2
79
37.5
403.125
COMPONENT
LAST
CARRIER
(kHz)
The combined PHY and MAC in the MAX2992 meet the
transmitter/receiver technical requirements for highly
reliable data communication in powerline networks, as
shown in Table 2 and Table 3.
Table 2. Frame Error Rate Requirements
in AWGN Channels (100 Bytes)
SIGNAL-TONOISE RATIO
(dB)
MODULATION
AND CODING
RATE
FRAME ERROR
RATE (%)
-1.2
ROBO
0.01
2.6
DBPSK
0.01
6.1
DQPSK
0.01
9.9
D8PSK
0.01
Table 3. Receiver Specification with
MAX2991
RECEIVER SPECIFICATION
Sensitivity
REQUIREMENT
1mV
Dynamic range
60dB
Clock frequency tolerance
±25ppm
Maxim Integrated │ 18
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
OFDM MODULATOR
MAPPING
DBPSK
DQPSK
D8PSK
PREEMPHASIS
FCH
IFFT
ADD CP
WINDOWING
INTERLEAVER
SCRAMBLER
DATA
REED-SOLOMON
ENCODER
BIT
CONVOLUTIONAL
ENCODER
AFE
ROBUST (RC4)
S-ROBUST (RC6)
FEC ENCODER
POWER LINE
OFDM DEMODULATOR
JAMMER
CANCELLER
DETECTED
JAMMER
DETECTOR
AFE
SYNC
DETECTION
REMOVE
CP
DEMODULATOR
DBPSK
DQPSK
D8PSK
FFT
NOT
DETECTED
RMS
MEASUREMENT
DEINTERLEAVER
ROBUST4
AND
ROBUST
COMBINER
CHANNEL
ESTIMATION
VITERBI
DECODER
REED-SOLOMON
DECODER
DATA
DESCRAMBLER
FCH
FEC DECODER
Figure 5. Transmitter/Receiver Block Diagram of the Baseband Processor
www.maximintegrated.com
Maxim Integrated │ 19
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Absolute Maximum Ratings
VDDIO to VSS........................................................-0.5V to +4.0V
VDDC to VSS.........................................................-0.5V to +1.5V
VDD to VSS............................................................-0.5V to +1.5V
XTAL1A, XTAL2A, XTAL1S, XTAL2S to VSS........-0.5V to +4.0V
All I/O Pins............................................................-0.5V to +5.5V
Continuous Power Dissipation (TA = +70°C)
LQFP (derate 25mW/°C above +70°C)......................2000mW
Operating Temperature Range.......................... -40°C to +105°C
Junction Temperature.......................................................+125°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 2)
LQFP
Junction-to-Ambient Thermal Resistance (θJA)...........40°C/W
Junction-to-Case Thermal Resistance (θJC)..................8°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VDDIO = +3.3V, VDDC = VDD = +1.2V, VSS = 0, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.
Specifications over the entire operating temperature range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
POWER-SUPPLY CHARACTERISTICS
Digital Supply Voltage Range
VDDIO
Core Supply Voltage Range
VDDC
PLL Supply Voltage Range
VDD
CONDITIONS
Pins 15 and 50
VDDIO supply current
Operating Supply Current
IOPERATING VDDC supply current
VDD supply current
VDDIO supply current
Idle Mode Current
IIDLE
VDDC supply current
VDD supply current
VDDIO supply current
Stop Mode Current
ISTOP
VDDC supply current
VDD supply current
IOH = -5mA
Output Voltage High
VOH
IOH = -8mA (pins 55 and 57)
IOl = 5mA
Output Voltage Low
VOL
IOl = 8mA (pins 55 and 57)
LOGIC INPUT CHARACTERISTICS
Input High Voltage
VIH
Input Low Voltage
Input Capacitance
Input Leakage current
GPIO Pullup Resistance
VIL
CIN
IIN
RPU
www.maximintegrated.com
XTAL1S, XTAL1A
XTAL1S and XTAL1A
Internal pullup disabled
Internal pullup enabled
MIN
TYP
MAX
UNITS
3.0
1.14
1.14
3.3
1.2
1.2
25
40
1
25
12
1
2
1.8
0.2
3.6
1.32
1.32
V
V
V
70
3
mA
mA
mA
2.4
2.4
V
0.4
0.4
2
2
-0.3
5.5
3.6
+0.8
3
-10
25
45
+10
60
V
V
V
pF
µA
kΩ
Maxim Integrated │ 20
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
AC Electrical Characteristics
(VDDIO = +3.3V, VDDC = VDD = +1.2V, VSS = 0, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.
Specifications over the entire operating temperature range are guaranteed by design and characterization.)
PARAMETER
External Crystal/Input Frequency
SYMBOL
1/tXTAL
External Crystal/Clock Tolerance
CONDITIONS
ESR < 90Ω for 19.2MHz (Note 4)
MIN
TYP
MAX
UNITS
2
19.2
30
MHz
(Note 4)
25
ppm
CPU Clock Frequency
1/tCPU
As configured by G3-PLC firmware
(Note 4)
76.8
MHz
AFE Clock Frequency
1/tAFE
As configured by G3-PLC firmware
(Note 4)
48
MHz
1/16 x
tCPU
bps
As configured by G3-PLC firmware
(Notes 3 and 4)
UART Baud Rate
115,200
SPI MASTER (Flash Bootloader, See Figure 6)
SPI Master Operating Frequency
1/tMCK
Flash boot after POR (Note 4)
1/2 x
tXTAL
User programmable after bootstrap
(Note 4)
1/ 2 x
tCPU
I/O Rise/Fall Time
tMRF
SCLK Output Pulse Width High/
Low
tMCH,
tMCL
CL = 100pF, pullup = 560Ω
MOSI Output Valid to SCLK
Sample Edge
tMOH
MOSI Output Hold after SCLK
Last Sample Edge
tMOV
SCLK Last Sample Edge to
MOSI Output Change
tMLH
MOSI last hold
MISO Input Valid to SCLK
Sample Edge
tMIS
MISO setup
MISO Input Hold After SCLK
Sample Edge
tMIH
MOSI setup
5
MHz
ns
tMCK/2
- tRF
ns
tMCK/2
- tRF
ns
tMCK/2
- tRF
ns
tMCK +
tRF
ns
10
ns
0
ns
SPI SLAVE (See Figure 7)
SPI Slave Operating Frequency
1/tSCK
(Note 4)
MHz
5
ns
I/O Rise/Fall Time
tSRF
SCLK Input Pulse Width High/
Low
tSCH,
tSCL
tCPU
ns
SSEL Active to First Shift Edge
tSSE
0
ns
MOSI Input to SCLK Sample
Edge Rise/Fall Setup
tSIS
tCPU
ns
www.maximintegrated.com
CL = 100pF, pullup = 560Ω
1/8 x
tCPU
Maxim Integrated │ 21
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
AC Electrical Characteristics (continued)
(VDDIO = +3.3V, VDDC = VDD = +1.2V, VSS = 0, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.
Specifications over the entire operating temperature range are guaranteed by design and characterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MOSI Input from SCLK Sample
Edge Transition Hold
tSIH
MISO Output Valid after SCLK
Shift Edge Transition
tSOV
SSEL Inactive to Next SSEL
Asserted
tSSH
2x
tCPU
ns
SCLK Inactive to SSEL
Deasserted
tSD
3x
tCPU
ns
MISO Output Disabled After
SSEL Edge Deasserted
tSLH
4x
tCPU
ns
tCPU
ns
4x
tCPU
ns
AFE INTERFACE SERIAL MODE (See Figure 8)
AFE Interface Operating
Frequency
1/tTRCK
(Note 5)
MHz
5
ns
0.6 x
tTRCK
ns
Clock Rise/Fall Time
tCRF
RXCLK/TXCLK Output Pulse
Width High/Low
tRCH,
tRCL
0.4 x
tTRCK
SDI Input Setup to RXCLK Active
Edge
tRIS
6
ns
SDI Input Hold After RXCLK
Active Edge
tRIH
1
ns
RXEN/TXEN Inactive Level
Output Pulse Width
tTREW
0.8 x
tTRCK
RXCLK/TXCLK to RXEN/TXEN
Active
tTREDF
RXCLK/TXCLK to RXEN/TXEN
Inactive
TXCLK to SDO Output
CL = 100pF
48
1.2 x
tTRCK
ns
0
10
ns
tTREDR
0
10
ns
tTOD
0
10
ns
tTRCK
Note 3: Typical values are measured at TA = +25°C, VDDC = 1.2V.
Note 4: Guaranteed by design.
Note 5: The maximum operating frequency is 20MHz when paired with the MAX2991.
www.maximintegrated.com
Maxim Integrated │ 22
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
SHIFT
SSEL
(SAS = 0)
SAMPLE
SHIFT
SAMPLE
tMCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tMCH
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tMCL
tMOV
tMOH
MSB
MOSI
tMLH
MSB-1
LSB
tMIH
tMIS
MSB
MISO
tRF
MSB-1
LSB
Figure 6. SPI Master Timing Diagram
SHIFT
SSEL
SAMPLE
SHIFT
SAMPLE
tSSH
tSSE
tSD
tSCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tSCH
tSCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tSIS
MOSI
tSIH
MSB-1
MSB
tRF
tSOV
MOSO
MSB
LSB
MSB-1
tSLH
LSB
Figure 7. SPI Slave Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 23
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
tTREW
TXCONV
tTREDR
tTREDF
tRCH
tRCL
TXCLK
tTOD
TXDATA
tTREW
RXCONV
tTREDR
tTREDF
tRCH
tRCL
RXCLK
tRIS
tRIH
RXDATA
Figure 8. AFE Timing Diagram
Applications Information
The MAX2992 is a powerline communications device that
transports information from the application layer across a
powerline network. In a typical application, the MAX2992
is used with an external host processor that handles
application layers and an IPV6 stack. For instance, in
a metering application, an external host processor that
is connected to the MAX2992 using the UART or SPI
interface processes metering data and encapsulates
the processed data into IPV6 packets to be transported
over the AC line. Additionally, the host implements interface primitives to communicate to the MAX2992. These
primitives direct data transfer as well as status and control
commands between the host and the MAX2992. Refer to
the MAX2992 G3-PLC Interface Guide for a description of
the interface primitives.
www.maximintegrated.com
External Crystal Requirements
The MAX2992 accepts crystals of various designs to set
the clock frequency. For example, use a crystal with a
maximum ESR of 1kΩ and CL of 20pF between 2MHz
and 6MHz. Use a crystal with a maximum ESR of 160Ω
and CL of 16pF between 6MHz and 10MHz. Use a crystal
with a maximum ESR of 90Ω and CL of 12pF between
10MHz and 20MHz. Use a crystal with a maximum ESR
of 40Ω and CL of 8pF between 20MHz and 30MHz.
External Flash Requirements
An external flash device is required for the automatic
bootstrap from the external flash option (see the Boot
Options section). The external flash supported by the
MAX2992 for booting is the AT45DB021D.
Maxim Integrated │ 24
MAX2992
Network Support
Depending on the application requirements, the MAX2992
can use various network topologies. In a star topology,
communication is established between devices and a
single central controller. Applications such as industrial
control and monitoring, sensor networks, asset and inventory tracking, and security benefit from the star topology.
The MAX2992 can also operate in a tree network topology where a controller communicates with devices in the
network either directly or by having messages forwarded
by other devices in the network. Applications such as
metering and lighting automation benefits from the tree
network topology.
The MAX2992 supports peer-to-peer mesh network
topologies. In peer-to-peer mesh networks, two devices
communicate with each other using other devices as forwarders without either of the devices in the network being
a controller.
G3-PLC MAC/PHY Powerline Transceiver
When a device receives a route request message, it calculates the route cost required for the message to get to
it. It stores that route cost and sends on the route request
message with the route cost it calculated. Since there
are many devices forwarding the route request message,
devices are likely to receive more than one route request
messages to support the creation of the same route.
The redundant copies of the message have the same
or higher calculated route cost. All the redundant copies
are dropped. When the message forwarding is complete,
the devices along the best path have the lowest route
cost back to the route request originator in their memory.
Figure 12 shows the route generated in bold by the route
request that makes up the best path from the requester to
the target. The lighter lines show messages that are not
on the optimal path.
MAX2992 Routing
The MAX2992 network of devices discovers routes
among the devices in the network. A route is discovered
by a device sending a route request message. The route
request message is sent by a device when the device
does not know how to route its message to the desired
device. Every device in the network except the target
device forwards the route request message at least once.
Figure 10. Tree Network Topology
Figure 9. Star Network Topology
www.maximintegrated.com
Figure 11. Peer-to-Peer Network Topology
Maxim Integrated │ 25
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
When the route request message reaches the target
device, it broadcasts a route reply message. This message includes the lowest route cost from the requestor
it received. Other devices update the message and
rebroadcast it if the route reply message contains a
route cost from the requester that is more than the route
A
Figure 12. Route Request Message Flow
www.maximintegrated.com
B
cost back to the requester in their memory. Each device
updates its routing table with the path that is the lowest
route cost from the target. Figure 13 shows the route
reply messages generated in this example. The MAX2992
builds an optimal route from device A to device B.
A
B
Figure 13. Route Reply Message Flow
Maxim Integrated │ 26
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Ordering Information (continued)
PART
TEMP RANGE
PIN-PACKAGE
MAX2992ECB+T
-40°C to +85°C
64 LQFP
MAX2992GCB+
-40°C to +85°C
64 LQFP
MAX2992GCB+T
-40°C to +85°C
64 LQFP
+Denotes lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
64 LQPF
C64-8
21-0083
90-0141
Chip Information
PROCESS: CMOS
www.maximintegrated.com
Maxim Integrated │ 27
MAX2992
G3-PLC MAC/PHY Powerline Transceiver
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
3/11
Initial release
1
4/14
Updated General Description, Benefits and Features, Ordering Information, Pin
Description, Electrical Characteristics table, AC Electrical Characteristics table
sections and Table 1
DESCRIPTION
—
1, 11,
18, 20, 21
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2014 Maxim Integrated Products, Inc. │ 28
工商网监
湘ICP备2023018690号
