MAX5318PMB#

EVALUATION KIT AVAILABLE MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface General Description The MAX5318 is a high-accuracy, 18-bit, serial SPI input, buffered voltage output digital-to-analog converter (DAC) in a 4.4mm x 7.8mm, 24-lead TSSOP package. The device features Q2 LSB INL (max) accuracy and a Q1 LSB DNL (max) accuracy over the full temperature range of -40NC to +105NC. The DAC voltage output is buffered resulting in a fast settling time of 3Fs and a low offset and gain drift of Q0.5ppm/NC of FSR (typ). The force-sense output (OUT) maintains accuracy while driving loads with long lead lengths. Additionally, a separate AVSS supply, allows the output amplifier to go to 0V (GND) while maintaining full linearity performance. The MAX5318 includes user-programmable digital gain and offset correction to enable easy system calibration. At power-up, the device resets its outputs to zero or midscale. The wide 2.7V to 5.5V supply voltage range and integrated low-drift, low-noise reference buffer amplifier make for ease of use. The MAX5318 features a 50MHz 3-wire SPI interface. The MAX5318 is available in a 24-lead TSSOP package and operates over the -40NC to +105NC temperature range. Benefits and Features S Ideal for ATE and High-Precision Instruments  INL Accuracy Guaranteed with ±2 LSB (Max) Over Temperature S Fast Settling Time (3µs) with 10kI || 100pF Load S Safe Power-Up-Reset to Zero or Midscale DAC Output (Pin-Selectable)  Predetermined Output Device State in Power-Up and Reset in System Design S Negative Supply (AVSS) Option Allows Full INL and DNL Performance to 0V S SPI Interface Compatible with 1.8V to 5.5V Logic S High Integration Reduces Development Time and PCB Area  Buffered Voltage Output Directly Drives 2kI Load Rail-to-Rail  Integrated Reference Buffer  No External Amplifiers Required S Small 4.4mm x 7.8mm, 24-Pin TSSOP Package Ordering Information and Typical Operating Circuit appear at end of data sheet. Applications Test and Measurement Equipment Programmable Voltage and Current Sources Automatic Test Equipment Automatic Tuning and Calibration Gain and Offset Adjustment Data-Acquisition Systems Functional Diagram Communication Systems VDDIO REF AVDD1 AVDD2 24 18 14 21 Medical Imaging Process Control and Servo Loops LDAC 5 CS 9 DIGITAL OFFSET SCLK 8 SPI DIN 7 DOUT 6 SPI INTERFACE READY 2 For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX5318.related. 17 REFO BUFFER MAX5318 BUSY 4 RST 1 M/Z 3 TC/SB 10 PD 11 7.8kI DIGITAL GAIN INPUT/DAC REGISTER DIN 18-BIT DAC 7.8kI 7.8kI OUTPUT BUFFER CONTROL LOGIC POWER-ON RESET 16 RFB 15 OUT 7.8kI SHUTDOWN 23 22 13 19 20 12 DGND BYPASS AGND AGND_S AGND_F AVSS For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-6465; Rev 0; 9/12 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ABSOLUTE MAXIMUM RATINGS AGND to DGND....................................................-0.3V to +0.3V AGND_F, AGND_S to AGND................................-0.3V to +0.3V AGND_F, AGND_S to DGND................................-0.3V to +0.3V AVDD to AGND........................................................-0.3V to +6V AVDD to REF............................................................-0.3V to +6V AVSS to AGND.........................................................-2V to +0.3V VDDIO to DGND........................................................-0.3V to +6V BYPASS to DGND........................................ -0.3V to the lower of (VAVDD_ or VDDIO + 0.3V) and +4.5V OUT, REFO, RFB to AGND.......................... -0.3V to the lower of (VAVDD + 0.3V) and +6V REF to AGND....................-0.3V to the lower of VAVDD and +6V SCLK, DIN, CS, BUSY, LDAC, READY, M/Z, TC/SB, RST, PD, DOUT to DGND........ -0.3V to the lower of (VDDIO + 0.3V) and +6V Continuous Power Dissipation (TA = +70NC) TSSOP (derate 13.9mW/NC above +70NC).............1111.1mW Operating Temperature Range......................... -40NC to +105NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) TSSOP Junction-to-Case Thermal Resistance (qJA)................13°C/W Junction-to-Ambient Thermal Resistance (qJA)...........72°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VAVDD = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N Integral Nonlinearity (Note 3) INL Differential Nonlinearity (Note 3) DNL Zero Code Error OE Zero Code Error Drift (Note 4) Gain Error Gain Error Temperature Coefficient (Note 4) Output Voltage Range Maxim Integrated GE 18 DIN = 0x00000 to 0x3FFFF (binary mode), DIN = 0x20000 to 0x1FFFF (two’s complement mode) DIN = 0x01900 to 0x3FFFF (binary mode), DIN = 0x21900 to 0x1FFFF (two’s complement mode), VAVSS = 0V Bits -2 Q0.5 +2 LSB -1 Q0.275 +1 LSB -48 Q4 +48 DIN = 0, TA = -40NC to +105NC DIN = 0 -1.6 Q14 Q0.10 +1.6 TA = +25NC -16 Q1 +16 DIN = 0, TA = +25NC TA = -40NC to +105NC TCGE Q27 -2.5 No load 0 Q0.10 LSB ppm/NC LSB +2.5 ppm/NC of FSR VAVDD 0.1 V   2 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2) PARAMETER SYMBOL CONDITIONS RST = pulse low Reset Voltage Output VOUT-RESET RST = pulse low, VAVSS = 0V RST = DGND RST = DGND, VAVSS = 0V DC Output Impedance (Normal Mode) ROUT Output Resistance (Power-Down Mode) Output Current IOUT Load Capacitance to GND CL RL Short-Circuit Duration DC Power-Supply Rejection ISC TSC DC PSRR TYP MAX UNITS 75 FV M/Z = VDDIO 2.048 V M/Z = DGND 10 mV M/Z = VDDIO 2.048 V M/Z = DGND -68 mV M/Z = VDDIO 2.036 V M/Z = DGND M/Z = VDDIO Closed-loop connection (RFB connected to OUT) PD = VDDIO Load Resistance to GND Short-Circuit Current MIN M/Z = DGND 10 mV 2.036 V 4 mI 2 kI Source/sink within 100mV of the supply rails Q4 Source/sink within 800mV of the supply rails Q25 mA 200 For specified performance 2 OUT shorted to AGND or AVDD Q60 REFO shorted to AGND or AVDD Q65 BYPASS shorted to AGND or AVDD Q48 Short to AGND or AVDD pF kI mA s Indefinite VOUT at full scale, VAVDD = 4.5V to 5.5V -2.5 Q0.20 +2.5 VAVSS = -1.5V to -0.5V -2.5 Q0.012 +2.5 LSB/V STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION VAVDD 0.1 2.4 V Reference High Input Range VREF Reference Input Capacitance CREF 10 pF Reference Input Resistance RREF 10 MI IB Q0.15 FA Reference Input Current STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION Reference High Output Range Reference High Output Load Regulation Reference Output Capacitor Maxim Integrated VAVDD 0.1 2.4 RESR < 5I V 500 ppm/ mA 0.1 nF   3 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDDIO = 4.5V to 5.5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 4.096V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.3 2.4 2.5 V 1 8 FF STATIC PERFORMANCE—VBYPASS OUT SECTION Output Voltage Load Capacitance to GND VBYPASS CL Required for stability, RESR = 0.1I (typ) POWER-SUPPLY REQUIREMENTS Positive Analog Power-Supply Range VAVDD 4.5 5.5 V Digital Interface Power-Supply Range VDDIO 1.8 VAVDD V Negative Analog Power-Supply Range VAVSS -1.5 -1.25 0 V Positive Analog Power-Supply Current IAVDD No load, external reference, output at zero scale 5.2 6.5 mA Negative Analog Power-Supply Current IAVSS No load, external reference, output at zero scale Interface Power-Supply Current IVDDIO Digital inputs at VDDIO or DGND 0.2 5.0 FA Positive Analog Power-Supply Power-Down Current PD = VDDIO, power-down mode 20 50 FA Negative Analog Power-Supply Power-Down Current PD = VDDIO, power-down mode -1.5 -5 -1.0 mA -3 FA 4.9 V/Fs 3 Fs 1.9 Fs DYNAMIC PERFORMANCE Voltage Output Slew Rate SR From 10% to 90% full scale, positive and negative transitions Voltage Output Settling Time tS From falling edge of LDAC to within 0.003% FS, RL = 10kI, DIN = 04000h (6.25% FS) to 3C000h (93.75% FS) Busy Time tBUSY (Note 5) DAC Glitch Impulse Major code transition (1FFFFh to 20000h), RL = 10kI, CL = 50pF 4 nVs Digital Feed Through CSB = VDDIO, fSCLK = 1kHz, all digital inputs from 0V to VDDIO 1 nVs Output Voltage-Noise Spectral Density At f = 1kHz to 10kHz, without reference, code = 20000h 26 nV/√Hz Output Voltage Noise At f = 0.1Hz to 10Hz, without reference, code = 20000h 1.55 FVP-P Wake-Up Time From power-down mode 75 Fs Power-Up Time From power-off 2 ms Maxim Integrated   4 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N Integral Nonlinearity (Note 3) INL Differential Nonlinearity (Note 3) DNL Zero Code Error OE Zero Code Error Drift (Note 4) Gain Error Gain Error Temperature Coefficient (Note 4) GE 18 DIN = 0x00000 to 0x3FFFF (binary mode), DIN = 0x20000 to 0x1FFFF (two’s complement mode) DIN = 0x01900 to 0x3FFFF (binary mode), DIN = 0x21900 to 0x1FFFF (two’s complement mode), VAVSS = 0V DIN = 0, TA = +25NC Output Current IOUT -1.0 Q0.3 +1.0 LSB -50 Q6 +50 Q25 Q1.4 +2.7 -16 Q1.5 +16 TA = -40NC to +105NC RST = pulse low, VAVSS = 0V RST = DGND, VAVSS = 0V ROUT LSB -2.7 RST = DGND DC Output Impedance +2.0 DIN = 0 Q35 No load VOUT-RESET Q0.75 TA = +25NC RST = pulse low Reset Voltage Output -2.0 DIN = 0, TA = -40NC to +105NC TCGE Output Voltage Range Bits ppm/NC of FSR 0 VAVDD 0.1 V M/Z = DGND 75 FV M/Z = VDDIO 1.25 V M/Z = DGND 10 mV M/Z = VDDIO 1.25 V mV M/Z = DGND -40 M/Z = VDDIO 1.25 V M/Z = DGND 10 mV M/Z = VDDIO 1.24 V 4 mI Closed-loop connection, RFB connected to OUT Source/sink within 100mV of the supply rails Q4 Source/sink within 800mV of the supply rails Q25 mA 200 CL RL For specified performance OUT shorted to AGND or AVDD Q60 Short-Circuit Current ISC REFO shorted to AGND or AVDD Q65 BYPASS shorted to AGND or AVDD Q48 Maxim Integrated LSB +3.2 Load Capacitance to GND tSC ppm/NC -3.2 Load Resistance to GND Short-Circuit Duration LSB Short to AGND or AVDD 2 pF kI Indefinite mA s   5 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2) PARAMETER DC Power-Supply Rejection SYMBOL DCPSRR CONDITIONS MIN TYP MAX VOUT at full scale, VAVDD = 2.7V to 3.3V -2.5 Q0.4 +2.5 VAVSS = -1.5V to -0.5V -2.5 Q0.04 +2.5 UNITS LSB/V STATIC PERFORMANCE—VOLTAGE REFERENCE INPUT SECTION VAVDD 0.1 Reference High Input Range VREF Reference Input Capacitance CREF 10 pF Reference Input Resistance RREF 10 MI IB Q0.15 FA Reference Input Current 2.4 V STATIC PERFORMANCE—VOLTAGE REFERENCE OUTPUT SECTION Reference High Output Range VAVDD 0.1 2.4 Reference High Output Load Regulation RESR < 5I Reference Output Capacitor V 500 ppm/mA 0.1 nF STATIC PERFORMANCE—VBYPASS OUT SECTION Output Voltage Load Capacitance to GND VBYPASS CL 2.3 Required for stability, RESR = 0.1I (typ) 2.4 2.5 V 1 8 FF POWER-SUPPLY REQUIREMENTS Positive Analog Power-Supply Range VAVDD 2.7 3.3 V Interface Power-Supply Range VDDIO 1.8 5.5 V Negative Analog Power-Supply Range VAVSS -1.5 -1.25 0 V Positive Analog Power-Supply Current IAVDD No load, external reference, output at zero scale 5.0 6.5 mA Negative Analog Power-Supply Current IAVSS No load, external reference, output at zero scale Interface Power-Supply Current IVDDIO Digital inputs at VDDIO or DGND 0.2 5.0 FA Positive Analog Power-Supply Power-Down Current PD = VDDIO, power-down mode 20 50 FA Negative Analog Power-Supply Power-Down Current PD = VDDIO, power-down mode -1.5 -5 -0.8 mA -2 FA 4.9 V/Fs 3 Fs DYNAMIC PERFORMANCE Voltage Output Slew Rate SR From 10% to 90% full scale, positive and negative transitions Voltage Output Settling Time tS From falling edge of LDAC to within 0.003% FS, RL = 10kI, DIN = 04000h (6.25% FS) to 3C000h (93.75% FS) Maxim Integrated   6 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDDIO = 2.7V to 3.3V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V, VREF = 2.5V, TC/SB = PD = LDAC = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, GAIN = 0x3FFFF, OFFSET = 0x00000, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (GAIN = 0x3FFFF and OFFSET = 0x00000.)(Note 2) PARAMETER Busy Time SYMBOL tBUSY CONDITIONS MIN TYP MAX UNITS (Note 5) 1.9 Fs DAC Glitch Impulse Major code transition (1FFFFh to 20000h), RL = 10kI, CL = 50pF 2.5 nVs Digital Feedthrough CSB = VDDIO, fSCLK = 1kHz, all digital inputs from 0V to VDDIO 1 nVs Output Voltage-Noise Spectral Density At f = 1kHz to 10kHz, without reference, code = 20000h 26 nV/√Hz Output Voltage Noise At f = 0.1Hz to 10Hz, without reference, code = 20000h 1.55 FVP-P Wake-Up Time From power-down mode 75 Fs Power-Up Time From power-off 2 ms DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (VAVDD = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, LDAC, M/Z, RST) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis (Note 4) 0.7 x VDDIO V 0.3 x VDDIO 200 VIHYST 300 Input Leakage Current IIN Q0.1 Input Capacitance CIN 10 DIGITAL OUTPUT CHARACTERISTICS (DOUT, READY, BUSY) ISOURCE = 5.0mA Output Low Voltage VOL V mV Q1 FA pF 0.25 VDDIO - 0.25 V Output High Voltage VOH ISINK = 5.0mA, except for BUSY Output Three-State Leakage IOZ DOUT only Q0.1 Output Three-State Capacitance COZ DOUT only 15 pF Output Short-Circuit Current IOSS VDDIO = 5.25V Q150 mA Maxim Integrated V Q1 FA   7 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued) (VAVDD = 5V, VDDIO = 2.7V to 5.5V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS Stand-alone, write mode Serial Clock Frequency fSCLK 50 Stand-alone, read mode and daisychained read and write modes (Note 5) 12.5 MHz Stand-alone, write mode 20 SCLK Period tCP Stand-alone, read mode and daisychained read and write modes 80 SCLK Pulse Width High tCH 40% duty cycle 8 ns SCLK Pulse Width Low tCL 40% duty cycle 8 ns Stand-alone, write mode 8 Stand-alone, read mode and daisy-chained read and write modes 38 ns CS Fall to SCLK Fall Setup Time tCSSO First SCLK falling edge CS Fall to SCLK Fall Hold Time tCSH0 Inactive falling edge preceding first falling edge 0 ns SCLK Fall to CS Rise Hold Time tCSH1 24th falling edge 2 ns ns DIN to SCLK Fall Setup Time tDS 5 ns DIN to SCLK Fall Hold Time tDH 4.5 ns SCLK Rise to DOUT Settle Time tDOT CL = 20pF (Note 6) SCLK Rise to DOUT Hold Time tDOH CL = 0pF (Note 6) 2 SCLK Fall to DOUT Disable Time tDOZ 24th active edge deassertion 2 30 ns CS Fall to DOUT Enable tDOE Asynchronous assertion 2 30 ns 32 ns ns Stand-alone, aborted sequence 35 Daisy-chained, aborted sequence 70 tCRF 24th falling-edge assertion, CL = 20pF 30 tCRH 24th falling-edge assertion, CL = 0pF SCLK Fall to BUSY Fall tCBF BUSY assertion CS Rise to READY Rise tCSR CL = 20pF CS Rise to SCLK Fall tCSA 24th falling edge, aborted sequence 20 ns CS Pulse Width High tCSPW Stand alone 20 ns SCLK Fall to CS Fall tCSF 24th falling edge 100 ns 20 ns 20 ns 20 ns CS Rise to DOUT Disable tCSDOZ SCLK Fall to READY Fall SCLK Fall to READY Hold LDAC Pulse Width LDAC Fall to SCLK Fall Hold RST Pulse Width Maxim Integrated tLDPW tLDH tRSTPW Last active falling edge 2 ns ns ns 5 ns 35 ns   8 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (VAVDD = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, LDAC, M/Z, RST) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis (Note 4) 0.8 x VDDIO 0.2 x VDDIO 200 VIHYST Input Leakage Current IIN Input Capacitance CIN V Input = 0V at VDDIO 300 Q0.1 V mV Q1 10 FA pF DIGITAL OUTPUTS CHARACTERISTICS (DOUT, READY, BUSY) Output Low Voltage VOL ISOURCE = 1.0mA Output High Voltage VOH ISINK = 1.0mA, except for BUSY Output Three-State Leakage IOZ DOUT only Output Three-State Capacitance COZ DOUT only Output Short-Circuit Current IOSS VDDIO = 2.7V 0.2 VDDIO - 0.2 V V Q0.1 Q1 FA 15 pF Q150 mA TIMING CHARACTERISTICS Serial Clock Frequency fSCLK Stand-alone write mode 50 Stand-alone read mode and daisychained read and write modes (Note 6) 8 MHz Stand-alone write mode 20 SCLK Period tCP Stand-alone read mode and daisychained read and write modes 125 SCLK Pulse-Width High tCH 40% duty cycle 9 ns SCLK Pulse-Width Low tCL 40% duty cycle 9 ns Stand-alone write mode 12 Stand-alone read mode and daisy-chained read and write modes 72 CS Fall to SCLK Fall Setup Time tCSSO First SCLK falling edge CS Fall to SCLK Fall Hold Time tCSH0 Inactive falling edge preceding first falling edge SCLK Fall to CS Rise Hold Time tCSH1 24th falling edge ns ns 0 ns 4 ns DIN to SCLK Fall Setup Time tDS 8 ns DIN to SCLK Fall Hold Time tDH 8 ns SCLK Rise to DOUT Settle Time tDOT CL = 20pF (Note 7) SCLK Rise to DOUT Hold Time tDOH CL = 0pF (Note 7) Maxim Integrated 40 2 ns ns   9 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued) (VAVDD = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS = 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.) (Note 2) PARAMETER SYMBOL CONDITIONS SCLK Fall to DOUT Disable Time tDOZ 24th active edge deassertion CS Fall to DOUT Enable tDOE Asynchronous assertion tCSDOZ CS Rise to DOUT Disable MIN TYP MAX UNITS 2 40 ns 2 50 ns Stand-alone, aborted sequence 70 Daisy-chained, aborted sequence 130 60 ns SCLK Fall to READY Fall tCRF 24th falling edge assertion, CL = 20pF SCLK Fall to READY Hold tCRH 24th falling edge assertion, CL = 0pF SCLK Fall to BUSY Fall tCBF BUSY assertion CS Rise to READY Rise tCSR CL = 20pF CS Rise to SCLK Fall tCSA 24th falling edge, aborted sequence 20 ns CS Pulse Width High tCSPW Stand alone 20 ns 24th falling edge 100 ns 20 ns tCSF SCLK Fall to CS Fall tLDH LDAC Fall to SCLK Fall Hold ns 5 ns 60 Last active falling edge tRSTPW RST Pulse Width Note Note Note Note Note Note 2 tLDPW LDAC Pulse Width ns ns 20 ns 20 ns 2: All devices are 100% tested at TA = +25°C and TA = +105°C. Limits at TA = -40°C are guaranteed by design. 3: Linearity is tested from VREF to AGND. 4: Guaranteed by design. 5: The total analog throughput time from DIN to VOUT is the sum of tS and tBUSY (4.9µs, typ). 6: Daisy-chain speed is relaxed to accommodate (tCRF + tCSS0). 7: DOUT speed limits overall SPI speed.. DIN R3 R2 R1 R0 D17 tDS tDH 1 SCLK 3 2 4 D15 D14 D1 D0 – 5 6 7 8 21 22 – X 23 24 25 tCSA tCH tCSSO tCSH0 D16 tCP tCSH1 tCL CS tCSPW DOUT tDOT tDOE Z 0 R3 R2 R1 R0 D17 D16 D15 tDOH D2 tDOZ D1 D0 0 tCSF Z tCRH READY tCRF tCSR Figure 1. Serial Interface Timing Diagram, Stand-Alone Operation Maxim Integrated   10 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) 1.2 1.2 0.4 -0.4 INL (LSB) 0.4 INL (LSB) 0.8 0.4 0 0 -0.4 0 -0.4 -0.8 -0.8 -0.8 -1.2 -1.2 -1.2 -1.6 -1.6 -1.6 -2.0 -2.0 131072 196608 -2.0 0 65536 131072 196608 262144 0 131072 196608 CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 2.0 VREF = 4.096V VAVDD = 5V 1.6 2.0 1.2 1.2 0.8 0.4 0.4 0.4 -0.4 DNL (LSB) 0.8 DNL (LSB) 0.8 0 0 -0.4 0 -0.4 -0.8 -0.8 -0.8 -1.2 -1.2 -1.2 -1.6 -1.6 -1.6 -2.0 -2.0 65536 131072 CODE Maxim Integrated 196608 262144 VREF = 2.5V VAVDD = 3V 1.6 262144 MAX5318 toc06 CODE 1.2 0 65536 CODE VREF = 5V VAVDD = 5.25V 1.6 262144 MAX5318 toc05 2.0 65536 VREF = 2.5V VAVDD = 3V 1.6 0.8 0 DNL (LSB) 2.0 0.8 MAX5318 toc04 INL (LSB) 1.2 VREF = 4.096V VAVDD = 5V 1.6 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5318 toc03 VREF = 5V VAVDD = 5.25V 1.6 2.0 MAX5318 toc01 2.0 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5318 toc02 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE -2.0 0 65536 131072 CODE 196608 262144 0 65536 131072 196608 262144 CODE   11 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) -0.4 0 -0.8 -1.6 -3.2 -2.0 -4.0 -40 -25 -10 5 20 35 50 65 80 95 110 INTEGRAL NONLINEARITY vs. TEMPERATURE 100 +25°C 1.6 +105°C 0.8 80 60 VREF = 4.096V 2.4 INL (LSB) 120 4.0 MAX5318 toc09a -40°C 140 0 -2.4 20 -3.2 MIN INL 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 LSB Maxim Integrated MAX5318 toc09 70 60 -40°C +10°C 50 +25°C 40 30 20 10 -4.0 0 20 35 50 65 80 95 110 INL DISTRIBUTION vs. TEMPERATURE MAX INL -1.6 -40 -25 -10 5 TEMPERATURE (°C) -0.8 40 MIN DNL -1.2 20 35 50 65 80 95 110 DNL DISTRIBUTION vs. TEMPERATURE 3.2 -0.4 -2.0 -40 -25 -10 5 TEMPERATURE (°C) 160 0 -1.6 TEMPERATURE (°C) 180 MAX DNL 0.4 -0.8 MIN INL -2.4 VREF = 4.096V 1.2 0.8 0.8 -1.6 MIN DNL -1.2 1.6 DNL (LSB) INL (LSB) 0 2.0 MAX INL 1.6 0.4 -0.8 VREF = 2.5V 2.4 MAX DNL 0.8 DNL (LSB) 3.2 MAX5318 toc10a 1.2 COUNT (NO. OF UNITS) 4.0 MAX5318 toc08 VREF = 2.5V DIFFERENTIAL NONLINEARITY vs. TEMPERATURE MAX5318 toc10 1.6 MAX5318 toc07 2.0 INTEGRAL NONLINEARITY vs. TEMPERATURE COUNT (NO. OF UNITS) DIFFERENTIAL NONLINEARITY vs. TEMPERATURE 0 -40 -25 -10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 LSB   12 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE MAX DNL 0.8 0.8 +105°C 0.4 0.4 30 -0.4 -0.8 20 MIN DNL -2.0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.5 3.9 4.3 4.7 5.1 VAVDD (V) VAVDD (V) DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE ZERO-SCALE OUTPUT ERROR vs. SUPPLY VOLTAGE INL (LSB) 0.4 0 -0.4 -0.8 0.4 0 MIN INL -0.4 -0.8 MIN DNL 1.2 OUTPUT ERROR (LSB) MAX INL 0.8 0.8 0.4 0 -0.4 -0.8 -1.2 -1.2 -1.6 -1.6 -1.6 -2.0 -2.0 -1.2 2.8 3.2 3.6 4.0 4.4 REFERENCE VOLTAGE (V) Maxim Integrated 4.8 5.2 VREF = 2.5V CODE = 0x00000 1.6 5.5 MAX5318 toc15 1.2 MAX DNL 0.8 VAVDD = 5.25V 1.6 2.0 MAX5318 toc14 1.2 2.0 MAX5318 toc13 VAVDD = 5.25V 2.4 3.1 LSB 2.0 1.6 MIN INL -1.6 -2.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0 -0.4 -1.2 -1.6 0 MAX INL -0.8 -1.2 10 DNL (LSB) 1.2 +40°C 0 VREF = 2.5V 1.6 INL (LSB) 40 1.2 2.0 MAX5318 toc11 +25°C 50 VREF = 2.5V 1.6 DNL (LSB) COUNT (NO. OF UNITS) 60 2.0 MAX5318 toc10b 70 INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE MAX5318 toc12 INL DISTRIBUTION vs. TEMPERATURE -2.0 2.4 2.8 3.2 3.6 4.0 4.4 REFERENCE VOLTAGE (V) 4.8 5.2 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VAVDD (V)   13 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) 0 -0.4 -0.8 1 SINKING 0 SOURCING -1 -2 -1.2 -3 -1.6 -2.0 3.1 3.5 3.9 4.3 4.7 5.1 -4 5.5 3 6 +25°C 20 -50 -40 -30 -20 -10 0 10 20 30 40 50 40 30 ZERO CODE ERROR DRIFT +10°C 70 -40°C 40 30 20 10 10 +105°C 40 30 20 10 0 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 +40°C 60 50 50 20 0 70 60 COUNT (UNITS) +105°C LSB ZERO CODE ERROR DRIFT +40°C Maxim Integrated 30 12 15 18 21 24 27 30 COUNT (UNITS) 70 COUNT (NO. OF UNITS) 9 80 MAX5318 toc17b 80 LSB 40 OUTPUT CURRENT (mA) ZERO CODE ERROR DISTRIBUTION vs. TEMPERATURE 50 +25°C 0 0 VAVDD (V) 60 +10°C 50 10 MAX5318 toc17c 2.7 -40°C 60 MAX5318 toc17d 0.4 2 70 COUNT (NO. OF UNITS) OUTPUT ERROR (LSB) OUTPUT ERROR (LSB) 0.8 CODE = 0x00000 VAVSS = -1.25V VREF = 4.096V 3 80 MAX5318 toc17 VREF = 2.5V CODE = 0x3FFFF 1.2 4 MAX5318 toc16 2.0 1.6 ZERO CODE ERROR DISTRIBUTION vs. TEMPERATURE ZERO-SCALE OUTPUT ERROR vs. OUTPUT CURRENT MAX5318 toc17a FULL-SCALE OUTPUT ERROR vs. SUPPLY VOLTAGE 0 0.2 0.4 0.6 0.8 1.0 DRIFT (ppm/°C) 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 DRIFT (ppm/°C)   14 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) +105°C SINKING 0 SOURCING -1 -2 -3 40 30 10 10 6 9 12 15 18 21 24 27 30 0 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 DRIFT (ppm/°C) DRIFT (ppm/°C) OUTPUT CURRENT (mA) OUTPUT DRIVE CAPABILITY OUTPUT DRIVE CAPABILITY OUTPUT ERROR (LSB) 6 4 2 0 -2 -4 CODE = 0x00000 VAVSS = -1.25V VREF = 4.096V SINKING CURRENT TA = +25°C 8 6 OUTPUT ERROR (LSB) CODE = 0x01900 VAVSS = 0V VREF = 4.096V SINKING CURRENT TA = +25°C 8 10 MAX5318 toc19 10 4 2 OUTPUT DRIVE CAPABILITY 10 0 -2 -4 6 4 2 0 -2 -4 -6 -6 -8 -8 -8 -10 -10 -10 0 1 2 3 4 5 6 OUTPUT CURRENT (mA) Maxim Integrated 7 8 CODE = 0x3FFFF VAVDD = 4.2V VREF = 4.096V SOURCING CURRENT TA = +25°C 8 OUTPUT ERROR (LSB) 3 30 20 MAX5318 toc20 0 -40°C 40 20 0 -4 +10°C 50 COUNT (UNITS) 1 60 MAX5318 toc18b +40°C 50 COUNT (UNITS) OUTPUT ERROR (LSB) 60 2 GAIN ERROR TEMPERATURE COEFFICIENT 70 MAX5318 toc18a CODE = 0x3FFFF VREF = 4.096V 3 GAIN ERROR TEMPERATURE COEFFICIENT 70 MAX5318 toc18 4 MAX5318 toc21 FULL-SCALE OUTPUT ERROR vs. OUTPUT CURRENT -6 0 5 10 15 20 25 30 35 40 45 50 OUTPUT CURRENT (mA) 0 1 2 3 4 5 6 7 8 OUTPUT CURRENT (mA)   15 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) OUTPUT DRIVE CAPABILITY 0 -2 -4 4 2 0 -2 -6 -8 -8 -10 -10 5 CODE = 0x00000 VAVSS = -1.25V VREF = 2.5V SINKING CURRENT TA = +25°C -4 -6 0 MAX5318 toc23 6 0 10 15 20 25 30 35 40 45 50 5 8 5 2 -1 -7 -10 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 55 60 5.9 TA = +105°C OUTPUT CURRENT (mA) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 40 MAX5318 toc25 6.0 VPD = 5V 35 5.7 TA = +105°C 30 5.6 IAVDD (µA) IAVDD (mA) 11 -4 SUPPLY CURRENT vs. SUPPLY VOLTAGE 5.5 5.4 25 20 5.3 5.2 TA = +25°C 5.1 TA = +25°C 15 TA = -40°C 5.0 TA = -40°C 10 4.50 4.75 5.00 VAVDD (V) Maxim Integrated 14 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) 5.8 CODE = 0x3FFFF VAVDD = 5V VREF = 2.5V SOURCING CURRENT TA = +25°C 17 MAX5318 toc26 2 27 OUTPUT ERROR (LSB) 4 8 OUTPUT ERROR (LSB) 6 OUTPUT ERROR (LSB) MAX5318 toc22 CODE = 0x3FFFF VAVDD = 5V VREF = 4.096V SOURCING CURRENT TA = +25°C 8 OUTPUT DRIVE CAPABILITY 10 MAX5318 toc24 OUTPUT DRIVE CAPABILITY 10 5.25 5.50 4.50 4.75 5.00 5.25 5.50 VAVDD (V)   16 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) MAX5318 toc27 100 CODE = 0x20000 VOUT 1µV/div VOLTAGE NOISE (nV/rt-Hz) 90 80 MAX5318 toc28 OUTPUT NOISE DENSITY 0.1Hz TO 10Hz OUTPUT NOISE 70 60 50 40 30 20 10 0 10 1s/div 100 1k 10k 100k FREQUENCY (Hz) DIGITAL CLOCK FEEDTHROUGH GROUND CURRENT vs. CODE CURRENT THROUGH AGND_F AND AGND_S VREF = 4.096V CURRENT (µA) 500 MAX5318 toc30 MAX5318 toc29 600 VSCLK 5V/div 400 300 VOUT 1mV/div 200 100 0 0 65536 131072 196608 262144 2µs/div CODE Maxim Integrated   17 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) MAJOR CARRY GLITCH (1 LSB NEGATIVE STEP) MAJOR CARRY GLITCH (1 LSB POSITIVE STEP) MAX5318 toc31 MAX5318 toc32 VLDAC 5V/div VLDAC 5V/div VOUT 10mV/div VOUT 10mV/div 400ns/div 400ns/div SETTLING TIME (CODE = 0x3C000 to 0x04000) SETTLING TIME (CODE = 0x04000 to 0x3C000) MAX5318 toc33 MAX5318 toc34 VLDAC 5V/div VLDAC 5V/div VOUT 2V/div VOUT 2V/div VOUT 200µV/div 1µs/div Maxim Integrated VOUT 200µV/div 1µs/div   18 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Characteristics (continued) (VAVDD = VDDIO = 5V, VAVSS = -1.25V, VAGND = VDGND = VAGND_F = VAGND_S = 0V; VREF = 4.096V, TC/SB = PD = M/Z = DGND, RST = VDDIO, CREFO = 100pF, CL = 100pF, RL = 10kω, CBYPASS = 1µF, TA = +25°C, unless otherwise noted.) ENTERING POWER-DOWN RESPONSE EXITING POWER-DOWN RESPONSE MAX5318 toc35 MAX5318 toc36 VPD 1V/div VPD 1V/div VOUT 2V/div VOUT 2V/div RL = OPEN 10µs/div 10µs/div SLOW POWER-UP RESPONSE (RSTSEL = LOW) SLOW POWER-UP RESPONSE (RSTSEL = HIGH) MAX5318 toc37 4ms/div Maxim Integrated MAX5318 toc38 VAVDD 5V/div VAVDD 5V/div VAVSS 2V/div VBYPASS 2V/div VREFO 2V/div VAVSS 2V/div VBYPASS 2V/div VREFO 2V/div VOUT 2V/div VOUT 2V/div 4ms/div   19 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Pin Configuration TOP VIEW RST 1 READY + 24 VDDIO 2 23 DGND M/Z 3 22 BYPASS BUSY 4 21 AVDD2 LDAC 5 20 AGND_F DOUT 6 19 AGND_S DIN 7 18 REF SCLK 8 17 REFO CS 9 16 RFB TC/SB 10 15 OUT PD 11 14 AVDD1 AVSS 12 13 AGND MAX5318 TSSOP Pin Description PIN NAME FUNCTION 1 RST Active-Low Reset Input. Drive RST low to DGND to put the device into a reset state. A reset state sets all SPI input registers to their default power-on reset states as defined by the state of inputs M/Z and TC/SB. Set RST high to VDDIO, the DAC output remains at the state defined by M/Z until LDAC is taken low. 2 READY SPI Active-Low Ready Output. READY asserts low when the device successfully completes processing an SPI data frame. READY asserts high at the next rising edge of CS. In daisy-chain applications, the READY output typically drives the CS input of the next device in the chain or a GPIO of a microcontroller. 3 M/Z Reset Select Input. M/Z selects the default state of the analog output (OUT) after power-on or a hardware or software reset. Connect M/Z to VDDIO to set the default output voltage to midscale or to DGND to set the default output voltage to zero scale. 4 BUSY Maxim Integrated Digital Input/Open-Drain Output. Connect a 2kI pullup resistor from BUSY to VDDIO. BUSY goes low during the internal calculations of the DAC register data. During this time, the user can continue writing new data to the DIN, OFFSET, and GAIN registers, but no further updates to the DAC register and DAC output can take place. If LDAC is asserted low while BUSY is low, this event is stored. BUSY is bidirectional, and can be asserted low externally to delay LDAC action. BUSY also goes low during power-on reset, when RST is low, or when software reset is activated.   20 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Pin Description (continued) PIN NAME FUNCTION 5 LDAC Active-Low Load DAC Logic Input. If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC register and the DAC output is updated. If LDAC is taken low while BUSY is asserted low, the LDAC event is stored and the DAC register update is delayed until BUSY deasserts. Any event on LDAC during power-on reset or when RST is low is ignored. 6 DOUT 7 DIN SPI Bus Serial Data Input. See the Serial Interface section for details. SPI Bus Serial Data Output. See the Serial Interface section for details. 8 SCLK SPI Bus Serial Clock Input. See the Serial Interface section for details. 9 CS 10 TC/SB SPI Bus Active-Low Chip-Select Input. See the Serial Interface section for details. DIN Format Select Input. Connect TC/SB to DGND to set the data input format to straight binary or to VDDIO to set it to two’s complement. 11 PD Active-High Power-Down Input. Connect PD to DGND for normal operation. Connect PD to VDDIO to place the device in power-down. In power-down, OUT (analog voltage output) is connected to AGND through a 2kω resistor, but the contents of the input registers and the DAC latch do not change. The SPI interface remains active in power-down. 12 AVSS Negative Analog Power-Supply Input. Connect to AGND or a negative supply voltage. When connected to the negative supply voltage, bypass AVSS with a 0.1µF capacitor to AGND. 13 AGND Analog Ground. Connect to the analog ground plane. 14 AVDD1 Positive Analog Power-Supply Input. Bypass each AVDD_ locally with a 0.1µF and 10µF capacitor to AGND (analog ground plane). Connect AVDD1 and AVDD2 together. 15 OUT Buffered Analog Voltage Output. Connect OUT to RFB externally to close the output buffer feedback loop. The buffered output is capable of directly driving a 10kω load. The state of M/Z sets the poweron reset state of OUT (zero or midscale). In power-down, OUT is connected to AGND through a 2kω pulldown resistor. 16 RFB Feedback Resistor Input. RFB is connected through the internal feedback resistor to the inverting input of the analog output buffer. Externally connect RFB to OUT to close the output buffer feedback loop. 17 REFO 18 REF 19 AGND_S DAC Analog Ground Sense 20 AGND_F DAC Analog Ground Force. Connect to the analog ground plane. 21 AVDD2 Positive Analog Power-Supply Input. AVDD2 supplies power to the internal digital linear regulator. Bypass AVDD2 locally to AGND with 0.1µF and 10µF capacitors. Connect AVDD2 and AVDD1 together. 22 BYPASS Internal Bypass Connection. Connect BYPASS to DGND with 0.01µF and 1µF capacitors. 23 DGND Digital Ground 24 VDDIO Digital Interface Power-Supply Input. Connect to a 1.8V to 5.5V logic-level supply. Bypass VDDIO with a 0.1µF capacitor to DGND. The supply voltage at VDDIO sets the logic-level for the digital interface. Maxim Integrated Voltage Reference Buffered Output. Bypass with a 100pF capacitor to AGND. High-Impedance 10Mω Voltage Reference Input   21 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Detailed Description up before AVDD at power up. Follow the recommendations described in the Power-Supply Sequencing section. The MAX5318 is a high-accuracy, 18-bit, serial SPI input, buffered voltage output digital-to-analog converter (DAC) in a 4.4mm x 7.8mm, 24-lead TSSOP package. The device features Q2 LSB INL (max) accuracy and a Q1 LSB DNL (max) accuracy over the full temperature range of -40NC to +105NC. Visit www.maximintegrated.com/products/references for a list of available external voltage-reference devices. The DAC voltage output is buffered resulting in a fast settling time of 3Fs and a low offset and gain drift of Q0.5ppm/NC of FSR (typ). The force-sense output (OUT) maintains accuracy while driving loads with long lead lengths. Additionally, a separate AVSS supply allows the output amplifier to go to 0V (GND) while maintaining full linearity performance. The MAX5318 includes user-programmable digital gain and offset correction capability to enable easy system calibration. At power-up, the device resets its outputs to zero or midscale, providing additional safety for applications, which drive valves or other transducers that need to be off on power-up. This is selected by the state of the M/Z input on power-up. The wide 2.7V to 5.5V supply voltage range and integrated low-drift, low-noise reference buffer amplifier makes for ease of use. Since the reference buffer input has a high input resistance, an external buffer is not required. The device accepts an external reference between 2.4V and VAVDD 0.1V for maximum flexibility and rail-to-rail operation. The MAX5318 features a 50MHz, 3-wire SPI, QSPI, MICROWIRE, and DSP-compatible serial interface. The separate digital interface supply voltage input (VDDIO) is compatible with a wide range of digital logic levels from 1.8V to 5.5V, eliminating the need for separate voltage translators. DAC Reference Buffer The external reference input has a high input (REF) impedance of 10MI||10pF and accepts an input voltage from +2.4V to VAVDD - 0.1V. Connect an external reference supply between REF and AGND. Bypass the reference buffer output REFO to AGND with a 100pF capacitor. Connect the anode of an external Schottky diode to REF and the cathode to AVDD1 to prevent internal ESD diode conduction in the event that the reference voltage comes Maxim Integrated Output Amplifier (OUT) The MAX5318 includes an internal buffer for the DAC output. The internal buffer provides improved load regulation for the DAC output. The output buffer slews at 5V/Fs and drives up to 2kI in parallel with 200pF. The buffer has a rail-to-rail output capable of swinging to within 100mV of AVDD_ and AVSS. The positive analog supply voltage (AVDD_) determines the maximum output voltage of the device as AVDD_ powers the output buffer. The output is diode clamped to ground, preventing negative voltage excursions beyond approximately -0.6V. Negative Supply Voltage (AVSS) The negative supply voltage (AVSS) determines the minimum output voltage. If AVSS is connected to ground, the output voltage can be set to as low as 100mV without degrading linearity. For operation down to 0V, connect AVSS to a negative supply voltage between -0.1V and -1.5V. The MAX1735 is recommended for generating -1.25V from a -5V supply. Force/Sense The MAX5318 uses force/sense techniques to ensure that the load is regulated to the desired output voltage despite line drops due to long lead lengths. Since AGND_F and AGND_S have code dependent ground currents, a ground impedance less than 13mω ensures that the INL will not degrade by more than 0.1 LSB. Form a star ground connection (Figure 2a) near the device with AGND_F, AGND_S, and AGND tied together. Always refer remote DAC loads to this system ground for best performance. Figure 2b shows how to configure the device and an external op amp for proper force/sense operation. The amplifier provides as much drive as needed to force the sensed voltage (measured between RFB and AGND_S) to equal the desired voltage.   22 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface 18-Bit Ideal Transfer Function The MAX5318 features 18-bit gain and 18-bit offset adjustment as shown in Figure 3. The incoming DIN code is multiplied and offset compensated by the generic equation shown in Equation 1. The resulting value is then applied to the DAC. OUT RFB MAX5318 AGND_F AGND_S AGND Equation 1) Generic gain and offset adjustment DAC = DIN × GAIN + OFFSET The GAIN code is always an 18-bit straight binary word. The OFFSET code is always two’s complement. It is therefore simply added to the output of the multiplier. Figure 2a. Star Ground Connection To guarantee that a gain of exactly 1 is possible, the actual gain coefficient applied to DIN is as defined in Equation 2. OUT RFB Equation 2) Calculation of gain G= (GAIN) + 1 AGND MAX5318 AGND_F 218 AGND_S When DIN is straight binary, the ideal transfer function is given by: Equation 3) Straight binary ideal transfer function Figure 2b. Force/Sense Connection VOUT =× G VDIN + VOFFSET When DIN is two’s complement, the ideal transfer function is given by: Equation 4) Two’s complement ideal transfer function LDAC OFFSET V VOUT = REF + G × VDIN + VOFFSET 2 VDIN and VOFFSET are the voltages to which the DIN and OFFSET codes are converted and VOUT is the voltage at the DAC output buffer. See the Conversion Formulas for DIN, GAIN, and OFFSET section for equations needed to convert the DIN and OFFSET codes into VDIN and VOFFSET. Maxim Integrated SPI INTERFACE GAIN DIN DAC REGISTER Figure 3. Gain and Offset Adjustment   23 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface The data DIN can be either straight binary or two’s complement. In straight binary, zero code results in a zeroscale output. In two’s complement, zero code results in a midscale output. To better understand how GAIN and OFFSET affect the output voltage, see Figure 4 and Figure 5. Consider the generation of a ramp. For now assume OFFSET is set to 0x00000. In straight binary mode, with GAIN set to 0x3FFFF (G = 1), DIN starts from 0x00000 and increases to 0x3FFFF. The output voltage will start at 0V and increase to (VREF - 1 LSB). If GAIN is reduced, the ramp will still start at 0V but the maximum level reached is reduced. With DIN set to two’s complement mode, to generate the same ramp, DIN would start at 0x20000 and increase until it wraps around to 0x00000. At this point the DAC output would be midscale. DIN then increases to 0x1FFFF where the output would be full-scale -1 LSB. As POSITIVE OFFSET IDEAL CHARACTERISTIC NEGATIVE OFFSET VOUT In both cases, a nonzero value for OFFSET results in the output moving up or down. Should the output of the gain and offset adjust block overflow full-scale or underflow zero-scale, the data is clipped so the DAC output will be clipped rather than overflow or underflow. The effect of gain and offset adjustment is shown in Figure 4 for straight binary mode and Figure 5 for two’s complement mode. If any of the DIN, GAIN, or OFFSET registers is changed, the device takes 1.9µs (tBUSY) to compute the new values to present to the DAC. While the device is computing the new DAC value, the BUSY output is set low. See the section on the BUSY output and LDAC input for details. POSITIVE OFFSET IDEAL CHARACTERISTIC NEGATIVE OFFSET FULL-SCALE VREF GAIN is reduced, the start of the ramp becomes larger and the end of the ramp becomes smaller. The ramp is therefore centered at midscale. VOUT FULL-SCALE VREF GAIN < 0x3FFFF (G < 1) MIDSCALE MIDSCALE GAIN < 0x3FFFF (G < 1) ZERO-SCALE 0V 00000h 20000h 3FFFFh DIN Figure 4. Gain and Offset Adjustment in Straight Binary Mode Maxim Integrated ZERO-SCALE 0V 20000h 00000h 1FFFFh DIN Figure 5. Gain and Offset Adjustment in Two’s Complement Mode   24 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Conversion Formulas for DIN, GAIN, and OFFSET Input, Gain, and Offset Ranges The ranges of DIN, GAIN, and OFFSET are summarized in Table 4 to Table 6. Also shown are the range values for the 18-bit MAX5318 with a 4.096V reference. Note that VREF is the reference voltage applied to REF and 1 LSB is equal to VREF/218. Tables 1a and 1b show how to convert the DIN code to VDIN in straight binary and two’s complement modes. Table 2 shows how to convert the GAIN code to the gain factor G, which is multiplied with VDIN. Table 3 shows how to convert the OFFSET code to VOFFSET, which is summed with the product G•VDIN. Table 1a. Converting DIN to VDIN (Straight Binary Mode) DIN EQUATION FOR VDIN V = DIN VREF × 0x00000 to 0x3FFFF DIN 2 18 RANGE 0V to (VREF - 1 LSB) Table 1b. Converting DIN to VDIN (Two’s Complement Mode) DIN EQUATION FOR VDIN AND VOFFSET RANGE 0x20000 to 0x3FFFF  DIN - 0x20000  VREF V= DIN VREF ×  2 2 18   VREF/2 to -1 LSB V= DIN VREF × 0x00000 to 0x1FFFF CODE 2 18 0V to (VREF/2 1 LSB) Table 2. Converting GAIN to G GAIN 0x00000 to 0x3FFFF EQUATION G= RANGE GAIN + 1 1/218 to 1 2 18 Table 3. Converting OFFSET to VOFFSET OFFSET EQUATION RANGE 0x20000 to 0x3FFFF  OFFSET − 0x20000  VREF VOFFSET = VREF ×  − 2 2 18   -VREF/2 to -1 LSB 0x00000 to 0x1FFFF Maxim Integrated VOFFSET = VREF × OFFSET 2 18 0V to (VREF/2 - 1 LSB)   25 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 4a. DIN Range (Straight Binary Mode) RANGE DIN VDIN (V) VALUE (V) Minimum 0x00000 0 0 Maximum 0x3FFFF (VREF - 1 LSB) 4.095984375 Table 4b. DIN Range (Two’s Complement Mode) RANGE DIN VDIN (V) VALUE (V) Minimum 0x20000 0 0 Maximum 0x1FFFF (VREF - 1 LSB) 4.095984375 Table 5. GAIN Range RANGE GAIN G VALUE (V) Minimum 0x00000 1/218 0.0000038147 Maximum 0x3FFFF 1 1 Table 6. OFFSET Range RANGE OFFSET VOFFSET (V) VALUE (V) Minimum 0x20000 -VREF/2 -2.048 Maximum 0x1FFFF (VREF/2 - 1 LSB) 2.047992188 Table 7. Straight Binary DIN Examples DIN 0x20000 0x30000 VDIN (V) 2.048 3.072 Maxim Integrated GAIN 0x2FFFF 0x0FFFF G 0.75 0.25 OFFSET 0x10000 0x30000 VOFFSET (V) CALCULATION COMMENT 1.024 VOUT = 0.75 x 2.048 + 1.024 = 2.56V • • • • For VOUT, use Equation 3 For VDIN, use Table 1a For G, use Table 2 For VOFFSET, use Table 3 second formula -1.024 VOUT = 0.25 x 3.072 - 1.024 = 0.512V • • • • For VOUT, use Equation 3 For VDIN, use Table 1a For G, use Table 2 For VOFFSET, use Table 3 first formula   26 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 8. Two’s Complement DIN Examples DIN 0x30000 0x10000 VDIN (V) -1.024 1.024 GAIN 0x2FFFF 0x0FFFF G 0.75 0.25 OFFSET 0x08000 0x38000 VOFFSET (V) CALCULATION 0.512 VOUT = 4.096/2 + 0.75 x (-1.024) + 0.512 = 1.792V • • • • For VOUT, use Equation 4 For VDIN, use Table 1b first formula For G, use Table 2 For VOFFSET, use Table 3 second formula -0.512 VOUT = 4.096/2 + 0.25 x 1.024 - 0.512 = 1.792V • • • • For VOUT, use Equation 4 For VDIN, use Table 1b first formula For G, use Table 2 For VOFFSET, use Table 3 first formula Numerical Examples Several numerical examples for the MAX5318, as shown in Table 7 and Table 8, illustrate how the gain and offset control changes the output voltage. The examples assume a reference voltage of 4.096V. Note that if the result of the calculation results in an under- or over-range output voltage, VOUT is set to its zero or full-scale value, respectively. An under-range output is less than 0V and an over-range output is greater than VREF - 1 LSB. Reset The device is reset upon power-on, hardware reset using RST, or software reset using register 0x4, bit 15, command RSTSW. After reset, the value of the input register, the DAC latch and the output voltage are set to the values defined by the M/Z input. If a hardware reset occurs during a SPI programming frame, anything before and after the reset for the frame will be ignored. A software reset initiated through the SPI interface takes effect after the end of the valid frame. Output State Upon Reset The output voltage can be set to either zero or midscale upon power-up, or a hardware or software reset, depending on the state of the M/Z input. After power-up, if the device detects that this input is low, the output voltage is set to zero scale. If M/Z is high, the output voltage is set to midscale. Maxim Integrated COMMENT Note that during reset, when RST is low or RSTSW is set to 0, the output voltage is set slightly lower than the value after coming out of reset. During reset, the output voltage is set to the values shown for the VOUT-RESET specification in the Electrical Characteristics. Power-Down The device can be powered down by either hardware (pulling PD high) or software (setting the PD_SW bit in either the 0x4 or 0xC registers). Note that the hardware and software inputs are ORed. Asserting either is enough to place the device in power-down mode. In order to restore normal operation to the device, satisfy both of these conditions: 1) Pull PD low. 2) Set the bits PD_SW’s (in both 0x4 and 0xC registers) to 0. In power-down, the output is internally connected to AGND through a 2kI resistor. The SPI interface remains active and the DAC register content remains unchanged. Data Format Selection (Straight Binary vs. Two’s Complement) The MAX5318 interprets the data code input (DIN) as either straight binary or two’s complement. To choose the straight binary format, set the TC/SB input low. For two’s complement, set the input high.   27 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface LDAC and BUSY Interaction event but does not implement it until processing is complete. Then, BUSY goes high and the device updates the DAC. The BUSY line is open drain and is normally pulled up by an external resistor. It is software-configurable bidirectional and can be pulled down externally. If any of the DIN, GAIN, and OFFSET registers is changed, the device must calculate the value to be presented to the DAC register. To indicate to the host processor that the device is busy, the device pulls the BUSY output low. Once computation is complete, the device releases BUSY and the host processor can load the DAC by toggling the LDAC input. If LDAC is set low while BUSY is low, the LDAC event is latched and implemented when the computation is complete and BUSY rises. 3) LDAC is held low. The host sends a new command and the device sets BUSY low. The device updates the DAC when the processing is complete and BUSY goes high. 4) BUSY is pulled down externally to delay DAC update. The BUSY pin is bidirectional. To use BUSY as an input, set the NO_BUSY bit to 1 using the 0x4 or 0xC command. When configured as an input, pulling BUSY low at least 50ns before the device releases the line delays DAC update. DAC update occurs only after BUSY is released and goes high. If used as an input, drive BUSY with an open-drain output with a pullup to VDDIO. The processing required for calculating the final DAC code is controlled by an internally generated clock. The clock frequency is not related to any external signals and the frequency is not precisely defined. Therefore, if the DAC must be updated at a precise time with the least amount of jitter, use option 1. There are four ways in which the LDAC and BUSY outputs can be used. This is shown graphically in Figure 6. 1) The host sends a new command. The device sets BUSY low. The host monitors BUSY to determine when it goes high. The device then pulses LDAC low to update the DAC. 2) The host sends a new command. The device sets BUSY low. The host toggles LDAC low then high before BUSY goes high. The device latches the LDAC DIN X 1 2 X 21 22 23 X INPUT REGISTER LOADED SCLK BUSY tBUSY LDAC tS tCBF OPTION 1 VOUT tLDPW LDAC tLDH OPTION 2 VOUT LDAC OPTION 3 OPTION 4 VOUT BUSY (USED AS INPUT) BUSY PULLED LOW EXTERNALLY 50ns LDAC VOUT Figure 6. BUSY and LDAC Timing Maxim Integrated   28 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Serial Interface upon the type of read command. Table 9 shows the bit positions for DOUT and DIN within the 24-bit SPI frame. Overview The SPI interface supports speeds up to 50MHz. When CS is high, the remaining interface inputs are disabled to reduce transient currents. The interface supports daisy chaining to enable multiple devices to be controlled on the same SPI bus. The device is designed such that SCLK idles low, and DIN and DOUT change on the rising clock edge and get latched on the falling clock edge. The SPI host controller should be set accordingly. Daisy-Chain SPI Operation Using READY Output The READY pulse appears 24 clock cycles after the negative edge of CS as shown in Figure 7 and can therefore be used as the CS line for the next device in the daisy chain. Since the device looks at the first 24 bits of the transmission following the falling edge of CS, it is possible to daisy-chain the device with different command word lengths. READY goes high after CS is driven high. The device has a double-buffered interface consisting of two register banks: the input register and the DAC register. The input register for DIN/GAIN/OFFSET is connected directly to the 24-bit SPI input shift register. The DAC latch contains the DAC code after digital processing and is loaded as defined in the LDAC and BUSY Interaction section above. A valid SPI frame is 24-bit wide with 4-bit command R3 to R0, 18-bit data D17 to D0, and 2 unused LSBs. A full 24-bit SPI command sequence is required for all SPI command operations, regardless of the number of data bits actually used for the command. Any commands terminating with less than a full 24-bit sequence will be aborted without impacting the operation of the part (subject to tCSA timing requirements). Data is not written into the SPI input register or DAC and it continues to hold the preceding valid data. If a command sequence with more than 24 bits is provided, the command will be executed on the 24th SCLK falling edge and the remainder of the command will be ignored. To perform a daisy-chain write operation, drive CS low and output the data serially to DIN. The propagation of the READY signal then controls how the data is read by the device. As the data propagates through the daisy chain, each individual command in the chain is executed on the 24th falling clock edge following the falling edge of the respective CS input. To update just one device in a daisy chain, send the no-op command to the other device in the chain. To update the first device in the chain, raise the CS input after writing to that device. Because daisy-chain operation requires paralleling the DOUTs of all the MAX5318 in the chain, the NO_HOLDEN bit in register 0x4 or 0xC should be set to 1 for all devices. Doing so ensures that DOUT goes into high-impedance after the SPI frame is complete (i.e. after the 24th clock cycle) as shown in Figure 8. All SPI commands result in the device assuming control of the DOUT line from the first SCLK edge through the 24th SCLK edge. After relinquishing the DOUT line, the MAX5318 returns to a high-impedance mode. An optional bus hold circuit can be engaged to hold DOUT at its last bit value while not interfering with other devices on the bus. Stand-Alone Operation The diagram in Figure 9 shows a stand-alone connection of the MAX5318 in a typical SPI application. If more than one peripheral device shares the DOUT bus, the NO_HOLDEN bit in register 0x4 or 0xC should be set to 1 for the MAX5318. Doing so ensures that DOUT goes into high-impedance after the SPI frame is complete (i.e. after the 24th clock cycle). DOUT is disabled at power-up and must be enabled through the SPI interface. When enabled, DOUT echoes the 4-bit command plus 18-bit data, which is being programmed. During readback, DOUT echoes the 4-bit command followed by the true readback data depending Table 9. SPI Command and Data Mapping with Clock Falling Edges CLOCK EDGE DIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 R3 R2 R1 R0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 R3 R2 R1 R0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Note that ‘X’ is don’t care. Maxim Integrated   29 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface µC MISO MOSI SCK SLAVE 1 SLAVE 2 CS DOUT DIN SCLK DOUT DIN SCLK DOUT DIN SCLK I/O SLAVE 3 READY READY CS READY CS Figure 7. Daisy-Chain SPI Connection Terminating with a Standard SPI Device. CS DIN SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA SCLK READY 1 1 2 3 4 20 21 22 23 24 1 2 3 4 5 21 22 23 24 1 2 3 4 5 21 22 23 24 READY 2 READY 3 HI-Z DOUT1 DOUT2 DOUT3 HI-Z HI-Z HI-Z Figure 8. Daisy-Chain SPI Connection Timing Maxim Integrated   30 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Command and Register Map All command and data registers have read and write functionality. The register selected depends on the command select bits R[3:0]. Each write to the device consists of 4 command select bits (R[3:0]), 18 data bits (which are detailed in Table 11 to Table 19), and 2 don’t care LSBs. A summary of the commands is shown in Table 10. Applications Information Power-On Reset (POR) Upon power-on, the output is set to either zero-scale (if M/Z is low) and midscale (if M/Z is high). The entire register map is set to their default values as shown in Table 11 to Table 19. TO OTHER DEVICES/CHAINS µC CSm MAX5318 CS1 CS CS SCLK SCLK DWRITE DIN DREAD DOUT Figure 9. Stand-Alone Operation Table 10. Register Map Summary HEX R3 R2 R1 R0 0 0 0 0 0 No-op. Used mainly in daisy-chain communications. FUNCTION 1 0 0 0 1 DIN register write 2 0 0 1 0 OFFSET register write 3 0 0 1 1 GAIN register write 4 0 1 0 0 Configuration register write 5–8 — — — — Reserved 9 1 0 0 1 DIN register read A 1 0 1 0 OFFSET register read B 1 0 1 1 GAIN register read C 1 1 0 0 Configuration and status register read. D–F — — — — Reserved Maxim Integrated   31 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Register Details Table 11. No-Op Command (0x0) BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME X X X X X X X X X X X X X X X X X X DEFAULT X X X X X X X X X X X X X X X X X X BIT NAME 17:0 DESCRIPTION No action on SPI shift register and DAC input registers. Use for daisy-chain purposes when R[3:0] = 0000. Don’t care Table 12a. Straight Binary DIN Write Register (TC/SB) = 0) (0x1) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME BIT B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 0x00000 when M/Z = DGND (zero scale) 0x20000 when M/Z = VDDIO (midscale) BIT NAME 17:0 DESCRIPTION 18-bit DAC input code in straight binary format. For clarity, a few examples are shown below: 00 0000 0000 0000 0000 0x00000 zero scale 01 0000 0000 0000 0000 0x10000 quarter scale 10 0000 0000 0000 0000 0x20000 midscale 11 0000 0000 0000 0000 0x30000 three-quarter scale 11 1111 1111 1111 1111 0x3FFFF full scale - 1 LSB B[17:0] Table 12b. Two’s Complement DIN Write Register (TC/SB) = 1) (0x1) BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 0x20000 when M/Z = DGND (zero scale) 0x00000 when M/Z = VDDIO (midscale) BIT 17:0 Maxim Integrated NAME DESCRIPTION B[17:0] 18-bit DAC input code in two’s complement format. For clarity, a few examples are shown below: 10 0000 0000 0000 0000 0x20000 zero scale 11 0000 0000 0000 0000 0x30000 quarter scale 11 1111 1111 1111 1111 0x3FFFF midscale - 1 LSB 00 0000 0000 0000 0000 0x00000 midscale 00 0000 0000 0000 0001 0x00001 midscale + 1 LSB 01 0000 0000 0000 0000 0x10000 three-quarter scale 01 1111 1111 1111 1111 0x1FFFF full scale - 1 LSB   32 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 13. OFFSET Register Write in Two’s Complement (0x2) BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 0x00000—Zero Offset BIT NAME 17:0 DESCRIPTION 18-bit offset code in two’s complement format. For clarity, a few examples are shown below: 10 0000 0000 0000 0000 0x20000 offset of -217 11 1111 1111 1111 1111 0x3FFFF offset of -1 00 0000 0000 0000 0000 0x00000 offset of 0 00 0000 0000 0000 0001 0x00001 offset of +1 01 1111 1111 1111 1111 0x1FFFF offset of 217 – 1 B[17:0] Table 14. GAIN Write Register (0x3) BIT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 0x3FFFF—Gain of 1 BIT 17:0 NAME B[17:0] Maxim Integrated DESCRIPTION 18-bit gain code. For clarity, a few examples are shown below: 11 1111 1111 1111 1111 3FFFF\h Gain of 1. (218 – 1 + 1)/218 11 1111 1111 1111 1110 3FFFE\h Gain of 0.999996. (218 – 2 + 1)/218 01 1111 1111 1111 1111 1FFFF\h Gain of 0.5. (217 – 1 + 1)/218 01 1111 1111 1111 1110 1FFFE\h Gain of 0.499996. (217 – 2 + 1)/218 00 0000 0000 0000 0000 00000\h Gain of 0.0000076. 1/218   33 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 15. General Configuration Write Register (0x4) BIT NAME 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD_SW NO_HOLDEN X X X X X X X X X X X X X 0 NO_BUSY 0 DOUT_ON 0 RST_SW 1 0 X X X X X X X X X X X X X DEFAULT BIT NAME 17 PD_SW DESCRIPTION Software PD (Power-Down). Equivalent to the PD input. 0: Normal mode 1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor. NO_HOLDEN SPI Bus Hold Enable. 0: Bus hold enabled for SPI DOUT output. DOUT stays at its last value after the SPI CS input rises at the end of the SPI frame (i.e. after the 24th clock cycle). 1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS input rises at the end of the SPI frame (i.e. after the 24th clock cycle). RST_SW Software Reset. Equivalent to the RST input. 0: Place device in reset 1: Normal operation Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low) NO_BUSY BUSY Input Disable. 0: BUSY input is active. 1: BUSY input is disabled. Note that this does not affect the BUSY bit in the General Configuration and Status Register. The BUSY pin is bidirectional. When enabled, it can be pulled down externally to delay DAC updates. 13 DOUT_ON SPI DOUT Output Disable. DOUT is disabled by default. 0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the duration of the SPI frame. 1: DOUT output enabled. 12:0 — 16 15 14 Maxim Integrated Don’t care. These bits are reserved for the corresponding read command.   34 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 16. DIN Read Register (0x9) BIT NAME DEFAULT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NAME 17:0 B[17:0] DESCRIPTION 18-bit DIN readback value. Table 17. OFFSET Read Register (0xA) BIT NAME DEFAULT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NAME 17:0 B[17:0] DESCRIPTION 18-bit OFFSET readback value in two’s complement. Table 18. GAIN Read Register (0xB) BIT NAME DEFAULT 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BIT NAME 17:0 B[17:0] Maxim Integrated DESCRIPTION 18-bit GAIN readback value.   35 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Table 19. General Configuration and Status Read Register (0xC) BIT NAME 17 16 15 14 13 12 11 10 9 8 7 6 5 2 1 0 PD_SW NO_ HOLDEN RST_SW NO_BUSY DOUT_ON BUSY X X X X X X REV_ID[3:0] X X 0 0 1 0 0 0 0 0 0 0 0001 0 0 DEFAULT BIT 17 NAME PD_SW 0 0 4 3 DESCRIPTION Software PD (Power-Down). Equivalent to the PD input. 0: Normal mode. 1: Power-down mode. OUT is internally connected to AGND using a 2kI resistor. NO_HOLDEN SPI Bus Hold Enable. 0: Bus hold enabled for SPI DOUT output. DOUT stays at its final value after the SPI CS input rises at the end of the SPI frame. 1: Bus hold disabled for SPI DOUT output. DOUT goes high impedance after the SPI CS input rises at the end of the SPI frame. RST_SW Software Reset. Equivalent to the RST input. 0: Place device in reset. 1: Normal operation. Set the active low RST_SW bit low to initiate a software reset (equivalent to pulling RST low). NO_BUSY BUSY Input Disable. 0: BUSY input is active. 1: BUSY input is disabled. Note that this does not affect the BUSY bit in the General Configuration and Status Register. The BUSY pin is bidirectional. When enabled, it can be pulled down externally to delay DAC updates. 13 DOUT_ON SPI DOUT Output Disable. DOUT is disabled by default. 0: DOUT output disabled. When DOUT is disabled, the output is pulled low for the duration of the SPI frame. 1: DOUT output enabled. 12 BUSY 11:6 — 5:2 REV_ID[3:0] 1:0 — 16 15 14 Maxim Integrated Global BUSY status readback. 0: Device is busy calculating output voltage. 1: Device is not busy. Reserved. Will read back 0. Device revision Reserved. Will read back 0.   36 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Power Supplies and Bypassing Considerations For best performance, use a separate supply for the MAX5318. Bypass VDDIO, AVDD_, and AVSS with highquality ceramic capacitors to a low-impedance ground as close as possible to the device. A typical high-quality X5R 10FF capacitor can become self resonant at 2MHz. Therefore, it is actually an inductor above 2MHz and is useless for decoupling signals above 2MHz. It is therefore recommended that several capacitors of different values are connected in parallel. Figure 10 shows the magnitude of impedance of typical 1FF, 100nF, and 10nF X5R capacitors. As the capacitance reduces, the self-resonant frequency increases. In addition, the parallel combination of all three is shown and exhibits a significant improvement over a single capacitor. These plots do not include any PCB trace inductance. Minimize lead lengths to reduce lead inductance. Adding just 2nH trace inductance to each of the typical capacitors above produces the effects shown in Figure 11. This shows significant reduction in the self-resonant frequencies of the capacitors. Internal Linear Regulator (BYPASS) BYPASS is the output of an internal linear regulator and is used to power digital circuitry. Connect BYPASS to DGND with a ceramic capacitor in the range of 1FF to 10FF with ESR in the range of 100mI to 20mI to ensure stability. The typical voltage on this pin is 2.4V. Use a low-leakage capacitor to ensure low power-down current. Power-Supply Sequencing During power-up, ensure that AVDD_ comes up before the reference does. If this is not possible, connect a Schottky diode between the REF and AVDD_ such as the MBR0530T1G. If REF does come up before AVDD_, the diode conducts and clamps REF to AVDD_. Once AVDD_ has come up, the diode no longer conducts. REF should always be below AVDD_ as specified in the Electrical Characteristics. AVDD_ and AVDD_ should be connected together and powered from the same supply. VDDIO and AVSS can be sequenced in any order. Always perform a reset operation after all the supplies are brought up to place the device in a known operating state. Layout Considerations Digital and AC transient signals on AGND inputs can create noise at the outputs. Connect both AGND inputs to form the star ground for the DAC system. Refer remote DAC loads to this system ground for the best possible performance (see the Force/Sense section). Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to AGND. Do not use wire-wrapped boards and sockets. Use ground plane shielding to improve noise immunity. Do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the device package. For a recommended layout, consult the MAX5318 Evaluation Kit datasheet. 3k 1k 3k 1k 100 IMPEDANCE (I) IMPEDANCE (I) 100 10nF 10nF 10 100nF 1 1µF 100m 10m 4m 100k 1M 100nF 1 1µF 100m 10M FREQUENCY (Hz) Figure 10. Typical X5R Capacitor Impedance Maxim Integrated 10nF 10 100M 10m 4m 100k 1M 10M 100M FREQUENCY (Hz) Figure 11. Typical X5R Capacitor Impedance with Additional 2nH PCB Trace Inductance   37 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Voltage Reference Selection and Layout The voltage reference should be placed close to the DAC. The same power-supply decoupling and grounding rules as the DAC should be implemented. Many voltage references require an output capacitor for stability or noise reduction. Provided the trace between the reference device and the DAC is kept short and well shielded, a single capacitor may be used and placed close to the DAC. However, for improved noise immunity, additional capacitors may be used but be careful not to exceed the recommended capacitance range for the voltage reference. Refer to Maxim Applications Note AN4300: Calculating the Error Budget in Precision Digital-to-Analog Converter (DAC) Applications for detailed description of voltage reference parameters and trading off the error budget. The MAX6126 is recommended for use with this device. the exact point at which the DAC update occurs is then determined internally as indicated by the BUSY line rising edge. This is not an exact time. BUSY Line Pullup Resistor Selection The BUSY pin is an open-drain output. It therefore requires a pullup resistor. 2kI value is recommended as a compromise between power and speed. Stray capacitance on this line can easily slow the rise time to an unacceptable level. The BUSY pin can sink up to 5mA. Therefore a resistor as low as VDDIO/0.005 may be used if faster rise times are required. Producing Unipolar High-Voltage and Bipolar Outputs Figure 11 and Figure 12 show how external op amps can be used to produce a unipolar high-voltage output and a bipolar output Optimizing Data Throughput Rate The LDAC and BUSY Interaction section details the timing of data written to the device and how the DAC is updated. Data throughput speed can be increased by overlapping the data load time with the calibration and settling time as shown below in Figure 12. Following the 24th SCLK falling edge, the device starts its calibration period. Providing that the LDAC falling edge arrives before the 24th SCLK falling edge, and assuming the SPI clock frequency is high enough, the throughput period is therefore limited by the internal calculation and settling times only. A slight further increase in throughput time can be gained by either toggling LDAC during the calculation time or by pulling it low permanently. However, Definitions Integral Nonlinearity (INL) INL is the deviation of the measured transfer function from a straight line drawn between two codes. This line is drawn between the zero and full-scale codes of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the DNL is less than or equal to 1 LSB, the DAC guarantees no missing codes and is monotonic. 24TH SCLK 24TH SCLK DIN BUSY tBUSY LDAC LDAC FALLING EDGE BEFORE 24TH SCLK FALLING EDGE OUT Figure 12. Optimum Throughput with Stable Update Period Maxim Integrated   38 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Offset Error Digital Feedthrough Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point. Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled. Gain Error The glitch impulse occurs at the major carry transitions along the segmented bit boundaries. It is specified as the net area of the glitch impulse which appears at the output when the digital input code changes by 1 LSB. The glitch impulse is specified in nanovolts-seconds (nV-s). Settling Time The digital-to-analog power-up glitch is the net area of the glitch impulse which appears at the output when the device exits power-down mode. Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The settling time is the amount of time required from the start of a LDAC high-to-low transition or BUSY low-to-high transition (whichever occurs last), until the DAC output settles to within 0.003% of the final value. Digital-to-Analog Glitch Impulse Digital-to-Analog Power-Up Glitch Impulse MAX44250 MAX5318 MAX9632 OUT -VREF TO VREF OUT 0V TO KVREF K = 1 + R2 /R1 MAX5318 R1 R1 R2 R2 REFO R1 = R2 Figure 13. Unipolar High-Voltage Output Maxim Integrated Figure 14. Bipolar Output   39 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Typical Operating Circuit 2.4V TO (VAVDD - 0.1V) 0.1µF 2.0kI BUSY 4 M/Z 3 2.7V TO 5V MBR0530T1G 1.8V TO 5V 0.01µF 1µF 0.1µF 10µF VDDIO REF BYPASS AVDD2 AVDD1 24 18 22 21 14 0.1µF LINEAR REGULATOR TS/SB 10 GPIO’s µC PD 11 RST 1 LDAC 5 READY 2 CS 9 SCLK SPI INTERFACE 7 DOUT 6 17 REFO BUFFER 100pF MAX5318 INTERFACE AND CONTROL 16 RFB INPUT REGISTER 8 DIN 10µF DIGITAL GAIN AND OFFSET DAC REGISTER 18-BIT DAC OUTPUT BUFFER 15 OUT RL 13 23 DGND AGND 19 AGND_S 12 20 AVSS AGND_F 0.1µF 0 TO -1.25V Ordering Information PART MAX5318GUG+ TEMP RANGE PIN-PACKAGE -40NC to +105NC 24 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. Chip Information PROCESS: BiCMOS Maxim Integrated Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 24 TSSOP U24+1 21-0066 90-0118   40 MAX5318 18-Bit, High-Accuracy Voltage Output DAC with Digital Gain, Offset Control, and SPI Interface Revision History REVISION NUMBER REVISION DATE 0 9/12 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ©  2012 Maxim Integrated 41 The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.