EVALUATION KIT AVAILABLE
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MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart
Power Selector, Automatic Detection, and USB
Enumeration
General Description
Benefits and Features
The MAX77301 is a JEITA-compliant* lithium-ion linear
battery charger that operates from a USB port, a dedicated charger, or universal adapter. The IC integrates independent battery charge switch, current sense circuit,
MOSFET pass elements, thermal regulation circuitry, and
eliminates the external reverse-blocking Schottky diode to
create the simplest and smallest USB-compliant charging
solution.
● Enables Charging from a USB Port
● Automatic Detection of Adapter Type
● Input Current Up to 1500mA and Charging Current Up
to 900mA
● Enumeration Without Processor Intervention
● Supports USB Low-Speed and Full-Speed
● Compliant with USB 2.0 Specification and Battery
Charging Specification (Revision 1.1)
● Compliant with Next Generation Low-Voltage Li-Ion
Battery Profiles
● Input Overvoltage Protection Up to 16V
● Smart Power Selector™ Allows Power Path Operation
with Discharged or No Battery
● Battery Detection Including Packs with Open
Protectors
● Thermal Regulation Prevents Overheating
● LED Indicator for Charge Done, Precharge, and Time/
Temperature Error
● Serial (400kHz) I2C-Compatible Interface
● 6µA (typ) Shutdown Current
● 2.44mm x 2.44mm, 25-Bump WLP Package
The IC includes automated detection of charge adapter
type, making it possible to distinguish USB 2.0 device,
USB charger, dedicated charger devices as well as standard input adapters. When enumeration is enabled, the IC
automatically negotiates with a USB host, making it possible to achieve the highest-charging current available from
a USB 2.0 device or USB charger without processor intervention. The adapter type detection is compliant with USB
2.0 as well as battery charging Specification Revision 1.1.
The IC controls the charging sequence for single-cell
Li+ batteries from battery detection, prequalification, fast
charge, top-off, and charge termination. Charging is controlled using constant current, constant voltage and constant die-temperature (CCCVCTj) regulation for safe operation under all conditions. The IC is also compliant with
JEITA battery charging requirements.
The Smart Power Selector feature makes the best use of
limited USB or adapter power. Battery charge current is
set independent of the input current limit. Power not used
by the system charges the battery. The battery assists the
input source when needed. System voltage is maintained
by allowing the application to operate without a battery, a
discharged battery, or a dead battery. Automatic input selection switches the system from battery to external power.
The I2C interface provides full programmability of battery
charge characteristics, input current limit, and protection
features. This provides flexibility for use with a wide range
of adapter and battery sizes.
Other features include undervoltage lockout (UVLO), overvoltage protection (OVP), charge status and fault flags, input power-OK monitor, charge timer, 3.3V/10mA auxiliary
output, and an external power-on switch.
Applications
• Smartphones, Bluetooth Headsets • AR/VR Glasses
• Hearables, Wearables • Portable Devices
19-6556; Rev 1; 12/20
Ordering Information appears at end of data sheet.
Simplified Operating Circuit
VBUS
4.0V TO 6.6V
(+16V OVP) BUS
I2 C
D+
D-
SYS
CONTROL
LOGIC
USB
INTERFACE
OSC
CHARGE AND
SYS LOAD
SWITCH
BATT
SYSTEM
LOAD
1-CELL LI-ION
MAX77301
Smart Power Selector is a trademark of Maxim Integrated
Products, Inc.
*U.S. Patent # 6,507,172
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data Contact Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
D+ and D- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low/Full Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Adapter Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
USB Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Keyboard Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Wake-Up and USB Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
USB Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Smart Power Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
System Load Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Setting Input Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Minimum VSYS Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Input Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power Monitor Output (UOK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Battery Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Charge Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Charge Termination (EOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CHG_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
IBUS_DEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Charge Status (CHG_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Maxim Integrated | 2
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
TABLE OF CONTENTS (CONTINUED)
Battery Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Automatic Detection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
NTC Detection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermistor Input (THM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
External Clock (Full Speed Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
USB Low-Speed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
External Crystal or Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Clock Timing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
External Power-On Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ESD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IEC 61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I2C Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I2C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Maxim Integrated | 3
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
LIST OF FIGURES
Figure 1. Block Diagram and Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2. Power-On Reset State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3. Adapter Detection Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4. Adapter Detection Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. Enumeration Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 6. USB BUS Traffic: Low-Speed Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. USB BUS Traffic: Full-Speed Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8. Smart Power Selector Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. Input Current Limit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. SYS Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. Charger State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Battery Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 14. Battery Present Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 15. JEITA Battery Safety Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 16. EXT_PWRON State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. Human Body ESD Test Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 18. Human Body Model Current Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 19. IEC61000-4-2 ESD Test Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 20. I2C Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21. I2C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 22. I2C START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 23. I2C Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 24. I2C Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 25. I2C Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 26. Recommended PCB Layout for Full Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. Recommended PCB Layout for Low Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
www.maximintegrated.com
Maxim Integrated | 4
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
LIST OF TABLES
Table 1. Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 2. Adapter Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3. Device Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 4. VBUS Valid Input Range (Rising) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. UOK States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6. CHG_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7. IBUS_DEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8. CHG_STAT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 10. CHIP_ID (Register 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11. CHIP_REV (Register 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 12. STATUS_A (Register 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 13. STATUS_B (Register 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 14. STATUS_C (Register 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 15. EVENT_A (Register 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 16. EVENT_B (Register 0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 17. IRQ_MASK_A (Register 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 18. IRQ_MASK_B (Register 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 19. USB_CNTL (Register 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 20. BAT_CNTL (Register 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 21. IBUS_CNTL (Register 0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 22. CHARGER_CNTL_A (Register 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 23. CHARGER_CNTL_B (Register 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 24. CHARGER_TMR (Register 0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 25. CHARGER_VSET (Register 0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 26. CHARGER_JEITA (Register 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 27. PRODUCT_ID_A (Register 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 28. PRODUCT_ID_B (Register 0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 29. VENDOR_ID_A (Register 0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 30. VENDOR_ID_B (Register 0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
www.maximintegrated.com
Maxim Integrated | 5
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Absolute Maximum Ratings
BUS_ to AGND .................................................... -0.3V to +16.0V
INT_3V3 to AGND .................................................... -0.3V to +6V
CHG_TYPE, IBUS_DEF, ENU_EN_HW, IRQ, D+, D-, UOK,
CHG_STAT, BAT_, SYS_, CEN, STDB_EN_HW to
AGND................................................................. -0.3V to +0.6V
XIN, THM, XOUT, to AGND ................ -0.3V to VINT_3V3 + 0.3V
EXT_PWRON, SDA, SCL to AGND .......... -0.3V to (VSYS + 0.3V
DGND to AGND..................................................... -0.3V to +0.3V
IBUS and ISYS Continuous Current (Note 1) ............ 2200mARMS
IBAT Continuous Current (Note 1) ............................ 1800mARMS
Continuous Power Dissipation (TA = +70ºC) WLP (derate
19.2mW/ºC above +70ºC). ..............................................1538mW
Operating Temperature......................................... -40ºC to +85ºC
Junction Temperature ....................................................... +150ºC
Storage Temperature Range .............................. -65ºC to +150ºC
Soldering Temperature (reflow) ........................................ +260ºC
Note 1: IBUS = IBUS_A + IBUS_B; ISYS = ISYS_A + ISYS_B; IBAT = IBAT_A + IBAT_B
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
WLP
Package Type
25 WLP (0.4mm pitch)
Package Code
W252H2+1
Outline Number
21-0453
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction-to-Ambient Thermal Resistance (θJA)
52°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7,
using a four-layer board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Electrical Characteristics
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
6.6
V
14
V
50
ms
USB-TO-SYS PREREGULATOR
USB Operating Range
VBUS
USB Standoff Voltage
USB_OK Debounce
Timer
www.maximintegrated.com
Initial VBUS voltage before enabling
charger
4.0
VBAT = VSYS = 0V, IBUS < 800μA
tUSB_DB
Time from BUS within valid range until
UOK goes high impedance
30
Maxim Integrated | 6
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Electrical Characteristics (continued)
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
SYMBOL
USB Undervoltage
Lockout Threshold
CONDITIONS
IDETECT
IENUMERATE
USB Input Supply
Current (Notes 3, 4)
ISUSPEND
MAX
Before initial
detection of
external device
3.85
4.0
4.15
UOK logic-low,
VBUS falling,
customer UVLO
For > 500mA
adapter and except
for ILIM [2:0] = 000,
111
3.40
3.55
3.70
USB 2.0 low-power
device
3.75
3.9
4.05
USB 2.0 highpower device
3.95
4.1
4.25
UOK logic-low, VBUS rising, 100mV
hysteresis
6.7
6.9
7.1
Charge type detection, ISYS = IBAT =
0mA
0.5
USB 2.0 enumeration in progress, ISYS =
IBAT = 0mA
100
Suspended mode, ISYS = IBAT = 0mA,
VSTDB_EN_HW = 0V
0.5
TA = 0ºC to +85ºC
IUSB_100mA
USB 2.0 low-power
device detected
IUSB_500mA
102.5
USB 2.0 highpower device
detected
500
USB 2.0 low-power
device detected
IENU
During USB enumeration, TA = +25ºC
80
90
98
IUSB_LP
USB 2.0 low-power device detected, TA =
+25ºC
80
90
98
IUSB_HP
USB 2.0 high-power device detected
455
475
490
ILIM = 000, TA = +25ºC
80
90
98
ILIM = 001 (default)
455
475
490
ILIMIT
During suspend
600
ILIM = 011
700
ILIM = 100
900
ILIM = 101
1000
ILIM = 110, TA = +25ºC (Note 3)
1344
1500
1650
ILIM = 110, TA = -40ºC to +85ºC
1324
1500
1700
200
320
VBAT 50mV
VBAT 20mV
VBUS = 5V, ISYS = 400mA
VSYS_to VBAT_ Reverse
Regulation
When SYS is in regulation and charging
stops, VSYS_ falling, 50mV typical
hysteresis
V
V
mA
0
ILIM = 010
VBUS_ to VSYS_ OnResistance
UNITS
100
TA = -40ºC to
+85ºC
ISUS
USB Input Current Limit
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TYP
UOK logic-low,
VBUS rising,
100mV hysteresis
UOK logic-low,
VBUS falling
USB Overvoltage
Protection Threshold
MIN
VBAT 80mV
mA
mI
Maxim Integrated | 7
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Electrical Characteristics (continued)
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
SYMBOL
Input Limiter Soft-Start
Time
Thermal-Limit Start
Temperature
CONDITIONS
MIN
Input current ramp time
TDIE_LIM
100
μs
90
THERM _REG = 10
110
SYS Regulation Voltage
VBAT > 3.45V, ISYS = 1mA to 1.6A
TDIE_LIM
+ 10ºC
ºC
5
%/ºC
140mV + 210mV +
VBAT
VBAT
V_SYS = 00
VBUS = 6V, ISYS =
1mA to 1.6A
ºC
120
ISYS reduction/die temperature
VSYS_UVLO
50
100
Thermal-Limit Gain
Undervoltage Lockout
UNITS
THERM _REG = 01
THERM _REG = 11
VSYS_MIN
MAX
THERM_REG = 00
Thermal-Limit Triggers
IRQ
Minimum SYS
Regulation Voltage
TYP
3.4
V_SYS = 01 TA =
+25ºC
4.2
4.35
4.524
V_SYS = 02 TA =
-40ºC to +85ºC
4.185
4.35
4.524
V_SYS = 10
4.4
V_SYS = 11
4.5
VBUS_ = 5.5V rising
3.0
VBUS_ = 5.5V falling
V
2.6
2.85
3.1
55
80
V
V
CHARGER
BAT-to-SYS OnResistance
BAT Undervoltage
Lockout (Register
0x10h, Bit 7 = 0)
VBAT = 4.2V, ISYS = 200mA
VBAT_UVLO_F
VBAT falling
BAT_UVLO_VPRE
Q = 1 (register
0x10h)
2.15
2.40
2.65
VBAT_UVLO_R
VBAT rising
BAT_UVLO_VPRE
Q = 1 (register
0x10h)
2.45
2.70
2.95
VBAT_UVLO_F
VBAT falling
BAT_UVLO_VPRE
Q = 0 (default,
register 0x10h)
1.60
1.85
2.10
VBAT_UVLO_R
VBAT rising
BAT_UVLO_VPRE
Q = 0 (default,
register 0x10h)
1.85
2.10
2.35
Charger Soft-Start Time
V
1
BAT Leakage Current
VBAT = 4.2V
mI
ms
VBUS not
connected
2
6
VBUS connected,
VCEN = 0V
6
15
μA
PRECHARGE MODE
BAT Precharge Current
www.maximintegrated.com
IPCHG
VBAT > 1.4V (Note 5)
50
mA
Maxim Integrated | 8
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Electrical Characteristics (continued)
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
VBAT_PCHG_F
VBAT falling
BAT_UVLO_VPRE
Q = 1 (register
0x10h)
2.60
2.70
2.80
VBAT_PCHG_R
VBAT rising
BAT_UVLO_VPRE
Q = 1 (register
0x10h)
2.70
2.80
2.95
VBAT_PCHG_F
VBAT falling
BAT_UVLO_VPRE
Q = 0 (default,
register 0x10h)
2.05
2.15
2.25
VBAT_PCHG_R
VBAT rising
BAT_UVLO_VPRE
Q = 0 (default,
register 0x10h)
2.15
2.25
2.40
BAT Prequalification
Threshold
UNITS
V
FAST-CHARGE MODE
BAT Charge-Current Set
Range
IFCHG
VBAT_FCHG_R
BAT Fast-Charge
Threshold
VBAT_FCHG_H
YS
IFCHG = 000
100
IFCHG = 010 (default)
200
IFCHG = 001
300
IFCHG = 110
370
IFCHG = 111
450
IFCHG = 011
600
IFCHG = 100
800
IFCHG = 101
900
VBAT rising
threshold, where
charging current
IFCHG is reduced
to ITCHG
VBAT hysteresis,
the falling threshold
where charging
current is increased
to IFCHG is:
VBAT_FCHG_HYS =
VBAT_FCHG_R VBAT_FCHG_F
BAT_FCHG = 00
3.8
BAT_FCHG = 01
3.9
BAT_FCHG = 10
(default)
3.88
4
BAT_FCHG = 11
4.1
BAT_FCHG_HYS
= 00
150
BAT_FCHG_HYS
= 01 (default)
200
BAT_FCHG_HYS
= 10
250
BAT_FCHG_HYS
= 11
300
mA
4.12
V
mV
TOP-OFF CHARGE MODE
Top-Off Charge Current
ITCHG
VBAT > 1.4V
(Note 5)
TCHG = 00
0.4 x
IFCHG
TCHG = 01
0.6 x
IFCHG
TCHG = 10
TCHG = 11
(default)
www.maximintegrated.com
0.8 x
mA
IFCHG
1.0 x
IFCHG
Maxim Integrated | 9
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Electrical Characteristics (continued)
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
Charge DONE
Qualification (Note 3)
SYMBOL
ICHG_DONE
CONDITIONS
MIN
CHG_DONE = 000
10
CHG_DONE = 001
20
BAT Regulation Voltage
(MAX77301A)
BAT Recharge
Threshold
VBAT_REG
VBAT_REG
VBAT_RECHG
MAX
CHG_DONE = 010
30
40
50
CHG_DONE = 011
37.5
50
62.5
45
60
75
CHG_DONE = 100 (default)
CHG_DONE = 101
80
CHG_DONE = 110
100
CHG_DONE = 111
BAT Regulation Voltage
(MAX77301)
TYP
IBAT_ = 0mA
IBAT_ = 0mA
With respect to
VBAT_REG
UNITS
mA
120
BAT_REG = 00
4.05
BAT_REG = 01
4.10
BAT_REG = 10
4.15
BAT_REG = 11
(default)
TA = +25ºC
4.179
4.200
4.221
BAT_REG = 11
(default)
TA = 0ºC to +85ºC
4.158
4.200
4.242
BAT_REG = 00
4.25
BAT_REG = 01
4.30
BAT_REG = 10
4.35
BAT_REG = 11
(default)
TA = +25ºC
4.378
4.40
4.422
BAT_REG = 11
(default)
TA = 0ºC to +85ºC
4.356
4.40
4.444
BAT_RECHG = 00
(default)
-350
BAT_RECHG = 10
-300
BAT_RECHG = 01
-250
BAT_RECHG = 11
-200
PCHG_TMR = 00
30
PCHG_TMR = 01
60
PCHG_TMR = 10
(default)
120
PCHG_TMR = 11
240
FCHG_TMR = 00
75
FCHG_TMR = 01
150
FCHG_TMR = 10
300
FCHG_TMR = 11
(default)
600
V
V
mV
CHARGE TIMER
Prequalification Timer
Fast-Charge Timer
www.maximintegrated.com
tPCHG
tFCHG
From start of
precharge until end
of prequalification
charge model
(Figure 11)
From start of fast
charge until
maintains charge
(Figure 11)
Minutes
Minutes
Maxim Integrated | 10
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Electrical Characteristics (continued)
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
Maintain-Charge Timer
SYMBOL
tMTCHG
CONDITIONS
(Figure 12)
MIN
TYP
MTCHG_TMR = 10
(default)
0
MTCHG_TMR = 01
15
MTCHG_TMR = 00
30
MTCHG_TMR = 11
60
Timer Accuracy
-30
MAX
UNITS
Minutes
+30
%
Timer Extend Threshold
Percentage of charge current below
which timer clock operates at half speed
50
%
Timer Suspend
Threshold
Percentage of charge current below
which timer clock pauses
20
%
INSERTION AND REMOVAL DETECTION
BAT Discharge Current
IDIS
1V ≤ VBAT ≤ 4.2V, CBAT ≤ 10μF
BAT Discharge Time
tDIS
Discharge timer expires if VBAT drop >
VBAT_UVLO threshold, battery cap ≤
10μF
Charge Debounce Timer
tDB
Delay before checking charge done
Battery Detecting
Current
0.375
1.125
150
mA
ms
100
150
200
ms
1
3
5
mA
IDM_SINK
50
100
150
μA
IDP_SRC
7
IBAT_DET
Charging in prograss (precharge, fastcharge or maintain charge);
if IBAT < IBAT_DET = battery absence
ADAPTER TYPE DETECTION
D- Current Sink
D+ Current source
D- Weak Current Sink
IDM_CD_PD
μA
μA
D+ Source Voltage
VDP_SRC
0.5
0.6
0.7
V
D+ Detection Threshold
VDAT_REF
0.25
0.32
0.40
V
D- Logic-High Threshold
VDM_IH
0.8
2.0
V
D+ Logic-High
Threshold
VDP_IH
0.8
2.0
V
D+/D- Detection
Threshold
D- Pulldown Resistor
IDP_SRC = 200μA
13
0.1
DP_25%
DM_25%
Detection threshold for custom chargers
as % of VBUS
23.75
25.0
26.25
DM_34%
Detection threshold for custom chargers
as % of VBUS
32.3
34
35.7
DP_47%
DM_47%
Detection threshold for custom chargers
as % of VBUS
44.65
47.00
49.4
DP_60%
DM_60%
Detection threshold for custom chargers
as % of VBUS
57
60
63
RDM_DWN
%
14.25
24.8
kΩ
D- Pullup Resistor
RDM_PU
External resistor = 33Ω, low speed only
1.425
1.500
1.575
kΩ
D+ Pullup Resistor
RDP_PU
External resistor = 33Ω, full speed only
1.425
1.500
1.575
kΩ
200
330
600
kΩ
D+ Charger Detection
Pullup Resistor
RDP_CD_PU
Data Contact Detection
Debounce Timer
tDCD_DBNC
www.maximintegrated.com
RDP_CD_PU connected to INT_3V3
30
ms
Maxim Integrated | 11
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Electrical Characteristics (continued)
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
D+ Source On Time
tDP_SRC_ON
100
ms
D+ Source to HighCurrent Time
tDP_SRC_HC
40
ms
Time from start of enumeration process
until enumeration
10
s
Time from suspend mode until it reenumerates, RWU_EN = 1
100
ms
Time from failed enumeration to adapter
type detection reenabled, nENU_EN = 0
3
s
Detecting Time
D+/D- open power source nENU_EN = 1
100
ms
Enumeration Fail to
Reconnect Timer
Time from enumeration fail at 500mA
until enumeration is retried at 100mA or
time from enumeration fail at 100mA until
reconnect timer is started
87
ms
Enumeration Time Limit
Reenumeration Timer
Reconnect Timer
tENUM
tRE_ENUM
tFAULT
tENU_FAULT
XIN, XOUT PINS
Oscillator Frequency
Accuracy
Internal oscillator (low speed), TA =
+25ºC
XIN, XOUT Input
Capacitance
With external crystal (full speed)
XIN Input Current
With external crystal (full speed)
5.91
6.00
3
0.667 x
VINT_3V
XIN Logic-High Input
Voltage
6.09
pF
10
FA
VINT_3V
V
3
3
XIN Logic-Low Input
Voltage
MHz
0.4
V
THERMISTOR MONITOR (THM)
THM Hot Threshold
T4
VTHM raising, 2% hysteresis
32.2
% of
VINT_3V3
THM Warm Threshold
T3
VTHM raising, 2% hysteresis
46.5
% of
VINT_3V3
THM Cool Threshold
T2
VTHM falling, 2% hysteresis
81.9
% of
VINT_3V3
THM Cold Threshold
T1
VTHM falling, 2% hysteresis
88.7
% of
VINT_3V3
VTHM falling, 2% hysteresis
3.4
% of
VINT_3V3
High impedance when no BUS or THM is
disabled
500
kΩ
THM Disable Threshold
THM Input Impedance
THM Input Leakage
THMZIN
THM = AGND
THERM_EN = 0
TA = +25ºC
THM = AGND
THERM_EN = 1
TA = +85ºC
-1
0.001
+1
μA
0.01
EXT_PWRON
Logic-Low Output
Voltage
www.maximintegrated.com
Sinking 10mA
35
100
mV
Maxim Integrated | 12
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Electrical Characteristics (continued)
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
SYMBOL
CONDITIONS
tEXT_PWR_RE
Time where EXT_PWRON is highimpedance during transition between two
EXT_PWRON low states
63
Logic-Low Output
Voltage
Sinking 10mA
35
Blink Period for
Temperature Suspend
Mode
50% duty cycle, battery present
1.5
s
Blink Period for Timeout
Mode
50% duty cycle, battery present
0.15
s
High-Impedance Time
SET
MIN
TYP
MAX
UNITS
ms
CHARGER STATUS (CHG_STAT)
100
mV
LOGIC I/O: UOK, CEN, ENU_EN_HW
Logic Input Voltage
High level
1.3
High level for SDA and SCL
1.4
V
Low level
Logic Input-Leakage
Current
VBUS = 0V to 5.5V
Logic-Low Output
Voltage (CHG_TYPE,
IRQ, UOK, Only)
Sinking 10mA
0.4
TA = +25ºC
0.001
TA = +85ºC
0.01
1
35
100
TA = +25ºC
0.001
1
TA = +85ºC
0.01
μA
mV
Logic-High OutputLeakage Current
(CHG_TYPE, IRQ,
UOK, Only)
VSYS = 5.5V
UOK Blink Period
During USB Suspend
Only for USB automatically entering
suspend mode, 50% duty cycle
1.5
s
UOK Blink Period with
Open D+/D- Detected
50% duty cycle
0.15
s
μA
I2C INTERFACE (See Figure 20) (Note 3)
Clock Frequency
Bus-Free Time Between
START and STOP
400
tBUF
Hold Time Repeated
START Condition
kHz
1.3
μs
0.6
μs
SCL Low Period
tLOW
1.3
μs
SCL High Period
tHIGH
0.6
μs
Setup Time Repeated
START Condition
tSU_STA
0.6
μs
SDA Hold Time
tHD_DAT
0
μs
SDA Setup Time
tSU_DAT
100
μs
Maximum Suppressed
Pulse Width
www.maximintegrated.com
Width of spikes that must be suppressed
by the input filter of both SDA and SCL
signals
50
ns
Maxim Integrated | 13
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Electrical Characteristics (continued)
(THM = AGND, CEN = INT_3V3, VBAT = 4.2V, VBUS_, EXT_PWRON, UOK, IRQ, CHG_TYPE, and CHG_STAT are unconnected, TA
= -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC.) (Note 2 )
PARAMETER
Setup Time for STOP
Condition
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
tSU_STO
0.6
μs
|VD+ - VD-|
0.2
V
USB DATA INTERFACE
Differential-Receiver
Input Sensitivity
Differential-Receiver
Common-Mode Voltage
0.8
D+, D- Input Impedance
300
D+, D- Output Low
Voltage
VOL
RLOAD = 1.5kΩ from VD- to 3.6V
D+, D- Output High
Voltage
VOH
RLOAD = 15kΩ from D+ and D- to AGND
Driver Output
Impedance
Excludes external resistor
2.5
kΩ
2.8
2
V
7
0.3
V
3.6
V
11
I
BUS Idle Time
tIDLE
Only valid when an adapter type is
detected as a USB 2.0 device; time BUS
is inactive until charging current is
reduced to ISUSPEND
3
ms
USB Host Remote
Wake-Up Timer
tRWU
Time delay from suspend mode until it
requests the host for a remote wake-up
100
ms
D+, D- Rise Time (Note
3)
tRISE
D+, D- Fall Time (Note
3)
tFALL
Rise/Fall-Time Matching
(Note 3)
Output-Signal Crossover
Voltage
CL = 50pF to 600pF, low speed only
75
250
CL = 50pF, full speed only
4
20
CL = 50pF to 600pF, low speed only
75
250
CL = 50pF to 600pF, full speed only
4
20
CL = 50pF to 600pF, low speed only
80
120
CL = 50pF to 600pF, full speed only
90
110
CL = 50pF to 600pF, low speed only
1.3
2.0
V
VBUS = 5V, IINT_3V3 = 0 to 10mA
3.0
3.6
V
ns
ns
%
INT_3V3 REGULATOR
INT_3V3 Voltage
3.3
ESD PROTECTION (D+, D-, BUS_)
Human Body Model
BUS bypassed with 1μF to AGND
±8
kV
Note 3: Specifications are 100% production tested at TA = +25ºC. Limits over the operating temperature range are guaranteed by
design and characterization.
Note 4: Guaranteed by design. Limits not production tested.
Note 5: Sum of input current limit and current used for INT_3V3.
Note 6: Maximum charging current is adaptively regulated to IILIM - ISYS though maximum ICHG.
www.maximintegrated.com
Maxim Integrated | 14
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Typical Operating Characteristics
(Circuit of [[Figure 1. Block Diagram and Typical Application Circuit]], TA = +25ºC unless otherwise noted.)
VB US INPUT SUPPL Y CURRENT
v s . V B US (FUL L SPEED)
1000
800
600
400
1000
800
600
400
200
STDB_EN_HW = AGND
0
6
8
10
12
16
14
VBUS (V)
4
3
2
1
4
6
8
10
12
14
VBAT = 4.2V
CEN = AGND
1400
1200
8
10
12
800
600
400
2
4
6
8
10
12
BUS UNCONNECTED, SDA = SCL = AGND,
CEN = INT_3V3
0
14
3.0
3.5
VBAT (V)
www.maximintegrated.com
4.0
4.5
16
1000
800
600
400
0
2.0
2
4
6
8
10
12
14
16
VBUS (V)
CHA RGE CURRENT v s . B A TTERY
VOL TA GE (L OW-POWER MODE)
1.5
1.0
100
90
80
70
60
50
40
30
20
0.5
VBAT = 3.6V, CEN = INT_3V3
BUS UNCONNECTED
10
0
0
2.5
14
1200
16
MAX77301 toc08
2.5
LEAKAGE CURRENT (µA)
MAX77301 toc07
0.5
12
VBAT = 4.2V
CEN = INT_3V3
1400
B A TTERY L EA K A GE CURRENT
v s . T E MP E R A T U R E
1.0
10
0
0
B A T T E R Y L E A K A GE C U R R E N T
v s . B A T T E R Y V OL T A GE
1.5
8
1600
VBUS (V)
2.0
6
200
VBUS (V)
2.5
4
VB US INPUT SUPPL Y CURRENT
v s . VB US (CHA RGER DISA B L ED)
1000
16
14
2
VBUS (V)
CHARGE CURRENT (mA)
6
400
0
0
4
600
16
200
0
LEAKAGE CURRENT (µA)
2
1600
INPUT SUPPLY CURRENT (µA)
MAX77301 toc04
INPUT SUPPLY CURRENT (mA)
BAT UNCONNECTED
CEN = INT_3V3
2
800
VB US INPUT SUPPL Y CURRENT
v s . VB US (CHA RGER DISA B L ED)
6
0
1000
VBUS (V)
VB US INPUT SUPPL Y CURRENT
v s . VB US (CHA RGER ENA B L ED)
5
1200
0
0
INPUT SUPPLY CURRENT (µA)
4
MAX77301 toc05
2
1400
200
0
0
MAX77301 toc03
1200
MAX77301 toc09
200
1400
1600
MAX77301 toc06
1200
MAX77301 toc02
1400
1600
INPUT SUPPLY CURRENT (µA)
MAX77301 toc01
INPUT SUPPLY CURRENT (µA)
1600
VB US INPUT SUPPL Y CURRENT
v s . VB US (L OW SPEED)
INPUT SUPPLY CURRENT (µA)
VB US INPUT SUPPL Y CURRENT
v s . VB US (SUSPEND MODE)
-40
-15
10
35
TEMPERATURE (°C)
60
85
2.0
2.5
3.0
3.5
4.0
4.5
BATTERY VOLTAGE (V)
Maxim Integrated | 15
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Typical Operating Characteristics (continued)
(Circuit of [[Figure 1. Block Diagram and Typical Application Circuit]], TA = +25ºC unless otherwise noted.)
100
50
150
100
MAX77301 toc12
200
220
215
50
210
205
200
195
190
185
0
4.0
4.5
180
2.0
2.5
BATTERY VOLTAGE (V)
4.206
4.204
4.202
4.200
4.198
SYS OUTPUT VOLTAGE (V)
4.208
THM = GND (DISABLED)
4.194
-15
-10
35
60
4.450
4.425
4.400
4.375
4.350
4.325
4.300
4.275
4.250
4.225
4.200
4.175
4.150
4.125
4.100
4.075
4.050
4
80
60
40
20
0
500
1000
ISYS (mA)
www.maximintegrated.com
1500
5
6
7
2000
4.3
SYSTEM LOAD SWITCH IN DROPOUT
3.9
3.8
3.7
4.35
4.30
4.20
4.15
4.10
3.00
3.50
3.75
4.00
4.25
4.50
4.6
1500
2000
VBAT = 4.2V
4.4
VSYS SUPPLEMENTED BY VBUS
4.2
4.0
3.8
3.6
3.4
3.2
1000
3.25
SYS OUTPUT VOL TA GE v s .
L OA D CURRENT (USB HIGH-POWER MODE)
3.0
ISYS (mA)
VBUS = 5V
VSYS = 4.35V
4.00
3.5
500
ISYS = 100mA
4.25
3.6
0
ISYS = 0mA
4.40
4.05
VSYS SUPPLEMENTED BY VBUS
4.0
85
VBATT (V)
VBAT = 4.2V
4.1
60
4.45
8
4.5
4.2
35
4.50
VBUS (V)
4.4
-10
SYS OUTPUT VOL TA GE
v s . B A T T E R Y V OL T A GE
VBAT = 4.2V
3
SYS OUTPUT VOLTAGE (V)
100
0
-15
TEMPERATURE (°C)
SYS OUTPUT VOL TA GE v s .
L OA D CURRENT (USB L OW-POWER MODE)
MAX77301 toc16
SYS DROP OUTPUT VOLTAGE (mV)
120
-40
ISYS = 20mA
85
B A T-SYS VOL TA GE DROP
v s . SYS CURRENT
BUS DISCONNECTED
VBAT = 3.6V
4.5
ISYS = 0mA
TEMPERATURE (°C)
140
4.0
SYS OUTPUT VOL TA GE v s . VB US
MAX77301 toc13
BATTERY REGULATION VOLTAGE (V)
4.210
-40
3.5
BATTERY VOLTAGE (V)
B A TTERY REGUL A TION VOL TA GE
v s . A MB IENT TEMPERA TURE
4.196
3.0
SYS OUTPUT VOLTAGE (V)
3.5
SYS OUTPUT VOLTAGE (V)
3.0
MAX77301 toc14
2.5
MAX77301 toc17
2.0
MAX77301 toc15
0
IFCHG = 200mA
MAX77301 toc18
150
MAX77301 toc11
200
250
CHARGE CURRENT (mA)
MAX77301 toc10
250
CHARGE CURRENT (mA)
CHA RGE CURRENT
v s . A MB IENT TEMPERA TURE
CHA RGE CURRENT v s . B A TTERY
VOL TA GE (1A DEDICA TED CHA RGER)
CHARGE CURRENT (mA)
CHA RGE CURRENT v s . B A TTERY
VOL TA GE (HIGH-POWER MODE)
SYSTEM LOAD SWITCH IN DROPOUT
0
500
1000
1500
2000
ISYS (mA)
Maxim Integrated | 16
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Typical Operating Characteristics (continued)
(Circuit of [[Figure 1. Block Diagram and Typical Application Circuit]], TA = +25ºC unless otherwise noted.)
4.2
4.1
3.20
3.15
SYSTEM LOAD
SWITCH IN DROPOUT
3.05
VBAT = 4.2V, SONY UB-10
0
500
1500
3
2000
MAX77301 toc22
4
5
6
7
0.20
700
0.18
3.8
400
3.6
300
3.4
200
IBAT
BATTERY = 1830mA-h
IFCHG = 600mA
100
IBAT (mA)
500
VBAT
HEADROOM VOLTAGE (V)
600
0.16
0.14
0.10
VBUS
ISYS = 150mA
0.08
VBUS
ISYS = 0mA
0.06
0.04
0
100
VBUS
ISYS = 300mA
0.12
200
300
EYE DIA GRA M (L OW SPEED)
MAX77301 toc23
3.6
3.1
2.6
2.1
1.6
1.1
50
100
150
200
0
250
DEDICA TED CHA RGER CONNECT
MAX77301 toc24
3.5
3.0
VBUS
2.5
VSYS
2.0
2.0
3.0
4.0
1.0
MAX77301 toc25a
5V/div
VBUS
5V/div IBUS
0.5A/div
VD+
0.5
2V/div
VD+
2V/div
2V/div
0
-0.5
VD0
1.0
2.0
3.0
4.0
5.0
TIME (x 10^ -8) s
www.maximintegrated.com
6.0
7.0
8.0
6.0
5V/div
2V/div
1.5
5.0
DEDICA TED CHA RGER CONNECT
MAX77301 toc25
4.0
1.0
TIME (x 10^ -7) s
IBAT (mA)
EYE DIA GRA M (FUL L SPEED)
D+, D- SIGNALS (V)
0
50 100 150 200 250 300 350 400 450
0.1
0
TIME (MINUTES)
100
TIME (MINUTES)
0
400
200
0.6
0.02
3.0
0
IBAT
BATTERY = 1830mA-h
IFCHG = 300mA
ICHG_DONE = 40mA
0
8
D+, D- SIGNALS (V)
4.2
3.2
300
HEA DROOM VOL TA GE v s . B A TTERY CURRENT
SYS VOL TA GE = 4.35V, IFCHG = 200m A
CHA RGE PROFIL E
(HIGH-POWER USB CHA RGER)
4.0
3.6
VBUS (V)
ISYS (mA)
4.4
400
3.0
3.10
1000
3.8
3.2
MAX77301 toc22a
3.7
500
VBAT
3.4
VBAT = 4V, IBAT = 200mA
REWORK REMOVED FOR
THIS MEASUREMENT
700
600
4.0
3.10
3.9
3.8
VBAT (V)
4.2
3.25
4.0
MAX77301 toc21
4.4
VBAT (V)
4.3
3.30
INT_3V3 (V)
SYS OUTPUT VOLTAGE (V)
4.4
B A TTERY CHA RGE PROFIL E
MAX77301 toc20
VSYS SUPPLEMENTED BY VBUS
MAX77301 toc19
4.5
INT_3V3 VOL TA GE v s . B US VOL TA GE
3.35
IBAT (mA)
SYS OUTPUT VOL TA GE v s .
L OA D CURRENT (DEDICA TED CHA RGER)
DEDICATED CHARGER
RSYS = 25Ω
VBAT = 3.6V
200ms/div
VD-
SONY U50A
RSYS = 25Ω
VBAT = 3.6V
200ms/div
Maxim Integrated | 17
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Typical Operating Characteristics (continued)
(Circuit of [[Figure 1. Block Diagram and Typical Application Circuit]], TA = +25ºC unless otherwise noted.)
DEDICA TED CHA RGER DISCONNECT
MAX77301 toc26
VBUS
MAX77301 toc26a
MAX77301 toc27
5V/div
IBUS
VSYS
0.5A/divVBUS
5V/div
VBAT = 3.6V
RSYS = 25Ω
VD+
VD+
2V/div
VD-
USB HIGH-POWER 2.0 CONNECT
DEDICA TED CHA RGER DISCONNECT
5V/div VBUS
2V/div
SONY U50A
RSYS = 25Ω
VBAT = 3.6V
VD-
2V/div
IBUS
2V/div
VD+
VD200ms/div
200ms/div
VBUS
5V/div
IBUS
VBAT = 3.6V
RSYS = 25Ω
2V/div
0
MAX77301 toc30
VBUS
5V/div
5V/div
0
100mA /div
0
I
100mA /div BUS
2V/div
VD+
U S B R E S U ME ( F R O M S U S P E N D )
MAX77301 toc29
MAX77301 toc28
VBUS
400ms /div
USB SUSPEND (GUI)
USB HIGH-POWER 2.0 DISCONNECT
2V/div
VD+
0
0
100mA /div
IBUS
VD+
2V/div
0
0
0
2V/div
2V/div
VD-
0
200ms /div
www.maximintegrated.com
VD-
0
20ms/div
0
VD-
0
20ms/div
Maxim Integrated | 18
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Pin Configuration
TOP VIEW
(BUMPS ON BOTTOM)
+
MAX77301
1
2
3
4
5
IBUS_DEF
CHG_TYPE
BAT_A
SYS_A
BUS_A
ENU_EN_HW EXT_PWRON
BAT_B
SYS_B
BUS_B
A
B
XIN
SDA
UOK
STDB_EN_HW
AGND
XOUT
SCL
CEN
CHG_STAT
D+
IRQ
THM
INT_3V3
DGND
D-
C
D
E
WLP
(0.4mm PITCH)
Pin Description
PIN
A1
NAME
IBUS_DEF
FUNCTION
Logic Input that Sets Input Current Limit. Only valid when enumeration is disabled or D+/D- are
open. Logic-high programs the ILIM[2:0] register value. Logic-low sets the input current limit at
100mA.
Low
Input current limit = 100mA
High
A2
A3, B3
CHG_TYPE
BAT_A
BAT_B
Input current limit = ILIM[2:0] (default = 500mA)
Open-drain Output. Used to signal to the processor the current capability of the external adapter.
Connect this pin to ground if not used.
CHG_TYPE
ADPATER TYPE
Low
USB 2.0 host 100mA or ILIM = 100mA
High impedance
ILIMIT ≥ 500mA
Li+ Battery Connection (VBAT). Connect a single-cell Li+ battery from VBAT to ground. Bypass
VBAT to DGND with a 10μF X5R or X7R ceramic capacitor. Both BAT_A and BAT_B must be
connected together externally.
System Supply Output (VSYS). Connect SYS_A and SYS_B to the system load.
A4, B4
SYS_A
SYS_B
When a valid voltage is present at VBUS, VSYS is programmed by the greater of register
V_SYS[1:0] or VBAT + 0.14V (typ). When VBUS is not present the SYS voltage is set to the battery
voltage minus a small voltage drop determined by the system load.
Bypass VSYS to DGND with a 10μF X5R or X7R ceramic capacitor. SYS_A and SYS_B must be
connected together externally.
www.maximintegrated.com
Maxim Integrated | 19
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Pin Description (continued)
PIN
A5, B5
B1
NAME
BUS_A
BUS_B
ENU_EN_H
W
FUNCTION
USB Power Input (VBUS). Connect input power source to BUS_A and BUS_B.
Bypass VBUS to DGND with a 10μF X5R or X7R ceramic capacitor. BUS_A and BUS_B must be
connected together externally.
Automatic Enumeration Enable. ENU_EN_HW is a logic-low input used to enable USB
enumeration. Connect ENU_EN_HW to AGND to allow the IC to automatically perform
enumeration. Connect to INT_3V3 or drive logic-high to disable automatic enumeration and enable
adapter detection. In case of USB host/hub, do not initiate USB enumeration, but set input current
according to IBUS_DEF.
The nENU_EN_HW_MASK bit is used to determine if nENU_EN is controlled by ENU_EN_HW
logic input or if controlled by I2C directly.
B2
EXT_PWRO
N
Open-Drain Output. Used to enable other parts of the system when valid supply is present.
Connect this pin to ground if not used.
Crystal Oscillator Input.
C1
XIN
For full-speed operation, connect XIN to one side of a parallel resonant 12MHz ±0.25% crystal and
a 33pF capacitor to AGND. XIN can also be driven by an external clock referenced to INT_3V3.
For low-speed operation only, a crystal or clock signal is not required. Connect XIN to AGND and
connect XOUT to INT_3V3. In this case the internal oscillator is used, and only low-speed
operation is supported.
C2
C3
C4
SDA
Data Input for I2C Serial Interface. Connect an external 2.2kΩ pullup resistor from SDA to the logic
supply. SDA is high impedance when off.
UOK
Active-Low Adapter Type Detection. UOK is an open-drain output that pulls low when adapter
detection is successfully completed. In USB suspend mode, UOK flashes with a duty cycle of 50%
and a period of 1.5s. When D+/D- open is detected and bit nENU_EN = 1, the UOK pin flashes
with a duty cycle of 50% and a period of 0.15s. When no adapter is detected, UOK is high
impedance. Connect this pin to ground if not used.
STDB_EN_H
W
Standby Mode Enable. STDB_EN_HW is a logic-low input used to force the IC into suspend mode.
Connect STDB_EN_HW to INT_3V3 or drive logic high for automatic detect mode. In automatic
detect mode the IC determines when to enter suspend mode depending on the status of SUS_EN
register and USB conditions.
The nSTDB_EN_HW_MASK bit determines if nSTDB_EN is controlled by STDB_EN_HW logic
input or if controlled by I2C directly.
C5
AGND
Analog Ground. Connect AGND to quiet ground, including crystal oscillator and INT_3V3 ground
nodes.
Crystal Oscillator Output.
D1
XOUT
For full-speed operation, connect XOUT to one side of a parallel resonant 12MHz ±0.25% crystal
and a 33pF capacitor to AGND. Connect XOUT unconnected if XIN is driven by an external clock.
For low-speed operation only, a crystal or clock signal is not required. Connect XOUT to INT_3V3
and connect XIN to AGND. In this case the internal oscillator is used, and only low-speed
operation is supported.
D2
D3
SCL
Clock Input for Serial Interface. Connect an external 2.2kΩ pullup resistor from SCL to the logic
supply. SCL is high impedance when off.
CEN
Charger Enable Input. Logic-high input used to control charge status. Connect CEN to logic-high to
enable battery charging when a valid source is connected at VBUS. Connect to AGND or drive
logiclow to disable battery charging. The CEN_MASK bit is used to determine if CHG_EN is
controlled by CEN logic input or if controlled by I2C directly.
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Maxim Integrated | 20
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Pin Description (continued)
PIN
D4
NAME
FUNCTION
CHG_STAT
Charge Status Output. Logic-low open drain output indicating battery charging. When a
temperature fault is detected, the output is pulsed at 50% duty cycle with a period of 1.5s. When a
charge timer fault is detected CHG_STAT is pulsed at 50% duty cycle with a period of 0.15s. When
no battery is connected, CHG_STAT is pulsed at a 0.1s period and 10%–20% duty cycle. Connect
this pin to ground if not used.
D5
D+
USB D+ Signal. Connect a 33Ω resistor between D+ a USB connector to add signal integrity.
E1
IRQ
Interrupt Request. Logic-low open-drain output that indicates when an interrupt has occurred.
E2
THM
Thermistor Input. Battery temperature detect input. Connect a negative temperature coefficient
(NTC) thermistor close to the battery pack. Connect the other thermistor lead to AGND. Connect a
pullup resistor from THM to INT_3V3 (47kΩ pullup resistor is recommended with a 100kΩ
thermistor). Connect to AGND to disable this feature. Note the thermistor and pullup resistor are
required for battery NTC detection mode.
E3
INT_3V3
3.3V Logic Supply Output. Connect a 1μF capacitor from INT_3V3 to AGND. The output is rated
for up to a 10mA load. The INT_3V3 output is active whenever a valid voltage is present on BUS_
pins.
E4
DGND
Digital Ground. Connect DGND to power ground, including input capacitor, system capacitor, and
battery capacitor ground nodes.
E5
D-
www.maximintegrated.com
USB D- Signal. Connect a 33Ω resistor between D- a USB connector.
Maxim Integrated | 21
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Detailed Description
VBUS_A
VBUS_B
USB POWER
MANAGEMENT
SYS_A
SYS_B
10µF
TO
SYSTEM
LOAD
22µF
MAX77301
1kΩ
5.6V
SET INPUT
CURRENT LIMIT
ILIM
10kΩ
INT_3V3
SUPPLY
INT_3V3
1µF
VBUS
RD+
D+
RDD-
D+
ISYS_
SET INPUT
CURRENT LIMIT
ILIM
CHARGER
DEVIATION
Li+ BATTERY
CHARGER
ILIM
ISYS
IC THERMAL ICHG
REGULATION
ICHG_MAX
USB ADAPTER
TYPE DETECTION
AND
ENUMERATION
EXTERNAL
POWER-ON
TRIGGER
EXT_PWRON
CHARGER
CURRENT
VOLTAGE
CONTROL
BAT_A
BAT_B
BAT+
D-
10µF
NO BAT
DETECTION
BAT-
GND
THERMISTOR
MONITOR
JEITA
I2C CLOCK
IRQ
AUTOMATIC SUSPEND MODE
FORCED SUSPEND MODE
SYS_EN_HW
AUTOMATIC ENUMERATION DISABLED
AUTOMATIC ENUMERATION ENABLED
ENU_EN_HW
100mA /ILIM 2:0 INPUT CURRENT LIMIT
ISUS/100mA INPUT CURRENT LIMIT
NTC
47kΩ
I2C DATA
500mA+ INPUT CURRENT LIMIT
100mA MAX INPUT CURRENT LIMIT
THM
USB/I2C
INTERFACE
LOGIC
CHARGE
TIMER
OTP
OPTIONS
INT_3V3
CHG_STAT
POR
TIME AND
TEMP
ERROR
INDICATOR
CHARGER
STATUS
CEN
CHG_TYPE
CHARGER ENABLED
CHARGER DISABLED
XIN
INT_3V3
IBUS_DEF
OSC
XOUT
DGND
AGND
INT_3V3
LOW SPEED
FULL SPEED
Figure 1. Block Diagram and Typical Application Circuit
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Maxim Integrated | 22
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Overview
The MAX77301 is a USB-compliant linear battery charger that operates from a USB port, a dedicated charger, or a
universal adapter. The IC provides automatic detection of adapter type and enumeration with a USB host. All power
switches and charging circuitry is integrated.
The IC is capable of negotiating more than 100mA of charging current from a USB host or hub without processor
intervention. Alternatively, the IC automatically detects a dedicated charger and sets the input current limit accordingly.
The battery charge current and the input current limit can be set up to 900mA and 1500mA, respectively. If enumeration
is disabled or a nonvalid adapter is connected to the IC the current depends on the logic level of IBUS_DEF (IBUS_DEF
logic-low sets the current limit to 100mA; logic-high sets the current limit to register value ILIM[2:0] (default = 500mA).
Data Contact Detection
USB plugs are designed so that when the plug is inserted into the receptacle, the power pins make contact before the
data pins make contact. This ensures that BUS voltage is applied to data pin contact.
To detect when the data pins have made contact, the data pins are prebiased so at least one of the data pins changes
state. When this change is detected, the IC is allowed to check which type of port is attached.
The IC has two different modes of operation during the data contact detection.
The first mode allows up to 3s (see the Electrical Characteristics table) for the D+/D- to be connected. If D+/D- are still
open after 3s, an interrupt is issued and the IC allows the input current to be user defined. The IC continues to monitor
D+ and D- for connection.
The second mode occurs when enumeration is disabled. In this mode, the IC initiates with user defined current limit and
then transitions to the ideal charging current determined by the USB enumeration engine.
Power-On Reset
To guarantee the correct startup, the IC triggers power-on reset when a valid adapter or battery is detected. Power-on
reset ensures that all I2C registers are set to the default values.
When only a battery is connected to the IC and the battery voltage is above VBAT_UVLO_F all internal circuitry is
powered down except the internal BAT to SYS switch, UVLO comparator, and I2C. If the battery voltage drops below
VBAT_UVLO_F, the I2C interface and the BAT to SYS switch are disabled.
If a valid power source is present at the BUS input, the mode of operation depends on the battery voltage.
For battery voltage above VBAT_UVLO_F: The system is supported by battery power when the external adapter current
limit is exceeded.
For battery voltage below VBAT_UVLO_F: The system cannot be supported by an external adapter and battery power.
The IC enters fault mode and the charger input current is disabled. This is done to ensure that system does not
continuously attempt to start up with an underpowered adapter. Exit this mode by disconnecting the adapter. Use this
mode to disconnect the charger.
Interrupt Request (IRQ)
IRQ is an active-low, open-drain output signal that indicates an interrupt event has occurred and status information
is available in the EVENT_ and STATUS_ registers. Interrupts indicate temperature and voltages and current fault
conditions. Events are triggered by a state change in the associated register. The event registers are reset to default
condition when read. When the EVENT_ registers are read in page mode the IRQ is not released until the last bit been
read. New interrupt events are held until a complete read of all registers has occurred.
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Maxim Integrated | 23
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
USB Interface
An integrated USB peripheral controller provides autoenumeration in full-speed and low-speed modes. The USB
controller completes the following tasks:
● Adapter type detection, or
● USB enumeration with USB type inputs
With no crystal oscillator, the IC operates in USB lowspeed mode. An external 12MHz crystal oscillator and decouling
capacitors are required for USB full-speed mode. This flexibility allows the IC to interface with any USB connector type.
USB_OK = 0
USB_OK = 0
SHUTDOWN
VBAT > VBAT_UVLO_R
OR USB_OK = 1
VBAT < VBAT_UVLO_F
AND USB_OK = 0
VBAT < VBAT_UVLO_F
USB_OK = 0
VBAT < VBAT_UVLO_F
AND USB_OK = 0
P OR
RESET ALL I2C REGISTER
TO DEFAULT VALUE
VBAT > VBAT_UVLO_R
AND USB_OK = 0
IDL E MODE
I2C ENABLED
(ONLY SELECTED
REGISTERS ACTIVE. ALL
NONACTIVE REGISTERS
ARE RESET.)
VBAT < VBAT_UVLO_R
AND USB_OK = 1
VBAT > VBAT_UVLO_R
AND USB_OK = 1
USB_OK = 1
USB_OK = 0
F A U L T M OD E
CHARGER OFF
I2C DISABLED
ILIM = 1 AT
SYS < VSYS_UVLO
A CTIVE MODE
WITH BATTERY
I2C ENABLED
STDB_EN_HW = LOW
VBAT < VBAT_UVLO_F
VBAT > VBAT_UVLO_R
STDB_EN_HW = HIGH
ILIM = 1 AT
SYS < VSYS_UVLO
A CTIVE MODE
WITH NO BATTERY OR
DISCHARGED BATTERY
I2C ENABLED
STDB_EN_HW = LOW
STDB_EN_HW = HIGH
USB_OK = 0
STA NDB Y MODE
WITH BATTERY
I2C ENABLED
ILIM = 0
VBAT < VBAT_UVLO_F
VBAT > VBAT_UVLO_R
STA NDB Y MODE
WITH NO BATTERY OR
DISCHARGED BATTERY
I2C ENABLED
ILIM = 0
Figure 2. Power-On Reset State Diagram
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Maxim Integrated | 24
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Table 1. Status Registers
PIN
CONTROL
REGISTER
STATUS
REGISTER
STDB_EN_HW
0x09
ENU_EN_HW
0x09
0x04
0x04
DESCRIPTION
During power-on reset of the IC, the logic status of the input STDB_EN_HW is used to
set the default value of nSTDB_EN. The standby control is always controlled by the
value of the nSTDB_EN I2C bit. The nSTDB_EN bit can be set using HW input
STDB_EN_HW or by writing directly to the nSTDB_EN bit using I2C. The mode of
operation is determined by nSTDB_EN_MASK. Setting this bit to 0 forces the
nSTDB_EN to always be equal to the logic input STDB_EN_HW. Setting nSTDB_
EN_MASK to 1 disables the STDB_EN_HW logic input and only I2C can be used to
change the value of the nSTDB_EN bit. The status of STDB_EN_HW can always be
read from register 0x04h.
During power-on reset of the IC, the logic status of the input ENU_EN_HW is used to
set the default value of nENU_EN. The enable of automatic enumeration is always
controlled by the value of the ENU_EN I2C bit. The nENU_EN bit can be set using
HW input ENU_EN_HW or by writing directly to the nENU_EN bit using I2C. The
mode of operation is determined by the nENU_EN_MASK. Setting this bit to 0 forces
nENU_EN to always be equal to the logic input nENU_EN_HW. Setting nENU_EN_
MASK to 1 disables the ENU_EN_HW logic input so only I2C can be used to change
the value of the nENU_EN bit. The status of ENU_EN_HW can always be read using
the nENU_EN_HW in 0x04h.
When the nENU_EN bit = 1, the logic stat on the IBUS_DEF pin sets the input current
limit for certain type of chargers. This type of charger is:
● D+/D- open
● nENU_EN is set to 1 and adapter type is DCP or SDP For this type of adapter, the
input current limit is set to following:
IBUS_DEF
CEN
XIN/XOUT
N/A
0x04
0x0C
0x04
N/A
0x04
IBUS_DEF = L
100mA
IBUS_DEF = H
Determined by contents of register, ILIM[2:0]
During power-on reset of the IC, the logic status of CEN is used to used to set the
default value of CHG_EN. The status of the charger is always equal to the CHG_EN
bit. The CHG_EN bit can be set using HW input CEN or by writing directly to the
CHG_EN bit using I2C. The mode of operation is determined by the CEN_MASK.
Setting the CEN_MASK bit to 0 forces CHG_EN to always be equal to the logic input
CEN. Setting CEN_MASK to 1 disables CEN so only I2C can be used to change the
value of the CHG_EN bit. The status of CEN can always be read using the CEN in
0x04h.
The FS_DET bit register 0x04 is used to read the status of the external crystal
connection. A 0 indicates only low speed operation is active. A 1 indicates full speed
is supported.
Table 2. Adapter Type
ADAPTER TYPE
OUTPUT VOLTAGE
OUTPUT CURRENT
Dedicated charger
4.75V to 5.25V at ILOAD <
500mA
2.0V to 5.25V for ILOAD <
500mA
500mA to 1.8A
Charger
downstream port
4.75V to 5.25V at ILOAD <
500mA
2.0V to 5.25V for ILOAD <
500mA
500mA to 900mA for low speed, full speed, and full speed 500mA to 1.5A for low
speed and full speed
Apple 500mA
4.75V to 5.25V at ILOAD <
500mA
500mA (max)
Apple 1A
4.75V to 5.25V at ILOAD <
1A
1A (max)
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Maxim Integrated | 25
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Table 2. Adapter Type (continued)
ADAPTER TYPE
OUTPUT VOLTAGE
OUTPUT CURRENT
Apple 2A
4.75V to 5.25V at ILOAD <
2A
2A (max)
Sony 500mA
4.75V to 5.25V at ILOAD <
500mA
500mA (max)
Sony 500mA Type
B
4.75V to 5.25V at ILOAD <
500mA
500mA (max)
USB 2.0 low power
4.25V to 5.25V
100mA (max)
USB 2.0 high
power
4.75V to 5.25V
500mA (max)
D+ and DD+ and D- are the I/O data pins for the internal USB transceiver. These pins are ESD protected up to ±8kV. Connect D+
and D- to a USB B or custom connector through external 33Ω series resistors. The IC automatically configures D+/Dwith an automatic switchable 1.5kΩ pullup resistor for D- for low-speed and D+ for full-speed.
Low/Full Speed
The IC can operate as a low-speed or a full-speed slave device. Full-speed mode requires an external 12MHz crystal
oscillator connected to XIN and XOUT.
The IC has an 6MHz internal clock for use in low-speed mode. For low-speed mode, tie XIN and the AGND pin and
XOUT to the INT_3V3 pin.
Adapter Detection
Upon insertion, the IC identifies the type of adapter.
Adapter types include:
●
●
●
●
●
Dedicated charger
Noncompliant dedicated chargers
Charger downstream port (host or hub)
USB 2.0 (host or hub) low power
USB 2.0 (host or hub) high power
The IC determines the adapter type and programs the appropriate current limit and battery charge level, as shown in
Figure 3.
Low-Power Mode
The nSTDB_EN bit forces the system to operate from battery power. The current drawn in this mode is less than 500nA
for the low-speed mode and 2.5mA for the fullspeed mode. In this mode, the D+ and D- lines are high impedance. The
I2C interface is maintained.
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Maxim Integrated | 26
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
USB Suspend
According to USB 2.0 specifications, when a USB host stops sending traffic for more than 3ms, the peripheral must enter
a power-down state called SUSPEND after no more than 10ms of inactivity. Once suspended, the peripheral must have
enough of its internal logic active to recognize the host’s resume signaling, or for generating remote wakeup.
When no activity is present on D+/D- for 3ms (typ) ,the IC automatically enters suspend mode to be complaint with the
USB specification. To enter suspend mode, SUS_EN must be enabled by a logic 1 in register 0x09h. When entering
suspend mode, the charger is disabled and SYS is powered from BAT to reduce the input current drawn from BUS to less
than 500μA. In low-speed suspend state, the bus is IDLE: D+ is low and D- is kept high by a pullup resistor. In full-speed
suspend state, the bus is IDLE: D- is low and D+ is kept high by a pullup resistor.
During suspend mode, UOK pulses with a 1.5s period and 50% duty cycle.
USB_OK = 0 FROM ANY CONDITION
CHG_TYPE = 0000, DISABLE VDP_SRC,
DISABLE IDP_SRC, DISABLE IDM_SINK,
DISABLE RDM_PU, DISABLE IDM_PD,
DISABLE RDP_CD_PU, nUOK = H,
IBUS_DET[1:0] = 00
USB_OK = 1
NO
YES
DEBOUNCE tUSB_DB
nSTDBY_EN = 0
FROM ANY CONDITION
AND USB_OK = 1
nDET_DONE_IRQ = 1, CHG_TYPE = 0000
DISABLE DM_PU/DP_PU, DISABLE VDP_SRC,
DISABLE IDP_SRC, DISABLE IDM_SINK,
DISABLE RDM_PU, DISABLE IDM_PD,
DISABLE RDP_CD_PU, UOK = H
IBUS_DET[1:0] = 00
nSTDB_EN = "0"
YES
NO
ENABLE RDM_DWN START TIMER
NO
CHG_TYPE = 0111, nUOK = L,
DET_DONE_IRQ = 1,
IBUS_DET = IBUS_DEF
YES
CHG_TYPE = 0111, nUOK = L,
DET_DONE_IRQ = 1,
IBUS_DET[1:0] = 11
YES
DP > 60%
DISABLE RDM_DWN
DELAY, tDCD_DBNC
NO
NO
DM > 34%
YES
TIMER > tFAULT
YES
UOK = 50% DUTY T = 0.15SEC
CHG_TYPE_DET = 1100
DET_DONE_IRQ = 1
RESTART TIMER
IBUS_DET = IBUS_DEF
UOK = L
CHG_TYPE_DET = 1100
DET_DONE_IRQ = 1
IBUS_DET = IBUS_DEF
NO
YES
ENABLE IDM_SINK
DELAY, tDCD_DBNC
47% < DP < 60%
25% < DM < 47%
DM > VDAT_REF,
DEBOUNCE, tDCD_DBNC
DISABLE RDM_DWN
ENABLE IDP_SRC, ENABLE IDM_SINK
NO
NO
NO
CHG_TYPE = 0101, nUOK = L,
DET_DONE_IRQ = 1,
IBUS_DET[1:0] = 11
YES
25% < DP < 47%
47% < DM < 60%
CHG_TYPE = 1010, nUOK = L,
DET_DONE_IRQ = 1,
IBUS_DET[1:0] = 10
YES
NO
CHG_TYPE = 0100, nUOK = L,
DET_DONE_IRQ = 1,
IBUS_DET[1:0] = 10
YES
25% < DP < 47%
47% < DM < 47%
CHG_TYPE = 1011, nUOK = L,
DET_DONE_IRQ = 1,
IBUS_DET[1:0] = 11
NO
CHG_TYPE = 0111, nUOK = L
DET_DONE_IRQ = 1
IBUS_DET = IBUS_DEF
NO
DP > 60%
DP < VDP_IH
DEBOUNCE
tDCD_DBNC
NO
YES
NO
DISABLE IDP_SRC
DISABLE IDM_SINK
nENU_EN = 1
AND DCD_EN = 0
YES
DISABLE IDP_SRC
DP > 25%
YES
CHG_TYPE = 0111, nUOK = L,
DET_DONE_IRQ = 1
IBUS_DET = IBUS_DEF
CHG_TYPE = 0111, nUOK = L
DET_DONE_IRQ = 1
IBUS_DET = IBUS_DEF
ENABLE VDP_SRC
DELAY tDP_SRC_ON
YES
DM > VDM_IH
NO
CONTINUED
ON FIGURE 3b
CONTINUED ON FIGURE 3b
CONTINUED
ON FIGURE 3b
Figure 3. Adapter Detection Flow Chart
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Maxim Integrated | 27
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
CONTINUED
FROM FIGURE 3a
CONTINUED
FROM FIGURE 3a
CONTINUED FROM FIGURE 3a
YES
DM > VDAT_REF
NO
DISABLE VDP_SRC, DISABLE IDM_SINK,
ENABLE IDM_CD_PD, ENABLE RDP_CD_PU
DELAY tDP_SRC_HC
NO
CHG_TYPE = 1101, DET_DONE_IRQ = 1
YES
DISABLE IDM_PD
DISABLE DP_CD_PU
DM > VDM_IH
CHG_TYPE = 0001
DET_DONE_IRQ = 1
YES
DISABLE VDP_SRC, DISABLE IDM_SINK,
IBUS_DET[1:0] = 01, DELAY tDP_SRC_HC
ENABLE DM_PU/DP_PU
NO
UOK = L
IBUS_DET = IBUS_DEF
ENUMERATION
SUCCEEDED
DISABLE IDM_CD_PD, DISABLE RDP_CD_PU
ENABLE DM_PU/DP_PU, IBUS_DET[1:0] = 01
DISABLE DM_PU/DP_PU,
nUOK = ENUM_FLT = 1, CHG_TYPE = 0000
IBUS_DET[1:0]= 00, DELAY TFAULT
NO
CHG_TYPE = 0001
UOK = L
IBUS_DET= IBUS_DEF
nUOK = L
NO
DISABLE IDM_CD__PD, DISABLE RDP_CD_PU
CHG_TYPE = 0011, UOK = L
DET_DONE_IRQ = 1. IBUS_DET[1:0] = 11
nENU_EN = 1
YES
nENU_EN = 1
NO
YES
DISABLEDM_PU/PD_PU
UOK = H
ENUM_FLT = 1
CHG_TYPE = 0000
IBUS_DET[1:0] = 00
DELAY tFAULT
IBUS_DET[1:0] = 01 OR 10
CHG_TYP = 1000 OR 1001
UOK = L
ENUM_FLT = 0
DET_DONE_IRQ = 1
ENUMERATION
SUCCEEDED
YES
CHG_TYPE = 0010, ENUM_FLT = 0
DET_DONE_IRQ = 1, nUOK = L
IBUS_DET[1:0] = 11
NO
USB SUSPEND?
YES
NO
USB SUSPEND?
YES
SUS_EN = 0
YES
NO
YES
IBUS_DET[1:0] = 0
SUS_IRQ = 1
UOK = 50% DUTY
T=1.5sec
SUS_EN = 0
RESUMES_IRQ = 1
NO
IBUS_DET[1:0] = 00, SUS_IRQ = 1
nUOK = 50% DUTY, T = 1.5sec
RESUME_IRQ = 1
YES
USB HOST
D+/D- H TO L
TRANSITION
YES
NO
DELAY TRWU
INITIATE RESUME
NO
DELAY TRWU
INITIATE RESUME
CHARGE DONE
RWU
SUPPORTED
BY HOST?
NO
NO
YES
YES
NO
YES
RWU SUPPORTED
BY HOST?
RWU_EN = 1
CHARGE DONE
YES
NO
YES
USB HOST
D+/D- H TO L
TRANSITION
NO
RWU_EN = 1
NO
YES
DELAY TRE_ENUM
DELAY TRE_ENUM
Figure 4. Adapter Detection Flow Chart
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Maxim Integrated | 28
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
ENUMERATION INITIATED
ILIM = 500mA
SEND CONNECT
YES
NO
t < tENUM
YES
DISABLE
DM_PU LOW SPEED
DP_PU FULL SPEED
NO
IC IS IN
CONFIGURED
STATUS
YES
ENUM_500mA
DELAY tENU_FAULT
ILIM = 100mA ENABLE
DM_PU LOW SPEED
DP_PU FULL SPEED
NO
t < tENUM
YES
DISABLE DM_PU
DELAY tENU_FAULT
ENUM_FAIL
NO
IC IS IN
CONFIGURED
STATUS
YES
ENUM_100mA
RETURN TO MAIN LOOP
Figure 5. Enumeration Flow Chart
Keyboard Test Mode
In normal operation, keyboard test mode is disabled. This function is only used during USB certification.
Writing a 1 to the KB_TM_EN bit while writing a 0 to nENU_EN_HW_MASK enters keyboard test mode and disables the
logic input ENU_EN_HW. Toggling this logic
input while in keyboard test mode sends a mute command that is used to generate traffic on the USB interface as well
as verification of golden tree commands.
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Maxim Integrated | 29
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Wake-Up and USB Resume
The IC can wake up from suspend mode four ways:
● By setting nSTDB_EN to 0 followed by 1 to initiate redetection of the adapter type.
● If nSTDB_EN is 1 and SUS_EN is 1, the IC monitors the bus activity on the D+/D- line. If the host resumes bus activity
the IC detects this as a 1 to 0 transition on D+/D-. Once this occurs, the device restarts the oscillator and waits for it
to stabilize.
● Remote wake-up can be enabled by the host during the enumeration process. Once suspended the state of the
battery charger is monitored. If the charger is not in the DONE state, the IC initiates a remote wake-up signal. If the
charger is in the DONE state, a remote wake-up is not initiated until the RESTART threshold is reached. When the
IC initiates a remote wake-up, it first restarts the oscillator and waits for the oscillator to stabilize. Then it sends the
remote wake-up event to signal the host that it needs to be driven out of the suspend status.
● If RWU_EN is a logic 1 in register 0x09 and the remote wake-up feature has not been set by the host during
enumeration, the IC waits tRE_ENUM after entering suspend mode, then disconnects the pullup resistor from D+ or
D- and reinitiates the charger-type detection.
USB Enumeration
When the USB 2.0 host/hub or charger downstream port detects a peripheral (MAX77301), it interrogates the device to
learn about its capabilities and requirements, and configures it to bring it online. This process is known as enumeration.
USB bus enumeration identifies and assigns unique addresses to the devices connected to the bus.
Once the IC detects VBUS is valid for tUSB_DB, the IC initiates the detection process to determine the type of device
connected. If the device is a USB 2.0 host/hub or charger downstream port and nENU_EN is logic 0, the IC connects a
1.5kΩ pullup resistor from D- (low speed) or D+ (full speed) to INT_3V3. If nENU_EN is set to 1, the pullup resistor from
D-/D+ to INT_3V3 is disabled and the current limit is set according to IBUS_DEF logic input.
During enumeration the host sends multiple requests to the device (MAX77301) requesting for a descriptor (stored in
ROM table data) that defines the device.
The enumeration is managed by the IC’s serial interface engine (SIE) without any processor intervention.
The SIE supports the following features:
●
●
●
●
●
●
●
USB 2.0 low speed (1.5Mb/s), D- pulls high to indicate to the host that it is a low-speed device
Full speed (12Mb/s) operation, D+ pulls high to indicate to the host that it is a full-speed device
Human interface device (HID) in the consumer page (the IC does not require any custom driver)
8 bytes endpoint zero (control endpoint)
1 byte endpoint one (INT-IN endpoint)
USB suspend/resume support
Remote wake-up capability
At the end of enumeration (if successful), the IC is ready to transfer data (if needed) and enabled to sink the negotiated
current from BUS.
Figure 6 shows USB bus traffic as captured by a CATC USB bus analyzer. The traces show a PC (host) enumerating the
peripheral. Notice that the LS field indicates the low-speed (1.5Mb/s) operation of IC’s low-speed configuration.
1. The host uses the default CONTROL endpoint EP0 (shown in the ENDP boxes) to send request to the device. The
host initially sends requests to address 0 (shown in the ADDR boxes) to communicate with a device to which it has
not yet assigned a unique address.
2. The host begins by sending a Get_Descriptor_Device request (Transfer 0 in Figure 6). It does this to determine the
maximum packet size of the device’s EP0 buffer. The host then resets the device by issuing a bus reset (packet 69).
3. In Transfer 1, the host assigns a unique address to the peripheral by using the Set_Address request. The assigned
address depends on how many other USB host/hubs are currently attached to the host. In this case, the address
assigned to our peripheral device is 3. Thereafter, the IC responds only to requests directed to address 3. This
address remains in force until the host does a bus reset or the device is disconnected. Notice that the peripheral
address field (ADDR) in the bus traces change from 0 to 3 after Transfer 1.
4. In transfers 2 to 11, the host asks for various descriptors. The device FSM needs to determine from the eight setup
bytes which descriptor to send, use this information to access one of several character arrays (ROMs) representing
www.maximintegrated.com
Maxim Integrated | 30
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
the descriptor arrays.
5. In transfer 12, the host requests the device to use the specified configuration (1) and the device enters the Configured
state.
According to the USB 2.0 specification, a bus powered device can be either low power (it cannot draw more than 100mA)
or high power (it cannot draw more than 500mA).
All devices must default to low power: the transition to high power is under software control (running on the host side). It
is the responsibility of software to ensure adequate power is available before allowing devices to consume high-power.
The IC initiates enumeration by asking for 500mA of current. If the IC does not enter configured status before the tENUM
(10s typ), it interprets this as an indication that the host is not able to support the requested current.
The IC disconnects the pullup resistor on D-/D+, respectively, waits for tENU_FAULT and then retries to enumerate, but
now as a low current device (100mA). If the IC has still not reached the configured status after tENUM, the IC assumes
that either the host is nonresponsive or a wrong adapter type is detected. In this case, the IC disables the pullup resistor
on D- if it is configured as low speed and D+ if configured as full speed, waits for tENU_FAULT + tFAULT before starting
the adapter detection process again.
Figure 7 shows the USB traffic captured during the full-speed enumeration. Notice the field FS indicates the full-speed
(12Mb/s) operation.
www.maximintegrated.com
Maxim Integrated | 31
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
0
S
GE T
0
0
GET_DESCRIPTOR
DEVICE TYPE
0x0000
DEVICE DESCRIPTOR
6.80ms
00002.2673 4787
PACKET
DIR
RESET
TIME
TIME STAMP
69
_>
25.881ms
52.919ms
00002.2722 1739
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
wLENGTH
TIME
TIME STAMP
1
S
SET
0
0
SET_A DDRESS
NEW ADDRESS 3
0x0000
0
46.999ms
00002.3145 4675
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
2
S
GE T
3
0
GET_DESCRIPTOR
DEVICE TYPE
0x0000
DEVICE DESCRIPTOR
6.000ms
00002.3521 4587
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
3
S
GE T
3
0
GET_DESCRIPTOR
CONFIGURATION TYPE, INDEX O
0x0000
CONFIGURATION DESCRIPTOR
5.000ms
00002.3569 4579
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
4
S
GE T
3
0
GET_DESCRIPTOR
CONFIGURATION TYPE, INDEX O
0x0000
4 DESCRIPTORS
21.000ms
00002.3609 4563
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
5
S
GE T
3
0
GET_DESCRIPTOR
STRING TYPE, L A NGID CODES, REQUESTED
LANGUAGE ID 0x0000
LANG SUPPORTED
5.000ms
00002.3777 4539
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
6
S
GE T
3
0
GET_DESCRIPTOR
STRING TYPE, INDEX 1
LANGUAGE ID 0x0409
USB CHARGER
8.000ms
00002.3817 4515
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
7
S
GE T
3
0
GET_DESCRIPTOR
STRING TYPE, LANGID CODES REQUESTED
LANGUAGE ID 0x0000
LANG SUPPORTED
5.000ms
00002.3881 4499
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
8
S
GE T
3
0
GET_DESCRIPTOR
STRING TYPE, INDEX 1
LANGUAGE ID 0x0409
USB CHARGER
11.013 ms
00002.3921 4491
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
9
S
GE T
3
0
GET_DESCRIPTOR
DEVICE TYPE
0x0000
DEVICE DESCRIPTOR
5.986ms
00002.4009 5299
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
10
S
GE T
3
0
GET_DESCRIPTOR
CONFIGURATION TYPE, INDEX O
0x0000
CONFIGURATION DESCRIPTOR
5.000ms
00002.4057 4459
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
11
S
GE T
3
0
GET_DESCRIPTOR
CONFIGURATION TYPE, INDEX O
0x0000
4 DESCRIPTORS
8.000ms
00002.4097 4451
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
wLENGTH
TIME
TIME STAMP
12
S
SET
3
0
SET_CONFIGURATION
NEW CONFIGURATION 1
0x0000
0
18.999ms
00002.4161 4435
TRANSFER
L
CONTROL
A DDR
ENDP
D
Tp
R
bREQUEST
wVALUE
wINDEX
wLENGTH
STA L L
TIME
TIME STAMP
13
S
SET
3
0
H_>D
C
I
0x 0A
0x0000
0x0000
0
0x08
3.000ms
00002.4313 4403
TRANSFER
L
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
TIME STAMP
14
S
GE T
3
1
GET_DESCRIPTOR
REPORT_DESCRIPTOR TYPE
0x0000
REPORT DESCRIPTOR
15.000ms
00002.4337 4395
TRANSFER
L
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
TIME STAMP
15
S
IN
3
1
1
8.009ms
00002.4457 4371
TRANSFER
L
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
TIME STAMP
16
S
IN
3
1
1
7.991ms
00002.4521 4899
TRANSFER
L
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
TIME STAMP
17
S
IN
3
1
1
8.000ms
00002.4585 4339
TRANSFER
L
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
TIME STAMP
18
S
IN
3
1
1
8.000ms
00002.4649 4323
TRANSFER
L
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
TIME STAMP
19
S
IN
3
1
1
8.009ms
00002.4713 4307
TRANSFER
L
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
TIME STAMP
20
S
IN
3
1
1
7.991ms
00002.4777 4843
Figure 6. USB BUS Traffic: Low-Speed Enumeration
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Maxim Integrated | 32
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
1
S
SET
0
0
GET_DESCRIPTOR
DEVICE TYPE
0x0000
DEVICE DESCRIPTOR
RESET
IDLE
26.370ms
6627
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
TIME
1
S
SET
0
0
SET_A DDRESS
NEW ADDRESS 1
47.002ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
2
S
GE T
1
0
GET_DESCRIPTOR
DEVICE TYPE
0x0000
DEVICE DESCRIPTOR
6.000ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPT0RS
TIME
3
S
GE T
1
0
GET_DESCRIPTOR
CONFIGURATION TYPE
0x0000
CONFIGURATION DESCRIPTOR
5.000ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPT0RS
TIME
4
S
GE T
1
0
GET_DESCRIPTOR
CONFIGURATION TYPE
0x0000
4 DESCRIPTORS
9.000ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
STA L L
TIME
5
S
GE T
1
0
GET_DESCRIPTOR
DESCRIPTOR TYPE 0X06, INDEX 0
0x0000
0x78
3.001ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
6
S
GE T
1
0
GET_DESCRIPTOR
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPT0RS
TIME
7
S
GE T
1
0
GET_DESCRIPTOR
STRING TYPE, INDEX 1
LANGUAGE ID 0x0409
STRING: USB CHARGER
8.000ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPT0RS
TIME
8
S
GE T
1
0
GET_DESCRIPTOR
STRING TYPE, L A NGID CODES REQUESTED
LANGUAGE ID 0x0000
0x0409
5.001ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
9
S
GE T
1
0
GET_DESCRIPTOR
STRING TYPE, INDEX 1
LANGUAGE ID 0x0409
STRING: USB CHARGER
30.001ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPT0RS
TIME
10
S
GE T
1
0
GET_DESCRIPTOR
DEVICE TYPE
0x0000
DEVICE DESCRIPTOR
6.001ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPT0RS
TIME
11
S
GE T
1
0
GET_DESCRIPTOR
CONFIGURATION TYPE, INDEX O
0x0000
CONFIGURATION TYPE, INDEX O
8.000ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
DESCRIPT0RS
TIME
12
S
GE T
1
0
GET_DESCRIPTOR
CONFIGURATION TYPE
0x0000
4 DESCRIPTORS
8.000ms
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
13
S
SET
1
0
SET_CONFIGURATION
TRANSFER
F
CONTROL
A DDR
ENDP
bREQUEST
wVALUE
wINDEX
STA L L
TIME
14
S
SET
1
0
0x0A
0x0000
0x0000
0x78
3.000ms
TRANSFER
15
F
CONTROL
bREQUEST
wVALUE
wINDEX
DESCRIPTORS
TIME
GET
A DDR
1
ENDP
S
0
GET_DESCRIPTOR
DESCRIPTOR TYPE 0x22, INDEX 0
0x0000
HID REPORT DESCRIPTOR
16.001ms
TRANSFER
F
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
16
S
IN
1
1
32.001ms
TRANSFER
F
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
17
S
IN
1
1
1
32.001ms
TRANSFER
F
INTERRUPT
A DDR
ENDP
BYTES TRANSFERRED
TIME
18
S
IN
1
1
1
32.001ms
TRANSFER
F
INTERRUPT
A DDR
ENDP
19
S
IN
BYTES TRANSFERRED
1
1
1
1
wVALUE
STRING TYPE. L A NGID CODES REQUESTED
wVALUE
wINDEX
DESCRIPT0RS
TIME
LANGUAGE ID 0x0000
0x0409
5.000ms
TIME
NEW CONFIGURATION 1
20.001ms
TIME
0ns
Figure 7. USB BUS Traffic: Full-Speed Enumeration
Table 3. Device Descriptor
FIELD
LENGTH
(BITS)
OFFSET
(BITS)
DECODED
HEX
VALUE
8
0
0x12
0x12
Descriptor size is 18 bytes.
DEVICE descriptor type.
bLength
DESCRIPTION
bDescriptorType
8
8
0x01
0x01
bcdUSB
16
16
0x0200
0x0200
bDeviceClass
8
32
0x00
0x00
Each interface specifies its own class information
bDeviceSubClass
8
40
0x00
0x00
Each interface specifies its own subclass information
bDeviceProtocol
8
48
0x00
0x00
No protocols the device basis
bMaxPacketSize0
8
56
0x08
0x08
Maximum packet size for end point zero is 8
idVendor
16
64
*
*
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Device compliant to the USB specification version 2.00
Vendor ID is set using I2C interface*
Maxim Integrated | 33
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Table 3. Device Descriptor (continued)
LENGTH
(BITS)
OFFSET
(BITS)
DECODED
HEX
VALUE
idProduct
16
80
*
*
bcdDevice
16
96
0x0100
0x0100
iManufacturer
8
112
0x00
0x00
The device does not have the string descriptor
describing the manufacturer
iProduct
8
120
0x01
0x01
The product stringed descriptor index is 1
iSerialNumber
8
128
0x00
0x00
The device does not have the string descriptor
describing the serial number
bNumConfigurations
8
136
0x01
0x01
The device has 1 possible configuration
FIELD
DESCRIPTION
Product ID is set using I2C interface*
The device release number is 1.00 code is 0x0100
*Contact factory for available preset values.
Smart Power Selector
The Smart Power Selector seamlessly distributes power among the external BUS input, the battery BAT, and the system
load SYS (Figure 8). The Smart Power Selector basic functions are:
● With both an external adapter and battery connected:
a) When the system load requirements are less than the input current limit, the battery is charged with residual
power from the input.
b) When the system load requirements exceed the input current limit, the battery supplies supplemental current
to the load.
● When the battery is connected and there is no external power input, the system is powered from the battery.
● When an external power input is connected and there is no battery, the system is powered from BUS.
BUS
VSYS
Q1
CHARGE
CURRENT
LOAD
CURRENT
Q2 CHARGE
AND SYS LOAD
SWITCH
SYSTEM
LOAD
BAT
1-CELL Li+
MAX77301
GND
Figure 8. Smart Power Selector Block Diagram
System Load Switch
An internal 200mΩ (typ) MOSFET connects SYS to BAT (Q2 of Figure 8) when no voltage source is available on BUS.
When an external source is detected at BUS, this switch opens and SYS is powered from the input source through the
input current limiter.
The SYS to BAT switch also prevents VSYS from falling below VBAT when the system load exceeds the input current
limit. If VSYS drops to VBAT due to the current limit, the load switch turns on so the load is supported by
the battery. If the system load continuously exceeds the input current limit the battery is not charged. This is useful for
handling loads that are nominally below the input current limit, but have high current peaks exceeding the input current
limit. During these peaks battery energy is used, but at all other times the battery charges.
The user can select undervoltage and precharge settings as required by new, low voltage lithium-ion, or standard
lithium-ion batteries. The battery undervoltage lockout and precharge threshold voltages are identified in the Electrical
Characteristics table and can be toggled through the BAT_CNTL register (0x10), bit 7.
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Maxim Integrated | 34
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Input Limiter
The input limiter distributes power from the external adapter to the system load and battery charger. In addition to the
input limiter’s primary function of passing power to the system load and charger, it performs several additional functions
to optimize use of available power:
Invalid BUS voltage protection: If VBUS is above the overvoltage threshold (VBUS_OVP), the IC enters overvoltage
protection (OVP). OVP protects the IC and downstream circuitry from high-voltage stress up to 16V at BUS. During OVP,
INT_3V3 remains on and an interrupt is sent to the host. During OVP, the charger turns off and the system load switch
closes, allowing the battery to power SYS. VBUS is also invalid if it is less than VBAT, or less than the USB undervoltage
threshold (VBUS_UVLO_F). With an invalid input voltage, the system load switch closes, allowing the battery to power
SYS.
BUS input current limit: The BUS input current is limited to prevent input overload. The input current limit is
automatically selected to match the capabilities of the source, whether it’s a 100mA/500mA USB 2.0 source, a 500mA to
2.0A dedicated adapter, or a charger downstream port.
Thermal limiting: The IC reduces the input current by 5%/ºC when its die temperature exceeds TDIE_LIM. The system
load (ISYS) has priority over charger current, so the input current is first reduced by lowering the charge current. If the
junction temperature reaches TDIE_LIM +20ºC no input current is drawn from BUS and the battery powers the entire
system load.
Setting Input Current Limit
The input current limit is set with IBUS_DET_SW of register 0x0A. See Figure 9. The IC automatically sets the
initial value of IBUS_DET_SW according to the device detected. This value can be overwritten using I2C interface if
different input current is desired.
If IBUS_DET_SW is set to ILIM the input current limit is set to the value specified in ILIM of register 0x0A. This gives the
user more options to meet specific needs.
Minimum VSYS Threshold
The minimum VSYS regulating threshold is programmable using V_SYS of register 0x0A. The VSYS is adapted to the
battery voltage, maintaining a value of 140mV (typ) above VBAT with the minimum voltage determined by the value
programmed in V_SYS. See Figure 10. The V_SYS minimum voltage regulation reduces the ripple on VSYS during peak
load conditions where the input current limit is tripped.
The minimum VSYS regulating threshold is programmable by V_SYS bits. The VSYS is adapted to the battery voltage with
a delta value of VSYS 140mV (typ) above VBAT with a minimum voltage determined by V_SYS. The voltage on V_SYS
is maintained at or above the programmed voltage. This allows the system to operate with a discharged or damaged
battery and provides at the optimum voltage setpoint.
Input Current Limit
If the connected adapter is a USB 2.0 device, the input current limit is default set to 100mA by default. The IC
proceeds to enumerate to determine if the external USB host/hub is a low- or high-power device and set the input current
limit to 100mA or 500mA, respectively.
For a dedicated charger, charger downstream port, or generic adapter, the optimum current limit is set for the specific
value.
When the input current limit is reached, the battery charge current is reduced so as to maintain the system load with- out
exceeding the input current limit. If the charge current is reduced to zero and ISYS exceeds the input current limit, VSYS
begins to fall. When VSYS drops to 50mV above VBAT, the SYS to BAT switch turns on, powering the system load from
the battery during the load peak.
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Maxim Integrated | 35
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
INPUT CURRENT LIMIT
I_LIM 2:0
100mA
500m A
600mA
700mA
900mA
1000mA
1500mA
RESERVED
000
001
010
011
100
101
110
111
IBUS_DET_SW
REGISTER 0x05
IS U S
100mA
500mA
I_LIM
00
01
10
11
Figure 9. Input Current Limit Settings
Power Monitor Output (UOK)
UOK is an open-drain output that pulls low when VBUS is valid and a valid adapter type is detected. This event also
issues an interrupt to the host and sets a flag in the event register. The UOK monitor has several different thresholds,
depending of type of adapter detected. See Table 4.
The initial detection threshold allows all type of adapters to be detected on BUS. Once the type of adapter is determined
the UVLO threshold is changed.
● For any USB 2.0 device, the UVLO thresholds are set to be compliant with USB specification.
● In adaptive mode, the UVLO threshold is lowered to VSYS + 150mV to allow for supporting collapsing charger types
that allow the IC to operate with lower power dissipation.
Note: Since the BUS UVLO threshold is changed after initial detection of the device type there are conditions where the
IC can toggle between BUS valid and not valid. This is an indication of that the adapter is not within the specified limits.
Soft-Start
To prevent input transients that can cause instability in the USB power source, the rate of change of input current and
charge current is limited. When a valid USB 2.0 input is connected, the input current limit is ramped from 0 to 100mA in
50μs. Once enumeration is complete the current can be ramped to 500mA or to the new input current limit value in 50μs.
140mV (typ)
ADAPTIVE
REGULATION
MIN V_SYS
VSYS
VBAT
VBAT = 2.5V
TIME
Figure 10. SYS Regulation
Table 4. VBUS Valid Input Range (Rising)
UVLO (V)
Initial VBUS detection (VBUS rising)
4.0 (typ)
For USB 2.0 low power (VBUS falling)
3.9 (typ)
For USB 2.0 high power (VBUS falling)
4.1 (typ)
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OVLO (V)
6.9 (typ) (VBUS rising)
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Selector, Automatic Detection, and USB
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Table 5. UOK States
BUS STATUS
UOK BEHAVIOR
Valid adapter detected on BUS
Low (continuous)
Suspended mode
Pulses low with 1.5s period and 50% duty cycle
D+/D- open detected and nENU_EN = 1
Pulses low with 0.15s period and 50% duty cycle
No valid adapter detected
High impedance
When the charger is enabled, the charge current ramps from zero to the final value in typically 1.5ms. Charge current also
ramps when transitioning to fast charge from prequalification and when changing the USB charge current from 100mA to
500mA.
Battery Charger
The battery charger has several different states of operation as shown in the charge profile (Figure 11) and state diagram
(Figure 12).
● Prequalification: Prequalification is used to gently charge a deeply discharged battery until its voltage is high enough
to safely begin fast charge. Prequalification occurs while the battery voltage is below VBAT_PCHG and the battery
is charged at maximum IPCHG. If IPCHG > ILIM, then the charging current is determined by the ILIM (input current
limit). Prequalification mode prevents charging a Li+ battery at a high rate when it is fully discharged, which can
cause the battery to become unstable and potentially dangerous and can also reduce life cycle of the Li+ battery.
The user can select precharge and undervoltage settings as required by new, low voltage lithium-ion, or standard
lithium-ion batteries. The battery undervoltage lockout and precharge threshold voltages are identified in the Electrical
Characteristics table and can be toggled through the BAT_CNTL register (0x10), bit 7.
● Fast charge: In fast-charge mode, the maximum charging current is set to IFCHG. The actual charging current is also
constrained by the input current limit, so the charge current is the lesser of IFCHG and ILIM-ISYS.
● Top-off charge: Top-off mode begins when the battery voltage reaches the set point. During top-off, the battery
voltage is regulated and the charge current declines. This prevents overcharging of the battery, and also minimizes
the power dissipation in the battery.
● Maintains charge: The charger enters this mode when the charging current has dropped below ICHG_ DONE
threshold. The charger continues to charge for tMTCHG time to insure battery is fully charged before charger is
disabled.
● Charge done: Charger is disabled and only engages again if the battery voltage drops below the VBAT_RECHG
threshold.
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VCHG_REG
VBAT_FCHG_R
IFCHG
60% x IFCHG
ICHG_DONE
VBAT_PCHG_R
IPCHG
PRECHARGE
t < tPCHG
FAST CHARGE
TOPOFF
t < tFCHG
MAINTAINS
CHARGE
CHARGE
DONE
TIME
t = tMTCHG
Figure 11. Charge Profile
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Selector, Automatic Detection, and USB
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NO VA L ID VB US
VBUS_UVLO > VBUS_ OR
VBUS_OVP < VBUS_
FROM ANY STATE
UOK = HIGH-Z
CHG_STAT = HIGH-Z
CHG_STAT = 000
ICHG = 0mA
VBUS_UVLO < VBUS < VBUS_OVP
C H A R GE R OF F
UOK = LOW
CHG_STAT = HIGH-Z
CHG_STAT = 000
ICHG = 0mA
CHARGER ENABLED
FROM ANY STATE
CHARGER ENABLED
P R E QU A L
UOK = LOW
CHG_STAT = LOW
CHG_STAT = 010
ICHG = IPCHG
tCHG_TIMER > tPCHG
VBAT > VPCHG_R
RESET CHARGE TIMER
VBAT < VPCHG_F
RESET CHARGE
TIMER
FA ULT
UOK = LOW
CHG_STAT
= 0.15s BLINKING
CHG_STAT = 111
ICHG = 0mA
FA ST CHA RGE
VBAT < VBAT_FCHG_F
UOK = LOW
CHG_STAT = LOW
CHG_STAT = 011
*ICHG = IFCHG
tCHG_TIMER >
tFCHG
VBAT > VBAT_FCHG_R
TOPOFF
C H A R GE
UOK = LOW
CHG_STAT = LOW
CHG_STAT = 100
ICHG = ITCHG
VBAT < VPCHG_F
RESET CHARGE TIMER
ICHG > ICHG_DONE
RESET CHARGE
TIMER
MA INTA IN
C H A R GE
UOK = LOW
CHG_STAT = LOW
CHG_STAT = 101
ICHG < ICHG_DONE
tCHG_TIMER > tMTCHG
VBAT < VBAT_REG + VBAT_RECHG
RESET CHARGE TIMER
C H A R GE
DONE
UOK = LOW
CHG_STAT = HIGH-Z
CHG_STAT = 110
ICHG = 0mA
tCHG_TIMER > tFCHG
ICHG < ICHG_DONE AND
IBUS < ILIM
tDIE < tDIE_LIM
RESET CHARGE TIMER
*CHARGE TIMER
SLOWED DOWN BY X2
IF: ICHG < IFCHG/2
AND PAUSED IF:
ICHG < IFCHG/5
FROM ANY CHARGING STATE
TTHM_COLD < TA
TTHM_COLD > TA OR
< TTHM_HOT
TTHM_HOT < TA
TEMPERATURE
SUSPEND
UOK = LOW
CHG_STAT = 1.5s BLINKING
CHG_STAT = 001
ICHG = 0mA
CHARGE TIMER PAUSED
Figure 12. Charger State Diagram
Charge Enable
The charger is enabled using either logic input CEN or with I2C bit CHG_EN, determined by the state of the CEN_MASK
bit.
Set nCEN_MASK to 0 to enable the use of the logic input CEN. Drive CEN logic-high to enable the charger or logic-low
to disable the charger.
Set nCEN_MASK to 1 to control charger enable by writing directly to the CHG_EN bit. Write 1 to CHG_EN to enable the
charger or 0 to disable the charger.
Enabling or disabling the charger does not affect VSYS. In many systems, there is no need for the system controller
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Selector, Automatic Detection, and USB
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(typically a microprocessor) to disable the battery charger, because the IC’s Smart Power Selector circuitry independently
manages charging and USB-battery power handover.
Charge Termination (EOC)
When the charger is in top-off mode and the charge current falls below the charge done threshold (ICHG_DONE), an
interrupt is sent to the host. Charging continues in maintains-charge mode for tMTCHG and then enters the DONE state
where charging stops. ICHG_DONE and tMTCHG are programmable through I2C.
Note that if charge current falls to ICHG_DONE as a result of the input current limit or thermal regulation, the charger
does not enter the DONE state. For the charger to enter DONE, charge current must be less than ITERM, the charger
must be in top-off mode (voltage regulation), and the input current limit or thermal regulation must not be reducing charge
current. The charger exits the DONE state and top-off or fast-charge resumes if the battery voltage subsequently drops
by VBAT_RECHG.
While in fast-charge mode, a large system load or device self-heating can cause the IC to reduce charge current. Under
these circumstances, the fast-charge timer adjusts to ensure that adequate charge time is still allowed. Consequently,
the fast-charge timer is slowed by 2x if charge current is reduced below 50% of the programmed fast-charge level. If
charge current is reduced to below 20% of the programmed level, the fast charge timer is paused. The fast-charge
timer is not adjusted when the charger is in top-off mode where charge current reduces due to current tapering under
normal charging. The timer settings are programmable through I2C and if the timer expires, charging is terminated and
an interrupt is sent to the host and a flag is set in the event register.
To exit a fault state, toggle CEN, CHG_EN, or remove and reconnect the BUS input source.
CHG_TYPE
CHG_TYPE is an open-drain output that is used to signal to the processor the current capability of the external adapter.
CHG_TYPE is low for 100mA or high-impedance for 500mA or greater.
Table 6. CHG_TYPE
CHG_TYPE
INPUT CURRENT LIMIT (mA)
0
100 or less
1
500 or more
IBUS_DEF
The IBUS_DEF input is only valid when nENU_EN is set to 1 or when D+/D- are unconnected. In this case, the adapter
type detection is activated. If the adapter type is detected as a USB 2.0 device, the input current is set to IBUS_DEF
value and does not initiate USB enumeration. See Table 7.
Table 7. IBUS_DEF
IBUS_DEF, nENU_EN = 1 OR D+/D- OPEN
INPUT CURRENT LIMIT
0
100mA
1
ILIM
Charge Status (CHG_STAT)
The charge status is indicated by an open-drain output CHG_STAT. See Table 8. A temperature fault or timers expiring
changes the charge state immediately and thus changes the output status.
Table 8. CHG_STAT Output
CHARGER STATUS
CHG_STAT BEHAVIOR
Charge in progress
Low (continuous)
Charge suspend (due to temperature fault(s))
Pulses with 1.5s period and 50% duty cycle
Timer fault
Pulses with 0.15s period and 50% duty cycle
Charge done
High impedance
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Selector, Automatic Detection, and USB
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Table 8. CHG_STAT Output (continued)
CHARGER STATUS
CHG_STAT BEHAVIOR
Battery removed
Pulses with 0.1s period, 10%-20% duty cycle
Battery Detection
The IC reliably detects insertion and removal of battery packs under various conditions. This includes battery packs with
open or closed protection circuit. A normal Li-ion battery pack includes protection circuitry that ensures the battery is
protected against overload. If an overload occurs, the protection circuitry opens its internal MOSFETs making the battery
pack output high impedance. To reset the protection, a voltage must be applied to the battery pack. The protector detects
this and closes the MOSFETs after a time delay.
When a valid power source is detected on BUS the battery detection state machine is enabled. The first task is to
determine the type of detection method used for predicting battery present condition.
The two methods are automatic detection and NTC detection. The type of algorithm used is determined by the I2C bit
BAT_DET_CNTL. Any change in the state of this bit reinitiates the detection algorithm as shown in Figure 13.
FROM ANY CONDITION
UPDATE OF
BAT_DET_CNTL
BAT_DET_CNTL = 0
AUTODETECTION
MODE
INITIAL MODE
BAT_DET_CNTL = 1
NTC
DETECTION
MODE
BAT_DET = 1
NTC DETECTED
NTC NOT DETECTED
NTC
DETECTION
MODE
BAT_DET = 0
Figure 13. Battery Detection State Diagram
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FROM ANY CONDITION
BAT_DET_CNTL CHANGED
FROM 1 TO 0
FROM ANY CONDITION
USB_OK = 0 OR ILIM = 1 OR
CHG_STAT = [000; 001; 111]
AUTO DETECTION
MODE
BAT_DET = 1
USB_OK = 1
ILIM = 0
CHG_STAT ≠
[000; 001;111]
NO
NO
YES
DELAY tDB
YES
IBAT > IBAT_DET
DEBOUNCE tDB
NO
SUSPEND
CHARGER
ENABLE IDIS
DELAY TDIS
DISABLE IDIS
VBAT > VBAT_UVLO
NO
ENABLE CHARGER
BAT_DET = 0
YES
ENABLE CHARGER
ICHG > IBAT_DET
DEBOUNCE tDB
BAT_DET = 1
CHG_STAT = 110
NO
YES
YES
NO
Figure 14. Battery Present Flow Chart
Automatic Detection Mode
Automatic battery detection is used when the BAT_DET_ CNTL bit is cleared. The automatic detection starts
by discharging the battery with IDIS for tDIS. Then it looks at the battery voltage. If the battery voltage is above
VBAT_UVLO_F, it indicates that a battery is present. If the battery voltage is below VBAT_UVLO_F then no battery is
detected.
Automatic detection continues to monitor VBAT as long as one of the following conditions exists:
● USB_OK = 0 no valid device connected to BUS
● ILIM = 1 input current limit active
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● CHG_STAT = [000, charger disabled: 001, charger in temperature suspend; 111 charger fault]
If none of the conditions above exist, automatic detection continues into the next phase.
In the second phase the charger is enabled for tDB. This is to allow a battery pack with open protection circuits to detect
the presence of the charger and reset itself.
After the tDB if the charging current is less than IBAT_DET it indicates that no battery is present. In this case the IC
suspends the charger and discharges the battery with a current sink of IDIS for tDIS. If only a capacitor is present at BAT,
the capacitor is discharged during the tDIS. After tDIS the battery voltage is compared to recharge threshold. If VBAT is
still above 2.4V, it indicates that a battery is present and the charger is enabled again. If the battery voltage drops below
the restart threshold this indicates that no battery is present, the status is latched into the I2C register, and the automatic
battery detection algorithm now only monitors the charging current. As long as the charging current is below IBAT_DET, it
indicates that no battery is present. If the charging current increases above IBAT_DET, the algorithm restarts the battery
detection.
If the automatic detection algorithm determines that a battery is present and that charger is in the DONE state, no further
action is taken as long as the charge remains in the DONE state (CHG_STAT is 110).
NTC Detection Mode
In NTC detection mode, the THM input is used to determine when a battery is connected. NTC detection mode is used
when the THERM_EN and BAT_DET_CNTL bits are set. If BAT_DET_CNTL = 1 and THERM_EN = 0, the IC presumes
that battery is present and sets BAT_DET to 1.
NTC detection monitors the voltage on the THM input to determine if an external NTC is present or not. This information
is used to control the status of BAT_DET. See Figure 13.
Thermistor Input (THM)
VTHM is monitored to provide battery temperature information to the charge controller. The JEITA temperature profiles
shown in Figure 15 utilize a 47kΩ bias resistor between the INT_3V3 and THM pins. The thermistor is a 100kΩ NTC
NTC-type beta of 4250K, which is tied from NTC to ground.
The IC is compliant with the JEITA specification for safe use of secondary lithium ion batteries (A Guide to the Safe Use of
Secondary Lithium Ion Batteries in Notebook type Personal Computers, JEITA and Battery Association of Japan, April 20,
2007). Once the JEITA parameters have been initialized for a given system, no software interaction is required. The four
temperature thresholds change the battery charger operation: T1, T2, T3, and T4. When the thermistor input exceeds the
extreme temperatures (< T1 or > T4), the charger shuts off and all respective charging timers are suspended. While the
thermistor remains out of range, no charging occurs, and the timer counters hold their state. When the thermistor input
comes back into range, the charge timers continue to count. The middle thresholds (T2 and T3) do not shut the charger
off, but have the capability to adjust the current/voltage targets to maximize charging while reducing battery stress.
T1
T2
T3
T4
C
T1
T2
0
10
T3
T4
45
60
VREG
100
-100mV
75
IFCHG (%)
VBAT_REG_OFFSET
50
-125mV
-150mV
25
-175mV
0
10
25
TEMPERATURE (°C)
45
60
75
25
75
TEMPERATURE (°C)
Figure 15. JEITA Battery Safety Regions
The behavior when the battery temperature is between T1 and T2 is controlled by THM_T1_T2 and the behavior when it
is between T3 and T4 is controlled by THM_T3_T4.
The JEITA specification recommends that systems reduce all loading on the battery when the battery temperature
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exceeds the maximum battery temperature for discharge (TMD). The IC generates an interrupt and sets the
WHIGH_BAT_T_IRQ bit when the battery temperature exceeds the T4 threshold.
If the THM disable threshold is exceeded, an interrupt is generated and the BAT_DET_IRQ bit is cleared in the event
register.
If the thermistor functionality is not required, clearing the THERM_EN disables temperature sensing and the thermistor
input is then high impedance.
The IC is compatible with a 100kΩ thermistor with a β of 4250K. The general relation of thermistor resistance to
temperature is defined by the following equation:
1
1
RT = R25 × θ{β( T + 273 − 298 )}
where RT is the resistance in Ω of the thermistor at temperature T in Celsius, R25 is the resistance in Ω of the thermistor
at +25ºC, β is the material constant of the thermistor (typically ranges from 3000K to 5000K), and T is the temperature of
the thermistor in ºC.
Thermal Overload Protection
Thermal overload protection limits total power dissipation in the IC. If the junction temperature exceeds 160ºC, the device
turns off, allowing the IC to cool. Continuous thermal-overload can result in a pulsed charge current ondition. Thermal
overload protection operates independent of the thermal regulation feature for additional protection. Typically, thermal
regulation prevents the die temperature from reaching the point where thermal overload protection is activated.
External Clock (Full Speed Only)
USB 2.0 full-speed operation requires that the system clock of the transceiver is within ±2500ppm, over temperature,
aging, etc. Therefore, an external crystal, resonator, or clock source is required to stay within this limit. The IC local
oscillator and internal digital clocks are derived from the reference clock at the XIN input.
USB Low-Speed Operation
For USB low-speed operation, the internal GMz clock can be used and no external crystal or external source is required.
Connect XIN to AGND and XOUT pin to INT_3V3 pin to enable USB low-speed mode.
External Crystal or Ceramic Resonator
XIN and XOUT connect to an external 12MHz crystal or ceramic resonator. Connect 33pF load capacitors from both XIN/
XOUT to analog ground.
Requirements for the external resonator/crystal for full speed:
Frequency: 12MHz ±0.25%
CLOAD: 33pF ±20%
Drive level: 200μW
Series resonance resistance: 60Ω (max), 30Ω (typ)
Note: Series resonance resistance is the resistance observed when the resonator is in the series resonant condition.
This is a parameter often stated by quartz crystal vendors and is called R1. When a resonator is used in the parallel
resonant mode with an external load capacitance, as is the case with the IC’s oscillator circuit, the effective resistance is
sometimes stated. The effective resistance at the loaded frequency of oscillation is:
REFF = R1[1 + ( C
CO
LOAD
)]
2
where R1 is the series resonance resistance, CO is the crystal capacitance, and CLOAD is the external load capacitance.
For typical CO and CLOAD values, the effective resistance can be greater than R1 by a factor of 2.
External Clock
The IC can also be driven from an external clock. The external clock can be a digital level square wave or sinusoidal
and can be directly coupled to XIN without the need for additional components. If the peaks of the reference clock are
above VINT_3V3 or below ground, the clock signal must be driven through a DC-blocking capacitor (approximately 33pF)
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connected to XIN.
The external clock source can be enabled using either the UOK or INT_3V3 signals depending on if the clock source is
active-low or active-high enabled.
Clock Timing Accuracy
USB 2.0 specification requires the system clock to be within ±2500ppm over temperature, aging, etc. It is recommended
to use a clock source with tighter initial accuracy to ensure that over time an accuracy of ±2500ppm is maintained.
External Power-On Signal
The EXT_PWRON output is used to enable power to other external circuits.
EXT_PWRON is an open-drain output, and is high impedance when no battery is detected or when a valid adapter is
detected.
If a valid battery is detected, the IC pulls EXT_PWRON low. This signal can be used to enable other parts of the system.
If a valid adapter is connected to the system while the battery is below the VBAT_UVLO threshold, the EXT_PWRON
transitions from high impedance to low as soon as the adapter type is determined and UOK goes from high impedance
to low.
From battery only or adapter only mode, the IC can enter adapter and battery mode, for this to occur, the IC must detect
a valid battery and at the same time a valid adapter type on the VBUS input. Once this occurs the IC generates a 63ms
high-impedance pulse on EXT_PWRON. This signal can be used to wake up the remainder of the system. See Figure
16 for the EXT_PWRON state diagram.
ESD Protection
D+, D-, and VBUS_ possess extra protection against static electricity to protect the IC up to ±8kV (HBM). The ESD
structures withstand high ESD in all operating modes: normal operation, suspend mode, and powered down. BUS
requires 1μF ceramic capacitors connected to ground as close to BUS_A and BUS_B as possible.
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SHUTDOWN
CONDITION
BAT_DET = 0
nUOK = 1
EXT_PWRON = HI-Z
VBAT > VBAT_UVLO_F
+ VBAT_UVLO_HYS
nUOK = 1
VBAT < VBAT_UVLO_F
B ATTERY ONLY
MODE
BAT_DET = 1
nUOK = 1
EXT_PWRON = L
nUOK = 0
A DA PTER A ND
B ATTERY MODE
BAT_DET = 1
nUOK = 0
EXT_PWRON = L
nUOK = 0
nUOK = 1
BAT NOT PRESENT
DETECTED
A DA PTER ONLY
MODE
BAT_DET = 0
nUOK = 0
EXT_PWRON = L
BAT PRESENT DETECTED
EXT_PWRON = HI-Z
DELAY 500µS
Figure 16. EXT_PWRON State Diagram
ESD Test Conditions
ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test
methodology, and test results. The Figure 17 shows the Human Body Model, and Figure 18 shows the current waveform
generated when discharged into low impedance. This model consists of a 100pF capacitor charged to the ESD voltage
of interest, which then discharges into the test device through a 1.5kΩ resistor.
RD
1.5kΩ
CHARGE-CURRENT
LIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
CS
100pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 17. Human Body ESD Test Models
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IP 100%
90%
IR
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
0
0
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 18. Human Body Model Current Waveform
RC
50MΩ TO 100MΩ
CHARGE-CURRENT
LIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
CS
150pF
RD
330Ω
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 19. IEC61000-4-2 ESD Test Model
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. It does not specifically refer
to integrated circuits. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is a
higher peak current in IEC 61000-4-2, due to lower series resistance. Hence, the ESD withstand voltage measured to
IEC 61000-4-2 generally is lower than that measured using the Human Body Model. Figure 18 shows the IEC 61000-4-2
model. The Contact-Discharge method connects the probe to the device before the probe is charged. The Air-Gap
Discharge test involves approaching the device with a charged probe.
I2C Functional Description
An I2C-compatible, 2-wire serial interface controls the charger settings as well as read back of adapter detection. The
serial bus consists of a bidirectional serial-data line (SDA) and a serial-clock input (SCL). The IC is a slave-only device,
relying upon a master to generate a clock signal. The master initiates data transfer to and from the IC and generates SCL
to synchronize the data transfer.
I2C is an open-drain bus. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a
pullup resistor. They both have Schmitt triggers and filter circuits to suppress noise spikes on the bus to assure proper
device operation. A bus master initiates communication with the IC as a slave device by issuing a START condition
followed by the IC address. The IC address byte consists of 7 address bits and a read/ write bit (RW). After receiving the
proper address, the IC issues an acknowledge bit by pulling SDA low during the ninth clock cycle.
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I2C Slave Address
A bus master initiates communication with a slave device (MAX77301) by issuing a START condition followed by the
slave address. The slave address byte consists of 7 address bits (0b0000010) followed by a read/write bit (R/W). So the
complete address byte is 0x05 for read operations and 0x04 for write operations. After receiving the proper address, the
IC issues an acknowledge by pulling SDA low during the ninth clock cycle.
SDA
tSU,STA
tSU,DAT
tLOW
tBUF
tHD,STA
tHD,DAT
tSU,STO
tHIGH
SCL
tHD,STA
tR
tF
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 20. I2C Interface Timing Diagram
I2C Bit Transfer
Each data bit, from the most significant bit to the least significant bit, is transferred one by one during each clock cycle.
During data transfer, the SDA signal is allowed to change only during the low period of the SCL clock and it must remain
stable during the high period of the SCL clock (Figure 21).
SCL
SDA
START
CONDITION (S)
DATA LINE STABLE
DATA VALID
DATA ALLOWED TO
CHANGE
STOP
CONDITION (P)
Figure 21. I2C Bit Transfer
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START and STOP Conditions
Both SCL and SDA remain high when the bus is not busy. The master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished
communicating with the IC, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission (Figure 22). Both START and STOP conditions are generated by the bus
master.
SDA
SCL
START
CONDITION
STOP
CONDITION
Figure 22. I2C START and STOP Conditions
Acknowledge
The acknowledge bit is used by the recipient to handshake the receipt of each byte of data (Figure 23). After data transfer,
the master generates the acknowledge clock pulse and the recipient pulls down the SDA line during this acknowledge
clock pulse so that the SDA line stays low during the high duration of the clock pulse. When the master transmits the
data to the IC, it releases the SDA line and the IC takes the control of the SDA line and generates the acknowledge bit.
When SDA remains high during this ninth clock pulse, this is defined as the not acknowledge signal. The master can then
generate either a STOP (P) condition to abort the transfer, or a REPEATED START (Sr) condition to start a new transfer.
SDA BY MASTER
D7
D6
D0
NOT ACKNOWLEDGE
SDA BY SLAVE
ACKNOWLEDGE
SCL
1
START CONDITION
2
8
9
CLOCK PULSE FOR
ACKNOWLEDGEMENT
Figure 23. I2C Acknowledge
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Maxim Integrated | 49
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Write Operations
The IC recognizes the write byte protocol as defined in the SMBus specification and shown in section A of Figure 24.
The write byte protocol allows the I2C master device to send 1 byte of data to the slave device. The write byte protocol
requires a register pointer address for the subsequent write. The IC acknowledges any register pointer even though only
a subset of those registers actually exists in the device.
The write byte protocol is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The master sends a START command.
The master sends the 7-bit slave address followed by a write bit (0x04).
The addressed slave asserts an acknowledge by pulling SDA low.
The master sends an 8-bit register pointer.
The slave acknowledges the register pointer.
The master sends a data byte.
The slave updates with the new data.
The slave acknowledges the data byte.
The master sends a STOP condition.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL
1
7
1 1
8
S
SLAVE ADDRESS
0
A
NUMBER
OF BITS
1
8
1
1
REGISTER POINTER
A
DATA
A
P
8
1
8
1
8
1
A
DATA X + 1
A
R/W
b) WRITING TO MULTIPLE REGISTERS
1
S
7
SLAVE ADDRESS
1
1
0
A
REGISTER POINTER X
A
DATA X
R/W
8
1
8
1
DATA X + n - 1
A
DATA X + n
A
NUMBER
OF BITS
NUMBER OF BITS
P
Figure 24. I2C Write Operations
In addition to the write-byte protocol, the IC can write to multiple registers as shown in section B of Figure 24. This
protocol allows the I2C master device to address the slave only once and then send data to a sequential block of registers
starting at the specified register pointer.
Use the following procedure to write to a sequential block of registers:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The master sends a START command.
The master sends the 7-bit slave address followed by a write bit (0x04).
The addressed slave asserts an acknowledge by pulling SDA low.
The master sends the 8-bit register pointer of the first register to write.
The slave acknowledges the register pointer.
The master sends a data byte.
The slave updates with the new data.
The slave acknowledges the data byte.
Steps 6 to 8 are repeated for as many registers in the lock, with the register pointer automatically incremented each
time.
10. The master sends a STOP condition.
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Maxim Integrated | 50
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Read Operations
The method for reading a single register (byte) is shown in section A of Figure 25.
To read a single register:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
The master sends a START command.
The master sends the 7-bit slave address followed by a write bit (0x04).
The addressed slave asserts an acknowledge by pulling SDA low.
The master sends an 8-bit register pointer.
The slave acknowledges the register pointer.
The master sends a repeated START condition.
The master sends the 7-bit slave address followed by a read bit (0x05).
The slave assets an acknowledge by pulling SDA low.
The slave sends the 8-bit data (contents of the register).
The master assets an acknowledge by pulling SDA low.
The master sends a STOP condition.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
A. READING A SINGLE REGISTER
1
S
7
SLAVE ADDRESS
1
1
8
0
A
REGISTER POINTER
1
1
A Sr
7
1
1
SLAVE ADDRESS
1
A
R/W
1
1
DATA
8
A
P
8
1
DATA X
A
NUMBER OF BITS
R/W
B. READING MULTIPLE REGISTERS
1
7
1
1
8
1
1
7
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
Sr
SLAVE ADDRESS
R/W
1 1
1
A
NUMBER OF BITS
R/W
8
DATA X+1
1
A
8
DATA X+n-1
1
8
A
DATA X+n
1
1
NUMBER OF BITS
A P
Figure 25. I2C Read Operations
In addition, the IC can read a block of multiple sequential registers as shown in section B of Figure 25.
Use the following procedure to read a sequential block of registers:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
The master sends a START command.
The master sends the 7-bit slave address followed by a write bit (0x04).
The addressed slave asserts an acknowledge by pulling SDA low.
The master sends an 8-bit register pointer of the first register in the block.
The slave acknowledges the register pointer.
The master sends a repeated START condition.
The master sends the 7-bit slave address followed by a read bit (0x05).
The slave assets an acknowledge by pulling SDA low.
The slave sends the 8-bit data (contents of the register).
The master assets an acknowledge by pulling SDA low.
Steps 9 and 10 are repeated for as many registers in the block, with the register pointer automatically incremented
each time.
12. The master sends a STOP condition.
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Maxim Integrated | 51
MAX77301/MAX77301A
JEITA-Compliant, Li+ Charger with Smart Power
Selector, Automatic Detection, and USB
Enumeration
Table 9. I2C Register Map
FUNCTI
ON
R/W
ADDRE
SS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
CHIP_I
D
R
0x00
DIE_TYPE[7:4]
DIE_TYPE[3:0]
CHIP_R
EV
R
0X01
DASH[3:0]
MASK_SET[3:0]
STATU
S_A
R
0x02
CHG_TYPE[3:0]
STATU
S_B
R
0x03
SUS
ILIM
Reserve
d
STATU
S_C
R
0x04
IBUS_D
EF
nENU_E
N_ HW
BAT_DE
T
CHG_STAT[2:0]
ENUM_
FLT
USB_O
K
THERM_STAT[2:0]
nSTDB_
EN_HW
nCEN
THER_
SD
Reserve
d
HW_OU
T_ IRQ
HW_IN_
IRQ
BIT 0
FS_DET
nUOK
nEXT_
PWR_O
N
BAT_
DET_IR
Q
CHG_ STAT_IRQ
THERM
_
REG_IR
Q
TIME_O
UT_
IRQ
EVENT_
A
R
0x05
DET_D
ONE_
IRQ
EVENT_
B
R
0x06
SUS_IR
Q
RESUM
E_ IRQ
ILIM_IR
Q
ENUM_
FLT_IR
Q
BUS_O
K_ IRQ
WHIGH_BAT_
T_IRQ
HIGH_B
AT_
T_IRQ
LOW_B
AT_
T_IRQ
0x07
DET_D
ONE_
IRQ_MA
SK
Reserve
d
HW_OU
T_
IRQ_MA
SK
HW_IN_
I
RQ_MA
SK
BAT_DE
T_
IRQ_MA
SK
CHG_STAT_
IRQ_MASK
THERM
_REG_
IRQ_MA
SK
TIME_O
UT_
IRQ_MA
SK
RESUM
E_
IRQ_MA
SK
ILIM_IR
Q_
MASK
ENUM_
FLT_
IRQ_MA
SK
BUS_O
K_
IRQ_MA
SK
WHIGH_BAT_
T_IRQ_MASK
HIGH_B
AT_T_
IRQ_MA
SK
LOW_B
AT_T_
IRQ_MA
SK
nSTDB_
EN
nSTDB_
EN_
HW_MA
SK
nENU_E
N
nENU_EN_
HW_MASK
DCD_E
N
KB_TM_
EN
IRQ_MA
SK_A
R/W
IRQ_MA
SK_B
R/W
0x08
SUS_IR
Q_
MASK
USB_C
NTL
R/W
0x09
RWU_E
N
SUS_E
N
IBUS_C
NTL
R/W
0x0A
IBUS_LI
M
V_SYS[1:0]
ILIM[2:0]
IBUS_DET_SW[1:0
]
CHARG
ER_CN
TL_A
R/W
0x0B
Reserve
d
TCHG[1:0]
IFCHG[2:0]
THERM_REG[1:0]
CHARG
ER_
CNTL_B
R/W
0x0C
THERM
_EN
BAT_DE
T_
MASK
BAT_DE
T_
CNTL
CHARG
E_TMR
R/W
0x0D
Reserve
d
Reserve
d
MTCHG_TMR[1:0]
FCHG_TMR[1:0]
PCHG_TMR[1:0]
CHARG
ER_VS
ET
R/W
0x0E
BAT_RECHG[1:0]
BAT_REG[1:0]
BAT_FCHG_HYS[1:0]
BAT_FCHG[1:0]
CHARG
ER_JEI
TA
R/W
0x0F
VBAT_0
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