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MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
General Description
The MAX77874 is a quad-phase, high-current, step-down
buck regulator for CPU and GPU multicore processors. Proprietary IP provides industry-leading transient
response, output voltage accuracy, high efficiency, and
miniature PCB footprint.
The output voltage is I2C programmable from 0.25V to
1.30V in 5mV steps. Output current capability is 16A.
Rotational phase spreading ensures high efficiency and
low ripple at light loads with seamless operation across
all varying loads. Turbo skip mode combines the same
transient response of forced-PWM mode with light load
efficiency similar to Skip mode. Soft-start and DVS ramp
rates are I2C programmable and controlled through dedicated logic inputs.
The MAX77874 is offered in a 48-bump, 0.35mm pitch
WLP array and is specified over the -40°C to +85°C
temperature range.
Ordering Information appears and Benefits and Features
continued at end of data sheet.
Applications
●
●
●
●
Smartphones, Tablets, Ultrabooks
DSLR, Mirrorless, Action Cameras
Gaming, Drones, Robots, Virtual Reality
AI, Machine Vision, Embedded Microprocessors
Benefits and Features
● Operating Range
• VIN: 2.7V to 4.8V
• VOUT: 0.25V to 1.30V in 5mV Steps
• IOUT: Up to 16A
● Fast Load-Transient Response
• 25mV Droop in FPWM and Turbo-Skip Modes
• 40mV Droop in Skip Mode
• Conditions: 3.7VIN, 0.9VOUT, 200mA to 9.2A
● Tight VOUT Accuracy
• 0.28% (max) Initial Accuracy at 0.9VOUT
• 1.5% (max) Over Line/Temperature
• 3mVP-P (typ) Ripple at All Loads
Simplified Block Diagram for 16A Multiphase Buck for Multicore Processors
MAX77874
INPUT
2.7V TO 4.8V
LA
CIN
OUTPUT
0.25V TO 1.30V
UP TO 16A
LC
4-PHASE
PWM
BUCK
VDD
LB
COUT
LD
BIAS
AND
REF
MICROPROCESSOR
VIO
1.65V TO 4.8V
I2C INTERFACE AND
REGISTERS
SCL
SDA
IRQ
DVS
EN
19-8692; Rev 1; 9/21
© 2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A.
|
Tel: 781.329.4700
|
© 2021 Analog Devices, Inc. All rights reserved.
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
16A Quad-Phase Core Buck for High-Performance Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
WLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics - Quad Phase Core Buck Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics - I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Diagram and Simplified Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Detailed Description - Quad Phase Core Buck Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Skip, Turbo Skip, and Forced PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rotational Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Enhanced Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Enable and Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disable and Active Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Full Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Dynamic Voltage Scaling (DVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DVS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DVS and Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Interrupt Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power OK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Internal Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Trim Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Analog Devices │ 2
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
TABLE OF CONTENTS (CONTINUED)
Detailed Description - I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C Interface Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C Communication Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I2C Communication Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Writing to a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Writing Multiple Bytes to Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reading from a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reading from Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Engaging HS-mode for operation up to 3.4MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Detailed Description - Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Top-Level Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Top-Level Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Buck Regulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I2C Slave Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Buck I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Applications Information - Quad Phase Core Buck Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Local Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Remote Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bias Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Analog Devices │ 3
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
LIST OF FIGURES
Figure 1. DVS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2. I2C Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3. I2C
System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Example I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. Writing to a Single Register with the Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Writing to Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. Reading from a Single Register with the Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10. Reading Continuously from Sequential Registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Engaging HS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 12. Typical Applications Circuit to Power a Multicore CPU/GPU Processor Up to 16A with MAX77874 . . . . . 36
LIST OF TABLES
Table 1. I2C Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
www.analog.com
Analog Devices │ 4
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Absolute Maximum Ratings
PG_, AGND_, SNS- to AGND...............................-0.3V to +0.3V
EN, DVS, SDA, SCL, IRQ to AGND.............-0.3V to VIO + 0.3V
IN_, LX_ to PG_....................................................-0.3V to +5.5V
VDD_ANA to AGND..............................................-0.3V to +1.85V
SNS+ to AGND.............................................-0.3V to VCC + 0.3V
VDD_DIG to AGND...............................................-0.3V to +1.85V
VCC, VIO to AGND................................................-0.3V to +5.5V
VPP to AGND...........................................................-0.3V to +8V
LX_ Current (Note 1)......................................................4.3ARMS
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Soldering Temperature (reflow)........................................+260°C
Note 1: LX_ has internal clamping diodes to PG_ and IN_. Applications that forward bias these diodes should take care not to
exceed the power dissipation limits of the device.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
WLP
Package Code
W482B2+1
Outline Number
21-0784
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA)
57°C/W
Junction to Case (θJC)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VIN = 3.7V, VIO = 1.8V, VOUT = 0.9V, CVDD_ANA = 1μF, CVDD_DIG = 1μF, CVCC = 1μF, TA = -40°C to +85°C, typical values at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supplies
VCC Falling UVLO
Threshold
VUVLO_F
2.5
2.6
2.7
V
VCC Rising UVLO
Threshold
VUVLO_R
2.7
2.8
2.9
V
VCC Falling UVLO
Threshold Delay Time
tUVLO_F
VCC Operating Voltage
Range
VCC
VCC falling, 20mV overdrive
20
2.7
Shutdown Supply
Current
ISHDN
BUCK0EN[0] = 0, VIO = 0V,
VIN = VCC = VPP = 4.8V, TA = +25°C
0.2
Shutdown Supply
Current (Note 1)
ISHDN
BUCK0EN[0] = 0, VVIO = 0V,
VIN = VCC = VPP = 4.8V, TA = +85°C
1
www.analog.com
μs
4.8
V
5
μA
μA
Analog Devices │ 5
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Electrical Characteristics (continued)
(VIN = 3.7V, VIO = 1.8V, VOUT = 0.9V, CVDD_ANA = 1μF, CVDD_DIG = 1μF, CVCC = 1μF, TA = -40°C to +85°C, typical values at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
14
30
μA
Disable Supply Current
IDISABLE
BUCK0EN[0] = 0, VIO = 1.8V,
VIN = VCC = VPP = 4.8V, TA = +25°C
Disable Supply Current
(Note 1)
IDISABLE
BUCK0EN[0] = 0, VIO = 1.8V,
VIN = VCC = VPP = 4.8V, TA = +85°C
25
IQ,SKIP
BUCK0EN[0] = 1, TURBO[0] = 0,
FPWMEN[0] = 0, VOUT = 0.9V, no load, no
switching, includes current through SNS+
and SNS- internal dividers
275
550
μA
Turbo Skip Mode
Quiescent Supply
Current
IQ,TURBOSKIP
BUCK0EN[0] = 1, TURBO[0] = 1,
FPWMEN[0] = 0, VOUT = 0.9V, no load, no
switching, includes current through SNS+
and SNS- internal dividers
475
900
μA
VPP Input Current
IVPP
VPP = VCC, TA = +25°C
0.03
1
μA
VIO Input Voltage Range
VIO
Skip Mode Quiescent
Supply Curernt
VIO Static Supply
Current
IVIO,STATIC
VPP = VCC, TA = -40°C to +85°C
μA
0.1
1.65
μA
1.8
4.8
V
fSCL = fSDA = 0Hz, SCL and SDA pulled
high, EN = GND, BUCK0EN[0] = 0,
ENPD_EN[0] = 0
0.2
1
μA
VIO Dynamic Supply
Current
IVIO,DYN
fSCL = fSDA = 1MHz
10
μA
VCC Dynamic Supply
Current
ICC
fSCL = fSDA = 1MHz
30
μA
VDD_DIG AND VDD_ANA Supplies
VDD_DIG Output Voltage
VDD_DIG
1.575
V
VDD_ANA Output
Voltage
VDD_ANA
1.575
V
200
μs
VDD_ANA and VDD_DIG
Enable Time
tCE
VDD_ANA and VDD_DIG ready time from
VCC rising edge
GPIO/I/O Logic Pins
EN Pulldown
Resistance
RPD,EN
200
EN, DVS Input Logic
High Threshold
VIH,ENVIH,DVS
0.7 x
VIO
EN, DVS Input Logic
Low Threshold
VIL,ENVIL,DVS
400
800
kΩ
V
0.3 x
VIO
EN, DVS, IRQ Logic
Input Leakage Current
ILK,ENILK,DVSILK, VIO = 1.8V, TA = +25°C
IRQ
VIO = 1.8V, TA = -40°C to +85°C
-1
POK Threshold Falling
VOUT = 0.9V
607.5
675
741.5
mV
POK Threshold Rising
VOUT = 0.9V
648
720
792
mV
POK Threshold
Hysteresis
VOUT = 0.9V
39
46
52
mV
0.2
0.4
V
IRQ Output Voltage Low
www.analog.com
VOL,IRQ
ISINK = 10mA
+1
V
0.1
μA
Analog Devices │ 6
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Electrical Characteristics (continued)
(VIN = 3.7V, VIO = 1.8V, VOUT = 0.9V, CVDD_ANA = 1μF, CVDD_DIG = 1μF, CVCC = 1μF, TA = -40°C to +85°C, typical values at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Thermal Monitors
Thermal Alarm 1
TJ120
TJ rising, 5°C hysteresis
+120
°C
Thermal Alarm 2
TJ140
TJ rising, 5°C hysteresis
+140
°C
TJSHDN
TJ rising, 15°C hysteresis
+165
°C
Thermal Shutdown
Temperature
Electrical Characteristics—Quad Phase Core Buck Regulator
(VIN = 3.7V, VIO = 1.8V, VOUT = 0.9V, CVDD_ANA = 1μF, CVDD_DIG = 1μF, CVCC = 1μF, TA = -40°C to +85°C, typical values at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.3
V
+10
mV
mV
Output Voltage
Output Voltage Range
VOUT
Output Voltage Range
End-Point Error
8-bit resolution, 5mV/LSB
0.25
VOUT = 0.25V and 1.3V, IOUT = 0mA,
FPWMEN[0] = 1, TA = +25°C
-10
IOUT = 0mA, FPWMEN[0] = 1, TA = +25°C
-2.5
+2.5
IOUT = 0mA, TURBO[0] = 0,
FPWMEN[0] = 1, TA = -5°C to +85°C
-5
+5
IOUT = 0mA, TURBO[0] = 0,
FPWMEN[0] = 1, TA = -40°C to +85°C
-13
±1
DC Output Voltage Accuracy
Initial Output Voltage
Accuracy
Output Voltage Accuracy, FPWM Mode
mV
±1.75
+10
Output Voltage Accuracy, Turbo Skip Mode
IOUT = 0mA, TURBO[0] = 1,FPWMEN[0] = 0,
excludes output voltage ripple
±2.5
mV
Output Voltage Accuracy, Skip Mode
IOUT = 0mA, TURBO[0] = 0, FPWMEN[0] = 0,
excludes output voltage ripple
±2.5
mV
Load Regulation
FPWMEN[0] = 1, IOUT = 0 to 16A
0.1
mV/A
Line Regulation
VIN = 2.5V to 4.8V, IOUT = 0mA,
FPWMEN[0] = 1
-0.3
+0.3
mV/V
Switch Ratings
Maximum Output Current
Per phase, RMS rating
4000
PMOS Current Limit
ILIMP
Per phase
4.750
5.275
5.800
A
NMOS Valley Current
Limit
IVALLEY
Per phase
3.819
4.244
4.669
A
ILIMN
Per phase
-1800
-1500
-1200
mA
Zero-Crossing Current
Threshold
IZX
DC tested
+50
+115
+170
mA
Zero-Crossing Comparator Propagation Delay
tPD_ZX
NMOS Negative Current
Limit
Switching Frequency
www.analog.com
IOUT,MAX
fSW
mA
20
FPWM mode, no load, TA = +25°C
1.9
2.0
ns
2.1
MHz
Analog Devices │ 7
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Electrical Characteristics—Quad Phase Core Buck Regulator (continued)
(VIN = 3.7V, VIO = 1.8V, VOUT = 0.9V, CVDD_ANA = 1μF, CVDD_DIG = 1μF, CVCC = 1μF, TA = -40°C to +85°C, typical values at
TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
LX_ Leakage Current
SYMBOL
ILKG_LX
CONDITIONS
MIN
VLX_ = 0V or 4.8V, TA = +25°C
TYP
MAX
0.1
1
VLX_ = 0V or 4.8V, TA = -40°C to +85°C
(Note 1)
1
UNITS
μA
Main Switch
On-Resistance
RDSON_MS
ILX_ = 190mA
65
mΩ
Synchronous Rectifier
On-Resistance
RDSON_SR
ILX_ = -190mA
16
mΩ
BUCK0EN[0] = 0, BUCK0ADEN[0] = 1,
resistance from LX_ to PG_, per phase
100
140
4.5
5
5.5
BUCK0SSR[1:0] = 0b01, WARMSTART[0] = 1
9
10
11
BUCK0SSR[1:0] = 0b10, WARMSTART[0] = 1
18
20
22
Active Discharge
LX_ Active Discharge
Resistance
RLX_AD
Ω
Ramp Rates
BUCK0SSR[1:0] = 0b00, WARMSTART[0] = 1
Startup Ramp Rate
BUCK0SSR[1:0] = 0b11, WARMSTART[0] = 1
Cold Startup Ramp Rate
WARMSTART[0] = 0
DVS Ramp Rate
36
40
44
1.125
1.25
1.375
BUCK0RSR[1:0] = 0b00
4.5
5
5.5
BUCK0RSR[1:0] = 0b01
9
10
11
BUCK0RSR[1:0] = 0b10
18
20
22
BUCK0RSR[1:0] = 0b11
36
40
44
mV/μs
mV/μs
mV/μs
DVS Ramp Delay
Measured from DVS rising edge to first LX
pulse
1.5
Startup Ramp Delay
Measured from EN rising edge to first LX
pulse
50
200
μs
μs
SNS+ and SNS- Feedback Inputs
SNS+ Input Impedance
RIN,SNS+
75
120
160
kΩ
SNS- Input Impedance
RIN,SNS-
75
120
160
kΩ
I2C Electrical Characteristics
VIN = 3.7V, VIO = 1.8V, VOUT = 0.9V, CVDD_ANA = 1μF, CVDD_DIG = 1μF, CVCC = 1μF, TA = -40ºC to +85ºC, typical values are at
TA = +25ºC, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDA and SCL I/O Stage
SCL, SDA Input High
Voltage
VIH
VIO = 1.8V
SCL, SDA Input Low
Voltage
VIL
VIO = 1.8V
SCL, SDA Input
Hysteresis
www.analog.com
VHYS
0.7 x
VIO
V
0.3 x
VIO
0.05 x
VIO
V
V
Analog Devices │ 8
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
I2C Electrical Characteristics (continued)
VIN = 3.7V, VIO = 1.8V, VOUT = 0.9V, CVDD_ANA = 1μF, CVDD_DIG = 1μF, CVCC = 1μF, TA = -40ºC to +85ºC, typical values are at
TA = +25ºC, unless otherwise noted.) (Note 1)
PARAMETER
SCL, SDA Input
Leakage Current
SDA Output Low Voltage
SYMBOL
II
VOL
SCL, SDA Pin
Capacitance
CI
Output Fall Time from
VIH to VIL (Note 1)
tOF
CONDITIONS
VIO = 3.6V, VSCL = VSDA = 0V and 3.6V
MIN
TYP
-10
Sinking 20mA
MAX
UNITS
+10
μA
0.4
V
10
pF
120
ns
1000
kHz
I2C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST MODE PLUS) (Note 2)
Clock Frequency
Hold Time (REPEATED)
START Condition
fSCL
0
tHD;STA
0.26
μs
SCL Low Period
tLOW
0.5
μs
SCL High Period
tHIGH
0.26
μs
Setup Time REPEATED
START Condition
tSU_STA
0.26
μs
Data Hold Time
tHD_DAT
0
μs
Data Setup Time
tSU_DAT
50
ns
Setup Time for STOP
Condition
tSU_STO
0.26
μs
Bus Free Time Between
STOP and START
Condition
tBUF
0.5
μs
Pulse Width of
Suppressed Spikes
tSP
Maximum pulse width of spikes that must
be suppressed by the input filter
50
ns
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 100pF) (Note 2)
Clock Frequency
fSCL
3.4
MHz
Setup Time REPEATED
START Condition
tSU_STA
160
ns
Hold Time (REPEATED)
START Condition
tHD_STA
160
ns
tLOW
160
ns
SCL High Period
tHIGH
60
ns
Data Setup Time
tSU_DAT
10
ns
Data Hold Time
tHD_DAT
0
70
ns
SCL Rise Time
trCL
TA = +25°C
10
40
ns
Rise Time of SCL
Signal after REPEATED
START Condition and
after Acknowledge Bit
trCL1
TA = +25°C
10
80
ns
SCL Fall Time
tfCL
TA = +25°C
10
40
ns
SDA Rise Time
trDA
TA = +25°C
10
80
ns
SCL Low Period
www.analog.com
Analog Devices │ 9
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
I2C Electrical Characteristics (continued)
VIN = 3.7V, VIO = 1.8V, VOUT = 0.9V, CVDD_ANA = 1μF, CVDD_DIG = 1μF, CVCC = 1μF, TA = -40ºC to +85ºC, typical values are at
TA = +25ºC, unless otherwise noted.) (Note 1)
PARAMETER
SDA Fall Time
Setup Time for STOP
Condition
SYMBOL
tfDA
CONDITIONS
TA = +25°C
tSU_STO
Bus Capacitance
CB
Pulse Width of
Suppressed Spikes
tSP
MIN
TYP
10
MAX
UNITS
80
ns
160
ns
100
Maximum pulse width of spikes that must
be suppressed by the input filter
10
pF
ns
I2C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, CB = 400pF) (Note 2)
Clock Frequency
fSCL
1.7
MHz
Setup Time REPEATED
START Condition
tSU_STA
160
ns
Hold Time (REPEATED)
START Condition
tHD_STA
160
ns
tLOW
320
ns
SCL High Period
tHIGH
120
ns
Data Setup Time
tSU_DAT
10
ns
Data Hold Time
tHD_DAT
0
150
ns
SCL Rise Time
tRCL
TA = +25°C
20
80
ns
Rise Time of SCL
Signal after REPEATED
START Condition and
after Acknowledge Bit
tRCL1
TA = +25°C
20
80
ns
SCL Fall Time
tFCL
TA = +25°C
20
80
ns
SDA Rise Time
tRDA
TA = +25°C
20
160
ns
SDA Fall Time
tFDA
TA = +25°C
20
160
ns
SCL Low Period
Setup Time for STOP
Condition
Bus Capacitance
Pulse Width of Suppressed Spikes
tSU_STO
160
ns
CB
tSP
400
Maximum pulse width of spikes that must
be suppressed by the input filter
10
pF
ns
Note 1: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through correlation using statistical quality control methods.
Note 2: Guaranteed by design. Not production tested.
www.analog.com
Analog Devices │ 10
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Typical Operating Characteristics
(Figure 12, VIN = 3.7V, VOUT = 0.9V, VIO = 1.8V, L = TOKO DFE201210U-R24M ,TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD
100
100
3.7VIN
0.9VOUT
90
80
50
40
30
SKIP
TURBO
FPWM
10
80
0
0.001
85
80
75
70
0.01
0.1
1
60
10
DFE201210U TURBO
DFE201610E TURBO
0
5
LOAD CURRENT (A)
toc04
50
40
30
10
10
0
15
toc05
100
VIN = 3.7V
3.5A LOAD
90
80
80
80
70
70
70
60
50
40
30
20
2.5
3
3.5
4
4.5
50
40
30
0
5
0.25
0.5
0.75
QUIESCENT SUPPLY CURRENT
toc07
1
NO LOAD
BIAS ON
IQ (µA)
1
0.1
0.01
VIN (V)
www.analog.com
30
SKIP
TURBO
FPWM
0.25
0.5
0.75
5
1
1.25
OUTPUT ACCURACY vs. SETTING
toc09
VIN = 3.7V
NO LOAD
4
2
0
-2
-4
-6
VIO = 0V
4
toc06
6
SKIP
0.1
3
EFFICIENCY vs. VOUT
40
8
BIAS OFF
TURBO
5
50
10
toc08
10
1
4.5
60
0
1.25
100
10
4
VOUT (V)
SHUTDOWNSUPPLY CURRENT
1000
NO LOAD
2
3.5
VOUT (V)
FPWM
0.01
3
VIN = 3.7V
100mA LOAD
10
VIN (V)
100
2.5
20
SKIP
TURBO
FPWM
10
OUTPUT ERROR (mV)
0
60
20
SKIP
TURBO
FPWM
VOUT = 0.9V
100mA LOAD
90
EFFICIENCY (%)
90
10
SKIP
TURBO
FPWM
VOUT = 0.9V
3.5A LOAD
VIN (V)
EFFICIENCY vs. VOUT
100
EFFICIENCY (%)
EFFICIENCY (%)
60
LOAD CURRENT (A)
EFFICIENCY vs. VIN
100
70
20
65
toc03
90
EFFICIENCY (%)
60
EFFICIENCY vs. VIN
100
90
70
20
IQ (mA)
toc02
3.7VIN
0.9VOUT
95
EFFICIENCY (%)
EFFICIENCY (%)
toc01
EFFICIENCY vs. LOAD
vs. INDUCTOR SIZE
2
3
-8
4
VIN (V)
5
-10
SKIP
TURBO
FPWM
0.0
0.5
1.0
1.5
EXPECTED OUTPUT (V)
Analog Devices │ 11
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Typical Operating Characteristics (continued)
(Figure 12, VIN = 3.7V, VOUT = 0.9V, VIO = 1.8V, L = TOKO DFE201210U-R24M ,TA = +25°C, unless otherwise noted.)
10
toc10
OUTPUT ACCURACY vs. DC LOAD
toc11
10
VOUT = 0.9V
NO LOAD
8
4
4
0
-2
-4
-6
-8
-10
2
0
-2
-4
-6
SKIP
TURBO
FPWM
2.5
OUTPUT ERROR (mV)
6
4
3.0
3.5
4.0
4.5
-10
5.0
0
-4
SKIP
TURBO
FPWM
4
8
12
16
-10
-50
TURBO/SKIP
100
toc14
VLXA
5V/div
VLXB
5V/div
VLXC
5V/div
VLXD
5V/div
5mV/div
20mA
VOUT
50
TURBO/SKIP, 300mA LOAD
5mV/div
5mA
VOUT
LIGHT-LOADPHASE SPREADING
toc13
0mA
0
TEMPERATURE (°C)
IOUT (A)
OUTPUT VOLTAGERIPPLE
5mV/div
100mA
VOUT
5mV/div
500mA
VOUT
5mV/div
20µs/div
FPWMPHASE MATCHING
VLXA
1µs/div
LOAD TRANSIENT
toc15
VLXB
5V/div
VLXC
5V/div
VLXD
5V/div
toc16
0.2A TO 9.2A LOAD STEP
400A/µs
FPWM
5V/div
200ns/div
www.analog.com
0
-2
-8
VIN (V)
VOUT
2
-6
SKIP
TURBO
FPWM
-8
toc12
VIN = 3.7V
VOUT = 0.9V
100mA LOAD
8
6
2
OUTPUT ACCURACY
vs. TEMPERATURE
10
VIN = 3.7V
VOUT = 0.9V
6
OUTPUT ERROR (mV)
OUTPUT ERROR (mV)
8
OUTPUT ACCURACY vs. VIN
VGATE
(IOUT)
5V/div
VOUT
50mV/div
10µs/div
Analog Devices │ 12
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Typical Operating Characteristics (continued)
(Figure 12, VIN = 3.7V, VOUT = 0.9V, VIO = 1.8V, L = TOKO DFE201210U-R24M ,TA = +25°C, unless otherwise noted.)
LOAD TRANSIENT
LOAD TRANSIENT
toc17
0.2A TO 9.2A LOAD STEP
400A/µs
TURBO
VGATE
(IOUT)
5V/div
VOUT
50mV/div
VGATE
(IOUT)
5V/div
VOUT
50mV/div
10µs/div
10µs/div
LOAD TRANSIENT
LOAD TRANSIENT
toc19
0.2A TO 2.2A LOAD STEP
400A/µs
FPWM
5V/div
VOUT
50mV/div
VGATE
(IOUT)
5V/div
VOUT
50mV/div
10µs/div
10µs/div
LOAD TRANSIENT
toc21
0.2A TO 2.2A LOAD STEP
400A/µs
SKIP
VGATE
(IOUT)
www.analog.com
FPWM
50mV/div
10µs/div
toc22
1.6A TO 16A LOAD STEP
400A/µs
5V/div
VOUT
toc20
0.2A TO 2.2A LOAD STEP
400A/µs
TURBO
VGATE
(IOUT )
LOAD TRANSIENT
toc18
0.2A TO 9.2A LOAD STEP
400A/µs
SKIP
VGATE
(IOUT)
5V/div
VOUT
50mV/div
10µs/div
Analog Devices │ 13
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Typical Operating Characteristics (continued)
(Figure 12, VIN = 3.7V, VOUT = 0.9V, VIO = 1.8V, L = TOKO DFE201210U-R24M ,TA = +25°C, unless otherwise noted.)
LOAD TRANSIENT
LOAD TRANSIENT
toc23
1.6A TO 16A LOAD STEP
400A/µs
TURBO
VGATE
(IOUT)
5V/div
VOUT
50mV/div
VGATE
(IOUT)
5V/div
VOUT
50mV/div
10µs/div
LOAD TRANSIENT
10µs/div
LOAD TRANSIENT
toc25
0A TO 9A LOAD STEP
400A/µs
TURBO
5V/div
VOUT
50mV/div
VGATE
(IOUT)
5V/div
VOUT
50mV/div
10µs/div
10µs/div
LINE TRANSIENT
FPWMMODE
toc27
2A TO 4A LOAD STEP
400A/µs
FPWM
VGATE
(IOUT)
VIN
3.8V
toc28
200mV/div
3.3V
5V/div
VOUT
50mV/div
10µs/div
www.analog.com
toc26
0A TO 9A LOAD STEP
400A/µs
SKIP
VGATE
(IOUT)
LOAD TRANSIENT
toc24
1.6A TO 16A LOAD STEP
400A/µs
SKIP
VOUT
10mV/div
200µs/div
Analog Devices │ 14
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Typical Operating Characteristics (continued)
(Figure 12, VIN = 3.7V, VOUT = 0.9V, VIO = 1.8V, L = TOKO DFE201210U-R24M ,TA = +25°C, unless otherwise noted.)
LINE TRANSIENT
TURBO MODE
VIN
LINE TRANSIENT
SKIP MODE
toc29
3.8V
200mV/div
VIN
toc30
3.8V
3.3V
200mV/div
3.3V
VOUT
10mV/div
VOUT
10mV/div
200µs/div
200µs/div
REGULATORSOFT-START RATES
WARM RATES ONLY
REGULATORSOFT-START RATES
toc31
toc32
5V/div
EN
20mV/µs 10mV/µs
40mV/µs
200mV/div
5V/div
20mV/µs
EN
200mV/div
40mV/µs
5mV/µs
5mV/µs
1.25mV/µs
(COLD)
VOUT
VOUT
100µs/div
10mV/µs
40µs/div
REGULATORSHUTDOWN
ACTIVE DISCHARGE ENABLED
REGULATORENABLE vs. BIAS STATUS
toc33
5V/div
EN
200mV/div
EN
toc34
5V/div
VOUT
BIASEN = 1
BIASEN = 0
VOUT
200mV/div
10µs/div
www.analog.com
4ms/div
Analog Devices │ 15
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Typical Operating Characteristics (continued)
(Figure 12, VIN = 3.7V, VOUT = 0.9V, VIO = 1.8V, L = TOKO DFE201210U-R24M ,TA = +25°C, unless otherwise noted.)
REGULATORSHUTDOWN
ACTIVE DISCHARGE DISABLED
EN
DVS TRANSITION, RISING
toc35
toc36
5V/div
5V/div
VOUT
DVS
20mV/µs
100mV/div
40mV/µs
5mV/µs
VOUT
10mV/µs
200mV/div
4s/div
10µs/div
DVS TRANSITION, FALLING
toc37
DVS
5V/div
-5mV/µs
VOUT
-40mV/µs
-10mV/µs
100mV/div
-20mV/µs
10µs/div
www.analog.com
Analog Devices │ 16
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX77874
1
2
3
4
5
PGA
PGA
LXA
INAC
INAC
B
SCL
PGA
LXA
INAC
C
SDA
VPP
D
AGND3
AGND
E
AGND4
F
PGB
A
6
7
8
LXC
PGC
PGC
INAC
LXC
PGC
IRQ
SNS-
SNS+
EN
DVS
VCC
VIO
AGND
AGND
AGND1
AGND2
AGND
PGB
LXB
INBD
INBD
LXD
PGD
PGB
LXB
INBD
INBD
LXD
PGD
+
VDD_
DIG
VDD_
ANA
PGD
48 WLP
(2.22mm x 2.92mm)
Pin Description
PIN
NAME
A1, A2, B2
PGA
Power GND
A3, B3
LXA
Inductor Connection. Pulled to PG with 100Ω when EN is low and
BUCK0ADEN = 1.
A4, A5, B4,
B5
INAC
Power Input to Power FETs and Gate Drivers
A6, B6
LXC
Inductor Connection. Pulled to PG with 100Ω when EN is low and
BUCK0ADEN = 1.
A7, A8, B7
PGC
Power GND
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FUNCTION
REF SUPPLY
TYPE
GND
GND
IN
Power
Power
IN
Power
GND
GND
Analog Devices │ 17
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Pin Description
PIN
NAME
FUNCTION
REF SUPPLY
B1
SCL
Serial Clock Input. SCL accepts a clock frequency of up to 3.4MHz.
VDD
TYPE
Logic Input
Open-Drain
Logic Output
B8
IRQ
Open-Drain Interrupt Output. High impedance when EN = 0.
C1
SDA
Serial Data Input/Output for I2C 3.0 Interface
C2
VDD_DIG
Digital VDD
Power
C3
VPP
Power Pin for OTP Programming. Connect to VDD_DIG.
Power
C4
SNS-
Negative Differential Voltage Sense Input. SNS- connects to GND
at the point-of-load.
GND
Voltage
Sense
C5
SNS+
Positive Differential Voltage Sense Input. Connect SNS+ to the
output at the point-of-load.
VCC
Voltage
Sense
C6
EN
EN Logic Input. Drive high to enable the buck regulator output.
Drive low to disable the buck regulator output.
VDD
Logic Input
C7
DVS
DVS Logic Input. Drive high to set the target output voltage to the
contents of the VOUT_DVS register. Drive low to set the target
output voltage to the contents of the VOUT register.
VDD
Logic Input
C8
VCC
Powers the Battery Level Circuitry of the MAX77874
IN
Power
D1
AGND3
For Internal Use Only. Must be tied to AGND.
D2, D4,
D5, D8
AGND
Analog GND. Pin D2 is internally connected to AGND, and can be
left unconnected or tied to AGND3/AGND4.
VDD
Logic Input/
Output
GND
GND
D3
VIO
D6
AGND1
For Internal Use Only. Must be tied to AGND.
GND
D7
AGND2
For Internal Use Only. Must be tied to AGND.
GND
E1
AGND4
For Internal Use Only. Must be tied to AGND.
GND
E2, F1, F2
PGB
Power GND
E3, F3
LXB
Inductor Connection. Pulled to PG with 100Ω when EN is low and
BUCK0ADEN = 1.
E4, E5,
F4, F5
INBD
Power Input to Power FETs and Gate Drivers
E6, F6
LXD
Inductor Connection. Pulled to PG with 100Ω when EN is low and
BUCK0ADEN = 1.
E7, F7, F8
PGD
Power GND
E8
VDD_ANA
Analog VDD
www.analog.com
Power for SCL, SDA Pins. Bringing VIO to GND resets the registers.
GND
Power
GND
GND
IN
Power
Power
IN
Power
GND
GND
Power
Analog Devices │ 18
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Block Diagram and Simplified Schematic
VCC
INA
C
VPP
VDD_DIG
VDD_ANA
PHASE A
DRIVER
INTERNAL
REGULATORS
LXA
VIN
2.7V TO 4.8V
LA
PGA
INBD
VIO
1.65V TO
4.8V
PHASE B
DRIVER
LXB
VIN
2.7V TO 4.8V
LB
PGB
VOUT
0.25V TO
1.3V
SDA
REGISTERS, BIAS
SNS+
CONTROLLER
SCL
SERIAL
INTERFACE, I/O
STAGE,
ABITRATOR,
FLOOR/CEILING
REGISTERS
CLOAD RLOAD
SNSINAC
VIN
2.7V TO 4.8V
IRQ
PHASE C
DRIVER
EN
LXC
LC
PGC
TEMP SENSOR
AGND
INBD
VIN
2.7V TO 4.8V
RSR[1:0]
FSR[1:0]
SSR[1:0]
RAMP
CONTROL
WARMSTART
PHASE D
DRIVER
LXD
LD
PGD
OSC
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Analog Devices │ 19
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Detailed Description—Quad Phase Core
Buck Regulator
The MAX77874 is a highly efficient, small step-down converter that operates on an input voltage range of 2.7V to
4.8V and can output up to 16A of current. An integrated I2C
interface allows for configuration of output voltage, dynamic voltage scaling (DVS), interrupts, and control mode.
Control Scheme
The quad phase core buck regulator uses Maxim's proprietary Quick-PWM™ quick-response, constant-on-time
PWM control scheme. This control scheme handles wide
input/output voltage ratios (low duty-cycle applications)
with ease and provides immediate response to load
transients while maintaining a nearly constant switching
frequency. Additionally, the scheme exhibits excellent
stability with very high loop-bandwidth for minimal droop/
soar and rapid recovery during load transients.
Skip, Turbo Skip, and Forced PWM
When enabled, the quad phase core buck operates in
either skip, turbo skip, or forced PWM (FPWM) mode.
Program the operating mode using the FPWMEN and
TURBO_SKIP bits in the BUCK0CNFG0 register.
Skip mode provides the lowest supply current and highest
efficiency at light loads, but has more VOUT droop during
load transients than the other modes. Turbo skip mode
combines superior transient response (same as FPWM
mode) with light load efficiency and supply current nearly
as low as skip mode. For this reason, turbo skip mode is
the default setting. Forced PWM mode provides near constant switching frequency for noise-sensitive applications,
but has higher supply current and lower efficiency at light
loads. FPWM has similar transient response to turbo skip
mode. See the Typical Operating Characteristics section
for efficiency, supply current, and load transient response
for each operating mode.
The skip and turbo skip modes transition automatically
between PWM operation at heavy load and rotational
phase spreading at light loads to maintain high efficiency
and low output ripple across all loads.
Rotational Phase Spreading
At light loads, proprietary rotational phase spreading
switches all four phases in a rotational sequence with
extended time at zero current between switching pulses.
Compared to phase shedding techniques that disable
some phases entirely, rotational phase spreading transitions across varying loads more smoothly with less output
ripple and fewer glitches since phases do not get added
or dropped. See the output ripple scope waveforms in
the Typical Operating Characteristics section. To maintain efficiency, the phases are spread further and further
apart as loads decrease, with each phase entering a low
quiescent current mode when its current is zero and its
synchronous rectifier is off.
Enhanced Transient Response
In skip and turbo skip modes, the converter is capable of
activating all four phases simultaneously to respond to a
load transient. However, in skip mode, the response is not
as fast as in turbo skip mode in order to achieve a lower
quiescent current. This enhanced transient response
(ETR) circuit is not needed in FPWM mode due to the
high-loop bandwidth of the controller.
Enable and Soft-Start
VIN and VIO must both be valid to enable the quad phase
core buck regulator. See the Electrical Characteristics
table for the valid voltage ranges. When both voltages
are valid, enable the core buck regulator by using the
dedicated EN logic input pin or by using the BUCK0EN bit
in the BUCK0CNFG0 register. These two control mechanisms are a logic OR function, so setting either the pin or
the logic bit to logic 1 enables the regulator.
Once enabled, there is a short delay (see the Startup
Ramp Delay in Electrical Characteristics table) before the
quad phase core buck regulator soft-starts with a linear
voltage ramp at the output to control in-rush current and
output voltage overshoot. There are a total of five softstart ramp rates controlled through registers. The default
setting is for cold startup, with a slow ramp of 1.25mV/
μs for MAX77874B, or warm startup, with a fast ramp of
40mV/μs for MAX77874C. To enable warm startup ramp
rates, set the WARMSTART bit in the BUCK0CNFG1 register to logic 1. Then select the desired warm startup ramp
rate using the BUCK0SSR[1:0] bits in the BUCK0CNFG1
register. The default setting for warm startup ramp rate
is 5mV/μs for MAX77874B or 40mV/μs for MAX77874C.
The other settings are 10mV/μs and 20mV/μs. Set the
desired ramp rate prior to enabling the regulator.
Disable and Active Discharge
When both control mechanisms (BUCK0EN and the EN
pin) are logic 0, the buck regulator is off and the output is
high impedance.
The quad phase core buck regulator contains on-chip
resistors for optional active discharge when disabled. To
enable active discharge, set the BUCK0ADEN bit in the
BUCK0CNFG0 register to logic 1. When active discharge
is enabled and the regulator is disabled, four internal 100Ω
resistors are internally connected from LX_ to PG_ (one
resistor per phase for an effective discharge resistance of
Quick-PWM is a trademark of Maxim Integrated Product, Inc.
www.analog.com
Analog Devices │ 20
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
25Ω). When the buck is enabled, the discharge resistors
are automatically disconnected regardless the state of the
BUCK0ADEN bit. Therefore, if active discharge is always
desired, the bit can be left enabled (logic 1) without causing additional loading when the buck is enabled.
Full Shutdown
By default, when the buck regulator is disabled, its bias
circuits are also disabled to save supply current. When
enabling the buck regulator, the bias is automatically
enabled and disabled. If faster startup is desired, the bias
circuits can be pre-enabled by setting the BIASEN bit
in the BUCK0CNFG0 register to logic 1. This comes at
the expense of higher supply current when the buck is
disabled.
Even when the regulator and the bias are disabled, toplevel circuits in the MAX77874 are still alive. The I2C is
active and registers can still be read from and written
to. Setting VIO = 0V turns off the top-level circuits and
results in the lowest possible shutdown current at VIN.
Additionally, when VIO = 0V, all registers are reset to their
default values.
See the Typical Operating Characteristics for a graph of
supply current in each operating mode, as well as a scope
photo of the faster startup.
Output Voltage Selection
The output voltage is I2C programmable from 0.25V to
1.3V in 5mV steps using the I2C_SD0_VOUT[7:0] bits in
the I2C_SD0_VOUT configuration register. The default
setting is trimmed to 0x82 = 0.900V for MAX77874B or
0x6E = 0.800V for MAX77874C. Consult the factory if
a different default setting is required. This setting is programmable with the quad phase core buck enabled or
disabled.
Dynamic Voltage Scaling (DVS)
The quad phase core buck includes DVS functionality. The
DVS output voltage is I2C programmable from 0.25V to
1.3V in 5mV steps using the VBUCKDVS[7:0] bits in the
VBUCKDVS configuration register. The default setting is
trimmed to 0x82 = 0.900V for the MAX77874B or 0x6E =
0.800V for the MAX77874C. Consult the factory if a different default setting is required. The setting is programmable
with the quad phase core buck enabled or disabled.
DVS Functionality
The purpose of the DVS function is to allow the buck
output voltage to quickly change from one output voltage
to another. An I2C write of a register can take several
microseconds to a few milliseconds to complete depending upon the I2C speed. The I2C_SD0_VOUT[7:0] register controls the buck output voltage when the DVS pin is
low. When the DVS pin is high, the buck output voltage is
controlled by the VBUCKDVS[7:0] register. See Figure 1.
When the I2C_SD0_VOUT register is set at a higher
voltage than the VBUCKDVS register and the DVS pin
transitions from low to high, then the buck output voltage falls to the voltage set by the VBUCKDVS register
at a slew rate specified by the BUCK0FSR[1:0] bits in
the BUCK0CNFG1 register (when the FSREN bit in the
BUCK0CNFG0 register is 1). When the DVS pin transitions back from high to low, then the buck output voltage
rises to the value specified by the I2C_SD0_VOUT register at a slew rate specified by the BUCK0RSR[1:0] bits in
the BUCK0CNFG1 register.
When changing the buck output voltage without utilizing
the DVS pin, i.e., I2C writing to I2C_SD0_VOUT register when DVS pin is low or I2C writing to VBUCKDVS
register when DVS pin is high, the output voltage falling
and rising slew rates are also controlled by the same bits
BUCK0FSR[1:0] and BUCK0RSR[1:0], respectively.
VOLTAGE SPE CIFIED BY
I2C_SD0_VOUT
REGISTE R
BUCK OUTPUT
VOLTAGE
FALL S LEW RATE
SPECIFIED BY
BUCK0FSR
VOLTAGE SPE CIFIED BY
VBUCKDVS REGISTER
RISE SLEW RATE
SPECIFIED BY
BUCK0RSR
DVS PIN
Figure 1. DVS Functionality
www.analog.com
Analog Devices │ 21
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
DVS and Current Limit
Any time the buck performs a DVS slew to change to
a higher output voltage, extra current is required to
charge the output capacitors. If the device is operating at maximum output current (16A), there may not be
enough headroom to safely perform a DVS operation.
Applications that expect a large load current coming and
need to change the output voltage to respond to it should
perform the DVS before the load step hits to prevent
possible overcurrent damage to the inductors. Internal
current limits in the buck protect the internal switches and
synchronous rectifiers from damage.
Reading Output Voltage Register
When reading I2C_SD0_VOUT[7:0] bits in the I2C_
SD0_VOUT configuration register (0x21), the response
from the MAX77874 depends on the state of the DVS
pin. When the DVS pin is low, the MAX77874 responds
with the value stored in the I2C_SD0_VOUT[7:0] bits.
When the DVS pin is high, however, the MAX77874
responds with the value stored in VBUCKDVS[7:0] bits in
the VBUCKDVS configuration register (0x24), and if that
value is greater than 0xD2, the response value is clamped
to 0xD2. In other words, reading I2C_SD0_VOUT[7:0]
bits returns the output voltage setting at the moment with
respect to the DVS pin state.
On the other hand, the DVS pin state does not affect
writing to I2C_SD0_VOUT[7:0] bits. The value written to
I2C_SD0_VOUT[7:0] bits takes effect immediately when
the DVS pin is low. When the DVS pin is high, the written
value takes effect after the DVS pin pulls low.
Interrupt Events
The device has interrupt capability to monitor the status
of the buck converter through the IRQ pin, which is an
active-low, open-drain output that is typically routed to
the processor to allow for quick notification of interrupt
events. A pullup resistor is required for this pin.
Power OK
The buck regulator contains an internal, active-low POK
signal that triggers an interrupt on the IRQ pin if the output
voltage becomes invalid. This signal must be unmasked
with POK_INTM to assert IRQ. Note that POK is not
blanked during DVS slewing or startup.
Thermal Warnings
Two junction temperature thermal warnings, Thermal
Alarm 1 and Thermal Alarm 2, trigger an interrupt if
the junction temperature rises above their thresholds
(TJ120 and TJ140, respectively). These alarms must be
www.analog.com
unmasked with TJ120C_INTM and TJ140C_INTM to
assert IRQ. Monitor these interrupt events to protect the
device from overheating under heavy load conditions.
Thermal Shutdown
If the junction temperature of the device exceeds +165°C,
the device shuts down to reduce the temperature. Once
the temperature falls approximately 15°C, the device tries
to enable with soft-start. This try-retry process continues
indefinitely.
Internal Compensation
Regulation loop compensation is on-chip and not user
adjustable. The compensation is uniquely trimmed for
inductance value and feedback type (remote or local).
Although a given compensation can still function when used
with the incorrect inductor or feedback type, the optimum
transient response and loop stability are achieved when the
trim option matches the inductor and feedback type.
Trim Options
The quad phase core buck regulator is factory trimmed
using one-time programmable (OTP) registers. Optional
versions can be trimmed for current limit, default output
voltage settings, inductance value, switching frequency,
and local versus remote feedback. See the Ordering
Information at the end of this data sheet. Consult the factory for optional versions.
Detailed Description—I2C
General Description
The MAX77874 features a revision 3.0 I2C-compatible,
2-wire serial interface consisting of a bidirectional serial
data line (SDA) and a serial clock line (SCL). The
MAX77874 acts as a slave-only device, and relies on the
master to generate a clock signal. SCL clock rates from
0Hz to 3.4MHz are supported.I2C is an open-drain bus,
and therefore, SDA and SCL require pullups.Figure 3
shows the functional diagram for the I2C-based communications controller. For additional information on I2C, refer
the I2C bus specification and user manual that is available
from NXP (UM10204).
Features
● I2C Revision 3 Compatible Serial Communications
Channel
● 0Hz to 100kHz (standard mode)
● 0Hz to 400kHz (fast mode)
● 0Hz to 1MHz (fast mode plus)
● 0Hz to 3.4MHz (high-speed mode)
● Does Not Utilize I2C Clock Stretching
Analog Devices │ 22
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
COMMUNICATIONS CONTROLLER
VIO
SCL
INTERFACE
DECODERS
SHIFT REGISTERS
BUFFERS
COM
SDA
GND
PERIPHERAL
0
PERIPHERAL
1
PERIPHERAL
2
PERIPHERAL
N-1
PERIPHERAL
N
Figure 2. I2C Simplified Block Diagram
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Figure 3. I2C System Configuration
I2C System Configuration
The I2C bus is a multimaster bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
A device on the I2C bus that sends data to the bus in
called a transmitter. A device that receives data from the
bus is called a receiver. The device that initiates a data
transfer and generates the SCL clock signals to control
the data transfer is a master. Any device that is being
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addressed by the master is considered a slave. The
MAX77874 I2C-compatible interface operates as a slave
on the I2C bus with transmit and receive capabilities.
I2C Interface Power
The MAX77874’s I2C interface derives its power from VIO.
VIO accepts voltages from 1.65V to 4.8V (VIO). Cycling
VIO resets the I2C registers. See External Components
and Figure 12 for bypass capacitor considerations.
Analog Devices │ 23
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
I2C Data Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SCL
is high are control signals. See the I2C Start and Stop
Conditions section. Each transmit sequence is framed by
a START (S) condition and a STOP (P) condition. Each
data packet is nine bits long: eight bits of data followed by
the acknowledge bit. Data is transferred with the MSB first.
I2C Start and Stop Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to low
transition on SDA with SCL high. A STOP condition is
a low-to-high transition on SDA, while SCL is high. See
Figure 4.
A START condition from the master signals the beginning of a transmission to the MAX77874. The master
terminates transmission by issuing a not-acknowledge followed by a STOP condition (see the I2C Acknowledge Bit
section for information on not-acknowledge). The STOP
condition frees the bus. To issue a series of commands to
the slave, the master can issue repeated start (Sr) commands instead of a STOP command to maintain control of
the bus. In general, a repeated start command is functionally equivalent to a regular start command.
S
When a STOP condition or incorrect address is detected,
the MAX77874 internally disconnects SCL from the serial
interface until the next START condition, minimizing digital
noise and feedthrough.
I2C Acknowledge Bit
Both the I2C bus master and the MAX77874 (slave)
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each nine bit data
packet. To generate an acknowledge (A), the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep it
low during the high period of the clock pulse. See Figure 5.
To generate a not-acknowledge (nA), the receiving device
allows SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high during
the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
The MAX77874 issues an ACK for all register addresses
in the possible address space even if the particular register does not exist.
Sr
P
SDA
tSU;STA
tSU;STO
SCL
tHD;STA
tHD;STA
Figure 4. I2C
Start and Stop Conditions
NOT ACKNOWLEDGE (NA)
S
ACKNOWLEDGE (A)
SDA
tSU;DAT
SCL
1
2
8
tHD;DAT
9
Figure 5. Acknowledge Bit
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Analog Devices │ 24
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
S
1
SDA
1
0
0
0
0
R/W
1
A
ACKNOWLEDGE
1
SCL
2
3
4
5
6
7
8
9
Figure 6. Example I2C Slave Address
Table 1. I2C Slave Address Options
ADDRESS
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
Main Address
0x61, 0b 110 0001
0xC2, 0b 1100 0010
0xC3, 0b 1100 0011
Other Addresses*
0x62, 0b 110 0010
0x63, 0b 110 0011
0x64, 0b 110 0100
0xC4, 0b 1100 0100
0xC6, 0b 1100 0110
0xC8, 0b 1100 1000
0xC5, 0b 1100 0101
0xC7, 0b 1100 0111
0xC9, 0b 1100 1001
0x69, 0b 110 1001
0x6A, 0b 110 1010
0x6B, 0b 110 1011
0x6C, 0b 110 1100
0xD2, 0b 1101 0010
0xD4, 0b 1101 0100
Test Mode**
0xD6, 0b 1101 0110
0xD8, 0b 1101 1000
*These addresses are acknowledged, but are for internal use only. Do not use any other I2C devices with
same bus.
0xD3, 0b 1101 0011
0xD5, 0b 1101 0101
0xD7, 0b 1101 0111
0xD9, 0b 1101 1001
these addresses on the
**When test mode is unlocked, additional addresses are acknowledged. Test mode details are confidential. If possible, leave the test
mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation with Maxim.
I2C Slave Address
The I2C controller implements 7-bit slave addressing. An
I2C bus master initiates communication with the slave by
issuing a START condition followed by the slave address.
See Figure 6. The OTP address is factory programmable
for one of two options. See Table 1. All slave addresses
not mentioned in the Table 1 are not acknowledged.
I2C Clock Stretching
In general, the clock signal generation for the I2C bus is the
responsibility of the master device. The I2C specification
allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX77874 does not use any form of clock
stretching to hold down the clock line.
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I2C General Call Address
The MAX77874 does not implement the I2C specifications general call address. If the MAX77874 sees the
general call address (0b0000_0000), it does not issue an
acknowledge.
I2C Device ID
The MAX77874 does not support the I2C device ID feature.
I2C Communication Speed
The MAX77874 is compatible with all 4 communication
speed ranges as defined by the Revision 3 I2C specification:
● 0Hz to 100kHz (standard mode)
● 0Hz to 400kHz (fast mode)
● 0Hz to 1MHz (fast mode)
● 0Hz to 3.4MHz (high-speed mode)
Analog Devices │ 25
MAX77874
16A High-Performance Quad-Phase Buck Regulator
for Multicore CPU and GPU Processors
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through this
range is the combination of the bus capacitance and pullup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds, the
pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing
section of the I2C revision 3.0 specification (UM10204)
for detailed guidance on the pullup resistor selection. In
general for bus capacitances of 200pF, a 100kHz bus
needs 5.6kΩ pullup resistors, a 400kHz bus needs about
a 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω
pullup resistors. Note that when the open-drain bus is low,
the pullup resistor is dissipating power, lower value pullup
resistors dissipate more power (V2/R).
At power-up and after each stop condition, the MAX77874
inputs filters are set for standard mode, fast mode, or fast
mode plus (i.e., 0Hz to 1MHz). To switch the input filters
for high-speed mode, use the high-speed master code
protocols that are described in the I2C Communication
Protocols section.
I2C Communication Protocols
The MAX77874 supports both writing and reading from
its registers.
Writing to a Single Register
Figure 7 shows the protocol for the I2C master device to
write one byte of data to the MAX77874. This protocol is
the same as the SMBus specification’s write byte protocol.
The write byte protocol is as follows:
1) The master sends a start command (S).
2) The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
3) The addressed slave asserts an acknowledge (A) by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data
8) The slave acknowledges or not acknowledges the data
byte. The next rising edge on SDA loads the data byte
into its target register and the data becomes active.
9) The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
Operating in high-speed mode requires some special
considerations. For a full list of considerations, see the
I2C Specification section. The major considerations with
respect to the MAX77874:
● The I2C bus master use current source pullups to
shorten the signal rise.
● The I2C slave must use a different set of input filters
on its SDA and SCL lines to accommodate for the
higher bus.
● The communication protocols need to utilize the highspeed master code.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
7
1 1
8
1
8
S
SLAVE ADDRESS
0 A
REGISTER POINTER
A
DATA
R/nW
SDA
B1
B0
A
1
1
A OR NA P OR SR*
NUMBER
OF BITS
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
ACKNOWLEDGE
SCL
7
8
9
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR
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