CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
19-3913; Rev 0; 10/05
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
The MAX8770/MAX8771/MAX8772 are 2/1-phase interleaved Quick-PWM™ step-down VID power-supply controllers for notebook CPUs. True out-of-phase operation
reduces input ripple current requirements and output voltage ripple while easing component selection and layout
difficulties. The Quick-PWM control provides instantaneous response to fast load current steps. Active voltage
positioning reduces power dissipation and bulk output
capacitance requirements and allows ideal positioning
compensation for tantalum, polymer, or ceramic bulk output capacitors.
The MAX8770/MAX8771/MAX8772 are intended for two
different notebook CPU core applications: either bucking
down the battery directly to create the core voltage, or
else bucking down the +5V system supply. The singlestage conversion method allows this device to directly
step down high-voltage batteries for the highest possible
efficiency. Alternatively, 2-stage conversion (stepping
down the +5V system supply instead of the battery) at
higher switching frequency provides the minimum possible physical size.
A slew-rate controller allows controlled transitions
between VID codes, controlled soft-start and shutdown,
and controlled exit from suspend. A thermistor-based
temperature sensor provides a programmable thermalfault output (VRHOT). A power-monitor output (POUT)
provides an analog voltage output proportional to the
power consumed by the CPU. The MAX8770/MAX8771/
MAX8772 include output undervoltage protection (UVP)
and thermal protection, and the MAX8770/MAX8771 also
include overvoltage protection (OVP). When any of these
protection features detect a fault, the controller shuts
down. A voltage-regulator power-OK (PWRGD) output
indicates the output is in regulation. A clock enable
(CLKEN) output provides proper system startup sequencing. Additionally, the MAX8771 has a phase-good
(PHASEGD) output, and the MAX8770/MAX8772 includes
true differential current sense.
The MAX8770/MAX8771/MAX8772 implement the Intel
IMVP-6+ code set and the required IMVP-6+ control signals. The MAX8770/MAX8771/MAX8772 are available in a
40-pin TQFN package.
Features
♦ Single/Dual-Phase, Quick-PWM Controller
♦ ±0.4% VOUT Accuracy Over Line, Load, and
Temperature
♦ 7-Bit On-Board DAC: 0 to +1.5000V Output Adjust
Range
♦ Dynamic Phase Selection Optimizes Active/Sleep
Efficiency
♦ Transient Phase Overlap Reduces Output
Capacitance
♦ Integrated Boost Switches
♦ Active Voltage Positioning with Adjustable Gain
♦ Programmable 200kHz to 600kHz Switching
Frequency
♦ Accurate Current Balance and Current Limit
♦ Adjustable Slew-Rate Control
♦ Power-Good (PWRGD), Clock Enable (CLKEN),
Power Monitor (POUT) and Thermal Fault
(VRHOT) Outputs
♦ Phase Fault (PHASEGD) Output (MAX8771)
♦ Drives Large Synchronous Rectifier MOSFETs
♦ 4V to 26V Battery-Input-Voltage Range
♦ Output OV Protection (MAX8770/MAX8771)
♦ UV and Thermal-Fault Protection
♦ Power Sequencing and Timing
♦ Soft-Startup and Soft-Shutdown
Ordering Information
PART
TEMP
PIN-PACKAGE
MAX8770GTL+ -40°C to +105°C 40 Thin QFN 6mm x 6mm
MAX8771GTL+ -40°C to +105°C 40 Thin QFN 6mm x 6mm
MAX8772GTL+ -40°C to +105°C 40 Thin QFN 6mm x 6mm
+Denotes lead-free package.
Applications
IMVP-6+ Core Supply
Multiphase CPU Core Supply
Voltage-Positioned, Step-Down Converters
Notebook/Desktop Computers
Blade Servers
Pin Configuration appears at end of data sheet.
Intel is a registered trademark of Intel, Corp.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8770/MAX8771/MAX8772
General Description
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
ABSOLUTE MAXIMUM RATINGS
BST_ to GND ..........................................................-0.3V to +36V
LX_ to BST_ ..............................................................-6V to +0.3V
BST_ to VDD...........................................................-0.3V to +30V
DH_ to LX_ ..................................................-0.3V to VBST_ +0.3V
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation
40-Pin 6mm x 6mm Thin QFN
(derate 23.2mW/°C above +70°C) .............................2051mW
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
VCC, VDD to GND .....................................................-0.3V to +6V
D0–D6, CSP_ to GND...............................................-0.3V to +6V
CSN12 (MAX8771) to GND ......................................-0.3V to +6V
CSN_ (MAX8770/MAX8772) to GND........................-0.3V to +6V
PHASEGD (MAX8771) to GND.................................-0.3V to +6V
THRM, VRHOT, CLKEN to GND...............................-0.3V to +6V
TIME, PWRGD, POUT to GND ......................-0.3V to VCC + 0.3V
REF, FB, CCV, CCI to GND ..........................-0.3V to VCC + 0.3V
SHDN to GND (Note 1)...........................................-0.3V to +14V
TON to GND ...........................................................-0.3V to +30V
DPRSLPVR, DPRSTP, PSI to GND ...........................-0.3V to +6V
GNDS, PGND_ to GND .........................................-0.3V to +0.3V
DL_ to PGND_...............................................-0.3V to VDD + 0.3V
Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables
fault protection and disables overlapping operation.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_
= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Input Voltage Range
DC Output-Voltage Accuracy
VCC, VDD
VOUT
Includes loadregulation error
(Note 2)
4.5
5.5
V
DAC codes from
0.8375V to 1.500V
-0.4
+0.4
%
DAC codes from
0.500V to 0.825V
-4
+4
DAC codes below
0.4875V
-10
+10
mV
Boot Voltage
VBOOT
1.19
GNDS Input Range
VGNDS
-200
GNDS Gain
AGNDS
GNDS Input Bias Current
IGNDS
∆VOUT/∆VGNDS, -200mV ≤ VGNDS ≤ +200mV
FB Input Bias Current
IFB
CSP_ = CSN_ for both enabled phases
On-Time Accuracy (Note 3)
tON
VIN = 12V
VFB = VCCI = 1.2V
1.20
1.21
V
+200
mV
0.95
1.00
1.05
V/V
-25
-15
+2
µA
+2
µA
-2
RTON = 96.75kΩ
142
167
192
RTON = 200kΩ
300
333
366
RTON = 303.25kΩ
425
500
575
ns
TON Shutdown Input Current
SHDN = 0, VIN = 26V, VCC = VDD = 0 or 5V
0.01
0.1
µA
Minimum FB and CCI Voltages
for Pseudo-Fixed-Frequency
Operation
Switching frequency is reduced if FB and/or
CCI are less than this value
0.2
0.25
V
(Note 3)
300
375
ns
Minimum Off-Time
2
tOFF(MIN)
_______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_
= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
TIME Slew-Rate Accuracy
CONDITIONS
MIN
TYP
MAX
RTIME = 71.5kΩ (12.5mV/µs nominal)
-10
+10
RTIME = 35.7kΩ (25mV/µs nominal) to 178kΩ
(5mV/µs nominal)
-15
+15
DPRSTP = high, DPRSLPVR = high,
RTIME = 35.7kΩ to 178kΩ, SR = 6.25mV/µs
nominal to 1.25mV/µs nominal
-20
+20
Startup and shutdown, RTIME = 35.7kΩ
(3.125mV/µs nominal) to 178kΩ
(0.625mV/µs nominal)
-20
+20
UNITS
%
BIAS AND REFERENCE
Quiescent Supply Current (VCC)
ICC
Measured at VCC, FB forced above the
regulation point, DPRSLPVR = VCC
5
10
mA
Quiescent Supply Current (VDD)
IDD
Measured at VDD, FB forced above the
regulation point, DPRSLPVR = VCC
0.01
1
µA
Shutdown Supply Current (VCC)
ICC(SHDN)
Measured at VCC, SHDN = GND
0.01
1
µA
Shutdown Supply Current (VDD)
IDD(SHDN)
Measured at VDD, SHDN = GND
0.01
1
µA
2.000
2.014
V
Reference Voltage
VREF
Reference Load Regulation
∆VREF
VCC = 4.5V to 5.5V, IREF = 0
IREF = 0 to 500µA
1.986
-2
IREF = -100µA to 0
-0.2
0.21
6.2
250
300
350
1.75
1.80
1.85
mV
FAULT PROTECTION
Output Overvoltage Protection
Threshold
(MAX8770/MAX8771 Only)
Measured at FB with respect to unloaded
output voltage; rising edge;
PWM mode or skip mode after output reaches
the regulation voltage
VOVP
Measured at FB;
rising edge
Skip mode and output
have not reached the
regulation voltage
Minimum OVP threshold
Output OvervoltagePropagation Delay
(MAX8770/MAX8771 Only)
tOVP
FB forced 25mV above trip threshold
Output Undervoltage
Protection Threshold
VUVP
Measured at FB with respect to unloaded
output voltage
Output Undervoltage
Propagation Delay
tUVP
FB forced 25mV below trip threshold
CLKEN Startup Delay
(Boot Time Period)
tBOOT
Measured from the time when FB reaches the
boot target voltage based on the slew rate set
by RTIME
mV
V
0.8
10
-450
-400
µs
-350
10
20
60
mV
µs
100
µs
_______________________________________________________________________________________
3
MAX8770/MAX8771/MAX8772
ELECTRICAL CHARACTERISTICS (continued)
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_
= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.)
PARAMETER
PWRGD, PHASEGD Startup
Delay
SYMBOL
tPWRGD
CLKEN, PWRGD Threshold
CLKEN, PWRGD, PHASEGD
Delay
CLKEN, PWRGD, PHASEGD
Transition Blanking Time
PHASEGD Transition Blanking
Time
CONDITIONS
Measured at startup from the time when
CLKEN goes low
Measured at FB with
respect to unloaded
output voltage
Lower threshold, falling
edge (undervoltage)
15mV hysteresis (typ)
Upper threshold, rising
edge (overvoltage)
MIN
TYP
MAX
UNITS
3
5
8
ms
-350
-300
-250
mV
+150
+200
FB forced 25mV outside the PWRGD trip
thresholds
10
µs
tBLANK
Measured from the time when FB reaches the
target voltage based on the slew rate set by
RTIME
20
µs
tPHASEGD
Number of DH2 pulses from when phase 2 is
enabled
32
Cycles
PHASEGD Window
Comparator Thresholds
V(CCI, FB),
0.4V ≤ V(FB) ≤ 1.5V
Lower threshold,
0.6VFB nominal
-20
+20
15mV hysteresis (typ)
Upper threshold,
1.4VFB nominal
-20
+20
CLKEN, PWRGD, PHASEGD
Output Low Voltage
ISINK = 3mA
CLKEN, PWRGD, PHASEGD
Leakage Current
High state, CLKEN, PWRGD, PHASEGD forced
to 5V
VRHOT Trip Threshold
Measured at THRM, with respect to VCC; falling
edge, 115mV hysteresis (typ)
mV
29.5
30
VRHOT Delay
tVRHOT
THRM forced 25mV below the VRHOT trip
threshold; falling edge
10
VRHOT Output On-Resistance
RVRHOT
Low state
3.5
VRHOT Leakage Current
High state. VRHOT forced to 5V
THRM Input Leakage
VCC Undervoltage Lockout
Threshold
-100
VUVLO(VCC)
VCC Power-On Reset
Threshold
Thermal Shutdown Threshold
4
+250
TSHDN
Rising edge, 50mV hysteresis, DL_ pulled low
below this level
4.1
4.25
0.4
V
1
µA
30.5
%
µs
11
Ω
1
µA
+100
nA
4.45
V
Falling edge, typical hysteresis = 1.1V, faults
cleared and DL_ forced high when VCC falls
below this level
1.8
V
Hysteresis = 15°C
160
°C
_______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_
= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
+1.0
mV
610
µS
+1.0
mV
DROOP AND BALANCE
DC Droop Amplifier Offset
DC Droop Amplifier
Transconductance
-1.0
Gm(FB)
Current-Balance
Preamplifier Offset
Current-Balance Amplifier
Transconductance
Gm(CCI)
∆IFB/(Σ∆VCS),
VFB = VCSN_ = 1.2V,
VCSP_ - VCSN_ = 0 to +60mV
590
[V(CSP1, CSN_) - V(CSP2, CSN_)] at ICCI = 0
-1.0
∆ ICCI/∆ [V(CSP1, CSN_), V(CSP2, CSN_)]
CCI = FB = CSN_ = 0.45V to 1.5V, and
V(CSP_, CSN_) = -10mV to +10mV
600
200
µS
CURRENT LIMIT
Valley Current-Limit Threshold
(Positive)
VLIMIT
Valley Current-Limit Threshold
(Negative)
Zero Crossing Threshold
VZX
Current-Sense Input Current
CSP_ - CSN_
19.5
22.5
25.5
mV
CSP_, CSN_
-35
-30
-25
mV
PGND1 - LX1, DPRSLPVR = high (skip mode)
2.5
mV
CSP_
-0.2
+0.2
CSN_
-0.2
+0.2
CSN12 (MAX8771)
-0.4
+0.4
Common-Sense Common-Mode
Input Range
CSP_ -CSN_
Phase 2 Disable Threshold
Gate Drivers
CSP2
0
µA
2
V
3
VCC - 1 VCC - 0.4
GATE DRIVERS
DH_ Gate Driver
On-Resistance
RON(DH_)
DL_ Gate Driver
On-Resistance
RON(DL_)
DH_ Gate Driver Source/Sink
Current
DL_ Gate Driver Source Current
DL_ Gate Driver Sink Current
Driver Propagation Delay
DL_ Transition Time
DH_ Transition Time
IDH
High state (pullup)
0.9
2.5
Low state (pulldown)
0.7
2.5
High state (pullup)
0.7
2.0
Low state (pulldown)
0.25
0.5
DH_ forced to 2.5V, BST_ - LX_ forced to 5V
2.2
BST_ -LX_ forced
to 5V
IDL(SOURCE) DL_ forced to 2.5V
IDL(SINK)
DL_ forced to 2.5V
Ω
Ω
A
2.7
A
8
A
DH_ low to DL_ high
18
25
DL_ low to DH_ high
9
20
DL_ falling, CDL_ = 3nF
20
DL_ rising, CDL_ = 3nF
20
DH_ falling, CDH_ = 3nF
20
DH_ rising, CDH_ = 3nF
20
ns
ns
ns
_______________________________________________________________________________________
5
MAX8770/MAX8771/MAX8772
ELECTRICAL CHARACTERISTICS (continued)
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_
= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
Internal Boost Charging Switch
On-Resistance
CONDITIONS
MIN
VDD to BST_
TYP
MAX
UNITS
10
20
Ω
POWER MONITOR
Power-Monitor Output Voltage
for Typical HFM Conditions
VFB - VGNDS = 1.200V, Σ∆VCS = 30mV
2.08
2.16
2.24
V
Power-Monitor Gain Referred
to Feedback Voltage
Σ∆VCS = 30mV
1.72
1.80
1.88
V/V
Power-Monitor Gain Referred
to ΣV (CSP_, CSN)
VFB - VGNDS = 1.200V, TA = +25°C to +85°C
70.5
72
73.5
V/V
Sourcing: IPOUT = 0 to 500µA
Power-Monitor Load
Regulation
-6
Sinking: IPOUT = 0 to 100µA
µV/µA
50
mV
LOGIC AND I/O
Logic Input High Voltage
VIH
SHDN No-Fault Level
SHDN, DPRSLPVR, rising edge,
hysteresis = 200mV
1.2
To enable no-fault mode
11
Low-Voltage Logic Input High
Voltage
VIHLV
D0–D6, PSI, DRPSTP
Low-Voltage Logic Input Low
Voltage
VILLV
D0–D6, PSI, DRPSTP
Logic Input Current
6
SHDN, PSI, DPRSLPVR, D0–D6 = 0 to 5V
1.7
2.3
V
13
V
0.67
-1
_______________________________________________________________________________________
V
0.33
V
+1
µA
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_
= 1.200V, D0–D6 set for 1.20V (D0-D6 = 0001100). TA = -40°C to +105°C, unless otherwise specified. Typical values are at TA =
+25°C.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Input Voltage Range
DC Output Voltage Accuracy
VCC, VDD
VOUT
Includes loadregulation error
(Note 2)
4.5
5.5
V
DAC codes from
0.8375V to 1.500V
-0.6
+0.6
%
DAC codes from
0.500V to 0.825V
-6
+6
DAC codes below
0.4875V
-15
+15
mV
Boot Voltage
VBOOT
1.182
1.218
V
GNDS Input Range
VGNDS
-200
+200
mV
GNDS Gain
AGNDS
0.95
1.05
V/V
RTON = 96.75kΩ
142
192
RTON = 200kΩ
300
366
RTON = 303.25kΩ
425
575
On-Time Accuracy (Note 3)
tON
Minimum FB and CCI Voltages
for Pseudo-Fixed-Frequency
Operation
Minimum Off-Time
tOFF(MIN)
TIME Slew-Rate Accuracy
∆VOUT/∆VGNDS, -200mV ≤ VGNDS ≤
+200mV
VIN = 12V
VFB = VCCI = 1.2V
ns
Switching frequency is reduced if FB and/or
CCI are less than this value
0.25
V
(Note 3)
375
ns
RTIME = 71.5kΩ (12.5mV/µs nominal)
-10
+10
RTIME = 35.7kΩ (25mV/µs nominal) to
178kΩ (5mV/µs nominal)
-15
+15
DPRSTP = high, DPRSLPVR = high, RTIME
= 35.7kΩ to 178kΩ, SR = 6.25mV/µs
nominal to 1.25mV/µs nominal
-20
+20
Startup and shutdown,
RTIME = 35.7kΩ (3.125mV/µs nominal) to
178kΩ (0.625mV/µs nominal)
-20
+20
%
BIAS AND REFERENCE
Quiescent Supply Current (VCC)
ICC
Measured at VCC, FB forced above the
regulation point, DPRSLPVR = VCC
10
mA
Quiescent Supply Current (VDD)
IDD
Measured at VDD, FB forced above the
regulation point, DPRSLPVR = VCC
1
µA
Shutdown Supply Current (VCC)
ICC(SHDN)
Measured at VCC, SHDN = GND
1
µA
Shutdown Supply Current (VDD)
IDD(SHDN)
Measured at VDD, SHDN = GND
1
µA
2.02
V
Reference Voltage
VREF
Reference Load Regulation
∆VREF
VCC = 4.5V to 5.5V, IREF = 0
IREF = 0 to 500µA
IREF = -100µA to 0
1.98
-2
6.2
mV
_______________________________________________________________________________________
7
MAX8770/MAX8771/MAX8772
ELECTRICAL CHARACTERISTICS
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_ =
1.200V, D0–D6 set for 1.20V (D0-D6 = 0001100). TA = -40°C to +105°C, unless otherwise specified. Typical values are at TA = +25°C.)
(Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
250
350
mV
1.75
1.85
V
FAULT PROTECTION
Output Overvoltage Protection
Threshold
(MAX8770/MAX8771 Only)
VOVP
Measured at FB with respect to unloaded
output voltage, rising edge,
PWM mode, or skip mode after output
reaches the regulation voltage
Skip mode and
Measured at FB,
output have not
rising edge
reached the
regulation voltage
Output Undervoltage Protection
Threshold
VUVP
Measured at FB with respect to unloaded
output voltage
-450
-350
mV
CLKEN Startup Delay (Boot Time
Period)
tBOOT
Measured from the time when FB reaches
the boot target voltage based on the slew
rate set by RTIME
20
100
µs
Measured at startup from the time when
CLKEN goes low
3
8
ms
-350
-250
PWRGD, PHASEGD Startup
Delay
tPWRGD
CLKEN, PWRGD Threshold
PHASEGD Window Comparator
Thresholds
CLKEN, PWRGD, PHASEGD
Output Low Voltage
VRHOT Trip Threshold
VRHOT Output On-Resistance
VCC Undervoltage Lockout
Threshold
Measured at FB
with respect to
unloaded output
voltage
Lower threshold,
falling edge
(undervoltage)
15mV hysteresis
(typ)
Upper threshold,
rising edge
(overvoltage)
+150
+250
V(CCI,FB),
0.4V ≤ V(FB) ≤ 1.5V
Lower threshold,
0.6VFB nominal
-20
+20
15mV hysteresis
(typ)
Upper threshold,
1.4VFB nominal
-20
mV
mV
ISINK = 3mA
VHOT
RVRHOT
VUVLO(VCC)
+20
0.4
V
30.5
%
11
Ω
4.1
4.45
V
-1.5
+1.5
mV
∆IFB/(Σ∆VCS),
VFB = VCSN_ = 1.2V,
VCSP_ - VCSN_ = 0 to +60mV
580
620
µs
[V(CSPI, CSN_) - V(CPS2, CSN_)]
at ICCI = 0
-1.5
+1.5
mV
Measured at THRM, with respect to VCC,
falling edge, 115mV hysteresis (typ)
29.5
Low state
Rising edge, 50mV hysteresis, DL_ pulled
low below this level
DROOP AND BALANCE
DC Droop Amplifier Offset
DC Droop Amplifier
Transconductance
Current-Balance
Preamplifier Offsets
8
Gm(FB)
_______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_ =
1.200V, D0–D6 set for 1.20V (D0-D6 = 0001100). TA = -40°C to +105°C, unless otherwise specified. Typical values are at TA = +25°C.)
(Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT LIMIT
Valley Current-Limit Threshold
(Positive)
CSP_ - CSN_
18.5
26.5
mV
Valley Current-Limit Threshold
(Negative)
CSP_ - CSN_
-36
-24
mV
Current-Sense Common-Mode
Input Range
CSP_, CSN_
0
2
V
Phase 2 Disable Threshold
CSP2
3
VLIMIT
VCC - 0.4
V
GATE DRIVERS
DH_ Gate Driver On-Resistance
RON(DH_)
DL_ Gate Driver On-Resistance
RON(DL_)
Driver Propagation Delay
Internal Boost Charging Switch
On-Resistance
BST_ – LX_ forced
to 5V
High state (pullup)
2.5
Low state (pulldown)
2.5
High state (pullup)
2.0
Low state (pulldown)
0.5
DH_ Low to DL_ High
15
DL_ Low to DH_ High
9
VDD to BST_
Ω
Ω
ns
20
Ω
POWER MONITOR
Power-Monitor Output Voltage for
Typical HFM Conditions
VFB - VGNDS = 1.200V, Σ∆VCS = 30mV
2.04
2.28
V
Power-Monitor Gain Referred to
Feedback Voltage
Σ∆VCS = 30mV
1.70
1.90
V/V
Power-Monitor Gain Referred to
ΣV(CSP_,CSN)
VFB - VGNDS = 1.200V
70
74
V/V
Power-Monitor Load Regulation
Sourcing: IPOUT = 0 to 500µA
-6
SHDN, DPRSLPVR, rising edge,
hysteresis = 200mV
1.2
0.67
µV/µA
LOGIC AND I/O
Logic-Input High Voltage
VIH
Low-Voltage Logic-Input High
VIHLV
D0–D6, PSI, DRPSTP
Low-Voltage Logic-Input Low
VILLV
D0–D6, PSI, DRPSTP
2.3
V
0.33
V
V
Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. The output voltage has a DC regulation higher
than the trip level by 50% of the output ripple. When pulse skipping, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ and DH_ pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual incircuit times may be different due to MOSFET switching speeds.
Note 4: Specifications to TA = -40°C and +105°C are guaranteed by design and are not production tested.
_______________________________________________________________________________________
9
MAX8770/MAX8771/MAX8772
ELECTRICAL CHARACTERISTICS (continued)
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
Typical Operating Characteristics
(Circuit of Figure 1. VIN = 12V, VCC = VDD, SHDN = PSI = 5V, DPRSLPVR = GND, D0–D6 set for 1.1500V, TA = 25°C, unless otherwise specified.)
12V
90
1.2
80
20V
70
SKIP MODE
0.96
OUTPUT VOLTAGE (V)
7V
1.3
0.98
MAX8770 toc02
MAX8770 toc01
100
EFFICIENCY (%)
OUTPUT VOLTAGE (V)
1.4
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(LFM) = 0.9500V)
EFFICIENCY vs. LOAD CURRENT
(VOUT(HFM) = 1.2875V)
MAX8770 toc03
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(HFM) = 1.2875V)
0.94
PWM MODE
0.92
60
0.90
50
0.88
PSI = GND
1.1
40
50
0.1
0.68
MAX8770 toc04
12V
90
0
100
OUTPUT VOLTAGE
vs. LOAD CURRENT (VOUT(C4) = 0.6500V)
EFFICIENCY vs. LOAD CURRENT
(VOUT(LFM) = 0.9500V)
100
1
10
LOAD CURRENT (A)
0.66
OUTPUT VOLTAGE (V)
7V
80
20V
70
PSI - GND
60
4
8
12
LOAD CURRENT (A)
100
90
0.64
0.62
12V
7V
80
70
0.60
60
0.58
50
20V
1
10
LOAD CURRENT (A)
100
DPRSLPVR = VCC
0
4
8
12
LOAD CURRENT (A)
16
20
125
SUPPLY CURRENT (mA)
300
VOUT(HFM) = 1.2875V
200
100
100
IIN
100
75
50
ICC + IDD
25
DPRSLPVR = GND
DPRSLPVR = VCC
0
0
0
10
150
MAX8770 toc07
SWITCHING FREQUENCY (kHz)
VOUT(LFM) = 0.9500V
1
10
LOAD CURRENT (A)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (VOUT(HFM) = 1.2875V)
SWITCHING FREQUENCY
vs. LOAD CURRENT
400
0.1
MAX8770 toc08
0.1
10
20
30
LOAD CURRENT (A)
40
20
EFFICIENCY vs. LOAD CURRENT
(VOUT(C4) = 0.6500V)
DPRSLPVR = GND
DPRSLPVR = VCC
50
16
MAX8770 toc06
20
30
LOAD CURRENT (A)
EFFICIENCY (%)
10
MAX8770 toc05
0
EFFICIENCY (%)
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
50
0
5
10
15
INPUT VOLTAGE (V)
______________________________________________________________________________________
20
25
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
0.1
60
40
MAX8770 toc11
80
60
40
20
20
IIN
SAMPLE SIZE = 200
1.2000V
0.8125V
SAMPLE PERCENTAGE (%)
1
80
100
MAX8770 toc10
SAMPLE SIZE = 200
SAMPLE PERCENTAGE (%)
ICC + IDD
DPRSLPVR = VCC
0.01
0
5
10
15
INPUT VOLTAGE (V)
20
0
1.990
25
0
2.000
-3
2.010
-2
-1
1
2
3
OUTPUT OFFSET VOLTAGE (mV)
REFERENCE VOLTAGE (V)
Gm(FB) TRANSCONDUCTANCE
DISTRIBUTION
INDUCTOR CURRENT DIFFERENCE
vs. LOAD CURRENT
SAMPLE SIZE = 200
IL(CS) - IL(CM) (A)
80
60
40
MAX8770 toc13
0.3
MAX8770 toc12
100
SAMPLE PERCENTAGE (%)
SUPPLY CURRENT (mA)
100
MAX8770 toc09
10
0.2
0.1
20
RSENSE = 1mΩ
0
0
595
597
599
601
603
605
0
TRANSCONDUCTANCE (µS)
5
10
15
INPUT VOLTAGE (V)
20
25
SOFT-START (UP TO CLKEN)
SOFT-START (UP TO PWRGD)
MAX8770 toc15
MAX8770 toc14
A
0
0
B
0
C
0
D
A
0
0
B
C
0
D
E
0
0
E
F
0
0
F
G
0
RLOAD = 65mΩ
0
RLOAD = 65mΩ
200µs/div
1ms/div
A. SHDN, 5V/div
B. CLKEN, 10V/div
C. PWRGD, 10V/div
D. PHASEGD, 10V/div
E. VOUT, 1V/div
F. ILXI, 10A/div
G. ILX2, 10V/div
A. SHDN, 5V/div
B. CLKEN, 10V/div
C. LX1, 10V/div
D. VOUT, 1V/div
E. ILXI, 10A/div
F. ILX2, 10V/div
______________________________________________________________________________________
11
MAX8770/MAX8771/MAX8772
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD, SHDN = PSI = 5V, DPRSLPVR = GND, D0–D6 set for 1.1500V, TA = 25°C, unless otherwise specified.)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE AT SKIP MODE
OUTPUT OFFSET VOLTAGE DISTRIBUTION
REFERENCE VOLTAGE DISTRIBUTION
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD, SHDN = PSI = 5V, DPRSLPVR = GND, D0–D6 set for 1.1500V, TA = 25°C, unless otherwise specified.)
HFM LOAD TRANSIENT
(VOUT(HFM) = 1.2875V
SHUTDOWN WAVEFORMS
MAX8770 toc16
LFM LOAD TRANSIENT
(VOUT(LFM) = 0.9500V
MAX8770 toc17
MAX8770 toc18
A
0
B
0
C
A
0
1.28V
A
B
0
0
1V
D
1.22V
0.94V
20A
0.92V
E
0
0
0
RLOAD = 65mΩ
C
F
0
G
0
200µs/div
A. SHDN, 5V/div
B. CLKEN, 10V/div
C. DL1, 10V/div
D. PWRGD, 10V/div
10A
PSI = 0
40µs/div
C. ILXI, 10A/div
D. ILX2,10A/div
A. IOUT = 5A TO 36A, 10A/div
B. VOUT, 50mV/div
ENTERING DEEPER SLEEP
EXITING TO LFM
A. IOUT = 5A TO 15A, 10A/div
B. VOUT, 50mV/div
ENTERING DEEPER SLEEP
EXITING TO NEAREST VID
MAX8770 toc19
MAX8770 toc21
A
0
B
B
0
1.28V
C
C. ILXI, 10A/div
D. ILX2,10A/div
ENTERING DEEPER SLEEP
EXITING TO LFM
MAX8770 toc20
A
0
1.28V
C
0
D
40µs/div
E. VOUT, 1V/div
F. ILXI, 10A/div
G. ILX2, 10V/div
0
B
A
0
B
0
1.28V
C
C
0
D
0
D
0
D
0
E
0
E
0
E
100µs/div
A. DPRSTP, 5V/div
B. DPRSLPVR, 5V/div
C. VOUT, 500mV/div
IOUT = 2A
12
D. ILXI, 10A/div
E. ILX2, 10A/div
100µs/div
A. DPRSTP, 5V/div
B. DPRSLPVR, 5V/div
C. VOUT, 500mV/div
IOUT = 2A
D. ILXI, 10A/div
E. ILX2, 10A/div
100µs/div
A. DPRSTP, 5V/div
B. DPRSLPVR, 5V/div
C. VOUT, 500mV/div
IOUT = 2A
______________________________________________________________________________________
D. ILXI, 10A/div
E. ILX2, 10A/div
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
D0 DYNAMIC VID CODE CHANGE
PSI + 1-LSB TRANSITION
D3 DYNAMIC VID CODE CHANGE
MAX8770 toc23
MAX8770 toc22
A
0
MAX8770 toc24
A
0
0
A
B
0
0.93V
B
0.93V
C
D
C
0
0
E
0
B
0.93V
C
0
D
0
D
0
20µs/div
40µs/div
D. ILXI, 10A/div
E. ILX2, 10A/div
RSENSE = 1mΩ
VOUT = 1.2875V
POWER MONITOR (V) .
POWER MONITOR (V) .
0.8
0.6
0.4
C. ILXI, 10A/div
D. ILX2, 10A/div
POWER MONITOR VID TRANSITION RESPONSE
MAX8770 TOC28
4
MAX8770 toc25
RSENSE = 1mΩ
IOUT = 10A
A. D3, 5V/div
B. VOUT, 200mV/div
IOUT = 10A
POWER MONITOR vs. LOAD CURRENT
POWER MONITOR vs. OUTPUT VOLTAGE
1.0
20µs/div
C. ILXI, 10A/div
D. ILX2, 10A/div
MAX8770 toc26
A. PSI, 5V/div
B. D0, 5V/div
C. VOUT, 20mV/div
IOUT = 10A
A. D0, 5V/div
B. VOUT, 20mV/div
IOUT = 10A
3
0
A
B
1.185
C
0.72V
2
D
0
E
1
0
0.2
F
0
0
0
0
0.3
0.6
0.9
1.2
OUTPUT VOLTAGE (V)
1.5
0
10
20
30
LOAD CURRENT (A)
40
40µs/div
A. D3, 5V/div
B. VOUT, 200mV/div
C. POUT WITH RC FILTER
(10kΩ, 0.1µF), 200mV/div
D. POUT, 2V/div
E. ILX1, 10A/div
F. ILX2, 10A/div
IOUT = 10A
______________________________________________________________________________________
13
MAX8770/MAX8771/MAX8772
Typical Operating Characteristics (continued)
(Circuit of Figure 1. VIN = 12V, VCC = VDD, SHDN = PSI = 5V, DPRSLPVR = GND, D0–D6 set for 1.1500V, TA = 25°C, unless otherwise specified.)
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
MAX8770/MAX8771/MAX8772
Pin Description
PIN
1
2
NAME
FUNCTION
CLKEN
Clock-Enable Logic Output. This inverted logic output indicates when the output voltage sensed at FB is in
regulation. CLKEN is forced low during VID transitions. Except during startup, CLKEN is the inverse of
PWRGD. See the Startup Timing Diagram (Figure 9). When in pulse-skipping mode (DPRSLPVR high), the
upper CLKEN threshold is disabled.
PWRGD
Open-Drain, Power-Good Output. After output-voltage transitions, except during power-up and powerdown, if FB is in regulation then PWRGD is high impedance. During startup, PWRGD is held low and
continues to be low while the part is in boot mode and until 5ms (typ) after CLKEN goes low.
PWRGD is forced low in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is
active (output-voltage transitions).
When in pulse-skipping mode (DPRSLPVR high), the upper PWRGD threshold comparator is blanked.
A pullup resistor on PWRGD causes additional finite shutdown current.
Logic Input to Indicate Power Usage. PSI and DPRSLPVR together determine the operating mode as
shown in the truth table below. Blank the PWRGD upper threshold when the part is in skip mode. The part
is forced into full-phase PWM mode during startup, while in boot mode, during the transition from
boot mode to VID mode and during shutdown:
3
PSI
DPRSLPVR
1
1
0
0
PSI
0
1
0
1
Mode
Very low current (1-phase skip)
Low current (approximately 3A) (1-phase skip)
Intermediate power potential (1-phase PWM)
Max power potential (2- or 1-phase PWM as configured at CSP2)
4
POUT
Power-Monitor Output: VPOUT = KPWR x V(CSNpm, GNDS) x ΣV(CSP_, CSN_), where KPWR is the power
monitor scale factor:
CSNpm = CSN12 for MAX8771.
CSNpm = CSN2 for MAX8770/MAX8772.
POUT is zero in shutdown.
5
VRHOT
Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below
1.5V (30% of VCC). VRHOT is high impedance in shutdown.
6
THRM
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC and
GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of VCC) at the
desired high temperature.
Slew-Rate Adjustment Pin. Connect a resistor RTIME from TIME to GND to set the internal slew rate:
Slew rate = (12.5mV/µs) x (71.5kΩ_/ RTIME)
7
TIME
where RTIME is between 35.7kΩ and 178kΩ.
This slew rate applies to transitions into and out of the low-power pulse-skipping modes (and to the
transition from boot mode to VID mode. The slew rate for startup and shutdown is 1/8 this value. If the VID
DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are
clocked, up to a maximum slew rate equal to the one set by RTIME as defined above.
Switching-Frequency Setting Input. An external resistor between the input power source and TON sets the
switching period (TSW = 1/fSW) per phase according to the following equation:
8
TON
TSW = CTON (RTON + 6.5kΩ)
where CTON = 16.26pF.
TON is high impedance in shutdown.
9
14
CCV
Integrator Capacitor Connection. Connect a 470pF x (2/ηTOTAL) x 300kHz/fSW capacitor from CCV to GND
to set the integration time constant. The integrator is internally disabled when the part is in skip mode and
the output is above regulation.
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
PIN
NAME
FUNCTION
10
CCI
Current-Balance Compensation. Connect a 470pF capacitor between CCI and the positive side of the
feedback remote sense (or between CCI and GND). CCI is internally forced low in shutdown.
11
REF
2.0V Reference Output. Bypass to GND with a 1µF maximum low-ESR (ceramic) capacitor. Can source
500µA for external loads. Loading REF degrades OUT accuracy, according to the REF load-regulation error.
Output of the DC-Voltage Positioning Transconductance Amplifier. Connect a resistor RFB between FB and
the positive side of the feedback remote sense to set the DC steady-state droop based on the voltagepositioning gain requirement:
RFB = RDROOP / (RSENSE x Gm(FB))
12
FB
13
GNDS
Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load. GNDS
internally connects to a transconductance amplifier that fine tunes the output voltage— compensating for
voltage drops from the regulator ground to the load ground.
14
CSP2
Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive side of
the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing. Tie this pin to VCC for 1-phase operation.
CSN12
(MAX8771)
Combined Negative Current-Sense Input for Phases 1 and 2. The negative current-sense signals of the
two phases (taken from the negative sides of the output current-sensing resistors or the filtering capacitors
if the DC resistances of the output inductors are utilized for current sensing) are resistively averaged, and
the resulting signal is connected to this pin. Pay special attention to board layout to maximize currentsensing accuracy; either place the sense elements (inductors for lossless sensing or sense resistors)
close to each other, or equalize the layout paths and PC board trace resistances between the sense
elements and the remote load. CSN12 is also used as the voltage input to the power monitor.
CSN2
(MAX8770
/MAX8772)
Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the negative side
of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing. CSN2 is also used as the voltage input to the power monitor.
CSP1
(MAX8771)
Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of
the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing.
CSN1
(MAX8770/
MAX8772)
Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the negative side
of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing.
where RDROOP is the desired voltage-positioning slope and Gm(FB) = 600µS (typ). RSENSE is the value of
the current-sense resistors that are used to provide the (CSP_, CSN_) current-sense voltages. If lossless
sensing is used, RSENSE = RL. In this case, consider making RFB a resistor network that includes an NTC
thermistor to minimize the temperature dependence of the voltage-positioning slope. DC droop can be
disabled by shorting FB to the positive remote-sense point. FB is high impedance in shutdown.
15
16
______________________________________________________________________________________
15
MAX8770/MAX8771/MAX8772
Pin Description (continued)
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
MAX8770/MAX8771/MAX8772
Pin Description (continued)
PIN
NAME
PHASEGD
(MAX8771)
Open-Drain, Phase-Good Output. Used to signal the system that one of the two phases either has a fault
condition or is not matched with the other. Detection is done by identifying the need for a large on-time
difference between phases in order to achieve or move towards current balance. PHASEGD is low in
shutdown.
PHASEGD is forced high impedance whenever the slew-rate controller is active (output-voltage
transitions).
PHASEGD is forced high impedance while in 1-phase operation (DPRSLPVR = high or PSI = low).
CSP1
(MAX8770
MAX8772)
Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of
the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is
utilized for current sensing.
17
18
GND
Analog Ground. Connect to the exposed backside pad and low-current analog ground terminations.
19
VCC
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum.
20
BST2
Boost Flying-Capacitor Connection for the DH2 high-side gate driver. An internal switch between VDD and
BST2 charges the flying capacitor during the time the low-side FET is on.
21
DH2
Phase-2, High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
22
LX2
Phase-2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also
used as an input to the phase 2’s zero-crossing comparator.
23
PGND2
Power Ground for Phase 2. Ground connection for the DL2 driver. Also used as an input to phase 2’s zero
crossing comparator.
DL2
Phase-2, Low-Side Gate-Driver Output. DL2 swings from PGND2 to VDD. DL2 is forced high in shutdown.
DL2 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit
condition that may be present. DL2 is forced low in skip mode (DPRSLPVR high) after an inductor current
zero crossing (PGND2 - LX2) is detected. DL2 is forced low in 1-phase mode (TWO - PH = low).
VDD
Supply Voltage Input for the DL1 and DL2 Drivers. VDD is also the supply voltage used to internally
recharge the BST1, BST2 flying capacitors during the off-times of the respective phases. Connect VDD to
the 4.5V to 5.5V system supply voltage. Bypass VDD to PGND1 and PGND2 with a 1µF each or greater
ceramic capacitors.
26
DL1
Phase 1, Low-Side Gate-Driver Output. DL1 swings from PGND1 to VDD. DL1 is forced high in shutdown.
DL1 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit
condition that may be present. DL1 is forced low in skip mode (DPRSLPVR high) whenever an inductor
current zero crossing (PGND1 - LX1) is detected.
27
PGND1
Power Ground for Phase 1. Ground connection for the DL1 driver. Also used as an input to the phase 1’s
zero crossing comparator.
28
LX1
Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also
used as an input to the phase-1’s zero-crossing comparator.
29
DH1
Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.
30
BST1
Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between VDD
and BST1 charges the flying capacitor during the time the low-side FET is on.
24
25
16
FUNCTION
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
PIN
NAME
31–37
D0–D6
Low-Voltage VID DAC Code Input. The D0–D6 inputs do not have internal pullups. These 1.0V logic inputs
are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the
logic-level voltages on D0–D6 (see Table 4).
SHDN
Shutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal
operation. Connect to ground to put the IC into its 1µA max shutdown state. During startup, the output
voltage is ramped up to the boot voltage slowly at a slew rate that is 1/8 the slew rate set by the TIME
resistor. During the transition from normal operation to shutdown, the output voltage is ramped down at the
same slow slew rate. Forcing SHDN to 11V~13V disables both OVP and UVP protection circuits, clears the
fault latch, disables transient phase overlap, and disables the BST_ charging switches. Do not connect
SHDN to > 13V.
38
FUNCTION
Logic Input to Indicate Power Usage. PSI and DPRSLPVR together determine the operating mode as
shown in the truth table below. The PWRGD upper threshold is blanked when the part is in skip mode. The
part is forced into full-phase PWM mode during startup, while in boot mode, during the transition
from boot mode to VID mode, and during shutdown.
39
DPRSLPVR
40
DPRSTP
EP
EP
DPRSLPVR
1
1
0
0
PSI
0
1
0
1
Mode
Very low current (1-phase skip)
Low current (approximately 3A) (1-phase skip)
Intermediate power potential (1-phase PWM)
Max power potential (full-phase PWM: number of phases by CSP2)
1.0V Logic-Input Signal. This signal from the system is usually the logical complement of the DPRSLPVR
signal. However, there is a special condition during C4 exit when both DPRSTP and DPRSLPVR could
temporarily be simultaneously high. If this happens, the slew rate reduces to 1/4 of the normal (RTIMEbased) slew rate for the duration of this condition. The slew rate returns to normal when this condition is
exited. Note that only DPRSLPVR and PSI (but not DPRSTP) determine the mode of operation (PWM vs.
skip) and the number of active phases:
DPRSLPVR
DPRSTP
Functionality
0
0
Normal slew rate, number of phases set by PSI and CSP2
(DPRSLPVR low → DPRSTP is ignored)
0
1
Normal slew rate, number of phases set by PSI and CSP2
(DPRSLPVR low → DPRSTP is ignored)
1
0
Normal slew rate, 1-phase skip mode
1
1
Slew rate reduced to 1/4 of normal,1-phase skip mode
Exposed Backside Pad. Connect the exposed backside pad to AGND.
______________________________________________________________________________________
17
MAX8770/MAX8771/MAX8772
Pin Description (continued)
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Table 1. Component Selection for Standard Applications
1.2875V/36A COMPONENTS
(FIGURE 1)
1.1500V/44A COMPONENTS
(FIGURE 1)
0.9000V/9A COMPONENTS
(FIGURE 12)
Input Voltage Range
7V to 24V
7V to 24V
7V to 24V
VID Output Voltage
(D6–D0)
1.2875V
(D6–D0 = 0010001)
1.1500V
(D6–D0 = 0011100)
0.9000V
(D6–D0 = 0110000)
-2.1mV/A
-2.1mV/A
-5.1mV/A
36A
44A
9A
Inductor (per Phase)
0.36µH, 0.8mΩ
NEC/Tokin MPC1055LR36
0.33µH, 0.82mΩ
Panasonic ETQP5LR33XFC
0.56µH, 1.3mΩ
NEC/Tokin MPC1040LR56
Switching Frequency
300kHz (RTON = 200kΩ)
300kHz (RTON = 200kΩ)
300kHz (RTON = 200kΩ)
High-Side MOSFET
(NH, per Phase)
Siliconix (1) Si7892ADP
Siliconix (1) Si7892ADP
Siliconix (1) Si7892ADP
Low-Side MOSFET
(NL, per Phase)
Siliconix (2) Si7336ADP
Siliconix (2) Si7336ADP
Siliconix (1) Si7336ADP
Total Input Capacitance
(CIN)
(4) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
or
TDK C4532X5R1E106M
(4) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
or
TDK C4532X5R1E106M
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
or
TDK C4532X5R1E106M
Total Output Capacitance
(COUT)
(4) 330µF, 2.5V, 6mΩ
Panasonic EEFSX0D0D331XR
(4) 330µF, 2.5V, 6mΩ
Panasonic EEFSX0D0D331XR
(2) 330µF, 2.5V, 6mΩ
Panasonic EEFSX0D0D331XR
1.0mΩ
Panasonic ERJM1WTJ1M0U
1.0mΩ
Panasonic ERJM1WTJ1M0U
2.0mΩ
Panasonic ERJM1WTJ2M0U
DESIGNATION
Load Line
Maximum Load Current
Current-Sense Resistor
(RCS, per Phase)
Table 2. Component Suppliers
MANUFACTURER
WEBSITE
MANUFACTURER
WEBSITE
AVX
www.avxcorp.com
Pulse
www.pulseeng.com
BI Technologies
www.bitechnologies.com
Renesas
www.renesas.com
Central Semiconductor
www.centralsemi.com
Sanyo
www.secc.co.jp
Fairchild
Semiconductor
www.fairchildsemi.com
Siliconix (Vishay)
www.vishay.com
International Rectifier
www.irf.com
Sumida
www.sumida.com
Kemet
www.kemet.com
Taiyo Yuden
www.t-yuden.com
NEC/Tokin
www.nec-tokin.com
TDK
www.component.tdk.com
Panasonic
www.panasonic.com
TOKO
www.tokoam.com
18
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
R4
10kΩ
R3
1.9kΩ
R2
1.9kΩ
C2
2.2µF
VDD
VCC
R18
200kΩ
R22
0Ω
CLKEN
IMVPOK
BST1
PWRGD
D0
D1
D2
D3
D4
D5
D6
DAC INPUTS
(1V LOGIC)
INPUT VIN
8V TO 24V
RTON
PHASEGD
CLK_ENABLE#
5V BIAS
SUPPLY
C1
2.2µF
R1
10Ω
CIN
C3
0.22µF
DH1
NH1
RCS1
1mΩ
L1
LX1
DL1
NL1
R12
100Ω
PGND1
GND
PSI#
C11
2.2nF
PSI
DPRSTP#
CSP1
DPRSTP
*CSN1
DPRLSPVR
DPRSLPVR
VR_ON
MAX8770/MAX8771/MAX8772
3.3V BIAS
SUPPLY
C13
OPEN
R18
0Ω
SHDN
R9
3.40kΩ
R10
100Ω
CPU VCC
SENSE
FB
C5
470pF
CCV
C6
0.1µF
MAX8770
REF MAX8771
MAX8772
C7
470pF
C8
4700pF
R11**
10Ω
R18
0Ω
OUTPUT
CCI
R5
71.5kΩ
COUT
R23
0Ω
TIME
R16**
10Ω
BST2
DH2
NH2
R6
13kΩ
RCS1
1mΩ
L1
CPU GND
SENSE
LX2
VCC
THRM
DL2
NTC4
100kΩ
1.2V BIAS
SUPPLY
NL2
C11
2.2nF
R7
56Ω
CSP2
R8
10kΩ
VRHOT
POUT
C10
0.1µF
R12
100Ω
PGND2
*CSN2
R17
100
GNDS
C9
4700pF
* CSN1 and CSN2 are bonded together on the
MAX8771 and called CSN12
** Optional -- Resistor allow remote sensing for system
verification when the CPU is not present
+ PHASEGD is only on the MAX8771
Figure 1. Standard 2-Phase IMVP-6 44A Application Circuit
______________________________________________________________________________________
19
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
vides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by
a one-shot whose period is inversely proportional to
input voltage, and directly proportional to output voltage
or the difference between the main and secondary
inductor currents (see the On-Time One-Shot section).
Another one-shot sets a minimum off-time. The on-time
one-shot triggers when the error comparator goes low,
the inductor current of the selected phase is below the
valley current-limit threshold, and the minimum off-time
one-shot times out. The controller maintains 180° out-of-
MAX8770/MAX8771/MAX8772
Detailed Description
Free-Running, Constant On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator
with voltage feed-forward (Figure 2). This architecture
relies on the output filter capacitor’s ESR to act as the
current-sense resistor, so the output ripple voltage pro-
BST2
THRM
MAX8770
MAX8771
MAX8772
VRHOT
DH2
LX2
SECONDARY
PHASE DRIVERS
DL2
PGND2
0.3 x VCC
BLANK
CSP2
PHASEGD
CSN2
Q
22.5mV
CSP1
VCC
REF
TRIG
Q
22.5mV
REF
(2.0V)
5ms
STARTUP
DELAY
CURRENTBALANCEFAULT
ONE-SHOT
PHASE 2
ON-TIME
CSN1
MINIMUM
OFF-TIME
TRIG
CCI
CSN2
Gm(CCI)
ONE-SHOT
GND
TIME
FB
ONE-SHOT
R-TO-I
CONVERTER
Q
MAIN PHASE
DRIVERS
R
DAC
Gm(CCI)
TRIG
DPRSTP
D0–D6
Q
FAULT
Q
R
VDD
SKIP
CCV
BST1
Q
CSP1
CSN1
2.5mV
T
REF
TON
LX1
S
Q
CSN1
DH1
S
SHDN
CSP2
CSP1
PHASE 1
ON-TIME
DPRSLPVR
TARGET
DL1
Gm(CCV)
PGND1
TARGET
- 300mV
TARGET
+ 200mV
PWRGD
5ms
STARTUP
DELAY
FB
Gm(FB)
CLKEN
CSP_
60µs
STARTUP
DELAY
SKIP
x2
CSN_
GNDS
PHASE CONTROL
BLANK
DPRSTP
PSI
CSP1 - CSN1
DPRSLPVR
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
CSN1 - GNDS
POWER
MONITOR
POUT
CSP2 - CSN2
Figure 2. Functional Block Diagram
20
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Dual 180° Out-of-Phase Operation
The two phases in the MAX8770/MAX8771/MAX8772
operate 180° out-of-phase to minimize input and output
filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count—reducing cost, board space,
and component power requirements— making the
MAX8770/MAX8771/MAX8772 ideal for high-power,
cost-sensitive applications.
Typically, switching regulators provide power using
only 1 phase instead of dividing the power among several phases. In these applications, the input capacitors
must support high instantaneous current requirements.
The high RMS ripple current can lower efficiency due to
I2R® power loss associated with the input capacitor’s
effective series resistance (ESR). Therefore, the system
typically requires several low-ESR input capacitors in
parallel to minimize input voltage ripple, to reduce ESRrelated power losses, and to meet the necessary RMS
ripple current rating.
With the MAX8770/MAX8771/MAX8772, the controller
shares the current between two phases that operate
180° out-of-phase, so the high-side MOSFETs never
turn on simultaneously during normal operation. The
instantaneous input current of either phase is effectively
halved, resulting in reduced input voltage ripple, ESR
power loss, and RMS ripple current (see the Input
Capacitor Selection section). Therefore, the same performance may be achieved with fewer or less-expensive input capacitors.
+5V Bias Supply (VCC and VDD)
The Quick-PWM controller requires an external +5V
bias supply in addition to the battery. Typically, this
+5V bias supply is the notebook’s 95% efficient +5V
system supply. Keeping the bias supply external to the
IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the +5V bias supply
can be generated with an external linear regulator.
The +5V bias supply must provide V CC (PWM controller) and VDD (gate-drive power), so the maximum
current drawn is:
IBIAS = ICC - fSW (QG(LOW) + QG(HIGH))
where ICC is provided in the Electrical Characteristics
Table, fSW is the switching frequency, and QG(LOW)
and QG(HIGH) are the MOSFET data sheet’s total gatecharge specification limits at VGS = 5V.
VIN and VDD can be tied together if the input power
source is a fixed +4.5V to +5.5V supply. If the +5V
bias supply is powered up prior to the battery supply,
the enable signal (SHDN going from low to high) must
be delayed until the battery voltage is present to
ensure startup.
Switching Frequency (TON)
Connect a resistor (RTON) between TON and VIN to set
the switching period TSW = 1/fSW, per phase:
TSW = CTON (RTON + 6.5kΩ)
where CTON = 16.26pF.
A 96.75kΩ to 303.25kΩ corresponds to switching periods of 167ns (600kHz) to 500ns (200kHz), respectively.
High-frequency (600kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be
acceptable in ultra-portable devices where the load
currents are lower and the controller is powered from a
lower voltage supply. Low-frequency (200kHz) operation offers the best overall efficiency at the expense of
component size and board space.
On-Time One-Shot
The core of each phase contains a fast, low-jitter,
adjustable one-shot that sets the high-side MOSFETs
on-time. The one-shot for the main phase varies the ontime in response to the input and feedback voltages.
The main high-side switch on-time is inversely proportional to the input voltage (VIN), and proportional to the
feedback voltage (VFB):
t ON(MAIN ) =
TSW (VFB + 0.075V)
VIN
where the switching period (TSW = 1/fSW) is set by the
resistor at the TON pin, and 0.075V is an approximation
to accommodate the expected drop across the lowside MOSFET switch.
The one-shot for the secondary phase varies the ontime in response to the input voltage and the difference
between the main and secondary inductor currents.
Two identical transconductance amplifiers integrate the
difference between the master and slave current-sense
signals. The summed output is internally connected to
I2R is a registered trademark of instruments for Research and
Industry, Inc.
______________________________________________________________________________________
21
MAX8770/MAX8771/MAX8772
phase operation by alternately triggering the main and
secondary phases after the error comparator drops
below the output voltage set point.
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
CCI, allowing adjustment of the integration time constant with a compensation network connected between
CCI and FB. The resulting compensation current and
voltage are determined by the following equations:
ICCI = GM (VCMP - VCMN) - GM (VCSP - VCSN)
VCCI = VFB + ICCIZCCI
where ZCCI is the impedance at the CCI output. The
secondary on-time one-shot uses this integrated signal
(VCCI) to set the secondary high-side MOSFETs ontime. When the main and secondary current-sense signals (VCM = VCMP - VCMN and VCS = VCSP -VCSM)
become unbalanced, the transconductance amplifiers
adjust the secondary on-time, which increases or
decreases the secondary inductor current until the current-sense signals are properly balanced:
⎛V
+ 0.075V ⎞
t ON(SEC) = TSW ⎜ CCI
⎟
VIN
⎝
⎠
⎛ VFB + 0.075V ⎞
⎛I Z
⎞
= TSW ⎜
+ TSW ⎜ CCI CCI ⎟
⎟
VIN
⎝
⎠
⎝ VIN ⎠
= (Main On-Time)
+ (Secondary Current Balance Correction)
This algorithm results in a nearly constant switching frequency and balanced inductor currents, despite the lack
of a fixed-frequency clock generator. The benefits of a
constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions
such as the 455kHz IF band; second, the inductor ripplecurrent operating point remains relatively constant,
resulting in easy design methodology and predictable
output voltage ripple. The on-time one-shots have good
accuracy at the operating points specified in the
Electrical Characteristics table. On-times at operating
points far removed from the conditions specified in the
Electrical Characteristics table can vary over a wider
range. For example, the 600kHz setting typically runs
about 5% slower, with inputs much greater than +12V
due to the very short on-times required.
On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical
Characteristics table are influenced by switching
delays in the external high-side MOSFET. Resistive
losses, including the inductor, both MOSFETs, output
capacitor ESR, and PC board copper losses in the output and ground tend to raise the switching frequency at
higher output currents. Also, the dead-time effect
increases the effective on-time, reducing the switching
frequency. It occurs only during forced-PWM operation
and dynamic output-voltage transitions when the induc22
tor current reverses at light or negative load currents.
With reversed inductor current, the inductor’s EMF
causes LX to go high earlier than normal, extending the
on-time by a period equal to the DH-rising dead time.
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switching frequency (per phase) is:
fSW =
(
(VOUT + VDIS )
t ON VIN + VDIS − VCHG
)
where VDIS is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VCHG is
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
PC board resistances; and tON is the on-time as determined above.
Current Sense
The output current of each phase is sensed. Low-offset
amplifiers are used for current balance, voltage-positioning gain, and current limit. Sensing the current at
the output of each phase offers advantages, including
less noise sensitivity, more accurate current sharing
between phases, and the flexibility of using either a
current-sense resistor or the DC resistance of the output inductor.
Using the DC resistance (RDCR) of the output inductor
allows higher efficiency. In this configuration, the initial
tolerance and temperature coefficient of the inductor’s
DCR must be accounted for in the output-voltage
droop-error budget and power monitor. This currentsense method uses an RC filtering network to extract
the current information from the output inductor (see
Figure 3). The resistive divider used should provide a
current-sense resistance (RCS) low enough to meet the
current-limit requirements, and the time constant of the
RC network should match the inductor’s time constant
(L/RCS):
⎛ R2 ⎞
RCS = ⎜
and
⎟R
⎝ R1 + R2 ⎠ DCR
RCS =
L
CEQ
1⎤
⎡1
⎢ R1 + R2 ⎥
⎣
⎦
where RCS is the required current-sense resistance,
and RDCR is the inductor’s series DC resistance. Use
the worst-case inductance and RDCR values provided
by the inductor manufacturer, adding some margin for
the inductance drop over temperature and load. To
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
but results in a significant peak current-sense voltage
error that results in unwanted offsets in the regulation
voltage and results in early current-limit detection.
Similar to the inductor DCR sensing method above, the
RC filter’s time constant should match the L/R time constant formed by the current-sense resistor’s parasitic
inductance:
LESL
= CEQR1
RSENSE
where LESL is the equivalent series inductance of the
current-sense resistor, RSENSE is current-sense resistance value, and CEQ and REQ are the time-constant
matching components.
INPUT (VIN)
CIN
DH_
SENSE RESISTOR
NH
LESL
L
RSENSE
LX_
DL_
NL
COUT
DL
PGND
R1
CEQR1 =
LSENSE
RSENSE
CEQ
CSP_
CSN_
A) OUTPUT SERIES RESISTOR SENSING
INPUT (VIN)
CIN
DH_
INDUCTOR
NH
L
DCR
LX_
DL_
RCS =
NL
DL
COUT
R1
B) LOSSLESS INDUCTOR SENSING
R2
R1 + R2
)
RDCR
R2
RDCR =
PGND
CSP_
CSN_
(
[
L
1 1
+
CEQ R1 R2
]
CEQ
FOR THERMAL COMPENSATION:
R2 SHOULD CONSIST OF AN NTC RESISTOR IN
SERIES WITH A STANDARD THIN-FILM RESISTOR
Figure 3. Current-Sense Methods
______________________________________________________________________________________
23
MAX8770/MAX8771/MAX8772
minimize the current-sense error due to the currentsense inputs’ bias current (ICSP_ and ICSN_), choose
R1||R2 to be less than 2kΩ and use the above equation
to determine the sense capacitance (CEQ). Choose
capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is
recommended for this current-sense method. See the
Voltage Positioning and the Loop Compensation section for detailed information.
When using a current-sense resistor for accurate output-voltage positioning, the circuit requires a differential
RC filter to eliminate the AC voltage step cause by the
equivalent series inductance (L ESL ) of the currentsense resistor (see Figure 3). The ESL-induced voltage
step does not affect the average current-sense voltage,
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Current Balance
Without active current-balance circuitry, the current
matching between phases depends on the MOSFETs’
on-resistance (RDS(ON)), thermal ballasting, on/off-time
matching, and inductance matching. For example, variation in the low-side MOSFET on-resistance (ignoring
thermal effects) results in a current mismatch that is
proportional to the on-resistance difference:
⎡ ⎛R
⎞⎤
IMAIN − ISEC = IMAIN ⎢1− ⎜ MAIN ⎟ ⎥
⎢⎣ ⎝ RSEC ⎠ ⎥⎦
However, mismatches between on-times, off-times, and
inductor values increase the worst-case current imbalance, making it impossible to passively guarantee
accurate current balancing.
The MAX8770/MAX8771/MAX8772 integrate the difference between the current-sense voltages and adjust the
on-time of the secondary phase to maintain current balance. The current balance now relies on the accuracy of
the current-sense resistors instead of the inaccurate, thermally sensitive on-resistance of the low-side MOSFETs.
With active current balancing, the current mismatch is
determined by the current-sense resistor values and the
offset voltage of the transconductance amplifiers:
IOS(IBAL) = ILMAIN − ILSEC =
VOS(IBAL)
RSENSE
where RSENSE = RCM = RCS and VOS(IBAL) is the current-balance offset specification in the Electrical
Characteristics table .
The worst-case current mismatch occurs immediately
after a load transient due to inductor value mismatches
resulting in different di/dt for the two phases. The time it
takes the current-balance loop to correct the transient
imbalance depends on the mismatch between the
inductor values and switching frequency.
Current Limit
The current-limit circuit employs a unique “valley” current-sensing algorithm that uses current-sense resistors
between the current-sense inputs (CSP_ to CSN12 for
MAX8771, CSP_ to CSN_ for MAX8770/MAX8772) as
the current-sensing elements. If the current-sense signal of the selected phase is above the current-limit
threshold, the PWM controller does not initiate a new
cycle until the inductor current of the selected phase
drops below the valley current-limit threshold. When
either phase trips the current limit, both phases are
effectively current limited since the interleaved controller does not initiate a cycle with either phase.
24
Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold
by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the currentsense resistance, inductor value, and battery voltage.
When combined with the UVP circuit, this current-limit
method is effective in almost every circumstance.
The positive current-limit threshold is fixed internally at
22.5mV. There is also a negative current limit that prevents excessive reverse inductor currents when VOUT
is sinking current. The negative current-limit threshold
is set at -30mV. When a phase drops below the negative current limit, the controller immediately activates an
on-time pulse—DL turns off, and DH turns on—allowing
the inductor current to remain above the negative current threshold.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs
(CSP_, CSN_). For the MAX8771, where the negative
current-sense returns are to a common pin, it is recommended that the current-sense elements (sense resistor or inductor DCR) be placed close to each other to
minimize any voltage differences that might arise due
to trace impedance between the two common nodes.
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier
(Steady-State Droop)
The MAX8770/MAX8771/MAX8772 include a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier’s input is generated
by summing the current-sense inputs, which differentially sense the voltage across either current-sense
resistors or the inductor’s DCR. The amplifier’s output
connects directly to the regulator’s voltage-positioned
feedback input (FB), so the resistance between FB and
the output-voltage sense point determines the voltagepositioning gain:
VOUT = VTARGET - RFBIFB
where the target voltage (VTARGET) is defined in the
Nominal Output Voltage Selection section, and the FB
amplifier’s output current (IFB) is determined by the
sum of the current-sense voltages:
ηPH
IFB = Gm(FB) ∑ VCSX
X =1
where VCS = VCSP - VCSN is the differential currentsense voltage, and Gm(FB) is typically 600µS as defined
in the Electrical Characteristics table.
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Integrator Amplifier
An integrator amplifier forces the DC average of the FB
voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure
2), allowing accurate DC output-voltage regulation
regardless of the output ripple voltage. The integrator
amplifier has the ability to shift the output voltage by
±60mV (typ), including DC offset and AC ripple. The integration time constant can be set easily with an external
compensation capacitor at the CCV pin. Use a 470pF x
(2/ηTOTAL) x 300kHz/fSW or greater ceramic capacitor.
The MAX8770/MAX8771/MAX8772 disable the integrator by connecting the amplifier inputs together at the
beginning of all VID transitions done in pulse-skipping
mode (DPRSLPVR = high). The integrator remains disabled until 20µs after the transition is completed (the
internal target settles) and the output is in regulation
(edge detected on the error comparator).
Transient-Overlap Operation
When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor
current. Multiphase controllers that remain 180° out-ofphase when a transient occurs actually respond slower
than an equivalent single-phase controller. In order to
provide fast transient response, the MAX8770/
MAX8771/MAX8772 support a phase-overlap mode that
allows the dual regulators to operate in-phase when
heavy load transients are detected, effectively reducing
the response time. After either high-side MOSFET turns
off, if the output voltage does not exceed the regulation
voltage when the minimum off-time expires, the controller
simultaneously turns on both high-side MOSFETs during
the next on-time cycle. This maximizes the total inductor
current slew rate. The phases remain overlapped until
the output voltage exceeds the regulation voltage after
the minimum off-time expires.
After the phase-overlap mode ends, the controller
automatically begins with the opposite phase. For
example, if the secondary phase provided the last ontime pulse before overlap operation began, the controller starts switching with the main phase when
overlap operation ends.
Nominal Output-Voltage Selection
The nominal no-load output voltage (V TARGET ) is
defined by the selected voltage reference (VID DAC)
plus the remote ground-sense adjustment (VGNDS), as
defined in the following equation:
VTARGET = VFB = VDAC + VGNDS
where VDAC is the selected VID voltage. On startup, the
MAX8770/MAX8771/MAX8772 slew the target voltage
from ground to the preset boot voltage.
DAC Inputs (D0–D6)
The digital-to-analog converter (DAC) programs the output voltage using the D0–D6 inputs. D0–D6 are low-voltage (1.0V) logic inputs, designed to interface directly
with the CPU. Do not leave D0–D6 unconnected.
Changing D0–D6 initiates a transition to a new outputvoltage level. Change D0–D6 together, avoiding greater
than 20ns skew between bits. Otherwise, incorrect DAC
readings may cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time.
The available DAC codes and resulting output voltages
are compatible with the IMVP-6 (Table 4) specifications.
______________________________________________________________________________________
25
MAX8770/MAX8771/MAX8772
Differential Remote Sense
The MAX8770/MAX8771/MAX8772 include differential,
remote-sense inputs to eliminate the effects of voltage
drops along the PC board traces and through the
processor’s power pins. The feedback-sense node
connects to the voltage-positioning resistor (RFB). The
ground-sense (GNDS) input connects to an amplifier
that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the
voltage drop in the ground path. Connect the voltagepositioning resistor (RFB), and ground sense (GNDS)
input directly to the processor’s remote-sense outputs
as shown in Figure 1.
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Table 3. Operating Mode Truth Table
INPUTS
SHDN
DPRSTP
DPRSLPVR
PSI
PHASE
OPERATION*
Low
X
X
X
DISABLED
X
Multiphase
forced PWM
1/8 RTIME slew
rate
Startup/Boot. When SHDN is pulled high, the
MAX8770/MAX8771/MAX8772 begin the startup sequence.
Once the REF is above 1.84V, the controller enables the PWM
controller and ramps the output voltage up to the boot
voltage. See Figure 9.
High
Multiphase
forced PWM;
normal RTIME
slew rate
Full Power. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4).
Low
1-phase forced
PWM;
normal RTIME
slew rate
Intermediate Power. The no-load output voltage is determined
by the selected VID DAC code (D0–D6, Table 4). When PSI is
pulled low, the MAX8770/MAX8771/MAX8772 immediately
disable phase 2—DH2, and DL2 pulled low.
1-phase pulse
skipping,
normal RTIME
slew rate
Deeper Sleep Mode. The no-load output voltage is
determined by the selected VID DAC code (D0–D6, Table 4).
When DPRSLPVR is pulled high, the MAX8770/MAX8771/
MAX8772 immediately enter 1-phase pulse-skipping
operation allowing automatic PWM/PFM switchover under
light loads. The PWRGD and CLKEN upper thresholds are
blanked. DH2 and DL2 are pulled low.
X
1-phase pulse
skipping,
1/4 RTIME slew
rate
Deeper Sleep Slow-Exit Mode. The no-load output voltage is
determined by the selected VID DAC code (D0–D6, Table 4).
When DPRSTP is pulled high while DPRSLPVR is already
high, the MAX8770/MAX8771/MAX8772 remain in 1-phase
pulse-skipping operation, allowing automatic PWM/PFM
switchover under light loads. The PWRGD and CLKEN upper
thresholds are blanked. DH2 and DL2 are pulled low.
X
Multiphase
forced-PWM,
1/8 R TIME slew
rate
Shutdown. When SHDN is pulled low, the
MAX8770/MAX8771/MAX8772 immediately pull PWRGD and
PHASEGD low, CLKEN becomes high impedance, all
enabled phases are activated, and the output voltage is
ramped down to ground. Once the output reaches zero, the
controller enters the low-power shutdown state. See Figure 9.
DISABLED
Fault Mode. The fault latch has been set by the MAX8770/
MAX8771/MAX8772 UVP or thermal shutdown protection, or
by the MAX8771 OVP protection. The controller remains in
FAULT mode until VCC power is cycled or SHDN toggled.
Rising
High
High
High
High
Falling
High
X
X
X
Low
High
X
X
X
Low
Low
High
High
X
X
X
X
OPERATING MODE
Low-Power Shutdown Mode. DL1 and DL2 forced high,
and the controller is disabled. The supply current drops to
1µA (max).
*Multiphase operation = All enabled phases active.
26
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
D6
D5
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE (V)
D6
D5
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE (V)
0
0
0
0
0
0
0
1.5000
1
0
0
0
0
0
0
0.7000
0
0
0
0
0
0
1
1.4875
1
0
0
0
0
0
1
0.6875
0
0
0
0
0
1
0
1.4750
1
0
0
0
0
1
0
0.6750
0
0
0
0
0
1
1
1.4625
1
0
0
0
0
1
1
0.6625
0
0
0
0
1
0
0
1.4500
1
0
0
0
1
0
0
0.6500
0
0
0
0
1
0
1
1.4375
1
0
0
0
1
0
1
0.6375
0
0
0
0
1
1
0
1.4250
1
0
0
0
1
1
0
0.6250
0
0
0
0
1
1
1
1.4125
1
0
0
0
1
1
1
0.6125
0
0
0
1
0
0
0
1.4000
1
0
0
1
0
0
0
0.6000
0
0
0
1
0
0
1
1.3875
1
0
0
1
0
0
1
0.5875
0
0
0
1
0
1
0
1.3750
1
0
0
1
0
1
0
0.5750
0
0
0
1
0
1
1
1.3625
1
0
0
1
0
1
1
0.5625
0
0
0
1
1
0
0
1.3500
1
0
0
1
1
0
0
0.5500
0
0
0
1
1
0
1
1.3375
1
0
0
1
1
0
1
0.5375
0
0
0
1
1
1
0
1.3250
1
0
0
1
1
1
0
0.5250
0
0
0
1
1
1
1
1.3125
1
0
0
1
1
1
1
0.5125
0
0
1
0
0
0
0
1.3000
1
0
1
0
0
0
0
0.5000
0
0
1
0
0
0
1
1.2875
1
0
1
0
0
0
1
0.4875
0
0
1
0
0
1
0
1.2750
1
0
1
0
0
1
0
0.4750
0
0
1
0
0
1
1
1.2625
1
0
1
0
0
1
1
0.4625
0
0
1
0
1
0
0
1.2500
1
0
1
0
1
0
0
0.4500
0
0
1
0
1
0
1
1.2375
1
0
1
0
1
0
1
0.4375
0
0
1
0
1
1
0
1.2250
1
0
1
0
1
1
0
0.4250
0
0
1
0
1
1
1
1.2125
1
0
1
0
1
1
1
0.4125
0
0
1
1
0
0
0
1.2000
1
0
1
1
0
0
0
0.4000
0
0
1
1
0
0
1
1.1875
1
0
1
1
0
0
1
0.3875
0
0
1
1
0
1
0
1.1750
1
0
1
1
0
1
0
0.3750
0
0
1
1
0
1
1
1.1625
1
0
1
1
0
1
1
0.3625
0
0
1
1
1
0
0
1.1500
1
0
1
1
1
0
0
0.3500
0
0
1
1
1
0
1
1.1375
1
0
1
1
1
0
1
0.3375
0
0
1
1
1
1
0
1.1250
1
0
1
1
1
1
0
0.3250
0
0
1
1
1
1
1
1.1125
1
0
1
1
1
1
1
0.3125
______________________________________________________________________________________
27
MAX8770/MAX8771/MAX8772
Table 4. IMVP-6 Output Voltage VID DAC Codes
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Table 4. IMVP-6 Output Voltage VID DAC Codes (continued)
28
D6
D5
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE (V)
D6
D5
D4
D3
D2
D1
D0
OUTPUT
VOLTAGE (V)
0
1
0
0
0
0
0
1.1000
1
1
0
0
0
0
0
0.3000
0
1
0
0
0
0
1
1.0875
1
1
0
0
0
0
1
0.2875
0
1
0
0
0
1
0
1.0750
1
1
0
0
0
1
0
0.2750
0
1
0
0
0
1
1
1.0625
1
1
0
0
0
1
1
0.2625
0
1
0
0
1
0
0
1.0500
1
1
0
0
1
0
0
0.2500
0
1
0
0
1
0
1
1.0375
1
1
0
0
1
0
1
0.2375
0
1
0
0
1
1
0
1.0250
1
1
0
0
1
1
0
0.2250
0
1
0
0
1
1
1
1.0125
1
1
0
0
1
1
1
0.2125
0
1
0
1
0
0
0
1.0000
1
1
0
1
0
0
0
0.2000
0
1
0
1
0
0
1
0.9875
1
1
0
1
0
0
1
0.1875
0
1
0
1
0
1
0
0.9750
1
1
0
1
0
1
0
0.1750
0
1
0
1
0
1
1
0.9625
1
1
0
1
0
1
1
0.1625
0
1
0
1
1
0
0
0.9500
1
1
0
1
1
0
0
0.1500
0
1
0
1
1
0
1
0.9375
1
1
0
1
1
0
1
0.1375
0
1
0
1
1
1
0
0.9250
1
1
0
1
1
1
0
0.1250
0
1
0
1
1
1
1
0.9125
1
1
0
1
1
1
1
0.1125
0
1
1
0
0
0
0
0.9000
1
1
1
0
0
0
0
0.1000
0
1
1
0
0
0
1
0.8875
1
1
1
0
0
0
1
0.0875
0
1
1
0
0
1
0
0.8750
1
1
1
0
0
1
0
0.0750
0
1
1
0
0
1
1
0.8625
1
1
1
0
0
1
1
0.0625
0
1
1
0
1
0
0
0.8500
1
1
1
0
1
0
0
0.0500
0
1
1
0
1
0
1
0.8375
1
1
1
0
1
0
1
0.0375
0
1
1
0
1
1
0
0.8250
1
1
1
0
1
1
0
0.0250
0
1
1
0
1
1
1
0.8125
1
1
1
0
1
1
1
0.0125
0
1
1
1
0
0
0
0.8000
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0.7875
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
0.7750
1
1
1
1
0
1
0
0
0
1
1
1
0
1
1
0.7625
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0.7500
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0.7375
1
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0.7250
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0.7125
1
1
1
1
1
1
1
0
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Output-Voltage Transition Timing
The MAX8770/MAX8771/MAX8772 perform mode transitions in a controlled manner, automatically minimizing
input surge currents. This feature allows the circuit
designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output-voltage level
with the lowest possible peak currents for a given output capacitance.
At the beginning of an output-voltage transition, the
MAX8770/MAX8771/MAX8772 blank PHASEGD,
CLKEN, and PWRGD upper and lower thresholds, preventing the open-drain outputs from changing states
during the transition. The controller enables the lower
CLKEN and PWRGD threshold approximately 20µs
after the slew-rate controller reaches the target output
voltage, but the upper CLKEN and PWRGD threshold is
enabled only if the controller remains in forced-PWM
operation. If the controller enters pulse-skipping operation, the upper CLKEN and PWRGD threshold remains
blanked. The slew rate (set by resistor RTIME) must be
set fast enough to ensure that the transition may be
completed within the maximum allotted time.
The MAX8770/MAX8771/MAX8772 automatically control the current to the minimum level required to complete the transition in the calculated time. The slew-rate
controller uses an internal capacitor and current source
programmed by RTIME to transition the output voltage.
The total transition time depends on RTIME, the voltage
difference, and the accuracy of the slew-rate controller
(CSLEW accuracy). The slew rate is not dependent on
the total output capacitance, as long as the surge current is less than the current limit. For all dynamic VID
transitions, the transition time (tTRAN) is given by:
t TRAN =
VNEW − VOLD
(dVTARGET / dt)
where dVTARGET/dt = 12.5mV/µs × 71.5kΩ / RTIME is
the slew rate, VOLD is the original output voltage, and
VNEW is the new target voltage. See TIME Slew Rate
Accuracy in Electrical Characteristics for slew-rate limits. For soft-start and shutdown, the controller automatically reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current per phase required to make an output
voltage transition is:
IL ≅
COUT
× (dVTARGET / dt)
ηTOTAL
where dVTARGET/dt is the required slew rate, COUT is
the total output capacitance, and ηTOTAL is the number
of active phases.
Deeper Sleep Transitions
When DPRSLPVR goes high, the MAX8770/MAX8771/
MAX8772 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance
(MAX8771 only), and enter pulse-skipping operation
(see Figures 4 and 5). If the VIDs are set to a lower voltage setting, the output drops at a rate determined by
the load and the output capacitance. The internal target
still ramps as before, and CLKEN and PWRGD upper
and lower thresholds remain blanked until 20µs after
the internal target reaches the programmed VID code.
Once this time expires, PWRGD monitors only the lower
threshold:
• Fast C4E Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR pulled low) while the output voltage still exceeds the deeper sleep voltage, the
MAX8770/MAX8771/MAX8772 quickly slew (50mV/µs
min regardless of RTIME setting) the internal target
voltage to the DAC code provided by the processor
as long as the output voltage is above the new target. The controller remains in skip mode until the output voltage equals the internal target. Once the
internal target reaches the output voltage, phase 2 is
enabled. The controller blanks PWRGD, PHASEGD,
and CLKEN (forced high impedance) until 20µs after
the transition is completed. See Figure 4.
______________________________________________________________________________________
29
MAX8770/MAX8771/MAX8772
Suspend Mode
When the processor enters low-power deeper sleep
mode, the IMVP-6 CPU sets the VID DAC code to a
lower output voltage and drives DPRSLPVR high. The
MAX8770/MAX8771/MAX8772 respond by slewing the
internal target voltage to the new DAC code, switching
to single-phase operation, and letting the output voltage gradually drift down to the deeper sleep voltage.
During the transition, the MAX8770/MAX8771/MAX8772
blank both the upper and lower PWRGD and CLKEN
thresholds until 20µs after the internal target reaches
the deeper sleep voltage. Once the 20µs timer expires,
the MAX8770/MAX8771/MAX8772 reenable the lower
PWRGD and CLKEN threshold, but keep the upper
threshold blanked. PHASEGD remains blanked high
impedance while DPRSLPVR is high.
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
• Slow C4 Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR high, DPRSTP pulled high) while
the output voltage is regulating to the deeper sleep
voltage, the MAX8770/MAX8771/MAX8772 remain in
1-phase skip mode and ramp the output voltage to the
LFM DAC code provided by the processor at 1/4 the
slew-rate set by RTIME. The controller blanks PWRGD,
PHASEGD, and CLKEN (forced high impedance) until
20µs after the transition is completed. See Figure 6.
• Standard C4 Deeper Sleep Exit: When exiting
deeper sleep (DPRSLPVR pulled low) while the output voltage is regulating to the deeper sleep voltage,
the MAX8770/MAX8771/MAX8772 immediately activate all enabled phases and ramp the output voltage
to the LFM DAC code provided by the processor at
the slew rate set by R TIME. The controller blanks
PWRGD, PHASEGD, and CLKEN (forced high
impedance) until 20µs after the transition is completed. See Figure 5.
ACTUAL VOUT
CPU CORE
VOLTAGE
INTERNAL TARGET
VID (D0–D6)
DEEPER SLEEP VID
DPRSLPVR
DO NOT CARE (DPRSLPVR DOMINATES STATE)
PSI
INTERNAL
PWM CONTROL
FORCED PWM
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)
NO PULSES: VOUT > VTARGET
DH1
PWM2
DH2
PWRGD
BLANK HIGH-Z
BLANK HIGH THRESHOLD ONLY
BLANK HIGH-Z
CLKEN
BLANK LO
BLANK HIGH THRESHOLD ONLY
BLANK LO
BLANK HIGH-Z
PHASEGD
SET TO 1.75V MIN
OVP
tBLANK
20µs TYP
TRACKS INTERNAL TARGET
tBLANK
20µs TYP
Figure 4. C4E (C4 Early Exit) Transition
30
______________________________________________________________________________________
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MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
MAX8770/MAX8771/MAX8772
ACTIVE VID
CPU CORE
VOLTAGE
ACTUAL VOUT
INTERNAL
TARGET
VID (D0–D6)
DEEPER SLEEP VID
LFM VID
DPRSLP VID
LFM VID
DPRSLPVR
DPRSTP
PSI
DO NOT CARE (DPRSLPVR DOMINATES STATE)
INTERNAL
PWM CONTROL
1-PHASE SKIP (DH1 ACTIVE, DL2 FORCED LOW)
1-PHASE FORCED PWM
NO PULSES: VOUT > VTARGET
DH1
DH2
PWRGD
CLKEN
BLANK HIGH-Z
BLANK HIGH THRESHOLD ONLY
BLANK HIGH-Z
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK LOW
BLANK HIGH-Z (1-PHASE OPERATION)
PHASEGD
SET TO 1.75V MIN
OVP
tBLANK
20µs TYP
TRACKS INTERNAL TARGET
tBLANK
20µs TYP
Figure 5. Standard C4 Transition
______________________________________________________________________________________
31
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MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
ACTIVE VID
CPU CORE
VOLTAGE
ACTUAL VOUT
INTERNAL
TARGET
VID (D0–D6)
DEEPER SLEEP VID
LFM VID
DPRSLP VID
LFM VID
DPRSLPVR
DPRSTP
PSI
DO NOT CARE (DPRSLPVR DOMINATES STATE)
INTERNAL
PWM CONTROL
1-PHASE SKIP (DH1 ACTIVE, DL2 FORCED LOW)
DH1
1-PHASE FORCED PWM
NO PULSES: VOUT > VTARGET
DH2
PWRGD
CLKEN
BLANK HIGH-Z
BLANK HIGH THRESHOLD ONLY
BLANK HIGH-Z
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK LOW
BLANK HIGH-Z (1-PHASE OPERATION)
PHASEGD
OVP
SET TO 1.75V MIN
tBLANK
20µs TYP
TRACKS INTERNAL TARGET
tBLANK
20µs TYP
Figure 6. Slow C4 Transition
32
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MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
phase 2. PHASEGD is blanked high impedance for 32
switching cycles on DH2, allowing sufficient time/cycles
for phase 1 and 2 to achieve current balance. In a typical
IMVP-6 application, the VID is reduced by 1 LSB
(12.5mV) when PSI is pulled low, and increased by 1
LSB when PSI is pulled high.
ACTIVE VID
CPU CORE
VOLTAGE
SLOW SLEW RATE
ACTUAL VOUT
INTERNAL
TARGET
VID (D0–D6)
LFM VID
DPRSLP VID
LFM VID
DEEPER SLEEP VID
DPRSLPVR
SLOW SLEW RATE
DPRSTP
DO NOT CARE (DPRSLPVR DOMINATES STATE)
PSI
INTERNAL
PWM CONTROL
1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 - FORCED LOW)
1-PHASE FORCED PWM
NO PULSES: VOUT > VTARGET
DH1
DH2
PWRGD
CLKEN
BLANK HIGH-Z
BLANK HIGH THRESHOLD ONLY
BLANK HIGH-Z
BLANK LOW
BLANK HIGH THRESHOLD ONLY
BLANK LOW
BLANK HIGH-Z (1-PHASE OPERATION)
PHASEGD
SET TO 1.75V MIN
OVP
tBLANK
20µs TYP
TRACKS INTERNAL TARGET
tBLANK
20µs TYP
Figure 7. PSI# Transition
______________________________________________________________________________________
33
MAX8770/MAX8771/MAX8772
PSI Transitions
When PSI is pulled low, the MAX8770/MAX8771/
MAX8772 immediately disable phase 2 (DH2 and DL2
forced low), blank PHASEGD high impedance, and enter
single-phase PWM operation (see Figure 7). When PSI is
pulled high, the MAX8770/MAX8771/MAX8772 enable
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Forced-PWM Operation (Normal Mode)
During soft-start, soft-shutdown, and normal operation—when the CPU is actively running (DPRSLPVR =
low, Table 5)—the MAX8770/MAX8771/MAX8772 operate with the low-noise, forced-PWM control scheme.
Forced-PWM operation disables the zero-crossing
comparators of all active phases, forcing the low-side
gate-drive waveforms to be constantly the complement
of the high-side gate-drive waveforms. This keeps the
switching frequency constant and allows the inductor
current to reverse under light loads, providing fast,
accurate negative-output-voltage transitions by quickly
discharging the output capacitors.
Forced-PWM operation comes at a cost; the no-load
+5V bias supply current remains between 10mA to
50mA per phase, depending on the external MOSFETs
and switching frequency. To maintain high efficiency
under light-load conditions, the processor may switch
the controller to a low-power, pulse-skipping control
scheme after entering suspend mode.
PSI determines how many phases are active when
operating in forced-PWM mode (DPRSLPVR = low).
When PSI is pulled low, the main phase remains active
but the secondary phase is disabled (DH2 and DL2
forced low).
Light-Load Pulse-Skipping Operation
(Deeper Sleep)
When DPRSLPVR is pulled high, the MAX8770/
MAX8771/MAX8772 operate with a single-phase,
pulse-skipping mode. The pulse-skipping mode
enables the driver’s zero-crossing comparator, so the
controller pulls DL1 low when its current-sense inputs
detect “zero” inductor current. This keeps the inductor
from discharging the output capacitors and forces the
controller to skip pulses under light-load conditions to
avoid overcharging the output.
When pulse skipping, the controller blanks the upper
PWRGD and CLKEN thresholds, and also blanks
PHASEGD high impedance for the MAX8771. Upon
entering pulse-skipping operation, the controller temporarily sets the OVP threshold to 1.80V, preventing
false OVP faults when the transition to pulse-skipping
operation coincides with a downward VID code
change. Once the error amplifier detects that the output
voltage is in regulation, the OVP threshold tracks the
selected VID DAC code. The MAX8770/MAX8771/
MAX8772 automatically use forced-PWM operation during soft-start and soft-shutdown, regardless of the
DPRSLPVR and PSI configuration.
Automatic Pulse-Skipping Switchover
In skip mode (DPRSLPVR = high), an inherent automatic switchover to PFM takes place at light loads (Figure
8). This switchover is affected by a comparator that
truncates the low-side switch on-time at the inductor
current’s zero crossing. The zero-crossing comparator
senses the inductor current across the low-side
MOSFETs. Once VLX drops below the zero crossing
comparator threshold (see the Electrical Characteristics
table), the comparator forces DL low (Figure 2). This
mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide
with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM
crossover occurs when the load current of each phase
is equal to 1/2 the peak-to-peak ripple current, which is
a function of the inductor value (Figure 8). For a battery-input 7V to 20V range, this threshold is relatively
constant, with only a minor dependence on the input
voltage due to the typically low duty cycles. The total
load current at the PFM/PWM crossover threshold
(ILOAD(SKIP)) is approximately:
⎞
⎛T V
⎞⎛ V − V
ILOAD(SKIP) = ηTOTAL ⎜ SW OUT ⎟ ⎜ IN OUT ⎟
⎝
⎠⎝
L
VIN
⎠
where ηTOTAL is the number of active phases.
The switching waveforms may appear noisy and asynchronous when light loading activates pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs between
PFM noise and light-load efficiency are made by vary-
∆i
∆t
INDUCTOR CURRENT
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
VBATT – VOUT
L
IPEAK
ILOAD = IPEAK/2
0
ON-TIME
TIME
Figure 8. Pulse-Skipping/Discontinuous Crossover Point
34
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MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Power-Up Sequence (POR, UVLO)
The MAX8770/MAX8771/MAX8772 are enabled when
SHDN is driven high (Figure 9). The reference powers
up first. Once the reference exceeds its UVLO threshold, the internal analog blocks are turned on and
masked by a 150µs one-shot delay. The PWM controller then begins switching.
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry
VCC
SHDN
INVALID
CODE
VID (D0–D6)
INVALID
CODE
SOFT-START =
1/8th SLEW RATE SET
BY RTIME
VCORE
INTERNAL
PWM CONTROL
SOFT-SHUTDOWN =
1/8th SLEW RATE SET
BY RTIME
FORCED PWM
FORCED PWM
PHASEGD
CLKEN
PWRGD
tBLANK
5ms TYP
tBLANK
60µs TYP
tBLANK
20µs TYP
tBLANK
20µs TYP
Figure 9. Power-Up and Shutdown Sequence Timing Diagram
______________________________________________________________________________________
35
MAX8770/MAX8771/MAX8772
ing the inductor value. Generally, low inductor values
produce a broader efficiency vs. load curve, while
higher values result in higher full-load efficiency
(assuming that the coil resistance remains fixed) and
less output-voltage ripple. Penalties for using higher
inductor values include larger physical size and
degraded load-transient response, especially at low
input-voltage levels.
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MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system
enables the controller, VCC above 4.25V and SHDN driven high. With the reference in regulation, the controller
ramps the output voltage to the 1.20V boot voltage at
1/8 the slew rate set by RTIME:
t TRAN(START) =
8VBOOT
(dVTARGET / dt)
where dVTARGET/dt = 12.5mV/µs x 71.5kΩ / RTIME is the
slew rate. The soft-start circuitry does not use a variable
current limit, so full output current is available immediately. CLKEN is pulled low approximately 60µs after the
MAX8770/MAX8771/MAX8772 reach the boot voltage. At
the same time, the MAX8770/MAX8771/MAX8772 slew
the output to the voltage set at the VID inputs at the programmed slew rate. PWRGD and PHASEGD become
high impedance approximately 5ms after CLKEN is
pulled low. The MAX8770/MAX8771/MAX8772 automatically use forced-PWM operation during soft-start and
soft-shutdown, regardless of the DPRSLPVR and PSI
configuration.
For automatic startup, the battery voltage should be
present before VCC. If the controller attempts to bring
the output into regulation without the battery-voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling SHDN
or cycling the VCC power supply below 0.5V.
If the VCC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately
and forces a high-impedance output.
Shutdown
When SHDN goes low, the MAX8770/MAX8771/MAX8772
enter low-power shutdown mode. CLKEN is pulled high
and PWRGD is pulled low immediately, and the output
voltage ramps down at 1/8 the slew rate set by RTIME:
t TRAN(SHDN) =
8VOUT
(dVTARGET / dt)
where dVTARGET/dt = 12.5mV/µs x 71.5kΩ / RTIME is
the slew rate. Slowly discharging the output capacitors
by slewing the output over a long period of time keeps
the average negative inductor current low (damped
response), thereby eliminating the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on
the low-side MOSFET (underdamped response). This
36
eliminates the need for the Schottky diode normally
connected between the output and ground to clamp
the negative output-voltage excursion. After the controller reaches the zero target, the MAX8770/
MAX8771/MAX8772 shut down completely—the drivers
are disabled (DL1 and DL2 driven high)—the reference
turns off, and the supply currents drop to about 1µA
(max) 20µs.
When a fault condition—output UVLO or thermal shutdown—activates the shutdown sequence, the protection
circuitry sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V.
Power Monitor (POUT)
The MAX8770/MAX8771/MAX8772 include a singlequadrant multiplier used to determine the actual output
power based on the inductor current (sum of the differential CS inputs) and output voltage (CSNpm to GNDS,
when CSNpm = CSN12 for MAX8771, CSNpm = CSN2
for MAX8770/MAX8772). The buffered output of this
multiplier is connected to POUT and provides a voltage
relative to the output power dissipation:
VPWR =
(VCSNpm − VGNDS )(ILOADRSENSE )
KPWR
where the power-monitor scale factor (KPWR) is typically 16.67mV. The power monitor allows the system to
accurately monitor the CPU’s power dissipation and
quickly predict if the system is about to overheat before
the significantly slower temperature sensor signals an
overtemperature alert.
Phase Fault (PHASEGD, MAX8771 Only)
The MAX8771 includes a phase-fault output that signals the system that one of the two phases either has a
fault condition or is not matched with the other.
Detection is done by identifying the need for a large ontime difference between phases in order to achieve or
move towards current balance. PHASEGD is forced low
when VCCI is below 0.6xVFB or above 1.4xVFB.
PHASEGD is high impedance when the MAX8771 is set
to run in 1-phase operation (DPRSLPVR high, or PSI
low and DPRSLPVR low). On exit to the 2-phase mode,
PHASEGD is forced high impedance for 32 switching
cycles on DH2.
PHASEGD is low in shutdown. PHASEGD is forced high
impedance whenever the slew rate controller is active
(output voltage transitions).
______________________________________________________________________________________
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MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Fault Protection (Latched)
Output Overvoltage Protection (MAX8770/
MAX8771 Only)
The OVP circuit is designed to protect the CPU against
a shorted high-side MOSFET by drawing high current
and blowing the battery fuse. The MAX8770/MAX8771
continuously monitor the output for an overvoltage fault.
The controller detects an OVP fault if the output voltage
exceeds the set VID DAC voltage by more than 300mV,
regardless of the operating state. During pulse-skipping operation (DPRSLPVR = high), the OVP threshold
is set at 1.8V once a downward VID transition occurs,
and reverts to track the VID DAC voltage when the output reaches the set VID code.
When the OVP circuit detects an overvoltage fault while
in multiphase mode (DPRSLPVR = low, PSI = high), the
MAX8770/MAX8771 immediately force DL1 and DL2
high and pull DH1 and DH2 low. This action turns on
the synchronous-rectifier MOSFETs with 100% duty
and, in turn, rapidly discharges the output filter capacitor and forces the output low. If the condition that
caused the overvoltage (such as a shorted high-side
MOSFET) persists, the battery fuse blows. Toggle
SHDN or cycle the VCC power supply below 0.5V to
clear the fault latch and reactivate the controller.
When an overvoltage fault occurs while in 1-phase
operation (DPRSLPVR = high, or PSI = low), the
MAX8770/MAX8771 immediately force DL1 high and
pull DH1 low. DL2 and DH2 remain low as phase 2 was
disabled. DL2 is forced high only when the output falls
below the UV threshold. Overvoltage protection can be
disabled through the no-fault test mode (see the NoFault Test Mode section).
Output Undervoltage Protection
The output UVP function is similar to foldback current
limiting, but employs a timer rather than a variable current limit. If the MAX8770/MAX8771/MAX8772 output
voltage is 400mV below the target voltage, the controller activates the shutdown sequence and sets the
fault latch. Once the controller ramps down to zero, it
forces the DL1 and DL2 high and pulls DH1 and DH2
low. Toggle SHDN or cycle the V CC power supply
below 0.5V to clear the fault latch and reactivate the
controller.
UVP can be disabled through the no-fault test mode
(see the No-Fault Test Mode section).
Thermal-Fault Protection
The MAX8770/MAX8771/MAX8772 feature a thermalfault-protection circuit. When the junction temperature
rises above +160°C, a thermal sensor sets the fault
latch and activates the soft-shutdown sequence. Once
the controller ramps down to zero, it forces the DL1 and
DL2 high and pulls DH1 and DH2 low. Toggle SHDN or
cycle the VCC power supply below 0.5V to clear the
fault latch and reactivate the controller after the junction
temperature cools by 15°C.
Thermal shutdown can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
No-Fault Test Mode
The latched fault-protection features can complicate
the process of debugging prototype breadboards
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a “no-fault” test
mode is provided to disable the fault protection—overvoltage protection, undervoltage protection, and thermal shutdown. Additionally, the test mode clears the
fault latch if it has been set. The no-fault test mode is
entered by forcing 11V to 13V on SHDN.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications where a large VIN - VOUT
differential exists. The high-side gate drivers (DH)
source and sink 2.2A, and the low-side gate drivers
(DL) source 2.7A and sink 8A. This ensures robust gate
drive for high-current applications. The DH_ floating
high-side MOSFET drivers are powered by internal
boost switch charge pumps at BST_, while the DL_ synchronous-rectifier drivers are powered directly by the
5V bias supply (VDD).
Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL and DH drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX8770/
______________________________________________________________________________________
37
MAX8770/MAX8771/MAX8772
Temperature Comparator (VRHOT)
The MAX8770/MAX8771/MAX8772 also feature an
independent comparator with an accurate threshold
(VHOT) that tracks the analog supply voltage (VHOT =
0.3VCC). This makes the thermal trip threshold independent of the VCC supply voltage tolerance. Use a resistor- and thermistor-divider between VCC and GND to
generate a voltage-regulator overtemperature monitor.
Place the thermistor as close to the MOSFETs and
inductors as possible.
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MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
BST
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
(RBST)*
INPUT (VIN)
CBST
DH
NH
L
LX
CBYP
VDD
DL
NL
(CNL)*
PGND
(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE
SWITCHING NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS
Figure 10. Gate Drive Circuit
MAX8771/MAX8772 interprets the MOSFET gates as
“off” while charge actually remains. Use very short,
wide traces (50 mils to 100 mils wide if the MOSFET is
1in from the driver).
The internal pulldown transistor that drives DL low is
robust, with a 0.25Ω (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high-input voltages and long inductive driver traces may require
rising LX edges that do not pull up the low-side
MOSFETs’ gate, causing shoot-through currents. The
capacitive coupling between LX and DL created by the
MOSFET’s gate-to-drain capacitance (CRSS), gate-tosource capacitance (C ISS - C RSS ), and additional
board parasitics should not exceed the following minimum threshold:
⎛C
⎞
VGS(TH) > VIN ⎜ RSS ⎟
⎝ CISS ⎠
Typically, adding a 4700pF between DL and power
ground (C NL in Figure 10), close to the low-side
38
Alternatively, shoot-through currents may be caused by
a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST
slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading
the turn-off time (RBST in Figure 10). Slowing down the
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
Multiphase Quick-PWM
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
• Input voltage range: The maximum value (VIN(MAX))
must accommodate the worst-case high-AC adapter
voltage. The minimum value (VIN(MIN)) must account
for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there
is a choice at all, lower input voltages result in better
efficiency.
• Maximum load current: There are two values to
consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit
ILOAD = ILOAD(MAX) x 80%.
For multiphase systems, each phase supports a fraction of the load, depending on the current balancing.
When properly balanced, the load current is evenly distributed among each phase:
I
ILOAD(PHASE) = LOAD
ηTOTAL
where ηTOTAL is the total number of active phases.
______________________________________________________________________________________
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MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
⎛
⎞⎛ V
VIN − VOUT
OUT ⎞
L = ηTOTAL ⎜
⎟⎜
⎟
f
I
LIR
V
⎝
⎝ SW LOAD(MAX)
⎠
IN ⎠
where ηTOTAL is the total number of phases.
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK):
⎛ ILOAD(MAX) ⎞ ⎛
LIR ⎞
IPEAK = ⎜
⎟ ⎜1 + 2 ⎟⎠
⎝ η TOTAL ⎠ ⎝
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low VIN - VOUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. For a dual-phase controller, the
worst-case output sag voltage may be determined by:
(
L ∆ILOAD(MAX)
VSAG =
+
)
2 ⎡⎛ VOUT TSW ⎞
⎢⎜
⎢⎣⎝
VIN
⎤
⎟ + t OFF(MIN) ⎥
⎠
⎥⎦
⎡⎛ ( VIN − 2VOUT )TSW ⎞
⎤
2COUT VOUT ⎢⎜
⎟ − 2t OFF(MIN) ⎥
VIN
⎢⎝
⎥
⎠
⎣
⎦
∆ILOAD(MAX)
2COUT
⎤
⎡⎛ VOUT TSW ⎞
⎢⎜
⎟ + t OFF(MIN) ⎥
V
⎝
⎠
⎥⎦
IN
⎣⎢
where t OFF(MIN) is the minimum off-time (see the
Electrical Characteristics table).
The amount of overshoot due to stored inductor energy
can be calculated as:
VSOAR ≈
(∆ILOAD(MAX) )
2
L
2η TOTALCOUT VOUT
where ηTOTAL is the total number of active phases.
Setting the Current Limit
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half the ripple current; therefore:
⎛ ILOAD(MAX) ⎞ ⎛
LIR ⎞
ILIMIT(LOW ) > ⎜
⎜1 −
⎟
⎟
2 ⎠
⎝ η TOTAL ⎠ ⎝
where ηTOTAL is the total number of active phases,
and I LIMIT(LOW) equals the minimum current-limit
threshold voltage divided by the current-sense resistor
(RSENSE). For the 22.5mV default setting, the minimum
current-limit threshold is 19.5mV.
______________________________________________________________________________________
39
MAX8770/MAX8771/MAX8772
• Switching frequency: This choice determines the
basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input
voltage due to MOSFET switching losses that are
proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid
improvements in MOSFET technology that are making higher frequencies more practical.
• Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values provide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction benefit.
The optimum operating point is usually found
between 20% and 50% ripple current.
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MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
Output Capacitor Selection
Output Capacitor Stability Considerations
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
In CPU VCORE converters and other applications where
the output is subject to large load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching
frequency. The boundary of instability is given by the
following equation:
(RESR
+ RPCB ) ≤
VSTEP
∆ILOAD(MAX)
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capacitor’s ESR. When operating multiphase systems out-ofphase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For multiphase operation, the maximum ESR to meet ripple
requirements is:
⎡
⎤
VINfSW L
RESR ≤ ⎢
⎥ VRIPPLE
⎢⎣ ( VIN − η TOTAL VOUT )VOUT ⎥⎦
where ηTOTAL is the total number of active phases and
fSW is the switching frequency per phase. The actual
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V SAG and V SOAR from causing
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the VSAG and VSOAR equations
in the Transient Response section).
40
fESR ≤
fSW
π
where:
1
and
2πREFFCOUT
REFF = RESR + RDROOP + RPCB
fESR =
where COUT is the total output capacitance, RESR is the
total ESR, RSENSE is the current-sense resistance (RCM
= RCS), RDROOP is the voltage-positioning gain, and
RPCB is the parasitic board resistance between the output capacitors and sense resistors.
For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below
50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP
capacitors in widespread use at the time of publication
have typical ESR zero frequencies below 50kHz. In the
standard application circuit, the ESR needed to support
a 30mVP-P ripple is 30mV/(40A x 0.3) = 2.5mΩ. Four
330µF/2.5V Panasonic SP (type SX) capacitors in parallel provide 1.5mΩ (max) ESR. With a 2mΩ droop and
0.5mΩ PC board resistance, the typical combined ESR
results in a zero at 30kHz.
Ceramic capacitors have a high ESR zero frequency,
but applications with significant voltage positioning can
take advantage of their size and low ESR. Do not put
high-value ceramic capacitors directly across the output
without verifying that the circuit contains enough voltage
positioning and series PC board resistance to ensure
stability. When only using ceramic output capacitors,
output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively
low capacitance value can cause output overshoot
when stepping from full-load to no-load conditions,
unless a small inductor value is used (high switching
frequency) to minimize the energy transferred from
inductor to capacitor during load-step recovery. The
efficiency penalty for operating at 600kHz is approximately 5% when compared to the 300kHz circuit, primarily due to the high-side MOSFET switching losses.
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
The multiphase Quick-PWM controllers operate out-ofphase while the Quick-PWM slave controllers provide
selectable out-of-phase or in-phase on-time triggering.
Out-of-phase operation reduces the RMS input current
by dividing the input current between several staggered stages. For duty cycles less than 100%/ηOUTPH
per phase, the IRMS requirements may be determined
by the following equation:
⎛ ILOAD ⎞
IRMS = ⎜
⎟
⎝ η TOTAL VIN ⎠
η TOTAL VOUT ( VIN − η TOTAL VOUT )
where η TOTAL is the total number of out-of-phase
switching regulators. The worst-case RMS current
requirement occurs when operating with V IN =
2ηTOTALVOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD/ηTOTAL.
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their
resistance to inrush surge currents typical of systems
with a mechanical switch or connector in series with the
input. If the Quick-PWM controller is operated as the
second stage of a two-stage power-conversion system,
tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less
than +10°C temperature rise at the RMS input current
for optimal circuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Calculate both of these sums.
Ideally, the losses at VIN(MIN) should be roughly equal
to losses at VIN(MAX), with lower losses in between. If
the losses at VIN(MIN) are significantly higher than the
losses at VIN(MAX), consider increasing the size of NH
(reducing RDS(ON) but with higher CGATE). Conversely,
if the losses at VIN(MAX) are significantly higher than the
losses at VIN(MIN), consider reducing the size of NH
(increasing RDS(ON) to lower CGATE). If VIN does not
vary over a wide range, the minimum power dissipation
occurs where the resistive losses equal the switching
losses.
Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderatesized package (i.e., one or two 8-pin SOs, DPAK, or
D2PAK), and is reasonably priced. Make sure that the
DL gate driver can supply sufficient current to support
the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction problems may occur (see the MOSFET Gate Driver section).
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the
minimum input voltage:
⎛V
⎞ ⎛ I
⎞
PD (NH Re sistive) = ⎜ OUT ⎟ ⎜ LOAD ⎟
⎝ VIN ⎠ ⎝ η TOTAL ⎠
2
RDS(ON)
where ηTOTAL is the total number of phases.
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation the in high-side MOSFET (NH) due to switching losses is difficult since it
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
______________________________________________________________________________________
41
MAX8770/MAX8771/MAX8772
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feed-back
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is
not enough voltage ramp in the output voltage signal.
This “fools” the error comparator into triggering a new
cycle immediately after the minimum off-time period
has expired. Double pulsing is more annoying than
harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop
instability can result in oscillations at the output after
line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
age, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for
breadboard evaluation, preferably including verification
using a thermocouple mounted on NH:
PD (NH
⎛ VIN(MAX)ILOADfSW ⎞
⎜
⎟
η TOTAL
⎝
⎠
SWITCHING) =
⎛ QG(SW ) ⎞
COSS VIN2 fSW
⎜ I
⎟ +
2
⎝ GATE ⎠
where COSS is the NH MOSFET’s output capacitance,
QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the C x
VIN2 x ƒSW switching-loss equation. If the high-side
MOSFET chosen for adequate RDS(ON) at low battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
PD (NL RESISTIVE) =
2
⎡
⎛ V
⎞⎤ ⎛ I
⎞
⎢1 − ⎜ OUT ⎟ ⎥ ⎜ LOAD ⎟ RDS(ON)
⎢
⎝ VIN(MAX) ⎠ ⎥⎦ ⎝ η TOTAL ⎠
⎣
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
ILOAD(MAX), but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To protect against this possibility, you can “overdesign” the
circuit to tolerate:
∆IINDUCTOR ⎞
⎛
ILOAD = ηTOTAL ⎜ IVALLEY(MAX) +
⎟
⎝
⎠
2
⎛ ILOAD(MAX)LIR ⎞
= ηTOTALIVALLEY(MAX) + ⎜
⎟
2
⎝
⎠
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
42
Choose a Schottky diode (DL) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current per phase during the dead times. This diode is optional and can be
removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high
side MOSFETs’ gates:
CBST =
N × QGATE
200mV
where N is the number of high side MOSFETs used for
one regulator, and QGATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC
(VGS = 5V). Using the above equation, the required
boost capacitance would be:
CBST =
2 × 24nC
= 0.24µF
200mV
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
Current-Balance Compensation (CCI)
The current-balance compensation capacitor (CCCI)
integrates the difference between the main and secondary current-sense voltages. The internal compensation resistor (R CCI = 200kΩ) improves transient
response by increasing the phase margin. This allows
the dynamics of the current-balance loop to be optimized. Excessively large capacitor values increase the
integration time constant, resulting in larger current differences between the phases during transients.
Excessively small capacitor values allow the current
loop to respond cycle-by-cycle, but can result in small
DC current variations between the phases. Likewise,
excessively large resistor values can also cause DC
current variations between the phases. Small resistor
values reduce the phase margin, resulting in marginal
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
MAX8770/MAX8771/MAX8772
POWER
GROUND
POWER
GROUND
CPU
OUTPUT
COUT
C
OUT
CIN
C
CIN
IN
CIN
IN
COUT
C
OUT
COUT
C
OUT
INDUCTOR
INDUCTOR
CIN
COUT
C
OUT
INDUCTOR
INDUCTOR
INPUT
PLACE CONTROLLER ON BACKSIDE WHEN POSSIBLE, USING THE
GROUND PLANE TO SHIELD THE IC FROM EMI.
SEE THE EVALUATION KIT FOR ANALOG/POWER GROUND AND
CONTROLLER LAYOUT EXAMPLE.
Figure 11. PC Board Layout Example
stability in the current-balance loop. For most applications, a 470pF capacitor from CCI to the switching regulator’s output works well.
Connecting the compensation network to the output
(VOUT) allows the controller to feed-forward the outputvoltage signal, especially during transients. To reduce
noise pickup in applications that have a widely distributed layout, it is sometimes helpful to connect the compensation network to the quiet analog ground rather
than VOUT.
rent-sense resistance to be used, reducing the overall
power dissipated.
Voltage Positioning and Loop
Compensation
where the effective current-sense resistance (RSENSE)
depends on the current-sense method (see the Current
Sense section), and the voltage-positioning amplifier’s
transconductance (G m(FB) ) is typically 600µS, as
defined in the Electrical Characteristics table. The controller sums together the input signals of the currentsense inputs (CSP_, CSN_).
When the inductors’ DCR is used as the current-sense
element (RSENSE = RDCR), each current-sense input
should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor’s power-dissipation
requirements. The controller uses a transconductance
amplifier to set the transient and DC output voltage
droop (Figure 2) as a function of the load. This adjustability allows flexibility in the selected current-sense
resistor value or inductor DCR, and allows smaller cur-
Steady-State Voltage Positioning
Connect a resistor (RFB) between FB and VOUT to set
the DC steady-state droop (load line) based on the
required voltage-positioning slope (RDROOP):
RFB =
RDROOP
RSENSEGm (FB)
______________________________________________________________________________________
43
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
3.3V BIAS
SUPPLY
R1
10Ω
R3
1.9kΩ
R2
1.9kΩ
C2
2.2µF
5V BIAS
SUPPLY
C1
2.2µF
VDD
VCC
R18
200kΩ
INPUT VIN
8V TO 24V
RTON
CLK_ENABLE#
R22
0Ω
CLKEN
IMVPOK
PWRGD
C3
0.22µF
BST1
CIN
PHASEGD+
D0
D1
D2
D3
D4
D5
D6
DAC INPUTS
(1V LOGIC)
DH1
NH1
RCS1
2mΩ
L1
COUT
DL1
NL1
R12
100Ω
PGND1
C11
2.2nF
GND
PSI#
PSI
DPRSTP#
OUTPUT
LX1
DPRSTP
R16*
10Ω
CSP1
*CSN1
DPRLSPVR
DPRSLPVR
VR_ON
R11*
10Ω
SHDN
C5
1000pF
C6
0.1µF
POWER GROUND
CCV
MAX8770
MAX8771
MAX8772
R9
4.12kΩ
CPU GND
SENSE
R10
100Ω
FB
C8
4700pF
CPU VCC
SENSE
REF
CCI
ANALOG GROUND
R5
71.5kΩ
BST2
TIME
DH2
LX2
R6
13kΩ
DL2
VCC
THRM
NTC4
100kΩ
1.2V BIAS
SUPPLY
PGND2
CSP2
R7
56Ω
*CSN2
R17
100Ω
VRHOT
GNDS
POUT
C10
0.1µF
R8
10kΩ
C9
4700pF
* CSN1 AND CSN2 ARE BONDED TOGETHER ON THE
MAX8771 AND CALLED CSN12.
** OPTIONAL -- RESISTOR ALLOW REMOTE SENSING FOR SYSTEM
VERIFICATION WHEN THE CPU IS NOT PRESENT;
PHASEGD IS ONLY ON THE MAX8771.
Figure 12. Single-Phase ULV Design
44
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
The output voltage-adjustable range for continuousconduction operation is restricted by the nonadjustable
minimum off-time one-shot and the number of phases.
For best dropout performance, use the slower (200kHz)
on-time settings. When working with low input voltages,
the duty-factor limit must be calculated using worstcase values for on- and off-times.
Manufacturing tolerances and internal propagation
delays introduce an error to the on-times. This error is
greater at higher frequencies. Also, keep in mind that
transient response performance of buck regulators
operated too close to dropout is poor, and bulk output
capacitance must often be added (see the VSAG equation in the Design Procedure section).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP/∆IDOWN is an indicator of the ability to
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and V SAG greatly increases
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows tradeoffs between VSAG, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
⎡V
− VDROOP + VCHG ⎤
VIN(MIN) = ⎢ VID
⎥
1
h × t OFF(MIN)fSW ⎥⎦
−
⎢⎣
where VDROOP is the voltage-positioning droop, VCHG
is the parasitic voltage drops in the charge path (see
the On-Time One-Shot section) and tOFF(MIN) is from
the Electrical Characteristics table. The absolute minimum input voltage is calculated with h = 1.
If the calculated VIN(MIN) is greater than the required minimum input voltage, then reduce the operating frequency
or add output capacitance to obtain an acceptable VSAG.
If operation near dropout is anticipated, calculate VSAG to
be sure of adequate transient response.
Dropout design example:
VVID = 1.15V
fSW = 300kHz
tOFF(MIN) = 375ns
VDROOP = 2.1mV/A x 44A = 92.4mV
VCHG = 150mV (44A Load)
h = 1.5
⎡ 1.15V − 92.4mV + 150mV ⎤
VIN(MIN) = ⎢
⎥ = 1.45V
⎣ 1 − (0.375µs × 1.5 × 300kHz) ⎦
Calculating again with h = 1 gives the absolute limit of
dropout:
⎡ 1.15V − 92.4mV + 150mV ⎤
VIN(MIN) = ⎢
⎥ = 1.36V
⎣ 1 − (0.375µs × 1.0 × 300kHz) ⎦
Therefore, VIN must be greater than 4.1V, even with
very large output capacitance, and a practical input
voltage with reasonable output capacitance would be
5.0V.
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention (Figure 11). If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one another. Follow these guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-free
operation.
2) Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the
Quick-PWM controller. This includes the VCC bypass
capacitor, REF and GNDS bypass capacitors, and
compensation (CCV) components.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes
a measurable efficiency penalty.
4) Keep the high-current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-
______________________________________________________________________________________
45
MAX8770/MAX8771/MAX8772
Minimum Input-Voltage Requirements and
Dropout Performance
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
power MOSFETs that require low-impedance gate
drivers to avoid shoot-through currents.
5) CSP_ and CSN_ connections for current limiting and
voltage positioning must be made using Kelvin-sense
connections to guarantee the current-sense accuracy.
6) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example, it
is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET or between the inductor and the output filter
capacitor.
7) Route high-speed switching nodes away from sensitive analog areas (REF, CCV, CCI, FB, CSP_, CSN_,
etc.).
Layout Procedure
Place the power components first, with ground terminals
adjacent (low-side MOSFET source, CIN, COUT, and D1
anode). If possible, make all these connections on the top
layer with wide, copper-filled areas:
Mount the controller IC adjacent to the low-side MOSFET.
The DL gate traces must be short and wide (50 mils to 100
mils wide if the MOSFET is 1in from the controller IC).Group
the gate-drive components (BST capacitors, VDD bypass
capacitor) together near the controller IC.
Make the DC-DC controller ground connections as shown
in the Standard Application Circuits. This diagram can be
viewed as having four separate ground planes: input/output ground, where all the high-power components go; the
power ground plane, where the PGND pin and VDD
bypass capacitor go; the master’s analog ground plane
where sensitive analog components, the master’s GND
pin, and VCC bypass capacitor go; and the slave’s analog
ground plane where the slave’s GND pin and VCC bypass
capacitor go. The master’s GND plane must meet the
PGND plane only at a single point directly beneath the IC.
Similarly, the slave’s GND plane must meet the PGND
plane only at a single point directly beneath the IC. The
respective master and slave ground planes should connect to the high-power output ground with a short metal
trace from PGND to the source of the low-side MOSFET
(the middle of the star ground). This point must also be
very close to the output capacitor ground terminal.
Connect the output power planes (VCORE and system
ground planes) directly to the output filter capacitor
positive and negative terminals with multiple vias. Place
the entire DC-DC converter circuit as close to the CPU
as is practical.
Chip Information
TRANSISTOR COUNT: 8990
PROCESS: BiCMOS
30 29 28 27 26 25 24 23 22 21
DH2
LX2
PGND2
DL2
VDD
DL1
PGND1
LX1
DH1
TOP VIEW
BST1
DH2
LX2
PGND2
DL2
VDD
DL1
PGND1
LX1
DH1
TOP VIEW
BST1
Pin Configurations
30 29 28 27 26 25 24 23 22 21
D0 31
20 BST2
D0 31
20 BST2
D1 32
19 VCC
D1 32
19 VCC
D2 33
18 GND
D2 33
18 GND
D3 34
17 CSP1
D3 34
17 PHASEGD
D4 35
16 CSN1
D4 35
15 CSN2
D5 36
15 CSN12
MAX8770
MAX8772
D5 36
16 CSP1
MAX8771
D6 37
14 CSP2
D6 37
14 CSP2
SHDN 38
13 GNDS
SHDN 38
13 GNDS
1
2
3
CCV
CCI
CLKEN
PWRGD
PSI
THIN QFN
6mm x 6mm
4
5
6
7
8
9
10
CCI
10
CCV
9
TON
8
TIME
7
THRM
6
TON
PSI
5
TIME
CLKEN
11 REF
4
THRM
3
VRHOT
2
POUT
1
12 FB
DPRSTP 40
VRHOT
11 REF
DPRSTP 40
DPRSLPVR 39
POUT
12 FB
DPRSLPVR 39
PWRGD
MAX8770/MAX8771/MAX8772
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
THIN QFN
6mm x 6mm
A "+" SIGN REPLACES THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
46
______________________________________________________________________________________
CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES
MAX8770/MAX8771/MAX8772 Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies
QFN THIN.EPS
(NE-1) X e
E
E/2
k
D/2
CL
(ND-1) X e
D
D2
D2/2
e
b
E2/2
L
CL
k
E2
e
L
CL
CL
L1
L
L
e
A1
A2
e
A
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
F
1
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN FOR REFERENCE ONLY.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
F
2
2
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 47
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX8770/MAX8771/MAX8772
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)