EVALUATION KIT AVAILABLE
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
General Description
The MAX9272 compact deserializer is designed to
interface with a GMSL serializer over 50I coax or 100I
shielded twisted-pair (STP) cable. The device pairs with
the MAX9271 or MAX9273 serializers.
The parallel output is programmable for single or double
output. Double output strobes out half of a parallel word
on each pixel clock cycle. Double output can be used
with GMSL serializers that have the double-input feature.
The device features an embedded control channel that
operates at 9.6kbps to 1Mbps in UART and mixed UART/
I2C modes, and up to 400kbps in I2C mode. Using the
control channel, a microcontroller (FC) is capable of programming serializer/deserializer and peripheral device
registers at any time, independent of video timing. Two
GPIO ports are included, allowing power-up and switching of the backlight in display applications and similar
uses. A continuously sampled GPI input supports touchscreen controller interrupt requests.
For use with longer cables, the device has a programmable equalizer. Programmable spread spectrum is
available on the parallel output. The serial input meets
ISO 10605 and IEC 61000-4-2 ESD standards. The core
supply range is 1.7V to 1.9V and the I/O supply range is
1.7V to 3.6V. The device is available in a 48-pin (7mm
x 7mm) TQFN-EP package with 0.5mm lead pitch and
operates over the -40NC to +105NC temperature range.
Applications
Automotive Camera Systems
Ordering Information appears at end of data sheet.
Typical Application Circuit appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX9272.related.
Benefits and Features
S Ideal for Camera Applications
Works with Low-Cost 50I Coax Cable and
FAKRA Connectors or 100I STP
Error Detection/Correction
9.6kbps to 1Mbps Control Channel in I2C-to-I2C
Mode with Clock Stretch Capability
Best-in-Class Supply Current: 90mA (max)
Double-Rate Clock for Megapixel Cameras
Cable Equalization Allows 15m Cable at Full
Speed
48-Pin (7mm x 7mm) TQFN-EP Package with
0.5mm Lead Pitch
S High-Speed Data Deserialization for Megapixel
Cameras
Up to 1.5Gbps Serial-Bit Rate with Single or
Double Output: 6.25MHz to 100MHz Clock
S Multiple Control-Channel Modes for System
Flexibility
9.6kbps to 1Mbps Control Channel in UART-to-
UART or UART-to-I2C Modes
S Reduces EMI and Shielding Requirements
Input Programmable for 100mV to 500mV
Single-Ended or 50mV to 400mV Differential
Programmable Spread Spectrum on the Parallel
Output Reduces EMI
Tracks Spread Spectrum on Serial Input
S Peripheral Features for Camera Power-Up and
Verification
Built-In PRBS Checker for BER Testing of the
Serial Link
Two GPIO Ports
Dedicated “Up/Down” GPI for Camera Frame
Sync Trigger and Other Uses
Remote/Local Wake-Up from Sleep Mode
S Meets Rigorous Automotive and Industrial
Requirements
-40NC to +105NC Operating Temperature
Q10kV Contact and Q15kV Air IEC 61000-4-2
ESD Protection
Q10kV Contact and Q30kV Air ISO 10605 ESD
Protection
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6383; Rev 1; 11/12
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Link Signaling and Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interfacing Command-Byte-Only I2C Devices with UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2 C
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Format for Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
I2C Communication with Remote-Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Control-Channel Broadcast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GPO /GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Maxim Integrated
2
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
TABLE OF CONTENTS (continued)
Line Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Additional Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
HV/VS Encoding and/or Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Coax-Mode Splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Cable Type Configuration Input (CX/TP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Link Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
ERR Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Autoerror Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Dual µC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Changing the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Fast Detection of Loss-of-Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Compatibility with other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Staggered Parallel Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Local Control-Channel Enable (LCCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Choosing I2C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Selection of AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Maxim Integrated
3
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
TABLE OF CONTENTS (continued)
Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LIST OF FIGURES
Figure 1. Reverse Control-Channel Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2. Test Circuit for Differential Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. Parallel Clock Output High and Low Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. Worst-Case Pattern Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Output Rise-and-Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Deserializer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Single-Output Waveform (Serializer Using Single Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Single-Output Waveform (Serializer Using Double Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Double-Output Waveform (Serializer Using Single Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Double-Output Waveform (Serializer Using Double Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. SYNC Byte (0x79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 19. ACK Byte (0xC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . . 27
Figure 21. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) . . . . . . . . . 27
Maxim Integrated
4
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
LIST OF FIGURES (continued)
Figure 22. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25. Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 26. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 27. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 28. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 29. 2:1 Coax-Mode Splitter Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 30. Coax-Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 31. State Diagram, Remote Microcontroller Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 32. Human Body Model ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 33. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 34. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LIST OF TABLES
Table 1. Power-Up Default Register Map (see Table 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. Output Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3. Data-Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. I2C Bit-Rate Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. MAX9262 Cable Equalizer Boost Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Parallel Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Configuration Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. Startup Procedure for Video-Display Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Startup Procedure for Image-Sensing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. MAX9272 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12. Staggered Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. Double-Function Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. Typical Power-Supply Currents (Using Worst-Case Input Pattern) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Suggested Connectors and Cables for GMSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. Register Table (see Table 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Maxim Integrated
5
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Absolute Maximum Ratings*
Junction Temperature......................................................+150°C
Operating Temperature Range......................... -40°C to +105°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
AVDD to EP...........................................................-0.5V to +1.9V
DVDD to EP...........................................................-0.5V to +1.9V
IOVDD to EP..........................................................-0.5V to +3.9V
IN+, IN- to EP........................................................-0.5V to +1.9V
All other pins to EP..............................-0.5V to (VIOVDD + 0.5V)
IN+, IN- short circuit to ground or supply .................Continuous
Continuous Power Dissipation (TA = +70°C)
TQFN (derate 40mW/°C above +70°C).......................3200mW
*EP is connected to PCB ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (BJA).............25°C/W
Junction-to-Case Thermal Resistance (BJC)......................1°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground, TA = -40°C to
+105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (I2CSEL, LCCEN, GPI, PWDN, MS/HVEN)
High-Level Input Voltage
VIH1
Low-Level Input Voltage
VIL1
Input Current
IIN1
0.65 x
VIOVDD
VIN = 0V to VIOVDD
-10
V
0.35 x
VIOVDD
V
+20
FA
THREE-LEVEL LOGIC INPUTS (CX/TP)
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Mid-Level Input Current
IINM
Input Current
0.7 x
VIOVDD
(Note 2)
IIN
V
0.3 x
VIOVDD
V
-10
+10
FA
-150
+150
FA
SINGLE-ENDED OUTPUTS (DOUT_, PCLKOUT)
High-Level Output Voltage
Low-Level Output Voltage
Maxim Integrated
VOH1
VOL1
DCS = 0
VIOVDD
- 0.3
DCS = 1
VIOVDD
- 0.2
IOUT = -2mA
IOUT = 2mA
V
DCS = 0
0.3
DCS = 1
0.2
V
6
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground, TA = -40°C to
+105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
DOUT_
Output Short-Circuit Current
IOS
PCLKOUT
MIN
TYP
MAX
15
25
39
3
7
13
20
35
63
5
10
21
15
33
50
5
10
17
VIOVDD = 3.0V to 3.6V
30
54
97
VIOVDD = 1.7V to 1.9V
9
16
32
VO = 0V,
DCS = 0
VIOVDD = 3.0V to 3.6V
VIOVDD = 1.7V to 1.9V
VO = 0V,
DCS = 1
VIOVDD = 3.0V to 3.6V
VIOVDD = 1.7V to 1.9V
VO = 0V,
DCS = 0
VIOVDD = 3.0V to 3.6V
VIOVDD = 1.7V to 1.9V
VO = 0V,
DCS = 1
OPEN-DRAIN INPUTS/OUTPUTS (GPIO0/DBL, GPIO1/BWS, RX/SDA/EDC, TX/SCL/ES, ERR, LOCK)
0.7 x
High-Level Input Voltage
VIH2
VIOVDD
Low-Level Input Voltage
VIL2
Input Current
IIN2
Low-Level Output Voltage
VOL2
IOUT = 3mA
mA
V
0.3 x
VIOVDD
(Note 3)
UNITS
RX/SDA, TX/SCL
-110
+1
LOCK, ERR, GPIO_
-80
+1
DBL, BWS, EDC, ES
-10
+20
VIOVDD = 1.7V to 1.9V
0.4
VIOVDD = 3.0V to 3.6V
0.3
V
FA
V
OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Differential High Output Peak
Voltage, (VIN+) - (VIN-)
VROH
No high-speed data transmission (Figure 1)
30
60
mV
Differential Low Output Peak
Voltage, (VIN+) - (VIN-)
VROL
No high-speed data transmission (Figure 1)
-60
-30
mV
DIFFERENTIAL INPUTS (IN+, IN-)
Differential High Input Threshold
(Peak) Voltage, (VIN+) - (VIN-)
VIDH(P)
(Figure 2)
Activity detector, medium
threshold (0x22 D[6:5] = 01)
60
Activity detector,
low threshold (0x22 D[6:5] = 00)
45
mV
Activity detector, medium
threshold (0x22 D[6:5] = 01)
-60
Activity detector, medium
threshold (0x22 D[6:5] = 00)
-45
Differential Low Input Threshold
(Peak) Voltage, (VIN+) - (VIN-)
VIDL(P)
Input Common-Mode Voltage
((VIN+) + (VIN-))/2
VCMR
1
1.3
1.6
V
RI
80
105
130
I
Differential Input Resistance
(Internal)
Maxim Integrated
(Figure 2)
mV
7
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground, TA = -40°C to
+105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (IN+, IN-)
Single-Ended High Input
Threshold (Peak) Voltage,
(VIN+) - (VIN-)
VIDH(P)
Single-Ended Low Input
Threshold (Peak) Voltage,
(VIN+) - (VIN-)
VIDL(P)
Input Resistance (Internal)
RI
Activity detector, medium threshold
(0x22 D[6:5] = 01)
43
Activity detector, low threshold
(0x22 D[6:5] = 00)
33
mV
Activity detector, medium threshold
(0x22 D[6:5] = 01)
-43
Activity detector, medium threshold
(0x22 D[6:5] = 00)
-33
mV
40
52.5
65
BWS = 0, single output, fPCLKOUT = 25MHz
EQ off
fPCLKOUT = 50MHz
42
65
61
90
BWS = 0, double output, fPCLKOUT = 50MHz
EQ off
fPCLKOUT = 100MHz
42
70
62
90
40
100
FA
5
70
FA
I
POWER SUPPLY
Worst-Case Supply Current
(Figure 3)
IWCS
Sleep Mode Supply Current
ICCS
Power-Down Current
ICCZ
PWDN = EP
VESD
Human Body Model,
IEC 61000-4-2,
RD = 330I,
CS = 150pF
ISO 10605,
RD = 2kI,
CS = 330pF
mA
ESD PROTECTION
IN+, IN- (Note 4)
All Other Pins (Note 5)
VESD
RD = 1.5kI, CS = 100pF
±8
Contact discharge
±10
Air discharge
±15
Contact discharge
±10
Air discharge
±30
kV
±4
Human Body Model, RD = 1.5kI, CS = 100pF
kV
AC Electrical Characteristics
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground, TA = -40°C to
+105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
Clock Frequency
Clock Duty Cycle
Clock Jitter
Maxim Integrated
fPCLKOUT
DC
tJ
BWS = 0, DRS = 1
8.33
16.66
BWS = 0, DRS = 0
16.66
50
BWS = 1, DRS = 1
6.25
12.5
BWS = 1, DRS = 0
12.5
37.5
BWS = 1, DRS = 0, 15-bit double input
25
75
BWS = 0, DRS = 0, 11-bit double input
33.33
100
tHIGH/tT or tLOW/tT (Figure 4, Note 6)
Period jitter, RMS, spread off, 1.5Gbps,
PRBS pattern, UI = 1/fPCLKOUT (Note 6)
40
50
0.05
60
MHz
%
UI
8
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
AC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground, TA = -40°C to
+105°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
9.6
1000
kbps
I2C/UART PORT TIMING
I2C/UART Bit Rate
Output Rise Time
tR
30% to 70%, CL = 10pF to 100pF,
1kI pullup to VIOVDD
20
120
ns
Output Fall Time
tF
70% to 30%, CL = 10pF to 100pF,
1kI pullup to VIOVDD
20
120
ns
Input Setup Time
tSET
I2C only (Figure 5, Note 6)
100
ns
Input Hold Time
tHOLD
I2C only (Figure 5, Note 6)
0
ns
SWITCHING CHARACTERISTICS
PCLKOUT Rise-and-Fall Time
Parallel Data Rise-and-Fall Time
(Figure 6)
Deserializer Delay
tR, tF
tR, tF
tSD
20% to 80%,
VIOVDD = 1.7V to
1.9V (Note 6)
20% to 80%,
VIOVDD = 3.0V to
3.6V (Note 6)
20% to 80%,
VIOVDD = 1.7V to
1.9V (Note 6)
20% to 80%,
VIOVDD = 3.0V to
3.6V (Note 6)
(Figure 7,
Notes 6, 7)
DCS = 1, CL = 10pf
0.4
2.2
DCS = 0, CL = 5pF
0.5
2.8
DCS = 1, CL = 10pF
0.25
1.7
DCS = 0, CL = 5pF
0.3
2.0
DCS = 1, CL = 10pf
0.5
3.1
DCS = 0, CL = 5pF
0.6
3.8
DCS = 1, CL = 10pF
0.3
2.2
DCS = 0, CL = 5pF
0.4
2.4
Spread spectrum
enabled
6960
Spread spectrum
disabled
2160
ns
ns
Bits
Reverse Control-Channel Output
Rise Time
tR
No forward-channel data transmission
(Figure 1, Note 6)
180
400
ns
Reverse Control-Channel Output
Fall Time
tF
No forward-channel data transmission
(Figure 1, Note 6)
180
400
ns
350
Fs
GPI-to-GPO Delay
tGPIO
Deserializer GPI to serializer GPO (cable
delay not included) (Figure 8)
Lock Time
tLOCK
(Figure 9,
Note 6)
Power-Up Time
tPU
(Figure 10)
Spread spectrum enabled
1.5
Spread spectrum disabled
1
6
ms
ms
Note 2: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than Q10FA.
Note 3: IIN min due to voltage drop across the internal pullup resistor.
Note 4: Specified pin to ground.
Note 5: Specified pin to all supply/ground.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured in serial link bit times. Bit time = 1/(30 x fPCLKOUT) for BWS = GND. Bit time = 1/(40 x fPCLKOUT) for BWS = 1.
Maxim Integrated
9
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Typical Operating Characteristics
(VAVDD = VDVDD = VIOVDD = 1.8V, DBL = low, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 0)
60
55
EQ ON
50
45
65
60
55
EQ ON
50
45
40
40
EQ OFF
35
5
10
15
20
25
30
35
40
45
50
5
20
25
30
35
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 0)
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 1)
SUPPLY CURRENT (mA)
SS ON
50
45
PRBS ON, EQ OFF,
COAX MODE
55
40
MAX9272 toc04
MAX9272 toc03
60
SS ON
50
45
40
40
SS OFF
SS OFF
35
35
5
10
15
20
25
30
35
40
45
50
5
10
15
20
25
30
35
40
OUTPUT POWER SPECTRUM vs. PCLKOUT
FREQUENCY (VARIOUS SPREAD)
OUTPUT POWER SPECTRUM vs. PCLKOUT
FREQUENCY (VARIOUS SPREAD)
0% SPREAD
-20
-30
-40
-60
-60
-70
1% SPREAD
-80
18.5
19.0
19.5
fPCLKOUT = 50MHz
-10
0% SPREAD
-20
-30
-40
-60
-60
-70
-80
-90
4% SPREAD
2% SPREAD
-90
0
OUTPUT POWER SPECTRUM (dBm)
-10
fPCLKOUT = 20MHz
MAX9272 toc06
PCLKOUT FREQUENCY (MHz)
MAX9272 toc05
PCLKOUT FREQUENCY (MHz)
0
OUTPUT POWER SPECTRUM (dBm)
15
PCLKOUT FREQUENCY (MHz)
55
2% SPREAD
4% SPREAD
-100
20.0
20.5
21.0
PCLKOUT FREQUENCY (MHz)
Maxim Integrated
10
PCLKOUT FREQUENCY (MHz)
PRBS ON, EQ OFF,
COAX MODE
60
EQ OFF
35
65
SUPPLY CURRENT (mA)
PRBS ON, SS OFF,
COAX MODE
70
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
65
MAX9272 toc02
PRBS ON, SS OFF,
COAX MODE
70
75
MAX9272 toc01
75
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 1)
21.5
47
48
49
50
51
52
53
PCLKOUT FREQUENCY (MHz)
10
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = VIOVDD = 1.8V, DBL = low, TA = +25°C, unless otherwise noted.)
SERIAL LINK SWITCHING PATTERN
WITH 6dB PREEMPHASIS (PARALELL
BIT RATE = 50MHz, 10m STP CABLE)
SERIAL LINK SWITCHING PATTERN
WITH 6dB PREEMPHASIS (PARALELL
BIT RATE = 50MHz, 20m COAX CABLE)
MAX9272 toc07
200ps/div
1.5Gbps
50mv/div
MAXIMUM PCLKOUT FREQUENCY
vs. STP CABLE LENGTH (BER P 10-10)
60
PCLKOUT FREQUENCY (MHz)
OPTIMUM PE/EQ
SETTINGS
40
6dB PE, EQ OFF
NO PE, 10.7dB EQ
20
NO PE, EQ OFF
6dB PE, EQ OFF
40
NO PE, 10.7dB EQ
NO PE, EQ OFF
20
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 10m
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 10m
0
0
5
10
1.5Gbps
MAXIMUM PCLKOUT FREQUENCY
vs. COAX CABLE LENGTH (BER P 10-10)
MAX9272 toc09
PCLKOUT FREQUENCY (MHz)
60
200ps/div
MAX9272 toc10
50mv/div
MAX9272 toc08
0
20
15
0
STP CABLE LENGTH (m)
5
10
15
20
25
COAX CABLE LENGTH (m)
PCLKOUT FREQUENCY (MHz)
60
MAX9272 toc11
MAXIMUM PCLKOUT FREQUENCY
vs. ADDITIONAL DIFFERENTIAL CL (BER P 10-10)
10m STP CABLE OPTIMUM PE/EQ
SETTINGS
50
6dB PE, EQ OFF
40
30
NO PE, 10.7dB EQ
20
NO PE, EQ OFF
BER CAN BE AS LOW AS 10-12 FOR
CL < 4pF FOR OPTIMUM PE/EQ SETTINGS
10
0
0
2
4
6
8
10
ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)
Maxim Integrated
11
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
DOUT19
DOUT18
DOUT17
DOUT16
DOUT15
DOUT14
DOUT13
DOUT12
DOUT11
DOUT10
TOP VIEW
DOUT9
DOUT8
Pin Configuration
36 35 34 33 32 31 30 29 28 27 26 25
DOUT7
37
24
DOUT20
DOUT6
38
23
DOUT21
DOUT5
39
22
DOUT22
DOUT4
40
21
DOUT23
IOVDD
41
20
IOVDD
DOUT3
42
19
DOUT24/HSO
DOUT2
43
18
DOUT25/ VSO
DOUT1
44
17
DOUT27/HS1
DOUT0
45
16
DOUT27/ VS1
PCLKOUT
46
15
LOCK
14
ERR
13
PWDN
8
IN-
9
10 11 12
DVDD
7
TX /SCL / ES
6
GPI
5
RX /SDA /EDC
4
IN+
GPI01/BWS
3
AVDD
2
1
LCCEN
48
CX / TP
AVDD
EP*
I2CSEL
47
+
GPIO0/DBL
MS/HVEN
MAX9272
TQFN
(7mm x 7mm X 0.75mm)
CONNECT EP TO GROUND PLANE
Pin Description
PIN
NAME
FUNCTION
GPIO1/BWS
GPIO/Bus Width Select Input. Function is determined by the state of LCCEN (Table 13).
GPIO1 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kI pullup to IOVDD.
BWS (LCCEN = low): Input with internal pulldown to EP. Set BWS = low for 22-bit input latch. Set
BWS = high for 30-bit input latch.
2
GPIO0/DBL
GPIO/Double-Mode Input. Function is determined by the state of LCCEN (Table 13).
GPIO0 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kI pullup to IOVDD.
DBL (LCCEN = low): Input with internal pulldown to EP. Set DBL = high to use double-input mode.
Set DBL = low to use single-input mode.
3
CX/TP
Coax/Twisted-Pair Three-Level Configuration Input (Table 8)
4
I2CSEL
I2C Select. Control-channel interface protocol select input with internal pulldown to EP.
Set I2CSEL = high to select I2C slave interface. Set I2CSEL = low to select UART interface.
1
Maxim Integrated
12
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Pin Description (continued)
PIN
NAME
FUNCTION
5
LCCEN
6, 48
AVDD
7
IN+
Noninverting Coax/Twisted-Pair Serial Input
8
IN-
Inverting Coax/Twisted-Pair Serial Input
9
GPI
General-Purpose Input. The GMSL deserializer GPI (or INT) input follows GPI.
Local Control-Channel Enable Input with Internal Pulldown to EP. LCCEN = high enables the controlchannel interface pins. LCCEN = low disables the control-channel interface pins and selects an
alternate function on the indicated pins (Table 13).
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1FF and 0.001FF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD.
RX/SDA/EDC
Receive/Serial Data/Error Detection Correction. Function is determined by the state of LCCEN (Table 13).
RX/SDA (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA
is the Rx input of the MAX9272’s UART. In the I2C mode, RX/SDA is the SDA input/output of the
MAX9272’s I2C master/slave. RX/SDA has an open-drain driver and requires a pullup resistor.
EDC (LCCEN = low): Input with internal pulldown to EP. Set EDC = high to enable error detection
correction. Set EDC = low to disable error detection correction.
11
TX/SCL/ES
Transmit/Serial Clock/Edge Select. Function is determined by the state of LCCEN (Table 13).
TX/SCL (LCCEN = high). Input/output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL
is the Tx output of the MAX9272’s UART. In the I2C mode, TX/SCL is the SCL input/output of the
MAX9272’s I2C master/slave. TX/SCL has an open-drain driver and requires a pullup resistor.
ES (LCCEN = low): Input with internal pulldown to EP. When ES is high, PCLKOUT indicates valid
data on the falling edge of PCLKOUT. When ES is low, PCLKOUT indicates valid data on the rising
edge of PCLKOUT. Do not change the ES input while the pixel clock is running.
12
DVDD
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD.
13
PWDN
Active-Low Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter power-down mode
to reduce power consumption.
14
ERR
10
Error Output. Open-drain data error detection and/or correction indication output with internal 60kI
pullup to IOVDD. ERR is an open-drain driver and requires a pullup resistor.
Open-Drain Lock Output with Internal 60kI Pullup to IOVDD. LOCK = high indicates that PLLs are
locked with correct serial-word-boundary alignment. LOCK = low indicates that PLLs are not locked or
an incorrect serial-word-boundary alignment. LOCK remains low when the configuration link is active
or during PRBS test. LOCK is high impedance when PWDN = low. LOCK is an open-drain driver and
requires a pullup resistor.
15
LOCK
16
DOUT27/VS1
Parallel Data/Vertical Sync 1 Output. Defaults to parallel data input on power-up.
Parallel data output when VS/HS encoding is disabled.
Decoded vertical sync for upper half of single output when VS/HS encoding is enabled (Table 2).
17
DOUT26/HS1
Parallel Data/Horizontal Sync 1 Output. Defaults to parallel data input on power-up.
Parallel data output when VS/HS encoding is disabled.
Decoded horizontal sync for upper half of single-output when VS/HS encoding is enabled (Table 2).
18
DOUT25/VS0
Parallel Data/Vertical Sync 0 Output. Defaults to parallel data input on power-up.
Parallel data output when VS/HS encoding is disabled.
Decoded vertical sync for lower half of single-output when VS/HS encoding is enabled (Table 2).
Maxim Integrated
13
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Pin Description (continued)
PIN
NAME
FUNCTION
19
DOUT24/HS0
20, 41
IOVDD
21–40,
42–45
DOUT23–
DOUT0
Parallel Data Outputs
46
PCLKOUT
Parallel Clock Output. Latches parallel data into the input of another device.
47
MS/HVEN
Mode Select/HS and VS Encoding Enable with Internal Pulldown to EP. Function is determined by the
state of LCCEN (Table 13).
MS (LCCEN = high). Set MS = low to select base mode. Set MS = high to select the bypass mode.
HVEN (LCCEN = low): Set HVEN = high to enable HS/VS encoding on DOUT_/HS_ and DOUT_/VS_.
Set HVEN = low to use DOUT_/HS_ and DOUT_/VS_ as parallel data outputs.
—
EP
Parallel Data/Horizontal Sync 0 Output. Defaults to parallel data input on power-up.
Parallel data output when VS/HS encoding is disabled.
Decoded horizontal sync for lower half of single-output when VS/HS encoding is enabled (Table 2).
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1FF and 0.001FF
capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB ground
plane through an array of vias for proper thermal and electrical performance.
Functional Diagram
PCLKOUT
SSPLL
CLKDIV
CDRPLL
DOUT [23:0]
IN+
SERIAL
TO
PARALLEL
DOUT24/HS0
DOUT25/ VS0
DOUT26/HS1
CML Rx
AND EQ
FIFO
DOUT27/ VS1
SCRAMBLE/
CRC/
HAMMING/
8b/10b
DECODE
1x[27:0]
OR
2x[10:0]
OR
2x[14:0]
Tx
REVERSE
CONTROL
CHANNEL
VS /HS
GPIO0/DBL
GPIO1/BWS
GPI
FCC
MAX9272
GPIO
UART/I2C
TX/SCL/ES
Maxim Integrated
IN-
RX/SDA/EDC
14
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
RL/2
IN+
REVERSE
CONTROL-CHANNEL
TRANSMITTER
VOD
VCMR
IN-
RL/2
IN+
IN-
IN-
IN+
VCMR
VROH
0.9 x VROH
(IN+) - (IN-)
0.1 x VROH
0.1 x VROL
tR
0.9 x VROL
VROL
tF
Figure 1. Reverse Control-Channel Output Parameters
Maxim Integrated
15
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
RL/2
IN+
VIN+
PCLKOUT
VID(P)
RL/2
IN-
_
+
_
CIN
+
_
VIN-
CIN
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
VID(P) = | VIN+ - VIN- |
VCMR = (VIN+ + VIN-)/2
Figure 2. Test Circuit for Differential Input Measurement
Figure 3. Worst-Case Pattern Output
tT
VOH MIN
tHIGH
PCLKOUT
VOL MAX
tLOW
Figure 4. Parallel Clock Output High and Low Times
START
CONDITION
(S)
PROTOCOL
tSU;STA
BIT 7
MSB
(A7)
tLOW
BIT 6
(A6)
tHIGH
BIT 0
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
1/fSCL
SCL
tSP
tBUF
tr
tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
Figure 5. I2C Timing Parameters
Maxim Integrated
16
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
CL
SINGLE-ENDED OUTPUT LOAD
0.8 x VI0VDD
0.2 x VI0VDD
tR
tF
Figure 6. Output Rise-and-Fall Times
SERIAL-WORD LENGTH
SERIAL WORD N
SERIAL WORD N+1
SERIAL WORD N+2
IN+/FIRST BIT
DOUT_
LAST BIT
PARALLEL WORD N-1
PARALLEL WORD N-2
PARALLEL WORD N
PCLKOUT
tSD
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 7. Deserializer Delay
VIH_MIN
DESERIALIZER
GPI
VIL_MAX
tGPIO
SERIALIZER
GPO
tGPIO
VOH_MIN
VOL_MAX
Figure 8. GPI-to-GPO Delay
Maxim Integrated
17
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
IN+/-
IN+ - IN-
PWDN
tLOCK
LOCK
VIH1
tPU
VOH
LOCK
VOH
PWDN MUST BE HIGH
Figure 9. Lock Time
Figure 10. Power-Up Delay
Detailed Description
The MAX9272 deserializer, when paired with the
MAX9271 or MAX9273 serializer, provides the full set of
operating features, but offers basic functionality when
paired with any GMSL serializer.
The deserializer has a maximum serial-bit rate of 1.5Gbps
for 15m or more of cable and operates up to a maximum
output clock of 50MHz in 28-bit, single-output mode, or
75MHz to 100MHz in 15-bit /11-bit, double-output mode,
respectively. This bit rate and output flexibility support
a wide range of displays, from QVGA (320 x 240) to
WVGA (800 x 480) and higher with 18-bit color, as well as
megapixel image sensors. Input equalization, combined
with GMSL serializer pre/deemphasis, extends the cable
length and enhances link reliability
The control channel enables a FC to program the serializer and deserializer registers and program registers on
peripherals. The control channel is also used to configure
and access the GPIO. The FC can be located at either
end of the link, or when using two FCs, at both ends.
Two modes of control-channel operation are available.
Base mode uses either I2C or GMSL UART protocol,
while bypass mode uses a user-defined UART protocol.
UART protocol allows full-duplex communication, while
I2C allows half-duplex communication.
Spread spectrum is available to reduce EMI on the parallel output. The serial input complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
Maxim Integrated
Register Mapping
Registers set the operating conditions of the deserializer
and are programmed using the control channel in base
mode. The deserializer holds its device address and the
device address of the serializer it is paired with. Similarly,
the serializer holds its device address and the address of
the deserializer. Whenever a device address is changed,
the new address should be written to both devices. The
default device address of the deserializer is set by the
CX/TP input and the default device address of any GMSL
serializer is 0x80 (see Table 1 and Table 8). Registers
0x00 and 0x01 in both devices hold the device addresses.
Bit Map
The parallel output functioning and width depend on
settings of the double-/single-output mode (DBL), HS/VS
encoding (HVEN), error correction used (EDC), and bus
width (BWS) pins. Table 2 lists the bit map for the control
pin settings. Unused output bits are pulled low.
The parallel output has two output modes: single and
double output. In single-output mode, the deserialized
parallel data is clocked out every PCLKOUT cycle. The
device accepts pixel clocks from 6.25MHz to 50MHz
(Figures 11 and 12).
In double-output mode, the device splits deserialized
data into two half-sized words that are output at twice the
serial-word rate (Figures 13 and 14). The serializer/deserializer use pixel clock rates from 33.3MHz to 100MHz
for 11-bit, double-output mode and 25MHz to 75MHz for
15-bit, double-output mode.
18
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
PCLKOUT
DOUT[27:0] OR
DOUT[21:0]
FIRST WORD
SECOND WORD
THIRD WORD
FOURTH WORD
VS0, VS1
VS (FROM FIRST WORD)
VS (FROM SECOND WORD)
VS (FROM THIRD WORD)
VS (FROM FOURTH WORD)
HS0, HS1
HS (FROM FIRST WORD)
HS (FROM SECOND WORD)
HS (FROM THIRD WORD)
HS (FROM FOURTH WORD)
NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS_ /HS_. VS_ /HS_ HAVE MINIMUM LENGTH REQUIREMENTS.
NOTE: HS_, VS_ ACTIVE ONLY WHEN HVEN = 1.
Figure 11. Single-Output Waveform (Serializer Using Single Input)
PCLKOUT
DOUT[14:0] OR
DOUT[10:0]
FIRST WORD (FROM LATCH A)
SECOND WORD (FROM LATCH A)
THIRD WORD (FROM LATCH A)
FOURTH WORD (FROM LATCH A)
DOUT[27:15] OR
DOUT[21:11]
FIRST WORD (FROM LATCH B)
SECOND WORD (FROM LATCH B)
THIRD WORD (FROM LATCH B)
FOURTH WORD (FROM LATCH B)
VS0, HS0
FIRST WORD (FROM LATCH A)
SECOND WORD (FROM LATCH A)
THIRD WORD (FROM LATCH A)
FOURTH WORD (FROM LATCH A)
VS1, HS1
FIRST WORD (FROM LATCH B)
SECOND WORD (FROM LATCH B)
THIRD WORD (FROM LATCH B)
FOURTH WORD (FROM LATCH B)
NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS_ /HS_. VS_ /HS_ HAVE MINIMUM LENGTH REQUIREMENTS.
NOTE: HS_, VS_ ACTIVE ONLY WHEN HVEN = 1.
Figure 12. Single-Output Waveform (Serializer Using Double Input)
Maxim Integrated
19
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
PCLKOUT
DOUT[14:0] OR
DOUT[10:0]
DOUTA FIRST WORD
VS0, HS0
(SERIALIZER
DBL = 0)
DOUTB FIRST WORD
DOUTA SECOND WORD
FIRST WORD
DOUTB SECOND WORD
SECOND WORD
NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS0 /HS0. VS0 /HS0 HAVE MINIMUM LENGTH REQUIREMENTS.
NOTE: HS0, VS0 ACTIVE ONLY WHEN HVEN = 1.
Figure 13. Double-Output Waveform (Serializer Using Single Input)
PCLKOUT
DOUT[14:0] OR
DOUT[10:0]
DOUTA FIRST WORD
DOUTB FIRST WORD
DOUTA SECOND WORD
DOUTB SECOND WORD
VS0, HS0
(SERIALIZER
DBL = 1)
DOUTA FIRST WORD
DOUTB FIRST WORD
DOUTA SECOND WORD
DOUTB SECOND WORD
NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS0 /HS0. VS0 /HS0 HAVE MINIMUM LENGTH REQUIREMENTS.
NOTE: HS0, VS0 ACTIVE ONLY WHEN HVEN = 1.
Figure 14. Double-Output Waveform (Serializer Using Double Input)
Maxim Integrated
20
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 1. Power-Up Default Register Map (see Table 16)
REGISTER
ADDRESS
(hex)
POWER-UP
DEFAULT
(hex)
0x00
0x80
0x01
0x90 or
0x92
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
SERID = 1000000, serializer device address
RESERVED = 0
DESID = 1001000 (CX/TP = high or low), DESID = 1001001 (CX/TP = midlevel), deserializer
device address is determined by the state of the CX/TP input at power-up
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
0x02
0x1F
SS = 00, spread spectrum disabled
RESERVED = 01
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
0x03
0x00
AUTOFM = 00, calibrate spread-modulation rate only once after locking
RESERVED = 0
SDIV = 00000, autocalibrate sawtooth divider
0x07
LOCKED = 0, LOCK output is low (read only)
OUTENB = 0, output enabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0, sleep mode deactivated (see the Link Startup Procedure section)
INTTYPE = 01, base mode uses UART
REVCCEN = 1, reverse control channel active (sending)
FWDCCEN = 1, forward control channel active (receiving)
0x05
0x24
I2CMETHOD = 0, I2C master sends the register address
DCS = 0, normal parallel output driver current
HVTRMODE = 1, full periodic HS/VS tracking
ENEQ = 0, equalizer disabled
EQTUNE = 1001, 10.7dB equalization
0x06
0x02 or 0x22
0x04
0x07
Maxim Integrated
0xXX
RESERVED = 00X00010
DBL = 0 or 1, single-/double-input mode setting determined by the state of LCCEN and
GPIO0/DBL at startup
DRS = 0, high data-rate mode
BWS = 0 or 1, bit width setting determined by the state of LCCEN and GPIO1/BWS at startup
ES = 0 or 1, edge-select input setting determined by the state of LCCEN and TX/SCL/ES at startup
HVTRACK = 0 or 1, HS/VS tracking setting determined by the state of LCCEN and MS/HVEN at
startup
HVEN = 0 or 1, HS/VS tracking encoding setting determined by the state of LCCEN and MS/HVEN
at startup
EDC = 00 or 10, error-detection/correction setting determined by the state of LCCEN and
RX/SDA/EDC at startup
21
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 1. Power-Up Default Register Map (see Table 16) (continued)
REGISTER
ADDRESS
(hex)
POWER-UP
DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
0x08
0x00
INVVS = 0, deserializer does not invert VSYNC
INVHS = 0, deserializer does not invert HSYNC
RESERVED = 0
UNEQDBL = 0, serializer DBL is not the same as deserializer
DISSTAG = 0, outputs are staggered
AUTORST = 0, error registers/output autoreset disabled
ERRSEL = 00, detected errors trigger ERR
0x09
0x00
I2CSCRA = 0000000, I2C address translator source A is 0x00
RESERVED = 0
0x0A
0x00
I2CDSTA = 0000000, I2C address translator destination A is 0x00
RESERVED = 0
0x0B
0x00
I2CSCRB = 0000000, I2C address translator source B is 0x00
RESERVED = 0
0x0C
0x00
I2CDSTB = 0000000, I2C address translator destination B is 0x00
RESERVED = 0
0x36
I2CLOCACK = 0, acknowledge not generated when forward channel is not available
I2CSLVSH = 01, 469ns/234ns I2C setup/hold time
I2CMSTBT = 101, 339kbps (typ) I2C-to-I2C master bit-rate setting
I2CSLVTO = 10, 1024Fs (typ) I2C-to-I2C slave remote timeout
0x0E
0x6A
RESERVED = 01
GPIEN = 1, enable GPI-to-GPO signal transmission to serializer
GPIIN = 0, GPI input is low (read only)
GPIO1OUT = 1, set GPIO1 to high
GPIO1IN = 0, GPIO1 input is low (read only)
GPIO0OUT = 1, set GPIO0 to high
GPIO0IN = 0, GPIO0 input is low (read only)
0x0F
0x00
DETTHR = 00000000, error threshold set to zero for detected errors
0x10
0x00
(read only)
0x11
0x00
0x12
0x00
(read only)
CORRERR = 00000000, zero errors corrected
0x13
0x00
(read only)
PRBSERR = 00000000, zero PRBS errors detected
0x14
0x00
(read only)
PRBSOK = 0, PRBS test not completed
RESERVED = 0000000
0x15
0x2X
RESERVED = 00100XXX
0x16
0x30
RESERVED = 00110000
0x17
0x54
RESERVED = 01010100
0x18
0x30
RESERVED = 00110000
0x0D
Maxim Integrated
DETERR = 00000000, zero errors detected
CORRTHR = 00000000, error threshold set to zero for corrected errors
22
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 1. Power-Up Default Register Map (see Table 16) (continued)
REGISTER
ADDRESS
(hex)
POWER-UP
DEFAULT
(hex)
0x19
0xC8
RESERVED = 11001000
0x1A
0xXX
(read only)
RESERVED = XXXXXXXX
0x1B
0xXX
(read only)
RESERVED = XXXXXXXX
0x1C
0xXX
(read only)
RESERVED = XXXXXXXX
0x1D
0x0X
(read only)
CXTP = 0, twisted-pair input
CXSEL = 0, noninverting input
I2CSEL = 0, UART input
LCCEN = 0, local control channel disabled
RESERVED = XXXX
0x1E
0x0A
(read only)
ID = 00001010, device ID is 0x0A
0x1F
0x0X
(read only)
RESERVED = 000
CAPS = 0, not HDCP capable
REVISION = XXXX
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
X = Indeterminate.
Table 2. Output Map
EDC
BWS
DBL
HVEN
DOUTA
DOUTB*
0
0
0
0
0:21
—
SERIAL LINK WORD BITS
0:21
0
0
0
1
0:17, 20:21, HS, VS
—
0:17, 20:21
0
0
1
0
0:10
0:10
0:21
0
0
1
1
0:10, HS, VS
0:10, HS, VS
0:21
0
1
0
0
0:21
—
0:21
0
1
0
1
0:17, 20:21, HS, VS
—
0:17, 20:21
0
1
1
0
0:14
0:14
0:29
0
1
1
1
0:14, HS, VS
0:14, HS, VS
0:29
1
0
0
0
0:15
—
0:15
1
0
0
1
0:15, HS, VS
—
0:15
1
0
1
0
0:7
0:7
0:15
1
0
1
1
0:7, HS, VS
0:7, HS, VS
0:15
1
1
0
0
0:21
—
0:21
1
1
0
1
0:17, 20:21, HS, VS
—
0:17, 20:21
1
1
1
0
0:11
0:11, HS, VS
0:23
1
1
1
1
0:11, HS, VS
0:11, HS, VS
0:23
*In double-output mode (DBL = 1), DOUTA output on the first cycle of PCLKOUT and DOUTB output on the second cycle of
PCLKOUT.
Maxim Integrated
23
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Serial Link Signaling and Data Format
opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
same serial cable, forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 2ms after power-up. The serializer temporarily
disables the reverse control channel for 350Fs after starting/stopping the forward serial link.
The serializer uses differential CML signaling to drive
twisted-pair cable and single-ended CML to drive
coax cable with programmable pre/deemphasis and
AC-coupling. The deserializer uses AC-coupling and
programmable channel equalization.
Input data is scrambled and then 8b/10b coded. The
deserializer recovers the embedded serial clock, then
samples, decodes, and descrambles the data. In 24-bit
or 32-bit mode, 22 or 30 bits contain the video data
and/or error-correction bits, if used. The 23rd or 31st bit
carries the forward control-channel data. The last bit is
the parity bit of the previous 23 or 31 bits (Figure 15).
Data-Rate Selection
The serializer/deserializer use DRS, DBL, and BWS to set
the PCLKOUT frequency range (Table 3). Set DRS = 1
for a PCLKOUT frequency range of 6.25MHz to 12.5MHz
(32-bit, single-output mode) or 8.33MHz to 16.66MHz
(24-bit, single-output mode). Set DRS = 0 for normal
operation. It is not recommended to use double-output
mode when DRS = 1.
Reverse Control Channel
The serializer uses the reverse control channel to receive
I2C/UART and GPO signals from the deserializer in the
Table 3. Data-Rate Selection Table
DRS SETTING
DBL SETTING
BWS SETTING
PCLKOUT RANGE (MHz)
0
0 (single input)
0 (24-bit mode)
16.66 to 50
0
0
1 (32-bit mode)
12.5 to 35
0
1 (double input)
0
33.3 to 100
0
1
1
25 to 75
1
0
0
8.33 to 16.66
1
0
1
6.25 to 12.5
1
1
0
Do Not Use
1
1
1
Do Not Use
24 BITS
D0
D1
VIDEO AND ERROR
CORRECTION DATA
32 BITS
D21
FCC
PCB
FORWARD
CONTROLCHANNEL BIT
PACKET
PARITY
CHECK BIT
D0
D1
D29
VIDEO AND ERROR
CORRECTION DATA
FCC
PCB
FORWARD
CONTROLCHANNEL BIT
PACKET
PARITY
CHECK BIT
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
Figure 15. Serial-Data Format
Maxim Integrated
24
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Control Channel and
Register Programming
The control channel is available for the FC to send and
receive control data over the serial link simultaneously
with the high-speed data. The FC controls the link from
either the serializer or the deserializer side to support
video-display or image-sensing applications. The control
channel between the FC and serializer or deserializer
runs in base mode or bypass mode, according to the
mode selection (MS/HVEN) input of the device connected to the FC. Base mode is a half-duplex control channel
and bypass mode is a full-duplex control channel.
UART Interface
In base mode, the FC is the host and can access the
registers of both the serializer and deserializer from
either side of the link using the GMSL UART protocol.
The FC can also program the peripherals on the remote
side by sending the UART packets to the serializer or
deserializer, with the UART packets converted to I2C
by the device on the remote side of the link. The FC
communicates with a UART peripheral in base mode
(through INTTYPE register settings), using the halfduplex default GMSL UART protocol of the serializer/deserializer. The device addresses of the serializer/
deserializer in base mode are programmable. The
default value is 0x80 for the serializer and is determined
by the CX/TP input for the deserializer (Table 8).
When the peripheral interface is I2C, the serializer/
deserializer convert UART packets to I2C that have
device addresses different from those of the serializer or
deserializer. The converted I2C bit rate is the same as the
original UART bit rate.
The deserializer uses differential line coding to send
signals over the reverse channel to the serializer. The
bit rate of the control channel is 9.6kbps to 1Mbps in
both directions. The serializer/deserializer automatically
detect the control-channel bit rate in base mode. Packet
bit-rate changes can be made in steps of up to 3.5
times higher or lower than the previous bit rate. See the
Changing the Clock Frequency section for more information on changing the control-channel bit rate.
Figure 16 shows the UART protocol for writing and reading in base mode between the FC and the serializer/
deserializer.
Figure 17 shows the UART data format. Figure 18 and
Figure 19 detail the formats of the SYNC byte (0x79)
and the ACK byte (0xC3). The FC and the connected
slave chip generate the SYNC byte and ACK byte,
respectively. Events such as device wake-up and GPI
generate transitions on the control channel that can be
ignored by the FC. Data written to the serializer/deserializer registers do not take effect until after the ACK byte
is sent. This allows the FC to verify that write commands
are received without error, even if the result of the write
command directly affects the serial link. The slave uses
the SYNC byte to synchronize with the host UART’s data
rate. If the GPI or MS/HVEN inputs of the deserializer
toggle while there is control-channel communication, or if
a line fault occurs, the control-channel communication is
corrupted. In the event of a missed or delayed acknowledge (~1ms due to control-channel timeout), the FC
should assume there was an error in the packet when the
slave device received it, or that an error occurred during
the response from the slave device. In base mode, the
FC must keep the UART Tx/Rx lines high for 16 bit times
before starting to send a new packet.
WRITE DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
BYTE 1
BYTE N
ACK
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE
READ DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 16. GMSL UART Protocol for Base Mode
Maxim Integrated
25
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
1 UART FRAME
START
D0
D1
D2
D3
FRAME 1
D4
D5
D6
D7
PARITY
STOP
FRAME 2
STOP
FRAME 3
START
STOP
START
Figure 17. GMSL UART Data Format for Base Mode
START
D0
D1
D2
D3
D4
D5
D6
D7
1
0
0
1
1
1
1
0
PARITY STOP
START
D0
D1
D2
D3
D4
D5
D6
D7
1
1
0
0
0
0
1
1
PARITY STOP
Figure 18. SYNC Byte (0x79)
Figure 19. ACK Byte (0xC3)
As shown in Figure 20, the remote-side device converts
packets going to or coming from the peripherals from
UART format to I2C format and vice versa. The remote
device removes the byte number count and adds or
receives the ACK between the data bytes of I2C. The I2C
bit rate is the same as the UART bit rate.
connected to the deserializer, there is a 1ms wait time
between setting MS/HVEN high and the bypass control channel being active. There is no delay time when
switching to bypass mode when the FC is connected to
the serializer. Do not send a logic-low value longer than
100Fs to ensure proper GPO functionality. Bypass mode
accepts bit rates down to 10kbps in either direction. See
the GPO/GPI Control section for GPI functionality limitations. The control-channel data pattern should not be
held low longer than 100Fs if GPI control is used.
Interfacing Command-Byte-Only
I2C Devices with UART
The serializer/deserializer UART-to-I2C conversion can
interface with devices that do not require register addresses, such as the MAX7324 GPIO expander. In this mode,
the I2C master ignores the register address byte and
directly reads/writes the subsequent data bytes (Figure
21). Change the communication method of the I2C master using the I2CMETHOD bit. I2CMETHOD = 1 sets
command-byte-only mode, while I2CMETHOD = 0 sets
normal mode where the first byte in the data stream is
the register address.
UART Bypass Mode
In bypass mode, the serializer/deserializer ignore UART
commands from the FC and the FC communicates with
the peripherals directly using its own defined UART protocol. The FC cannot access the serializer/deserializer
registers in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKOUT period Q 10ns of jitter
due to the asynchronous sampling of the UART signal
by PCLKOUT. Set MS/HVEN = high to put the control
channel into bypass mode. For applications with the FC
Maxim Integrated
I2C Interface
In I2C-to-I2C mode, the deserializer’s control-channel interface sends and receives data through an I2C-compatible
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master and slave(s). A FC
master initiates all data transfers to and from the device
and generates the SCL clock that synchronizes the data
transfer. When an I2C transaction starts on the local-side
device’s control-channel port, the remote-side device’s
control-channel port becomes an I2C master that interfaces with remote-side I2C perhipherals. The I2C master
must accept clock stretching, which is imposed by the
deserializer (holding SCL low). The SDA and SCL lines
operate as both an input and an open-drain output. Pullup
resistors are required on SDA and SCL. Each transmission
consists of a START condition (Figure 5) sent by a master,
followed by the device’s 7-bit slave address plus a R/W
bit, a register address byte, one or more data bytes, and
finally a STOP condition.
26
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
FC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
DEVICE ID + WR
SERIALIZER/DESERIALIZER
11
REGISTER ADDRESS
11
NUMBER OF BYTES
11
DATA 0
11
DATA N
11
ACK FRAME
PERIPHERAL
1
S
7
DEV ID
1 1
W A
8
REG ADDR
8
DATA 0
1
A
1
A
8
DATA N
1 1
A P
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)
FC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
DEVICE ID + RD
SERIALIZER/DESERIALIZER
11
REGISTER ADDRESS
11
NUMBER OF BYTES
11
ACK FRAME
11
DATA 0
11
DATA N
PERIPHERAL
1
S
7
DEV ID
8
REG ADDR
1 1
W A
1 1
A S
: SLAVE TO MASTER
: MASTER TO SLAVE
7
DEV ID
1 1
R A
S: START
8
DATA 0
P: STOP
1
A
8
DATA N
1 1
A P
A: ACKNOWLEDGE
Figure 20. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
FC
11
SYNC FRAME
SERIALIZER/DESERIALIZER
11
DEVICE ID + WR
SERIALIZER/DESERIALIZER
FC
11
REGISTER ADDRESS
PERIPHERAL
1
7
S DEV ID
11
NUMBER OF BYTES
11
DATA N
1 1
W A
8
DATA 0
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)
SERIALIZER/DESERIALIZER
11
11
11
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS
SERIALIZER/DESERIALIZER
11
DATA 0
11
NUMBER OF BYTES
11
ACK FRAME
11
ACK FRAME
1
A
8
DATA N
11
DATA 0
1 1
A P
11
DATA N
PERIPHERAL
1
S
: MASTER TO SLAVE
: SLAVE TO MASTER
7
DEV ID
S: START
1 1
R A
8
DATA 0
P: STOP
1
A
8
DATA N
1 1
A P
A: ACKNOWLEDGE
Figure 21. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1)
Maxim Integrated
27
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (Figure 22). When the master has
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 23). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure
24). Thus, each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the forward control channel is not active (not locked). To prevent
acknowledge generation when the forward control channel is not active, set the I2CLOCACK bit low.
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
Figure 22. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 23. Bit Transfer
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
SCL
2
8
9
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 24. Acknowledge
Maxim Integrated
28
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
beyond storing the register address (Figure 26). Any
bytes received after the register address are data bytes.
The first data byte goes into the register selected by the
register address, and subsequent data bytes go into
subsequent registers (Figure 27). If multiple data bytes
are transmitted before a STOP condition, these bytes
are stored in subsequent registers because the register
addresses autoincrement.
Slave Address
The serializer/deserializer have a 7-bit-long slave address.
The bit following a 7-bit slave address is the R/W bit, which
is low for a write command and high for a read command.
The slave address is 100100X1 for read commands and
100100X0 for write commands. See Figure 25.
Bus Reset
The device resets the bus with the I2C START condition
for reads. When the R/W bit is set to 1, the serializer/
deserializer transmit data to the master, thus the master
is reading from the device.
Format for Reading
The serializer/deserializer are read using the internally
stored register address as an address pointer, the same
way the stored register address is used as an address
pointer for a write. The pointer autoincrements after each
data byte is read using the same rules as for a write. Thus,
a read is initiated by first configuring the register address
by performing a write (Figure 28). The master can now
read consecutive bytes from the device, with the first data
byte being read from the register address pointed by
the previously written register address. Once the master
sends a NACK, the device stops sending valid data.
Format for Writing
A write to the serializer/deserializer comprises the transmission of the slave address with the R/W bit set to zero,
followed by at least one byte of information. The first
byte of information is the register address or command
byte. The register address determines which register of
the device is to be written by the next byte, if received.
If a STOP (P) condition is detected after the register
address is received, the device takes no further action
0
0
1
SDA
1
0
0
1/0
R/W
MSB
ACK
LSB
SCL
Figure 25. Slave Address
0 = WRITE
ADDRESS = 0x80
S
1
0
0
0
0
REGISTER ADDRESS = 0x00
0
0
0
A
0
0
0
0
0
0
REGISTER 0x00 WRITE DATA
0
0
A
D7
D6
D5
0
0
A
D1
D0
N
D4
D3
D2
D1
D0
A
P
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
Figure 26. Format for I2C Write
0 = WRITE
ADDRESS = 0x80
S
1
0
0
0
0
REGISTER ADDRESS = 0x0000
0
0
0
A
0
0
REGISTER 0x00 WRITE DATA
D7
D6
D5
D4
D3
D2
0
0
0
0
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
REGISTER 0x02 WRITE DATA
D1
D0
A
D7
D6
D5
D4
D3
D2
P
Figure 27. Format for Write to Multiple Registers
Maxim Integrated
29
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
0 = WRITE
ADDRESS = 0x80
S
1
0
0
0
0
REGISTER ADDRESS = 0x00
0
0
0
A
0
0
0
0
0
0
0
0
A
D1
D0
N
1 = READ
ADDRESS = 0x81
REPEATED START
S
1
0
0
0
0
REGISTER 0x00 READ DATA
0
0
0
A
D7
D6
D5
D4
D3
D2
P
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
Figure 28. Format for I2C Read
Table 4. I2C Bit-Rate Ranges
LOCAL BIT RATE
REMOTE BIT-RATE RANGE
I2CMSTBT SETTING
f > 50kbps
Up to 1Mbps
Any
20kbps > f > 50kbps
Up to 400kbps
Up to 110
f < 20kbps
Up to 10kbps
000
I2C Communication with Remote-Side Devices
The deserializer supports I2C communication with a
peripheral on the remote side of the communication link
using SCL clock stretching. While multiple masters can
reside on either side of the communication link, arbitration
is not provided. The connected masters need to support SCL clock stretching. The remote-side I2C bit-rate
range must be set according to the local-side I2C bit rate.
Supported remote-side bit rates can be found in Table 4.
Set the I2CMSTBT (register 0x0D) to set the remote I2C bit
rate. If using a bit rate different than 400kbps, local- and
remote-side I2C setup and hold times should be adjusted
by setting the SLV_SH register settings on both sides.
I2C Address Translation
The deserializer supports I2C address translation for
up to two device addresses. Use address translation
to assign unique device addresses to peripherals with
limited I2C addresses. Source addresses (address to
translate from) are stored in registers 0x09 and 0x0B.
Destination addresses (address to translate to) are
stored in registers 0x0A and 0x0C.
Maxim Integrated
Control-Channel Broadcast Mode
The deserializer supports broadcast commands to control multiple peripheral devices. Select an unused device
address to use as a broadcast device address. Program
the remote-side GMSL device to translate the broadcast
device address (source address stored in registers 0x09,
0x0B) to the peripheral device address (destination
address stored in registers 0x0A, 0x0C). Any commands
sent to the broadcast address are sent to all designated
peripherals, while commands sent to a peripheral’s unique
device address are sent to that particular device only.
GPO /GPI Control
GPO on the serializer follows GPI transitions on the
deserializer. This GPO/GPI function can be used to
transmit signals such as frame sync in a surround-view
camera system. The GPI-to-GPO delay is 0.35ms (max).
Keep the time between GPI transitions to a minimun
0.35ms. This includes transitions from the other deserializer in coax-splitter mode. Bit D4 of register 0x0E in
the deserializer stores the GPI input state. GPO is low
after power-up. The FC can set GPO by writing to the
serializer SET_GPO register bit. Do not send a logic-low
value on the deserializer RX/SDA input (UART mode)
longer than 100Fs in either base or bypass mode to
ensure proper GPO /GPI functionality.
30
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
PRBS Test
spectrum modulation frequency within 20kHz to 40kHz.
Additionally, manual configuration of the sawtooth divider
(SDIV: 0x03, D[5:0]) allows the user to set a modulation
frequency according to the PCLKOUT frequency. When
ranges are manually selected, program the SDIV value
for a fixed modulation frequency around 20kHz.
Line Equalizer
Manual Programming
of the Spread-Spectrum Divider
The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To run
the PRBS test, set PRBSEN = 1 (0x04, D5) in the deserializer and then in the serializer. To exit the PRBS test, set
PRBSEN = 0 (0x04, D5) in the serializer.
The deserializer includes an adjustable line equalizer to
further compensate cable attenuation at high frequencies. The cable equalizer has 11 selectable levels of
compensation from 2.1dB to 13dB (Table 5). The device
powers up with the equalizer disabled. To select other
equalization levels, set the corresponding register bits
in the deserializer (0x05 D[3:0]). Use equalization in the
deserializer, together with preemphasis in the serializer,
to create the most reliable link for a given cable.
Spread Spectrum
To reduce the EMI generated by transitions, the deserializer output is programmable for spread spectrum. If
the serializer driving the deserializer has programmable
spread spectrum, do not enable spread for both at the
same time or their interaction will cancel benefits. The
programmable spread-spectrum amplitudes are Q2%
and Q4% (Table 6).
The deserializer includes a sawtooth divider to
control the spread-modulation rate. Autodetection of
the PCLKOUT operation range guarantees a spread-
Table 5. Cable Equalizer Boost Levels
The modulation rate for the deserializer relates to the
PCLKOUT frequency as follows:
fM=
(1 + DRS)
fPCLKOUT
MOD × SDIV
where:
fM = Modulation frequency
DRS = DRS value (0 or 1)
fPCLKOUT = PCLKOUT frequency
MOD = Modulation coefficient given in Table 7
SDIV = 5-bit SDIV setting, manually programmed by
the FC
To program the SDIV setting, first look up the modulation coefficient according to the desired bus-width and
spread-spectrum settings. Solve the above equation for
SDIV using the desired pixel clock and modulation frequencies. If the calculated SDIV value is larger than the
maximum allowed SDIV value in Table 7, set SDIV to the
maximum value.
Table 6. Parallel Output Spread
BOOST SETTING
(0x05 D[3:0])
TYPICAL BOOST GAIN
(dB)
SS
00
No spread spectrum. Power-up default.
0000
2.1
01
Q2% spread spectrum.
0001
2.8
10
No spread spectrum.
0010
3.4
11
Q4% spread spectrum.
0011
4.2
0100
5.2
0101
6.2
0110
7
0111
8.2
1000
9.4
1001
10.7
Default*
1010
11.7
1011
13
SPREAD (%)
Table 7. Modulation Coefficients and
Maximum SDIV Settings
SPREADSPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
(dec)
SDIV UPPER
LIMIT (dec)
4
208
15
2
208
30
*The equalizer is disabled at power-up.
Maxim Integrated
31
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Additional Error Detection and Correction
In default mode (additional error detection and correction disabled), data encoding/decoding is the same as
in previous GMSL serializers/deserializers (parity only).
At the serializer, the parallel input word is scrambled and
a parity bit is added. The scrambled word is divided into
3 or 4 bytes (depending on the BWS setting), 8b/10b
encoded, and then transmitted serially. At the deserializer, the same operations are performed in reverse order.
The parity bit is used by the deserializer to find the word
boundary and for error detection. Errors are counted in
an error counter register and an error pin indicates errors.
The deserializer can use one of two additional errordetection/correction methods (selectable by register
setting):
1) 6-bit cyclic redundancy check
2) 6-bit hamming code with 16-word interleaving
Cyclic Redundancy Check (CRC)
When CRC is enabled, the serializer adds 6 bits of CRC
to the input data. This reduces the available bits in the
input data word by 6, compared to the non-CRC case
(see Table 2 for details). For example, 16 bits are available for input data instead of 22 bits when BWS = 0, and
24 bits instead of 30 bits when BWS = 1.
The CRC generator polynomial is x6 + x + 1 (as used in
the ITU-T G704 telecommunication standard).
The parity bit is still added when CRC is enabled, because
it is used for word-boundary detection. When CRC is
enabled, each data word is scrambled and then the
6-bit CRC and 1-bit parity are added before the 8b/10b
encoding.
At the deserializer, the CRC code is recalculated. If the
recalculated CRC code does not match the received
CRC code, an error is flagged. This CRC error is reported
to the error counter.
Hamming Code
Hamming code is a simple and effective error-correction
code to detect and/or correct errors. The MAX9272
deserializer (when used with the MAX9271/MAX9273
GMSL serializers) uses a single-error correction/doubleerror detection per pixel hamming-code scheme.
The deserializer uses data interleaving for burst error
tolerance. Burst errors up to 11 consecutive bits on the
serial link are corrected and burst errors up to 31 consecutive bits are detected.
Maxim Integrated
Hamming code adds overhead similar to CRC. See Table 2
for details regarding the available input word size.
HS/VS Encoding and/or Tracking
HS/VS encoding by a GMSL serializer allows horizontal
and vertical synchronization signals to be transmitted while conserving pixel data bandwidth. With HS/
VS encoding enabled, 10-bit pixel data with a clock up
to 100MHz can be transmitted using one video pixel of
data per HS/VS transition versus 8-bit data with a clock
up to 100MHz without HS/VS encoding. The deserializer
performs HS/VS decoding, tracks the period of the HS/VS
signals, and uses voting to filter HS/VS bit errors. When
using HS/VS encoding, use a minimum HS/VS low-pulse
duration of two PCLKOUT cycles when DBL = 0 on the
deserializer. When DBL = 1, use a minimum HS/VS lowpulse duration of five PCLKOUT cycles and a minimum
high-pulse duration of two PCLKOUT cycles. When using
hamming code with HS/VS encoding, do not send more
than two transitions every 16 PCLKOUT cycles.
When the serializer uses double-input mode (DBL = 1),
the active duration, plus the blanking duration of HS or VS
signals, should be an even number of PCLKOUT cycles.
When DBL = 1 in the serializer and DBL = 0 in the deserializer, two pixel clock cycles of HS/VS at the serializer
input are output at the HS0/VS0 and HS1/VS1 output of
the deserializer in one cycle. The first cycle of HS/VS goes
out of HS0/VS0 and the second cycle goes out of HS1/
VS1. HS1 and VS1 are not used when HVEN = 0.
If HS/VS tracking is used without HS/VS encoding, use
DOUT0 for HSYNC and DOUT1 for VSYNC. In this case,
if DBL values on the serializer/deserializer are different,
set the UNEQDBL register bit in the deserializer to 1. If
the serializer and deserializer have unequal DBL settings
and HVEN = 0, then HS/VS inversion should only be used
on the side that has DBL = 1. HS/VS encoding sends
packets when HSYNC or VSYNC is low; use HS/VS inversion register bits if input HSYNC and VSYNC signals use
an active-low convention in order to send data packets
during the inactive pixel clock periods.
Serial Input
The device can receive serial data from two kinds of
cables: 100I twisted pair and 50I coax (contact the
factory for devices compatible with 75I cables).
Coax-Mode Splitter
In coax mode, OUT+ and OUT- of the serializer are
active. This enables use as a 1:2 splitter (Figure 29). In
coax mode, connect OUT+ to IN+ of the deserializer.
32
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
GMSL
SERIALIZER
MAX9272
OUT+
IN+
OUT-
IN-
GMSL
SERIALIZER
MAX9272
OUT+
OUT-
IN+
IN-
AVDD
MAX9272
50I
IN+
IN-
Figure 29. 2:1 Coax-Mode Splitter Connection Diagram
Figure 30. Coax-Mode Connection Diagram
Connect OUT- to IN- of the second deserializer. Controlchannel data is broadcast from the serializer to both
deserializers and their attached peripherals. Assign a
unique address to send control data to one deserializer.
Leave all unused IN_ pins unconnected, or connect them
to ground through 50I and a capacitor for increased
power-supply rejection. If OUT- is not used, connect
OUT- to AVDD through a 50I resistor (Figure 30). When
there are FCs at the serializer, and at each deserializer,
only one FC can communicate at a time. Disable one
splitter control-channel link to prevent contention. Use
the DIS_REV_P or DIS_REV_N register bits to disable a
control-channel link.
Table 8. Configuration Input Map
Cable Type Configuration Input (CX/TP)
CX/TP determines the power-up state of the serial input.
In coax mode, CX/TP also determines which coax input
is active, along with the default device address (Table 8).
These functions can be changed after power-up by writing
to the appropriate register bits.
Sleep Mode
The deserializer includes a sleep mode to reduce power
consumption. The device enters or exits sleep mode by a
command from a local FC or a remote FC using the control channel. Set the SLEEP bit to 1 to initiate sleep mode.
The serializer sleeps immediately after setting its SLEEP
= 1. The deserializer sleeps after serial link inactivity or
8ms (whichever arrives first) after setting its SLEEP = 1.
To wake up from the local side, send an arbitrary controlchannel command to the deserializer, wait 5ms for the
chip to power up, and then write 0 to the SLEEP register
bit to make the wake-up permanent. To wake up from the
Maxim Integrated
CX/TP
FUNCTION
High
Coax+ input. Device address 0x90.
Mid
Coax- input. Device address 0x92.
Low
Twisted-pair input. Device address 0x90.
remote side, enable serialization. To deserializer detects
the activity on the serial link and then when it locks, it
automatically sets its SLEEP register bit to 0.
Power-Down Mode
The deserializer has a power-down mode that further
reduces power consumption compared to sleep mode.
Set PWDN low to enter power-down mode. In powerdown mode, the outputs of the device remain in high
impedance. Entering power-down resets the device’s
registers. Upon exiting power-down, the state of external
pins GPIO1/BWS, GPIO0/DBL, CX / TP, I2CSEL, LCCEN,
RX /SDA /EDC, TX /SCL /ES, and MS/HVEN are latched.
Configuration Link
The control channel can operate in a low-speed mode
called configuration link in the absence of a clock input.
This allows a microprocessor to program configuration
registers before starting the video link. An internal oscillator provides the clock for the configuration link. Set
CLINKEN = 1 on the serializer to enable the configuration
link. The configuration link is active until the video link is
enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
33
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Link Startup Procedure
Table 9 lists the startup procedure for video-display
applications. Table 10 lists the startup procedure for
image-sensing applications. The control channel is available after the video link or the configuration link is established. If the deserializer powers up after the serializer,
the control channel becomes unavailable until 2ms after
power-up.
Table 9. Startup Procedure for Video-Display Applications
NO.
µC
SERIALIZER
DESERIALIZER
Sets all configuration inputs. If any
configuration inputs are available on
one end of the link but not on the other,
always connects that configuration input
low.
—
FC connected to serializer.
Sets all configuration inputs. If any
configuration inputs are available on
one end of the link but not on the other,
always connects that configuration input
low.
1
Powers up.
Powers up and loads default settings.
Powers up and loads default settings.
2
Enables configuration link by
setting CLINKEN = 1 (if not
enabled automatically) and gets
an acknowledge. Waits for link to
be established (~3ms).
Establishes configuration link.
Locks to configuration link signal.
3
Writes one link configuration
bit (DRS, BWS, or EDC) in
the deserializer and gets an
acknowledge.
—
Configuration changed from default
settings (loss-of-lock can occur when
BWS or EDC changes).
4
Writes corresponding serializer
link configuration bit and gets an
acknowledge.
Configuration changed from default
settings.
Relocks to configuration link signal.
5
Waits for link to be established
(~3ms) and then repeats steps 3
and 4 until all serial link bits are
configured.
—
—
6
Writes remaining configuration
bits in the serializer/deserializer
and gets an acknowledge.
Configuration changed from default
settings.
Configuration changed from default
settings.
7
Enables video link by setting
SEREN = 1 and gets an
acknowledge. Waits for link to be
established (~3ms).
Begins serializing data.
Locks to serial link signal and begins
deserializing data.
Maxim Integrated
34
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 10. Startup Procedure for Image-Sensing Applications
NO.
µC
SERIALIZER
Sets all configuration inputs. If any
configuration inputs are available on
one end of the link but not on the other,
always connects that configuration
input low.
DESERIALIZER
Sets all configuration inputs. If any
configuration inputs are available on
one end of the link but not on the other,
always connects that configuration input
low.
—
FC connected to deserializer.
1
Powers up.
Powers up and loads default settings.
Establishes serial link.
Powers up and loads default settings.
Locks to serial link signal.
3
Writes deserializer configuration
bits and gets an acknowledge.
—
Configuration changed from default settings
(loss-of-lock can occur).
4
Writes serializer configuration
bits. Cannot get an acknowledge
(or gets a dummy acknowledge)
if loss-of-lock occurred.
Configuration changed from default
settings.
Relocks the serial link signal.
5
Enables video link by setting
SEREN = 1 (if not enabled
automatically). Cannot get an
acknowledge (or gets a dummy
acknowledge) if loss-of-lock
occurred. Waits for link to be
established (~3ms).
Begins serializing data.
Locks to serial link signal and begins
deserializing data.
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
SLEEP
WAKE-UP
SIGNAL
POWER-ON
IDLE
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER
FC SETS SLEEP = 1
SIGNAL
DETECTED
PWDN = HIGH,
POWER-ON
SERIAL PORT
LOCKING
GMSL
SERIALIZER
HIGH TO LOW
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
CONFIG LINK
LOCKED
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
GPI CHANGES FROM
LOW TO HIGH OR
SEND GPI TO
CONFIG LINK
UNLOCKED
0
SLEEP
PRBSEN = 0
ALL STATES
PWDN = LOW OR
POWER-OFF
POWER-DOWN
OR
POWER-OFF
VIDEO LINK
OPERATING
0
PRBSEN = 1
VIDEO LINK
PRBS TEST
SLEEP
Figure 31. State Diagram, Remote Microcontroller Application
Maxim Integrated
35
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Applications Information
Error Checking
The deserializer checks the serial link for errors and
stores the number of detected and corrected errors
in the 8-bit registers, DETERR (0x10) and CORRERR
(0x12). If a large number of 8b/10b errors are detected
within a short duration (error rate R 1/4), the deserializer
loses lock and stops the error counter. The deserializer
then attempts to relock to the serial data. DETERR and
CORRERR reset upon successful video link lock, successful readout of their respective registers (through FC),
or whenever autoerror reset is enabled. The deserializer
uses a separate PRBS register during the internal PRBS
test, and DETERR and CORRERR are reset to 0x00.
ERR Output
The deserializer has an open-drain ERR output. This
output asserts low whenever the number of detected/corrected errors exceeds their respective error thresholds
during normal operation, or when at least one PRBS error
is detected during PRBS test. ERR reasserts high whenever DETERR and CORRERR reset, due to DETERR/
CORRERR readout, video link lock, or autoerror reset.
Autoerror Reset
The default method to reset errors is to read the respective error registers in the deserializer (0x10, 0x12, and
0x13). Autoerror reset clears the error counters DETERR/
CORRERR and the ERR output ~1Fs after ERR goes low.
Autoerror reset is disabled on power-up. Enable autoerror reset through AUTORST (0x08, D2). Autoerror reset
does not run when the device is in PRBS test mode.
Dual µC Control
Usually systems have one FC to run the control channel,
located on the serializer side for video-display applications or on the deserializer side for image-sensing
applications. However, a FC can reside on each side
simultaneously and trade off running the control channel.
In this case, each FC can communicate with the serializer
and deserializer and any peripheral devices.
Contention occurs if both FCs attempt to use the control
channel at the same time. It is up to the user to prevent
this contention by implementing a higher-level protocol.
Maxim Integrated
In addition, the control channel does not provide arbitration between I2C masters on both sides of the link. An
acknowledge frame is not generated when communication fails due to contention. If communication across the
serial link is not required, the FCs can disable the forward
and reverse control channel using the FWDCCEN and
REVCCEN bits (0x04, D[1:0]) in the serializer/deserializer. Communication across the serial link is stopped and
contention between FCs cannot occur.
As an example of dual FC use in an image-sensing application, the serializer can be in sleep mode and waiting
for wake-up by the FC on the deserializer side. After
wake-up, the serializer-side FC assumes master control
of the serializer’s registers.
Changing the Clock Frequency
It is recommended that the serial link be enabled after
the video clock (fPCLKOUT) and the control-channel
clock (fUART/fI2C) are stable. When changing the clock
frequency, stop the video clock for 5Fs, apply the clock
at the new frequency, then restart the serial link or toggle
SEREN. On-the-fly changes in clock frequency are possible if the new frequency is immediately stable and
without glitches. The reverse control channel remains
unavailable for 350Fs after serial link start or stop. When
using the UART interface, limit on-the-fly changes in
fUART to factors of less than 3.5 at a time to ensure that
the device recognizes the UART sync pattern. For example, when lowering the UART frequency from 1Mbps to
100kbps, first send data at 333kbps then at 100kbps for
reduction ratios of 3 and 3.333, respectively.
Fast Detection of
Loss-of-Synchronization
A measure of link quality is the recovery time from lossof-synchronization. The host can be quickly notified of
loss-of-lock by connecting the deserializer’s LOCK output to the GPI input. If other sources use the GPI input,
such as a touch-screen controller, the FC can implement
a routine to distinguish between interrupts from lossof-sync and normal interrupts. Reverse control-channel
communication does not require an active forward link
to operate and accurately tracks the LOCK status of the
GMSL link. LOCK asserts for video link only and not for
the configuration link.
36
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Providing a Frame Sync
(Camera Applications)
The GPI/GPO provides a simple solution for camera
applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input, and connect the GPO
output to the camera frame sync input. GPI/GPO have
a typical delay of 275Fs. Skew between multiple GPI/
GPO channels is 115Fs (max). If a lower skew signal is
required, connect the camera’s frame sync input to one
of the GMSL deserializer’s GPIOs and use an I2C broadcast write command to change the GPIO output state.
This has a maximum skew of 1.5Fs.
Software Programming
of the Device Addresses
Both the serializer and the deserializer have programmable device addresses. This allows multiple GMSL
devices, along with I2C peripherals, to coexist on the
same control channel. The serializer device address
is in register 0x00 of each device, while the deserializer device address is in register 0x01 of each device.
To change a device address, first write to the device
whose address changes (register 0x00 of the serializer
for serializer device address change, or register 0x01 of
the deserializer for deserializer device address change).
Then write the same address into the corresponding register on the other device (register 0x00 of the deserializer
for serializer device address change, or register 0x01 of
the serializer for deserializer device address change).
Three-Level Configuration Inputs
CX/TP is a three-level input that controls the serialinterface configuration and power-up defaults. Connect
CX/TP through a pullup resistor to IOVDD to set a high
level, a pulldown resistor to GND to set a low level, or
IOVDD/2 or open to set a midlevel. For digital control,
use three-state logic to drive the three-level logic input.
Configuration Blocking
The deserializer can block changes to registers. Set
CFGBLOCK to make all registers read only. Once set,
the registers remain blocked until the supplies are
removed or until PWDN is low.
Compatibility with other GMSL Devices
The MAX9272/MAX9273 deserializers are designed to
pair with the MAX9271/MAX9273 serializers, but interoperate with any GMSL serializers. See the Table 11 for
operating limitations.
GPIOs
The deserializer has two open-drain GPIOs available
when not used as configuration inputs. GPIO1OUT and
GPIO0OUT (0x0E, D3 and D1) set the output state of the
GPIOs. Setting the GPIO output bits to 0 pulls the output
low, while setting the bits to 1 leaves the output undriven
and pulled high through internal/external pullup resistors.
The GPIO input buffers are always enabled. The input
states are stored in GPIO1 and GPIO0 (0x0E, D2 and
D0). Set GPIO1OUT/GPIO0OUT to 1 when using GPIO1/
GPIO0 as an input.
Staggered Parallel Outputs
The deserializer staggers the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduces
the power-supply transient requirements. By default, the
deserializer staggers outputs according to Table 12.
Disable output staggering through the DISSTAG bit
(0x08, D3).
Table 11. MAX9272 Feature Compatibility
MAX9272 FEATURE
HSYNC/VSYNC encoding
GMSL DESERIALIZER
If feature not supported in the serializer, must be turned off in the deserializer.
Hamming-code error correction
If feature not supported in the serializer, must be turned off in the deserializer.
I2C-to-I2C
If feature not supported in the serializer, must use UART-to- I2C or UART-to-UART.
CRC error detection
If feature not supported in the serializer, must be turned off in the deserializer.
Double output
If feature not supported in the serializer, the data is inputted as a single word at 1/2 the output
frequency.
Coax
If feature not supported in the deserializer, must connect unused serial output through 200nF
and 50I in series to AVDD and set the reverse control-channel amplitude to 100mV.
I2S encoding
If feature is supported in the serializer, must disable I2S in the serializer.
Maxim Integrated
37
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 12. Staggered Output Delay
OUTPUT DELAY RELATIVE TO DOUT0 (ns)
OUTPUT
DISSTAG = 0
DISSTAG = 1
DOUT0–DOUT5, DOUT21, DOUT22
0
0
DOUT6–DOUT10, DOUT23, DOUT24
0.5
0
DOUT11–DOUT15, DOUT25, DOUT26
1
0
DOUT16–DOUT20, DOUT27, DOUT28
1.5
0
PCLKOUT
0.75
0
Table 13. Double-Function Configuration
LCCEN
GPIO0/DBL
FUNCTION
GPIO1/BWS
FUNCTION
MS/HVEN FUNCTION
RX/SDA/EDC
FUNCTION
TX/SCL/ES
FUNCTION
High
Functions as GPIO
Functions as GPIO
MS input
(low = base mode,
high = bypass mode)
UART/I2C input/
output
UART/I2C input/
output
BWS input
(low = 24-bit mode,
high = 32-bit mode)
HVEN input
(low = HS/VS
encoding disabled,
high = HS/VS
encoding enabled)
EDC input
(low = error
detection/correction
disabled,
high = error
detection/correction
enabled)
ES input
(low = valid DOUT_
on rising edge of
PCLKOUT,
high = valid DOUT_
on falling edge of
PCLKOUT)
Low
DBL input
(low = single input,
high = double input)
Local Control-Channel Enable (LCCEN)
The deserializer provides inputs for limited configuration of the device when a FC is not connected. Connect
LCCEN = low upon power-up to disable the local control
channel and enable the double-function configuration
inputs (Table 13). All input configuration states are
latched at power-up.
Internal Input Pulldowns
The control and configuration inputs, except three-level
inputs, include a pulldown resistor to GND. External pulldown resistors are not needed.
Choosing I2C/UART Pullup Resistors
The I2C and UART open-drain lines require a pullup
resistor to provide a logic-high level. There are tradeoffs
between power dissipation and speed, and a compromise
may be required when choosing pullup resistor values.
Every device connected to the bus introduces some
capacitance even when the device is not in operation. I2C
specifies 300ns rise times (30% to 70%) for fast mode,
which is defined for data rates up to 400kbps (see the I2C
specifications in the AC Electrical Characteristics table
for details). To meet the fast-mode rise-time requirement,
Maxim Integrated
choose the pullup resistors so that rise time tR = 0.85 x
RPULLUP x CBUS < 300ns. The waveforms are not recognized if the transition time becomes too slow. The deserializer supports I2C/UART rates up to 1Mbps (UART-to-I2C
mode) and 400kbps (I2C-to-I2C mode).
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to
the voltage rating of the capacitor. Capacitors at the serializer output and at the deserializer input are needed for
proper link operation and to provide protection if either
end of the cable is shorted to a battery. AC-coupling
blocks low-frequency ground shifts and low-frequency
common-mode noise.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
38
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
(RTR), the CML/coax driver termination resistor (RTD), and
the series AC-coupling capacitors (C). The RC time constant, for four equal-value series capacitors, is (C x (RTD
+ RTR))/4. RTD and RTR are required to match the transmission line impedance (usually 100I differential and
50I single-ended). This leaves the capacitor selection
to change the system time constant. Use 0.2FF or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
Power-Supply Circuits and Bypassing
The deserializer uses an AVDD and DVDD of 1.7V to
1.9V. All inputs and outputs, except for the serial input,
derive power from an IOVDD of 1.7V to 3.6V that scales
with IOVDD. Proper voltage-supply bypassing is essential for high-frequency circuit stability. The GPI-to-GPO
delay is 0.35ms (max). Keep the time between GPI transmissions to a minimum 0.35ms.
Power-Supply Table
Power-supply currents shown in the Electrical
Characteristics table are the sum of the currents from
AVDD, DVDD, and IOVDD. Typical currents from the
individual power supplies are shown in Table 14.
Cables and Connectors
Interconnect for CML typically has a differential impedance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic impedance of 50I (contact the factory for 75I operation). Table 15 lists the suggested cables and connectors
used in the GMSL link.
The trace dimensions depend on the type of trace used
(microstrip or stripline). Note that two 50I PCB traces
do not have 100I differential impedance when brought
close together—the impedance goes down when the
traces are brought closer. Use a 50I trace for the singleended output when driving coax.
Route the PCB traces for differential CML channel in parallel to maintain the differential characteristic impedance.
Avoid vias. Keep PCB traces that make up a differential
pair equal length to avoid skew within the differential pair.
ESD Protection
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial link inputs are rated for ISO 10605
ESD protection and IEC 61000-4-2 ESD protection. All
pins are tested for the Human Body Model. The Human
Body Model discharge components are CS = 100pF and
RD = 1.5kI (Figure 32). The IEC 61000-4-2 discharge
components are CS = 150pF and RD = 330I (Figure 33).
The ISO 10605 discharge components are CS = 330pF
and RD = 2kI (Figure 34).
Table 15. Suggested Connectors and
Cables for GMSL
SUPPLIER
CONNECTOR
CABLE
TYPE
Rosenberger
59S2AX-400A5-Y
RG174
Coax
MX38-FF
A-BW-Lxxxxx
STP
GT11L-2S
F-2WME
AWG28
STP
D4S10A-40ML5-Z
Dacar 538
STP
JAE
Nissei
Rosenberger
Board Layout
Separate the LVCMOS logic signals and CML/coax highspeed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100I differential characteristic impedance.
Table 14. Typical Power-Supply Currents
(Using Worst-Case Input Pattern)
PCLK
(MHz)
AVDD
(mA)
DVDD
(mA)
IOVDD
(mA)
25
25.1
9.2
10.3
50
33.3
13.7
13.3
Maxim Integrated
1MI
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
100pF
RD
1.5kI
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 32. Human Body Model ESD Test Circuit
39
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
RD
330I
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
150pF
RD
2kI
DISCHARGE
RESISTANCE
HIGHVOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
Figure 33. IEC 61000-4-2 Contact Discharge ESD Test Circuit
CHARGE-CURRENTLIMIT RESISTOR
CS
330pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 34. ISO 10605 Contact Discharge ESD Test Circuit
Table 16. Register Table (see Table 1)
REGISTER
ADDRESS
0x00
BITS
NAME
VALUE
D[7:1]
SERID
XXXXXXX
D0
—
0
D[7:1]
DESID
D0
CFGBLOCK
0x01
0x02
D[7:6]
SS
D[5:4]
—
D[3:2]
D[1:0]
D[7:6]
PRNG
SRNG
AUTOFM
0x03
D5
D[4:0]
Maxim Integrated
—
SDIV
XXXXXXX
FUNCTION
Serializer device address.
Reserved.
Deserializer device address. Default address is
determined by the state of the CX/TP input (Table 8).
0
Normal operation.
1
Registers 0x00 to 0x1F are read only.
00
No spread spectrum.
01
Q2% spread spectrum.
10
No spread spectrum.
11
Q4% spread spectrum.
01
Reserved.
00
12.5MHz to 25MHz pixel clock.
01
25MHz to 50MHz pixel clock.
10
Do not use.
11
Automatically detect the pixel clock range.
00
0.5Gbps to 1Gbps serial-data rate.
01
1Gps to 2Gps serial-data rate.
10
Automatically detect serial-data rate.
11
Automatically detect serial-data rate.
00
Calibrate spread-modulation rate only once after locking.
01
Calibrate spread-modulation rate every 2ms after
locking.
10
Calibrate spread-modulation rate every 16ms after
locking.
11
Calibrate spread-modulation rate every 256ms after
locking.
0
Reserved.
00000
Autocalibrate sawtooth divider.
XXXXX
Manual SDIV setting. See the Manual Programming of
the Spread-Spectrum Divider section.
DEFAULT
VALUE
1000000
0
1001000,
1001001
0
00
01
11
11
00
0
00000
40
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
BITS
NAME
D7
LOCKED
D6
OUTENB
D5
PRBSEN
D4
SLEEP
D[3:2]
INTTYPE
0x04
VALUE
0
LOCK output is low.
1
LOCK output is high.
0
Enable outputs.
1
Disable outputs.
0
Disable PRBS test.
1
Enable PRBS test.
0
Normal mode.
1
Activate sleep mode.
00
Local control channel uses I2C when I2CSEL = 0.
01
Local control channel uses UART when I2CSEL = 0.
10, 11
D1
D0
D7
REVCCEN
DCS
D5
HVTRMODE
D4
ENEQ
0x05
D[3:0]
Maxim Integrated
Disable reverse control channel to serializer (sending).
1
Enable reverse control channel to serializer (sending).
0
Disable forward control channel from serializer
(receiving).
1
Enable forward control channel from serializer
(receiving).
0
I2C conversion sends the register address when
converting UART to I2C.
1
Disable sending of I2C register address when converting
UART to I2C (command-byte-only mode).
0
Normal parallel output driver current.
1
Boosted parallel output driver current.
I2CMETHOD
EQTUNE
DEFAULT
VALUE
0
(read only)
0
0
0
01
Local control channel disabled.
0
FWDCCEN
D6
FUNCTION
0
Partial periodic HS/VS tracking.
1
Full periodic HS/VS tracking.
0
Equalizer disabled. Power-up default.
1
Equalizer enabled.
0000
2.1dB equalizer-boost gain.
0001
2.8dB equalizer-boost gain.
0010
3.4dB equalizer-boost gain.
0011
4.2dB equalizer-boost gain.
0100
5.2dB equalizer-boost gain.
0101
6.2dB equalizer-boost gain.
0110
7dB equalizer-boost gain.
0111
8.2dB equalizer-boost gain.
1000
9.4dB equalizer-boost gain.
1001
10.7dB equalizer-boost gain. Power-up default.
1010
11.7dB equalizer-boost gain.
1011
13dB equalizer-boost gain.
11XX
Do not use.
1
1
0
0
1
0
1001
41
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
BITS
NAME
VALUE
0x06
D[7:0]
—
00000010
D7
D6
D5
D4
0
1
Double-input mode. Power-up default when LCCEN =
low and GPIO0/DBL = high.
0
High data-rate mode.
1
Low data-rate mode.
0
24-bit mode. Power-up default when LCCEN = high or
GPIO1/BWS = low.
1
32-bit mode. Power-up default when LCCEN = low and
GPIO1/BWS = high.
0
Output data valid on rising edge of PCLKOUT.
Power-up default when LCCEN = high or TX/SCL/ES
= low. Do not change this value while the pixel clock is
running.
1
Output data valid on rising edge of PCLKOUT.
Power-up default when LCCEN = low and TX/SCL/ES
= high. Do not change this value while the pixel clock is
running.
0
HS/VS tracking disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
1
HS/VS tracking enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
0
HS/VS encoding disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
1
HS/VS encoding enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
00
1-bit parity error detection (GMSL compatible).
Power-up default when LCCEN = high or RX/SDA/
EDC = low.
01
6-bit CRC error detection.
10
6-bit hamming code (single-bit error correct, doublebit error detect) and 16-word interleaving. Power-up
default when LCCEN = low and RX/SDA/EDC = high.
11
Do not use.
BWS
ES
0x07
D3
D2
D[1:0]
Maxim Integrated
HVTRACK
HVEN
EDC
Reserved.
Single-input mode. Power-up default when LCCEN =
high or GPIO0/DBL = low.
DBL
DRS
FUNCTION
DEFAULT
VALUE
00000010
0, 1
0
0, 1
0, 1
0, 1
0, 1
00, 10
42
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
BITS
D7
0x08
NAME
INVVS
D6
INVHS
D5
—
D4
UNEQDBL
D3
DISSTAG
D2
AUTORST
D[1:0]
ERRSEL
VALUE
0
No VS or DOUT0 inversion.
1
Invert VS when HVEN = 1. Invert DOUT0 when
HVEN = 0.
Do not use if DBL = 0 in the deserializer and DBL = 1 in
the serializer.
0
No HS or DOUT1 inversion.
1
Invert HS when HVEN = 1. Invert DOUT1 when
HVEN = 0. Do not use if DBL = 0 in the deserializer and
DBL = 1 in the serializer.
0
Reserved.
0
Serializer DBL is not the same as deserializer.
1
Serializer DBL same as deserializer (set to 1 only when
HVEN = 0 and HVTRACK = 1).
0
Enable staggered outputs.
1
Disable staggered outputs.
0
Do not automatically reset error registers and outputs.
1
Automatically reset DETERR and CORRERR registers
1Fs after ERR asserts.
00
ERR asserts when DETERR is larger than DETTHR.
01
ERR asserts when CORRERR is larger than CORRTHR.
10, 11
0x09
0x0A
0x0B
0X0C
D[7:1]
I2CSRCA
XXXXXXX
D0
—
0
D[7:1]
I2CDSTA
XXXXXXX
D0
—
0
D[7:1]
I2CSRCB
XXXXXXX
D0
—
0
D[7:1]
I2CDSTB
XXXXXXX
D0
—
0
Maxim Integrated
FUNCTION
ERR asserts when DETERR is larger than DETTHR or
CORRERR is larger than CORRTHR.
I2C address translator source A.
Reserved.
I 2C
address translator destination A.
Reserved.
I2C address translator source B.
Reserved.
I 2C
address translator destination B.
Reserved.
DEFAULT
VALUE
0
0
0
0
0
0
00
0000000
0
0000000
0
0000000
0
0000000
0
43
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
BITS
D7
D[6:5]
NAME
D[1:0]
D[7:6]
FUNCTION
0
Acknowledge not generated when forward channel is not
available.
1
I2C-to-I2C slave generates local acknowledge when
forward channel is not available.
00
352ns/117ns I2C setup/hold time.
I2CLOCACK
I2CSLVSH
0x0D
D[4:2]
VALUE
I2CMSTBT
I2CSLVTO
—
01
469ns/234ns I2C setup/hold time.
10
938ns/352ns I2C setup/hold time.
11
1046ns/469ns I2C setup/hold time.
000
8.47kbps (typ) I2C-to-I2C master bit-rate setting.
001
28.3kbps (typ) I2C-to-I2C master bit-rate setting.
010
84.7kbps (typ) I2C-to-I2C master bit-rate setting.
011
105kbps (typ) I2C-to-I2C master bit-rate setting.
100
173kbps (typ) I2C-to-I2C master bit-rate setting.
101
339kbps (typ) I2C-to-I2C master bit-rate setting.
110
533kbps (typ) I2C-to-I2C master bit-rate setting.
111
837kbps (typ) I2C-to-I2C master bit-rate setting.
00
64Fs (typ) I2C-to-I2C slave remote timeout.
01
256Fs (typ) I2C-to-I2C slave remote timeout.
10
1024Fs (typ) I2C-to-I2C slave remote timeout.
11
No I2C-to-I2C slave remote timeout.
DEFAULT
VALUE
0
01
101
10
01
Reserved.
0
Disable GPI-to-GPO signal transmission to serializer.
01
1
Enable GPI-to-GPO signal transmission to serializer.
0
GPI input is low.
1
GPI input is high.
0
Set GPIO1 to low.
1
Set GPIO1 to high.
0
GPIO1 input is low.
1
GPIO1 input is high.
0
Set GPIO0 to low.
1
Set GPIO0 to high.
0
GPIO0 input is low.
1
GPIO0 input is high.
0
(read only)
D5
GPIEN
D4
GPIIN
D3
GPIO1OUT
D2
GPIO1IN
D1
GPIO0OUT
D0
GPIO0IN
0x0F
D[7:0]
DETTHR
XXXXXXXX
Error threshold for detected errors.
00000000
0x10
D[7:0]
DETERR
XXXXXXXX
Detected error counter.
00000000
(read only)
0x11
D[7:0]
CORRTHR
XXXXXXXX
Error threshold for corrected errors.
00000000
0x12
D[7:0]
CORRERR
XXXXXXXX
Corrected error counter.
00000000
(read only)
0x0E
Maxim Integrated
1
0
(read only)
1
0
(read only)
1
44
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
BITS
NAME
VALUE
0x13
D[7:0]
PRBSERR
XXXXXXXX
D7
PRBSOK
D[6:0]
—
000000
Reserved.
0000000
(read only)
0x15
D[7:0]
—
00100XXX
Reserved.
00100XXX
0x16
D[7:0]
—
00110000
Reserved.
00110000
0x17
D[7:0]
—
01010100
Reserved.
01010100
0x18
D[7:0]
—
00110000
Reserved.
00110000
0x19
D[7:0]
—
11001000
Reserved.
11001000
0x1A
D[7:0]
—
XXXXXXXX
Reserved.
00000000
(read only)
0x1B
D[7:0]
—
XXXXXXXX
Reserved.
00000000
(read only)
0x1C
D[7:0]
—
XXXXXXXX
Reserved.
00000000
(read only)
D7
CXTP
D6
CXSEL
D5
I2CSEL
D4
LCCEN
D[3:0]
—
XXXX
D[7:0]
ID
00001010
D[7:5]
—
000
D4
CAPS
D[3:0]
REVISION
0x14
0x1D
0x1E
0x1F
FUNCTION
PRBS error counter.
0
PRBS test not completed.
1
PRBS test completed with success.
0
CX/TP input is low.
1
CX/TP input is high.
0
CXSEL is 0.
1
CXSEL is 1.
0
Input is low.
1
Input is high.
0
Input is low.
1
Input is high.
DEFAULT
VALUE
00000000
(read only)
0
(read only)
0
(read only)
0
(read only)
0
(read only)
0
(read only)
Reserved.
0000
(read only)
Device identifier (MAX9272 = 0x0A).
1010
(read only)
Reserved.
000
(read only)
0
Not HDCP capable.
1
HDCP capable.
0
(read only)
XXXX
Device revision.
(read only)
X = Don’t care.
Maxim Integrated
45
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Typical Application Circuit
CAMERA APPLICATION
PCLK
RGBHV
SHDN
CAMERA
PCLKOUT
PCLKIN
PCLK
DOUT0–DOUT15
DIN0–DIN15
RGBHV
GPO
CONF1
GPU
CONF0
MAX9271
MAX9272
RX/SDA/EDC
TX
TX/SCL/ES
RX
UART
TO PERIPHERALS
RX/SDA/EDC
TX/SCL/DBL
OUT+
OUT-
GPI
IN+
IN-
LOCK
CX/ TP
LCCEN
ECU
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
Package Information
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9272GTM+
MAX9272GTM/V+**
-40NC to +105NC
-40NC to +105NC
48 TQFN-EP*
48 TQFN-EP*
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
Chip Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
48 TQFN-EP
T4877+4
21-0144
90-0130
PROCESS: CMOS
Maxim Integrated
46
MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/12
Initial release
—
1
11/12
Added nonautomotive package to Ordering Information.
46
DESCRIPTION
PAGES
CHANGED
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012
Maxim Integrated
47
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
工商网监
湘ICP备2023018690号
