EPC23101ENGRT

eGaN® FET DATASHEET EPC23101 EPC23101 – ePower™ Chipset VIN , 100 V ILoad , 65 A Y NAR I M I REL EFFICIENT POWER CONVERSION P HAL EPC’s ePowerTM Stage and Chipset integrate input logic interface, level shifting, bootstrap charging and gate drive buffer circuits along with eGaN output FETs. Integration is implemented using EPC’s proprietary GaN IC technology. The end result is a Power Stage that translates logic level input to high voltage and high current power output that is smaller in size, easier to manufacture, simpler to design and more efficient to operate. Key Parameters PARAMETER VALUE UNIT Power Stage Load Current (1 MHz) Operating PWM Frequency Range Absolute Maximum Input Voltage Operating Input Voltage Range Nominal Bias Supply Voltage 65 [1] A MHz 3 [2] 100 80 5 V Output Current and PWM Frequency Ratings are functions of Operating Conditions. Appropriate derating should be applied to keep TJ at less than 125 °C. See Notes 1 & 2. Chipset Information PART NUMBER Rated RDS(on) at 25°C QFN Package Size (mm) EPC23101 3.3 mΩ 3.5 x 5 EPC2302 1.8 mΩ 3x5 All exposed pads feature wettable flanks that allow side wall solder inspection. High voltage and low voltage pads are separated by 0.6 mm spacing to meet IPC rules. Recommended to use EPC2302 as companion low side FET for the chipset. 50 96 40 94 30 92 20 500 kHz 750 kHz 1 MHz 90 88 0 10 20 30 40 IOUT (A) 50 60 Losses (W) Efficiency (%) Figure 1: Performance Curves 98 10 EPC23101 ePowerTM Chipset Applications • Buck, Boost, Half-Bridge, Full Bridge or LLC Converters • Motor Drive Inverter Features • Integrated high side eGaN® FET with internal gate driver and level shifter • 5 V external bias supply • 3.3 V or 5 V CMOS input logic levels • Independent high side and low side control inputs • Cross conduction lockout logic keeps both FETs off when logic inputs are both high at same time • External resistors to tune SW switching times and over-voltage spikes above rail and below ground • Robust level shifter operating for hard and soft switching conditions • False trigger immunity from fast switching transients • Synchronous charging for high side bootstrap supply • Low quiescent current mode from external VDRV supply when VDD Disable Input pin is pulled up • Undervoltage lockout for internal low side and high side bias supplies • Active gate pull-down for HS FET and LS gate drive with loss of VDRV supply • Chipset of compatible high and low side devices in QFN packages with optimized pinouts between the two devices 0 70 Buck Converter, VIN = 48 V, VOUT = 12 V, Deadtime = 10 ns, L = 2.2 µH, DCR = 700 µΩ, EPC23101 + EPC2302, Airflow = 1000 LFM. See See EPC90142 Quick Start Guide for details. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 1 eGaN® FET DATASHEET EPC23101 Figure 2: Functional Block Diagram 4 5 VDRV CDRV 3 High side VDD Enable VIN logic Sync boot EN 150 k GND 1 HSIN 2 LSIN CDD Logic + UVLO + Crossover LO Level shift VBoot 14 RBoot 13 VIN 10, 12 CBOOT VIN Gate driver CIN SW 9, 11 VDRV VDD Delay match Gate driver GND 8 SW RDRV 6 LGOUT 7 EPC2302 EPC23101 PGND General Description The EPC23101 ePowerTM IC integrates a half-bridge gate driver with an internal high side FET. It is designed as part of a chipset with a companion low side eGaN® FET such as the EPC2302. Integration is implemented using EPC’s proprietary GaN IC technology. The high side monolithic chip integrates input logic interface, level shifting, bootstrap charging and gate drive buffer circuits along with a high side eGaN output FET. The low side output FET is driven by the gate driver output of the GaN IC to configure a half-bridge power stage. The charging path for the floating bootstrap supply is activated with LSIN logic. It uses eGaN FET as the series switch that minimizes power losses by eliminating reverse recovery. This synchronous bootstrap charging circuit also minimizes voltage drop in the charging path. The on-chip gate drive buffers practically eliminate effects of common source inductance and gate drive loop inductance. Power loop inductance is minimized by compatible high side to low side pinout configuration that facilitates optimal layout technique. Switching times are tuned by external resistors to achieve 1–3 ns rise and fall times from 0–48 V at full load current. Over-voltage spikes can be controlled to less than +10 V above rail and –10 V below ground during hard switching transitions by choosing the tuning resistors, RBOOT and RDRV . Protection is provided by high side and low side under-voltage lockout to keep both FETs off at low supply voltages. If the supply voltages drop even lower or are lost while VIN is active at greater than 10 V, another active pull-down circuit is used with biasing from VIN to prevent destructive turn-on of both FETs from gate to drain leakage.. The EPC23101 IC only requires an external 5 V VDRV power supply. Internal low side and high side power supplies, VDD and VBOOT , are generated from the external supply via a series connected switch. The internal supplies can be cut off to save quiescent power by turning off the switch with 5 V applied to the EN pin. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | Robust level shifters from low side to high side channels are designed to operate correctly even at large negative clamped voltage and to avoid false trigger from fast dv/dt transients including those driven by external sources or other phases. The EPC23101 IC is capable of interfacing to digital controllers that use standard 3.3 V or 5 V CMOS logic levels. Separate and independent high side and low side logic control inputs allow external controllers to set fixed or adaptive dead times for optimal operating efficiency. Cross conduction prevention logic keeps both FETs off when logic inputs are both high at the same time. The FET gate drive voltages are derived from the internal low side and high side power supplies. Full gate drive voltages are only available after the HSIN and LSIN PWM inputs start to operate for a few cycles. | 2 eGaN® FET DATASHEET EPC23101 Figure 3: EPC23101 Transparent Top View Pin Pin Name Pin Type Description 12 1 HSIN I High side PWM logic input, level referenced to GND. Internal pull-down resistor is connected between HSIN and GND. 11 2 LSIN I Low side PWM logic input, level referenced to GND. Internal pull-down resistor is connected between LSIN and GND. 10 3 EN I VDD disable input, level referenced to GND. Internal VDD will be disabled when EN is connected to VDRV. VDD will follow VDRV when EN is connected to GND. Internal pull-down resistor is connected between EN and GND. 4 VDD S Internal power supply referenced to GND, connect a bypass capacitor from VDD to GND. 5 VDRV S External 5 V nominal power supply referenced to GND, connect a bypass capacitor from VDRV to GND. 6 RDRV O Insert resistor between RDRV to VDRV to control the turn-on slew rate of the driven low side FET. 7 LGOUT O Low side gate drive output to driven low side FET. Maintain short loop between LGOUT and kelvin source connection of low side FET to minimize common mode inductance. 8 GND S, O Logic ground. Connect bypass capacitors between operating bias supplies, VDRV and VDD to GND. Low side output gate driver is also referenced to same GND pin. 9, 11 SW P, S Output switching node. Connected to output of half-bridge power stage. The floating bootstrap power supply, VBOOT , is also referenced to SW. 10, 12 VIN P Power bus input. Connected to drain terminal of internal high side FET. Connect power loop capacitors from VIN to PGND or power source terminals of low side FET. 13 RBOOT O Insert resistor between RBOOT to VBOOT to control the turn-on slew rate of the internal high side FET. 9 13 8 14 7 1 2 3 4 5 6 Floating bootstrap power supply referenced to SW, connect an external bypass capacitor from VBOOT to SW. Pin Type: P = Power, S = Bias Supplies, I = Logic Inputs, O = Gate Drive Output 14 VBOOT S Figure 4: EPC2302 Transparent Top View Pin Description 7 6 5 1 Gate 2 Source 3 Drain 4 Source 5 Drain 6 Source 7 Drain 4 3 1 2 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 3 eGaN® FET DATASHEET EPC23101 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur and device reliability may be affected. All voltage parameters are absolute voltages referenced to GND unless indicated otherwise. Absolute Maximum Ratings SYMBOL PARAMETER VIN VSW(continuous) VDRV VDD VBOOT – VSW LGOUT HSIN, LSIN EN TJ TSTG Input Voltage (VIN to GND) Output Switching Node (SW to GND), Continuous External Bias Supply (VDRV to GND) Internal Low Side Supply Voltage (VDD to GND) Internal High Side Supply Voltage (VBOOT to SW) Low Side Gate Drive Output (LGOUT to GND) PWM Logic Inputs VDD Disable Input Junction Temperature Storage Temperature MIN MAX -55 100 100 6 6 6 6 5.5 5.5 150 150 MIN MAX UNITS V °C ESD Ratings ESD Ratings SYMBOL PARAMETER HBM CDM Human-body model (JEDEC JS-001) Charged-device model (JEDEC JESD22-C101) +/-1000 +/-500 UNITS V Thermal Characteristics RθJA_JEDEC is measured using JESD51-2 standard setup with 1 cubic foot enclosure with no forced air cooling, heat dissipated only through natural convection. The test used JEDEC Standard 4-layers PCB with 2oz top and bottom surface layers and 1oz buried layers. RθJA_EVB is measured using EPC90142 EVB with no forced air cooling, this rating is more indicative of actual application environment. Thermal Characteristics SYMBOL PARAMETER TYP UNITS RθJC_Top RθJB_Bottom RθJA_JEDEC RθJA_EVB Thermal Resistance, Junction-to-Case (Top surface of exposed die substrate) Thermal Resistance, Junction-to-Board (At solder joints of VIN and SW PCB pads) Thermal Resistance, Junction-to-Ambient (using JEDEC 51-2 PCB) Thermal Resistance, Junction-to-Ambient (using EPC90142 EVB) 0.4 3 43 25 °C/W Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND unless indicated otherwise. Recommended Operating Conditions SYMBOL VIN VSW(Q3 Mode) VSW(pulse2ns) VDRV VDD VBOOT – VSW LGOUT HSIN, LSIN EN TJ PW_min PW_max PARAMETER MIN Input Voltage (VIN to GND) Output Switch Node, 3rd Quadrant Mode [4] Output Switch Node, Transient PW= 10 V for the IC to be enabled. Below the minimum VIN the pass-transistor between VDRV and VDD will be off. Same condition when VDD disable pin, EN, is connected to 5 V. Note 4: The output switching node (SW) is clamped above VIN by the HS FET or below GND by the LS FET at their respective source drain voltage in the 3rd quadrant. This is an operating condition when both HS and LS FETs are in the off states during the dead time period which is set by the application circuit with typical value of 15 ns. The Absolute Minimum Rating is determined by LS FET 3rd quadrant clamp voltage below GND. Conversely the Absolute Maximum Rating is determined by HS FET 3rd quadrant clamp voltage above VIN. The time duration that the device can stay in the negative clamp voltage region is subjected to the amount of load current, power dissipation and maximum allowed junction temperature. Note 5: During HS FET or LS FET turn-on transitions with hard switching conditions, the fast di/dt of the HS FET or LS FET coupled with the power loop inductance (VPeak = LPower loop · di/dt) would cause a transient over-voltage spike above VIN or below GND. The Absolute Minimum Rating is amount of peak voltage spike, caused by LS FET di/dt, below GND for less than 2 ns pulse duration. Conversely the Absolute Maximum Rating is amount of peak voltage spike, caused by HS FET di/dt, above VIN, for less than 2 ns pulse duration. Note 6: For interfacing with analog controller operating from 12 VCC and outputting a 12 V drive signal, a resistor network in series should be inserted to divide the voltage to acceptable VIH level and limit the input current into the logic input pins HIN and LIN which is clamped to the VDD supply by ESD protection network. Note 7: LIN commands LS FET to turn-on to charge bootstrap supply through sync boot. Note 8: Internal logic follows HSIN, LSIN respectively but cross conduction lockout logic prevents both HS and LS FETs to turn on together as commanded if both HSIN and LSIN are set to logic “high”. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 7 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | A Ø330±2 Ø330±2 Ø330±2 Ø330±2 Type 8MM 12MM 16MM 24MM Ø100±2 Ø100±2 Ø100±2 Ø100±2 N Ø13.1±0.2 Ø13.1±0.2 Ø13.1±0.2 Ø13.1±0.2 C Top View Detail Top View D 5.6±0.5 5.6±0.5 5.6±0.5 5.6±0.5 w1 8.4+1.5 12.4+1.5 16.4+1.5 24.4+1.5 T w2 14.4 18.4 22.4 30,4 2.1±0.5 2.1±0.5 2.1±0.5 2.1±0.5 T Side View w2 w1 A C Bottom View Detail D N Bottom View Loaded tape feed direction eGaN® FET DATASHEET EPC23101 | 8 eGaN® FET DATASHEET EPC23101 13 12 10 E 23 PC X 1 X YY 01 X W X W X 11 9 8 7 6 5 4 Site/date code Lot code D 3 14 2 1 Pads 1-8,13 and 14 are IC pins; Pads 9 and 11 are SW pins ; Pads 10 and 12 are VIN pins 0.10 Max. C // ccc C 0.05 Max. A 2.600 Die size B A 7 eee C A1 A3 A1 Side View 2 Seating plane 12 K1 (3x) 11 e1 E 10 Exposed die 4.470 Die size K (3x) 5.00 9 aaa C 2x 13 8 Top View Side View 1 Dimension (mm) MIN Nominal MAX 0.60 0.00 0.65 0.02 0.20 Ref 0.25 0.20 3.50 BSC 5.00 BSC 0.50 BSC 0.85 BSC 0.60 0.20 0.70 0.05 0.20 0.15 0.55 0.15 6 bbb M C A B ddd M C A aaa C 2x A A1 A3 b b1 D E e e1 K K1 e 14 K (2x) 7 A3 SYMBOL L 0.30 0.25 0.65 0.25 Note 6 6 SYMBOL L aaa bbb ccc ddd eee N ND NE Notes 6 5 4 3 2 1 b (14x) b1 (2x) Bottom View Notes: Dimension (mm) MIN Nominal MAX 0.30 0.40 0.05 0.10 0.10 0.05 0.08 14 6 7 1, 2 0.50 Note 1. Dimensioning and tolerancing conform to ASME Y14.5-2009 2. All dimensions are in millimeters 3. N is the total number of terminals 3 5 5 4. Dimension b applies to the metallized terminal. If the terminal has a radius on the other end of it, dimension b should not be measured in that radius area. 5. ND and NE refer to the number of terminals on each D and E side respectively. 6. Dimension b applies to the metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has a radius on the other end of it, dimension b should not be measured in that radius area. 7. Coplanarity applies to the terminals and all the other bottom surface metallization. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | | 9 eGaN® FET DATASHEET EPC23101 Errata Sheet STATUS VERSION DATE REMARK ENGRT 1.1 12/09/2022 The following features and parameters do not meet the datasheet description and specifications: 1) The maximum operating VIN voltage should not exceed 64 V 2) The maximum transient voltage at the output switch node SW, should not exceed 70 V. Recommend to use at least 4.7 Ω for RBOOT and RDRV to module the over-voltage spike above VIN rail and below PGND to less than 10 V. Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2023 | Information subject to change without notice. December, 2022 | 10