S1C17M12/M13
(rev1.0)
16-bit Single Chip Microcontroller
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16KB Flash ROM: Read/program protection function, 2KB RAM
Supports 1.8V to 5.5V wide range operating voltage.
Five-digit seven-segment LED controller (8SEG × 1–5COM (max.))
Supports various kinds of interfaces (UART, SPI, I2C)
■ DESCRIPTIONS
The S1C17M12/M13 is a 16-bit embedded Flash MCU that features low power consumption. It includes various serial interfaces and a seven-segment LED controller on the compact die. It is suitable for control panels with a sevensegment display for housing equipment and FA equipment.
■ FEATURES
Model
CPU
CPU core
Other
Embedded Flash memory
Capacity
Erase/program count
Other
Embedded RAM
Capacity
Clock generator (CLG)
System clock source
System clock frequency (operating frequency)
IOSC oscillator circuit (boot clock source)
OSC3 oscillator circuit
EXOSC clock input
Other
I/O port (PPORT)
Number of general-purpose I/O ports
S1C17M12
S1C17M13
Seiko Epson original 16-bit RISC CPU core S1C17
On-chip debugger
16K bytes (for both instructions and data)
1,000 times (min.)
Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
2K bytes
3 sources (IOSC/OSC3/EXOSC)
16.8 MHz (max.)
700 kHz (typ.) embedded oscillator
23 µs (max.) starting time (time from cancelation of SLEEP state to vector table read by
the CPU)
16.8 MHz (max.) crystal/ceramic oscillator
4, 8, 12, and 16 MHz-switchable embedded oscillator
16.8 MHz (max.) square or sine wave input
Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
Input/output port: 38 bits (max.)
Output port:
1 bit (max.)
Pins are shared with the peripheral I/O.
Number of input interrupt ports
34 bits (max.)
Number of ports that support universal port 21 bits
multiplexer (UPMUX)
A peripheral circuit I/O function selected via software can be assigned to each port.
Number of high drive-capability Nch outputs 8 bits (max.)
7 mA output (max.)
Number of high drive-capability Pch outputs 5 bits (max.)
56 mA output (max., Total sum of 5 bits)
Timers
Watchdog timer (WDT2)
Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
16-bit timer (T16)
4 channels
Generates the SPIA master clock and the ADC12A trigger signal.
16-bit PWM timer (T16B)
1 channel
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 2 ports/channel
Supply voltage detector (SVD3)
Detection voltage
VDD or external voltage (two external voltage input ports are provided.)
Detection level
VDD: 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)
Other
Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
S1C17M12/M13
Model
Serial interfaces
UART (UART3)
Serial interfaces
Synchronous serial interface (SPIA)
I2C (I2C)
IR remote controller (REMC2)
Number of transmitter channels
Other
Seven-segment LED controller (LEDC)
LED control output
12-bit A/D converter (ADC12A)
Conversion method
Resolution
Number of conversion channels
Number of analog signal inputs
Multiplier/divider (COPRO2)
Arithmetic functions
Reset
#RESET pin
Power-on reset
Brownout reset
Key entry reset
Watchdog timer reset
Supply voltage detector reset
Interrupt
Non-maskable interrupt
Programmable interrupt
Power supply voltage
VDD operating voltage
VDD operating voltage for Flash programming
Operating temperature
Operating temperature range
Current consumption (Typ. value)
SLEEP mode
HALT mode
RUN mode
Shipping form
1
2
S1C17M12
S1C17M13
4 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function
2 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
1 channel
Baud-rate generator included
1 channel
EL lamp drive waveform can be generated for an application example.
Seven-segment LED outputs up to five digits (8SEG × 1–5COM(max.))
COM time-division dynamic drive control
Software configurable anode/cathode common mode and off-state pin status
Four-level brightness adjustment function
–
Successive approximation type
12 bits
1 channel
8 ports/channel
16-bit × 16-bit multiplier
16-bit × 16-bit + 32-bit multiply and accumulation unit
32-bit ÷ 32-bit divider
Reset when the reset pin is set to low.
Reset at power on.
Reset when the power supply voltage drops.
Reset when the P00 to P01/P02/P03 keys are pressed simultaneously (can be enabled/
disabled using a register).
Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Reset when the supply voltage detector detects the set voltage level (can be enabled/disabled using a register).
4 systems (Reset, address misaligned interrupt, debug, NMI)
External interrupt: 1 system (8 levels)
Internal interrupt: 14 systems (8 levels)
1.8 to 5.5 V
1.8 to 5.5 V (VPP = 7.5 V external power supply is required.)
-40 to 85 °C
0.5 µA (TBD)
IOSC = OFF, OSC3 = OFF
180 µA (TBD)
OSC3 = 4 MHz (internal oscillator)
600 µA (TBD)
OSC3 = 4 MHz (internal oscillator), CPU = OSC3 (1 wait cycle)
1,700 µA (TBD)
OSC3 = 16 MHz (internal oscillator), CPU = OSC3 (2 wait cycles)
TQFP12-48pin (Lead pitch: 0.5 mm)
Seiko Epson Corporation
S1C17M12/M13
■ BLOCK DIAGRAM
DCLK
DSIO
DST2
Coprocessor bus
Multiplier/divider
(COPRO2)
32-bit RAM bus
Internal RAM
2K bytes
Instruction bus
Flash memory
16K bytes
CPU core & debugger
(S1C17)
System clock
VPP
Interrupt request
16-bit internal bus
Interrupt signal
Clock generator
(CLG)
FOUT
IOSC
oscillator
OSC3
OSC4
OSC3
oscillator
EXOSC
EXOSC
input circuit
System reset controller
(SRC)
#RESET
Power-on reset
(POR)
Brownout reset
(BOR)
VDD
VDD2
VD1
VSS
VSS2
Power generator
(PWG)
Interrupt
controller
(ITC)
I/O port
(PPORT)
UART
(UART3)
1 Ch.
P00–07
P10–17
P20–24
P40–47
P50–54
PD0–D1
PD3–D4
PD2
Watchdog timer
(WDT2)
Supply voltage
detector
(SVD3)
EXSVD0–1
16-bit timer
(T16)
4 Ch.
16-bit PWM timer
(T16B)
1 Ch.
Synchronous
serial interface
(SPIA)
2 Ch.
USIN0
USOUT0
SDI0–1
SDO0–1
SPICLK0–1
#SPISS0–1
I2C
(I2C)
1 Ch.
SDA0
SCL0
IR remote
controller
(REMC2)
1 Ch.
REMO
CLPLS
Seven-segment
LED controller
(LEDC)
12-bit A/D
converter
(ADC12A)
1 Ch.
COM0–4
SEG0–7
∗
ADIN00–07
#ADTRG0
VREFA0
TOUT00–01
CAP00–01
EXCL00–01
* Not available in the S1C17M12.
Seiko Epson Corporation
3
S1C17M12/M13
■ PIN CONFIGURATION DIAGRAMS
Pin name
P40
P41
P42
P43
VSS2
P44
P45
P46
P47
VSS2
P50
P51
37
38
39
40
41
42
43
44
45
46
47
48
S1C17M12
P52/COM2
VDD2
P53/COM3
P54/COM4
P00/UPMUX
P01/UPMUX
P02/UPMUX
P03/UPMUX
P04/UPMUX
P05/UPMUX
P06/UPMUX
P07/UPMUX
P52
VDD2
P53
P54
P00
P01
P02
P03
P04
P05
P06
P07
1
2
3
4
5
6
7
8
9
10
11
12
Port function
or signal
assignment
P40/SEG0
P41/SEG1
P42/SEG2
P43/SEG3
VSS2
P44/SEG4
P45/SEG5
P46/SEG6
P47/SEG7
VSS2
P50/REMO/COM0
P51/CLPLS/COM1
36
35
34
33
32
31
30
29
28
27
26
25
VSS2
VPP
P24
P23
P22
P21
P20
PD2
PD1
PD0
VDD
#RESET
VSS2
VPP
P24/UPMUX
P23/UPMUX
P22/UPMUX
P21/UPMUX
P20/UPMUX
DCLK/PD2
DSIO/PD1
DST2/PD0
VDD
#RESET
S1C17M12 pin configuration diagram (TQFP12-48pin)
4
Seiko Epson Corporation
24
23
22
21
20
19
18
17
16
15
14
13
VSS
VD1
PD4
PD3
P17
P16
P15
P14
P13
P12
P11
P10
VSS
VD1
PD4/OSC4
PD3/OSC3
P17/UPMUX
P16/FOUT/UPMUX
P15/EXCL01/UPMUX
P14/EXCL00/UPMUX
P13/EXOSC/UPMUX
P12/UPMUX/EXSVD1
P11/UPMUX/EXSVD0
P10/UPMUX
S1C17M12/M13
S1C17M13
24
23
22
21
20
19
18
17
16
15
14
13
VSS
VD1
PD4
PD3
P17
P16
P15
P14
P13
P12
P11
P10
VSS
VD1
PD4/OSC4
PD3/OSC3
P17/#ADTRG0/UPMUX
P16/FOUT/UPMUX
P15/EXCL01/UPMUX
P14/EXCL00/UPMUX
P13/EXOSC/UPMUX
P12/UPMUX/EXSVD1
P11/UPMUX/EXSVD0
P10/UPMUX/VREFA0
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
P52
VDD2
P53
P54
P00
P01
P02
P03
P04
P05
P06
P07
Pin name
P40
P41
P42
P43
VSS2
P44
P45
P46
P47
VSS2
P50
P51
P52/COM2
VDD2
P53/COM3
P54/COM4
P00/UPMUX/ADIN07
P01/UPMUX/ADIN06
P02/UPMUX/ADIN05
P03/UPMUX/ADIN04
P04/UPMUX/ADIN03
P05/UPMUX/ADIN02
P06/UPMUX/ADIN01
P07/UPMUX/ADIN00
Port function
or signal
assignment
P40/SEG0
P41/SEG1
P42/SEG2
P43/SEG3
VSS2
P44/SEG4
P45/SEG5
P46/SEG6
P47/SEG7
VSS2
P50/REMO/COM0
P51/CLPLS/COM1
36
35
34
33
32
31
30
29
28
27
26
25
VSS2
VPP
P24
P23
P22
P21
P20
PD2
PD1
PD0
VDD
#RESET
VSS2
VPP
P24/UPMUX
P23/UPMUX
P22/UPMUX
P21/UPMUX
P20/UPMUX
DCLK/PD2
DSIO/PD1
DST2/PD0
VDD
#RESET
S1C17M13 pin configuration diagram (TQFP12-48pin)
Seiko Epson Corporation
5
S1C17M12/M13
■ PIN DESCRIPTIONS
Symbol meanings
Pin/pad
name
VDD
VDD2
VSS
VSS2
VPP
VD1
#RESET
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
6
Assigned
signal
VDD
VDD2
VSS
VSS2
VPP
VD1
#RESET
P00
UPMUX
ADIN07
P01
UPMUX
ADIN06
P02
UPMUX
ADIN05
P03
UPMUX
ADIN04
P04
UPMUX
ADIN03
P05
UPMUX
ADIN02
P06
UPMUX
ADIN01
P07
UPMUX
ADIN00
P10
UPMUX
VREFA0
P11
UPMUX
EXSVD0
I/O
P
P
P
P
P
A
I
I/O
I/O
A
I/O
I/O
A
I/O
I/O
A
I/O
I/O
A
I/O
I/O
A
I/O
I/O
A
I/O
I/O
A
I/O
I/O
A
I/O
I/O
A
I/O
I/O
A
Initial
state
Tolerant
fail-safe
structure
–
–
–
–
–
–
I (Pull-up)
Hi-Z
–
–
–
–
–
–
–
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Function
Power supply (+), I/O power supply (except for P50–54)
I/O power supply (P50–54)
GND (except for P40–47, P50–54)
GND (P40–47, P50–54)
Power supply for Flash programming
VD1 regulator output
Reset input
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 analog signal input 7
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 analog signal input 6
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 analog signal input 5
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 analog signal input 4
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 analog signal input 3
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 analog signal input 2
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 analog signal input 1
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 analog signal input 0
I/O port
User-selected I/O (universal port multiplexer)
12-bit A/D converter Ch.0 reference voltage input
I/O port
User-selected I/O (universal port multiplexer)
External power supply voltage detection input Ch.0
Seiko Epson Corporation
S1C17M12
S1C17M13
Assigned signal: The signal listed at the top of each pin is assigned in the initial state. The pin function must be
switched via software to assign another signal (see the “I/O Ports” chapter).
I/O:
I
= Input
O
= Output
I/O
= Input/output
P
= Power supply
A
= Analog signal
Hi-Z
= High impedance state
Initial state:
I (Pull-up)
= Input with pulled up
I (Pull-down) = Input with pulled down
Hi-Z
= High impedance state
O (H)
= High level output
O (L)
= Low level output
Tolerant fail-safe structure:
✓
= Over voltage tolerant fail-safe type I/O cell included (see the “I/O Ports” chapter)
The over voltage tolerant fail-safe type I/O cell allows interfacing without passing unnecessary current even if a voltage exceeding VDD is applied to the port. Also unnecessary current is not consumed when the port is externally biased without supplying VDD.
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Pin/pad
name
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P53
P54
PD0
PD1
PD2
Assigned
signal
P12
UPMUX
EXSVD1
P13
EXOSC
UPMUX
P14
EXCL00
UPMUX
P15
EXCL01
UPMUX
P16
FOUT
UPMUX
P17
#ADTRG0
UPMUX
P20
UPMUX
P21
UPMUX
P22
UPMUX
P23
UPMUX
P24
UPMUX
P40
SEG0
P41
SEG1
P42
SEG2
P43
SEG3
P44
SEG4
P45
SEG5
P46
SEG6
P47
SEG7
P50
REMO
COM0
P50
CLPLS
COM1
P50
COM2
P50
COM3
P50
COM4
DST2
PD0
DSIO
PD1
DCLK
PD2
I/O
I/O
I/O
A
I/O
I
I/O
I/O
I
I/O
I/O
I
I/O
I/O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
O
I/O
O
O
I/O
O
I/O
O
I/O
O
O
I/O
I/O
I/O
O
O
Initial
state
Tolerant
fail-safe
structure
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
Hi-Z
–
O (L)
–
I (Pull-up)
–
O (H)
–
Function
I/O port
User-selected I/O (universal port multiplexer)
External power supply voltage detection input Ch.1
I/O port
Clock generator external clock input
User-selected I/O (universal port multiplexer)
I/O port
16-bit PWM timer Ch.0 event counter input 0
User-selected I/O (universal port multiplexer)
I/O port
16-bit PWM timer Ch.0 event counter input 1
User-selected I/O (universal port multiplexer)
I/O port
Clock external output
User-selected I/O (universal port multiplexer)
I/O port
12-bit A/D converter Ch.0 trigger input
User-selected I/O (universal port multiplexer)
I/O port
User-selected I/O (universal port multiplexer)
I/O port
User-selected I/O (universal port multiplexer)
I/O port
User-selected I/O (universal port multiplexer)
I/O port
User-selected I/O (universal port multiplexer)
I/O port
User-selected I/O (universal port multiplexer)
I/O port
High drive-capability
Nch output
LED segment output
I/O port
High drive-capability
Nch output
LED segment output
I/O port
High drive-capability
Nch output
LED segment output
I/O port
High drive-capability
Nch output
LED segment output
I/O port
High drive-capability
Nch output
LED segment output
I/O port
High drive-capability
Nch output
LED segment output
I/O port
High drive-capability
Nch output
LED segment output
I/O port
High drive-capability
Nch output
LED segment output
I/O port
High drive-capability
Pch output
IR remote controller transmit data output
LED common output
I/O port
High drive-capability
Pch output
IR remote controller clear pulse output
LED common output
I/O port
High drive-capability
Pch output
LED common output
I/O port
High drive-capability
Pch output
LED common output
I/O port
High drive-capability
Pch output
LED common output
On-chip debugger status output
I/O port
On-chip debugger data input/output
I/O port
On-chip debugger clock output
Output port
Seiko Epson Corporation
S1C17M12
S1C17M13
S1C17M12/M13
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7
Pin/pad
name
PD3
PD4
Assigned
signal
PD3
OSC3
PD4
OSC4
I/O
I/O
A
I/O
A
Initial
state
Tolerant
fail-safe
structure
Hi-Z
–
Hi-Z
–
Function
I/O port
OSC3 oscillator circuit input
I/O port
OSC3 oscillator circuit output
Universal port multiplexer (UPMUX)
S1C17M12
S1C17M13
S1C17M12/M13
✓
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The universal port multiplexer (UPMUX) allows software to select the peripheral circuit input/output function to be assigned
to each pin from those listed below. Note, however, that a function cannot be assigned to two or more pins simultaneously.
Peripheral circuit
Signal to be assigned
Synchronous serial interface SDIn
(SPIA)
SDOn
SPICLKn
#SPISSn
I2C
SCLn
(I2C)
SDAn
UART
USINn
(UART3)
USOUTn
16-bit PWM timer
TOUTn0/CAPn0
(T16B)
TOUTn1/CAPn1
8
I/O
I
O
I/O
I
I/O
I/O
I
O
I/O
I/O
Channel number n
Function
SPIA Ch.n data input
n = 0, 1
SPIA Ch.n data output
SPIA Ch.n clock input/output
SPIA Ch.n slave-select input
I2C Ch.n clock input/output
n=0
I2C Ch.n data input/output
UART3 Ch.n data input
n=0
UART3 Ch.n data output
T16B Ch.n PWM output/capture input 0
n=0
T16B Ch.n PWM output/capture input 1
Seiko Epson Corporation
S1C17M12/M13
COM0
COM1
COM2
COM3
COM4
■ Basic External Connection Diagram
EXSVDn
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
REMO
IR transmitter module
RDBG
VDD
DCLK
DSIO
DST2
VPP
1.8–5.5 V
VDD
CPW1
+
CPW3
∗1
VD1
( )
OSC3
( )
OSC4
CG3
CD3 X'tal3/
Ceramic
External voltage
VDD2
S1C17M12/M13
[The potential of the substrate
(back of the chip) is VSS.]
#RESET
1.8–5.5 V
CPW2
+
∗2
VSS2
ICDmini
CVPP
I/O
SDIn
SDOn
SPICLKn
#SPISSn
SPI
SCL0
SDA0
I2C
TOUT00/CAP00
TOUT01/CAP01
VDD2
)
Pxy
USIN0
USOUT0
VSS
(
ADIN00–07
#ADTRG0
VREFA0
UART
PWM/Capture
A/D conversion inputs
*1: When OSC3 crystal/ceramic oscillator is selected
*2: Available only in the S1C17M13
( ): Do not mount components if unnecessary.
Sample external components
Symbol
X’tal3
Ceramic
CG3
CD3
CPW1
CPW2
CPW3
RDBG
CVPP
Name
Crystal resonator
Ceramic resonator
OSC3 gate capacitor
OSC3 drain capacitor
Bypass capacitor between VSS and VDD
Bypass capacitor between VSS2 and VDD2
Capacitor between VSS and VD1
DSIO pull-up resistor
Capacitor between VSS and VPP
Recommended components
CA-301 (4 MHz) manufactured by Seiko Epson Corporation
CSBLA_J (1 MHz) manufactured by Murata Manufacturing Co., Ltd.
Ceramic capacitor
Ceramic capacitor
Ceramic capacitor or electrolytic capacitor
Ceramic capacitor or electrolytic capacitor
Ceramic capacitor
Thick film chip resistor
Ceramic capacitor
Seiko Epson Corporation
9
S1C17M12/M13
NOTICE:
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Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out
of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation
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property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this
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material, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical information
furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other military purposes.
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©Seiko Epson Corporation 2016, All rights reserved
EPSON semiconductor website
MICRODEVICES OPERATIONS DIVISION
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http://global.epson.com/products/semicon/
Document Code: 413284400
Issue June 2016 in JAPAN L
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