S5U13714P00C000

GRAPHICS S1D13714 S1D13714 Mobile Graphics Engine August 2007 The S1D13714 is an LCD solution designed with support for the digital video revolution in mobile products. The S1D13714 contains an integrated dual port camera interface, hardware JPEG encoder/decoder and can be interfaced to an external MPEG codec. Seamlessly connecting to both direct and indirect CPU interfaces, it provides support for up to two LCD panels. The LCD controller supports all standard TFT panel types and many extended TFT types, eliminating the need for an external timing control IC. The S1D13714 with it’s 320K bytes of embedded SRAM and rich feature set provides a low cost, low power, single chip solution to meet the demands of embedded markets requiring Digital Video, such as Mobile Communications devices and Palm-size PCs. Additionally, products requiring a rotated display can take advantage of the SwivelViewTM feature which provides hardware rotation of the display memory transparent to the software application. The S1D13714 also provides support for “Picture-in-Picture Plus” (a variable size window with overlay functions). Higher performance is provided by the Hardware Acceleration Engine which provides 2D BitBLT functions. The S1D13714 provides impressive support for cellular and other mobile solutions requiring Digital Video support. However, its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications. ■ FEATURES • • • • • • • • • • • • Embedded 320K byte SRAM Display Buffer Low Operating Voltage Direct and Indirect CPU interfaces Programmable resolutions and color depths Support for 2 panels (LCD2 must be RAM integrated) Support for RGB, Serial and Parallel I/F panels Extended TFT interfaces including HR-TFT Internal PLL or digital clock input Dual port Camera interface w/resize function Hardware JPEG encoder/decoder YUV to RGB converter SwivelViewTM (90°, 180°, 270° hardware rotation of displayed image) • (Patent # 5,734,875 - Patent # 5,956,049 - Patent #6,262,751) • “Picture-in-Picture Plus” • 2D Hardware Acceleration Engine • Software Initiated Power Save Mode ■ SYSTEM BLOCK DIAGRAM Main Display RGB or Parallel Secondary Display 13714 Data and Control Signals S1D13714 Includes: • 320KB SRAM • JPEG Encoder/Decoder • View/Capture Resizer • 2D Hardware Acceleration • Multiple panel support X49A-C-001-01 Serial or Parallel (Ram Integrated) Camera Interface (dual port) CPU Revision 1.01 1 GRAPHICS S1D13714 ■ DESCRIPTION Integrated Display Buffer Display Features • 320K bytes of embedded SRAM • Addressable as a single linear address space • 8/16/32 bit-per-pixel (bpp) support • Picture-in-Picture Plus: displays a variable size win- CPU Interface • • • • 16-bit Generic Asynchronous CPU interface • Direct and Indirect addressing Panel Support Digital Video • Supports up to 2 LCD panels • LCD1: 9/12/18/24-bit RGB panel • Dual port Camera Interface (YUV 4:2:2) • Hardware JPEG Encoder / Decoder (YUV 4:2:2, LCD2: 8/9-bit Serial Ram Integrated panel • LCD1: 8/16/18/24-bit Parallel Ram Integrated panel • • LCD2: 8/9-bit Serial Ram Integrated panel • LCD1: 8/16/18/24-bit Parallel Ram Integrated panel LCD2: 8/16/18/24-bit Parallel Ram Integrated panel • LCD1: 9/12/18/24-bit RGB panel • LCD2: 8-bit Parallel Ram Integrated panel • TFT, HR-TFT, Casio TFT, α-TFT, ND-TFD, and • dow overlaid over the background image Overlay Functions Pixel Doubling: doubles the effective resolution Video Invert: inverts display data Extended TFT Typical resolution of: up to 320x480 at 16 bpp up to 320x240 at 32 bpp • • YUV 4:1:1, YUV 4:2:0) YUV Capture / Display (YUV 4:2:2, YUV 4:2:0) Memory Image JPEG Encode (YUV 4:2:2, YUV 4:1:1, YUV 4:2:0) View and Capture hardware resizer with trimming and reduction functions YUV to RGB and RGB to YUV converters Support for external MPEG codec interface Miscellaneous Acceleration • 2D BitBLT Engine • SwivelView: 90°, 180°, 270° hardware rotation of displayed image • • • • • Internal PLL or digital clock input Software initiated power save mode Multiple General Purpose IO pins COREVDD 1.8 volts and IOVDD 1.8 or 3.0 volts FCBGA and PFBGA 160-pin packages CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS • S1D13714 Technical Documentation • S1D13714 Evaluation Boards • Royalty Free source level driver code • CPU Independent Software Utilities Japan Seiko Epson Corporation IC International Sales Group 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/ North America Epson Electronics America, Inc. 2580 Orchard Parkway San Jose, CA 95131, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com/ Taiwan Epson Taiwan Technology & Trading Ltd. 14F, No. 7 Song Ren Road Taipei 110 Tel: 02-8786-6688 Fax: 02-8786-6677 http://www.epson.com.tw/ Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/ Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de/ Singapore Epson Singapore Pte Ltd 1 HarbourFront Place #03-02 HarbourFront Tower One Singapore, 098633 Tel: (65) 6586-5500 Fax: (65) 6271-3182 http://www.epson.com.sg/ © SEIKO EPSON CORPORATION 2003-2007. All rights reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. 2 Revision 1.01 X49A-C-001-01