PBL386652SHT

Preliminary May 2000 PBL 386 65/2 Subscriber Line Interface Circuit Description The PBL 386 65/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in DLC, Central Office and other telecommunications equipment. The PBL 386 65/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 65/2 emulates a transformer equivalent dc-feed, programmable between 2x25 Ω and 2x900 Ω, with short loop current limiting adjustable to max 65 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 65/2 is compatible with loop start and ground start signalling. Two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating impedance could be complex or real to fit every market. Longitudinal line voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet the DLC requirements. The PBL 386 65/2 package is 28-pin PLCC and 28-pin SSOP. Key Features • Selectable overhead voltage principle – All adaptive: The overhead voltage follows 0.6PeakV < signals < 6.2VPeak. – Semi adaptive: The overhead voltage follows 3.1VPeak < signals < 6.2VPeak. • Metering 2.2 Vrms • High and low battery with automatic switching • Battery supply as low as -10 V • Only +5 V in addition to GND and battery (VEE optional) • 39 mW on-hook power dissipation in active state • Long loop battery feed tracks VBat for maximum line voltage • 44V open loop voltage @ -48V battery feed • Constant loop voltage for line leakage 10 s, Note 2 TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2 TIP or RING, pulse < 250 ns, tRep > 10 s, Note 3 TStg TAmb TJ VCC VEE VBat VBat VBat2 PD VG -55 -40 -40 -0.4 VBat -75 -80 VBat +150 +110 +140 6.5 0.4 0.4 0.4 0.4 1.5 °C °C °C V V V V V W V V -5 VCC BGND +13 75 mA VDT, VDR IDT, IDR VID VOD IOD ITIPX, IRINGX VTA, VRA VTA, VRA VTA, VRA VTA, VRA VBat -5 -0.4 -0.4 VCC 5 VCC VCC 30 V mA V V mA -110 VBat VBat - 20 VBat - 40 VBat - 70 +110 2 5 10 15 mA V V V V Recommended Operating Condition Parameter Symbol Min Max Unit Ambient temperature VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND VBat2 with respect to BGND TAmb VCC VEE VBat -40 4.75 VBat -58 VBat +85 5.25 -4.75 -10 -10 °C V V V V Notes 1. 2. 3. The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V. A pulse ≤1µs is increased to the greater of |-70V| and |VBat -40V|. RF1, FR2 ≥20 Ω is also required. Pulse is supplied to TIP and RING outside RF1, FR2. 2 Preliminary Electrical Characteristics PBL 386 65/2 -40 °C ≤ TAmb ≤ +85 °C, VCC = +5V ±5 %, VEE = -5V ± 5%, VBat = -58V to -40V, RLC=18.7kΩ, IL = 27 mA, ZL = 600 Ω, RF1, RF2 =0 Ω, RRef = 15kΩ, CHP = 68nF, CLP=0.33 µF, RT = 120 kΩ, RSG = 24 kΩ, RRX = 120 kΩ, AOV- and VBat2 pin not connected, unless otherwise specified. Current definition: current is positive if flowing into a pin. Parameter Ref fig Conditions Min Typ Max Unit Two-wire port Overload level, VTRO ,ILDC ≥ 10 mA On-Hook, ILDC ≤ 5 mA Input impedance, ZTR Longitudinal impedance, ZLoT, ZLoR Longitudinal current limit, ILoT, ILoR Longitudinal to metallic balance, BLM 2 Active state 1% THD, Note 1 3.1 1.4 35 VPeak VPeak Ω/wire mArms /wire 3 Longitudinal to metallic balance, BLME 3 BLME = 20 • Log ELO VTR Note 2 ZT/200 0 < f < 100 Hz 20 active state 28 IEEE standard 455-1985, ZTRX=736Ω, active state Normal polarity: 0.2 kHz < f < 1.0 kHz, Tamb 0-70°C 63 1.0 kHz < f < 3.4 kHz, Tamb 0-70°C 58 0.2 kHz < f < 1.0 kHz, Tamb -40-85°C 58 1.0 kHz < f < 3.4 kHz, Tamb -40-85°C 54 Reverse polarity: 0.2 kHz < f < 3.4 kHz, Tamb -40-85°C 54 Active state Normal polarity: 0.2 kHz < f < 1.0 kHz, Tamb 0-70°C 63 1.0 kHz < f < 3.4 kHz, Tamb 0-70°C 58 0.2 kHz ≤ f ≤ 1.0 kHz, Tamb -40-85°C 58 1.0 kHz < f < 3.4 kHz, Tamb -40-85°C 54 Reverse polarity: 0.2 kHz < f < 3.4 kHz, Tamb -40-85°C 54 Active state Normal polarity: 0.2 kHz < f < 1.0 kHz, Tamb 0-70°C 1.0 kHz < f < 3.4 kHz, Tamb 0-70°C 0.2 kHz ≤ f ≤ 1.0 kHz, Tamb -40-85°C 1.0 kHz < f < 3.4 kHz, Tamb -40-85°C Reverse polarity: 0.2 kHz < f < 3.4 kHz, Tamb -40-85°C Active state 0.2 kHz < f < 3.4kHz dB dB dB dB dB dB dB dB dB dB Longitudinal to four-wire balance, BLFE 3 BLFE = 20 • Log ELO VTX 69 64 64 60 54 40 dB dB dB dB dB dB Metallic to longitudinal balance, BMLE BMLE = 20 • Log VTR VLO 4 Figure 2. Overload level, VTRO, two-wire port 1 20 kΩ. If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended. RFB VTX RTX VT ZT Z RX ZB PBL 386 65/2 Combination CODEC/Filter V RX RSN Figure 10. Hybrid function. 11 PBL 386 65/2 High-Pass Transmit Filter When CODEC/filter with a singel 5 V power supply is used, it is necessary to separate the different signal reference voltages between the SLIC and the CODEC/filter. In the transmit direction this can be done by connecting a capacitor between the VTX output of the SLIC and the CODEC/filter input. This capacitor will also form, together with RTX and/or the input impedance of the CODEC/filter, a high-pass RC filter. It is recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a fast enough response for the dc steps that may occur with DTMF signaling. Preliminary Capacitor CLP The capacitor CLP, which connects between the terminals LP and VBAT, positions the high end frequency break point of the low pass filter in the dc loop in the SLIC. CLP together with CHP and ZT (see section TwoWire Impedance) forms the total two wire output impedance of the SLIC. The choice of these programming components influence the power supply rejection ratio (PSRR) from VBAT to the two wire side in the low frequency range. RFeed RSG CLP CHP [Ω] [kΩ] [nF] [nF] 4.02 330 68 2•25 2•50 23.7 330 68 2•200 147 100 33 2•400 301 47 33 2•800 619 22 33 Table 1. RSG, CLP and CHP values for different feeding characteristics. Table 1 suggest values of CLP and CHP for different feeding characteristics. Adaptive Overhead Voltage, AOV The Adaptive Overhead Voltage feature minimises the power dissipation and at the same time provides a flexible solution for differing system requirements and possible future changes concerning voice, metering and other signal levels. This is done by using an overhead voltage which automatically adapts to the signal level (voice + metering). With the AOV-pin left open, the PBL 386 65/2 will behave as a SLIC with fixed overhead voltage for signals in the 0 - 20kHz frequency range and with an ampli- Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst undersampled). tude less than 3.1VPeak11. For signal amplitudes between 3.1VPeak and 6.2VPeak, the AOV-function will expand the overhead voltage making it possible for the signal, Vt, to propagate through the SLIC without distortion (see figure 11). The expansion of the overhead voltage occurs instantaneously. When the signal amplitude decreases, the overhead voltage returns to its initial value with a time constant of approximately one second. If the AOV-pin is connected to AGND, the overhead voltage will automatically be adjusted for signal levels between 0.6 VPeak and 6.2 VPeak. AOV In the Constant Current Region When the overhead voltage is automatically increased, the apparent battery (VApp, reference F in figure 15), will be reduced by the signal amplitude minus 3.1 VPeak(11), (Vt - 3.1(11)). In the constant current region this change will not affect the line current as long as VTR < VApp - (ILConst • RFeed) - (Vt-3.1(11)), (references A-C in figure 15). AOV In the Resistive Loop Feed Region The saturation guard will be activated when the SLIC is working in the resistive loop feed region, i.e. VTR > VApp - (ILConst • RFeed) - (Vt - 3.1(11)) (references D in figure 15). If the signal amplitude is greater than 3.1VPeak11 the line current, IL, will be reduced corresponding to the formula ∆IL = | (Vt - 3.1(11))/(RL + RFeed) |. This reduction of line current will introduce a transversal signal into the two-wire which under some circumstances may be audible (e g when sending metering signals > 3.1 VPeak without any speech signal burying the transversal signal generated from the linecurrent reduction). The sum of all signals should not exceed 6.2 VPeak. Line Feed If VTR < VApp - (ILConst • RFeed), the PBL 386 65/ 2 SLIC will emulate constant current feed (references A-C in figure 15). For VTR > VApp - (ILConst • RFeed) the PBL 386 65/2 SLIC will emulate resistive loop feed programmable between 2•25 Ω12 and 2•900 Ω (references D in figure 15). The current limitation region is adjustable between 0 mA and 65 mA13. When the line current is approaching open loop conditions, the overhead voltage is reduced. To ensure maximum open loop voltage, even with telephone line leakage, this occurs at a line current of approximately 5 mA (references E in figure 15). After the overhead voltage reduction, the line voltage is kept nearly constant with a steep slope corresponding to 2 • 25 Ω(reference G in figure 15). The open loop voltage, VTRMax, measured between the TIPX and RINGX terminals is tracking the battery voltage VBat (references H in figure 15). VTRMax is programmable by connecting the AOV-pin to AGND or by leaving the AOV-pin open. 12 Preliminary VTRMax is defined as the battery voltage on the VBat terminal minus the Battery Over Head voltage, VBOH, according to the equation VTRMax(at IL = 0 mA) = |VBat| - VBOH Refer to table 2 for typical VBOH values. VBOH(typ) [V] AOV-PIN NC 4.2 AOV-PIN to AGND 3.2 Table 2. The battery overhead voltages at open loop conditions. Resistive Loop Feed Region The resistive loop feed (reference D in figure 15) is programmed by connecting a resistor RSG , between terminals PSG and VBAT according to the equation RFeed = RSG + 40 + 2RF 400 PBL 386 65/2 Figure 12. Silent Polarity Reversal Constant Current Region The current limit (reference C in figure 15) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation: RLC = 500 ILProg 14 Battery Switch (VBAT2) To reduce short loop power dissipation, a second lower battery voltage may be connected to the device through an external diode at terminal VBAT2. The SLIC automatically switches between the two battery supply voltages without need for external control. The silent battery switching occurs when the line voltage passes the value VTR = |VBat2| - 40•IL - 6 15 Connect the terminal VBAT2 to the second power supply via the diode DB2 in figure 14. An optional diode DBB connected between terminal VBAT and the VB2 power supply, see figure 13, will make sure that the SLIC continues to work on the second battery even if the first battery voltage disappears. If the VB2 voltage is not available, an optional external power management resistor, RPM, may be connected between the VBAT2-pin and the VBAT-pin to move power dissipation outside the chip. Calculation of the external power management resistor to locate the maximum power dissipation outside the SLIC is according to: RPM = |VBat| - 3 ILProg where: VTTX is the voltage of the signal at the metering generator, ZLTTX is the line impedance seen by the 12 or 16 kHz metering signal, G2-4S is the transmit gain through the SLIC, i e -0.5. (Phase shift 180°) In metering applications with resistive line feeding characteristic and very strict requirements (as mentioned earlier in chapter “AOV in resistive loop feed region“), the metering signal level should not exceed 2.2 VRMS 16, since a reduction of the line current will generate a transversal, and sometimes audible, signal (which is not the case in the constant current region). Metering Applications, TTX It is very easy to use PBL 386 65/2 in metering applications; simply connect a suitable resistor (RTTX) in series with a capacitor (CTTX) between pin RSN and the metering source. Capacitor CTTX decouples all DC-voltages that may be superimposed on the metering signal. Choose 1/ (2πRTTXCTTX) ≥ 5kHz to suppress low frequency disturbances from the metering puls generator. The metering signal gain can be calculated from the equation: G4-2TTX = ZT • RTTX VTR = VTTX ZLTTX Silent Polarity Reversal The reversal time is set by a capacitor, Csprv, between the pin SPR and AGND. The reversal has a setup time and reversal time see figure 12. The setup time is different in Active- to Reversal-state and Reversal- to Active state but the silent polarity reversal time is the same Active- to Reversal-state and Reversal- to Active state. To calculate the silent polarity reversal time use following formula: tr =CSPR . 9500 αRSN ZT - G2-4S • (ZLTTX + 2RF) 13 PBL 386 65/2 Preliminary R FB PBL 386 65/2 KR RRLY VTX AGND RSN DET NC C1 C2 C3 VCC PLD PLC SPR REF VEE R TX RT RB + out +12 V /+5V C GG R F1 C RC VB C TC D B2 C HP TS NC R RX RING HP RINGX BGND TIPX VBAT VBAT2 out CODEC/ Filter OVP TIP R F2 VB2 DB VB CB R1 E RG R RF R RT R2 C LP D BB C B2 R SG VCC R LD R LC SYSTEM CONTROL INTERFACE AOV PSG LP DR DT R REF VEE C1 R3 R4 C2 +5 V C VCC VCC C VEE VBAT