GLT41016-40J4

G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Features : ∗ ∗ ∗ ∗ ∗ 65,536 words by 16 bits organization. Fast access time and cycle time. Dual CAS Input. Low power dissipation. Read-Modify-Write, RAS -Only Refresh, Description : The GLT41016 is a 65,536 x 16 bit highperformance CMOS dynamic random access memory. The GLT41016 offers Fast Page mode with Extended Data Output, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT41016 accepts 256-cycle refresh in 4ms interval. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 256 x 16 bits, within a page, with cycle times as short as 12ns. The GLT41016 is best suited for graphics, and DSP applications requiring high performance memories. CAS -Before- RAS Refresh, Hidden Refresh and Test Mode Capability. ∗ 256 refresh cycles per 4ms. ∗ Available in 40-pin 400 mil SOJ and 40/44 pin TSOP (II). ∗ Single 5.0V±10% Power Supply. ∗ All inputs and Outputs are TTL compatible. ∗ Extended Data-Out(EDO) Page Mode operation. HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) Max. CAS Access Time (tCAC) 30 30 ns 15 ns 12 ns 65 ns 10 ns 35 35 ns 18 ns 13 ns 70 ns 11 ns 40 40 ns 20 ns 15 ns 75 ns 12 ns 45 45 ns 22 ns 18 ns 80 ns 12 ns G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -1- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Pin Configuration : GLT41016 SOJ Top View TSOP(Type II) Top View Pin Descriptions: Name A0 - A7 RAS UCAS LCAS WE OE DQ0 - DQ15 VCC VSS NC Function Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Inputs / Outputs +5V Power Supply Ground No Connection G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -2- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Absolute Maximum Ratings* Operating Temperature, TA (ambient) Capacitance* TA=25°C, VCC=5V±10%, VSS=0V Unit pF pF pF Max. Parameter Symbol .......................................-0°C to +70°C 5 Address Input Storage Temperature(plastic)....-55°C to +150°C CIN1 Voltage Relative to VSS...............-1.0V to + 7.0V CIN2 7 RAS , LCAS , UCAS , WE , OE Short Circuit Output Current......................50mA 7 Data Input/ Output Power Dissipation......................................1.0W COUT *Note: Operation above Absolute Maximum Ratings *Note: Capacitance is sampled and not 100% tested can adversely affect device reliability. Electrical Specifications l l l CAS means UCAS and LCAS . All voltages are referenced to GND. After power up, wait more than 100µs and then, execute eight CAS -before- RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit. Block Diagram : G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -3- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Extended Data Output (EDO) Page Mode The EDO page mode is a kind of page mode with enhanced features. The two major features of the EDO page mode are as follows. 1. Data output time is extended. In the EDO page mode, the output data is held to the next CAS cycle‘s falling edge, instead of the rising edge. For this reason, valid data output time in the EDO page mode is extended compared with the fast page mode (=data extend function). In the fast page mode, the data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in the EDO page mode, the timing margin in read cycle is larger than of the fast page mode even if the CAS cycle time becomes shorter. 2. The CAS cycle time in the EDO page mode is shorter than that in the fast page mode. In the EDO page mode, due to the data extend function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. Taking a device whose tRAC is 60ns as an example, the CAS cycle time in the EDO page mode is 25ns while that in the fast page mode is 40ns. In the EDO page mode, read (data out) and write (data in) cycles can be executed repeatedly during one RAS cycle. The EDO page mode allows both read and write operations during one cycle, but the performance is equivalent to that of the fast page mode in that case. G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -4- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Truth Table: GLT41016 Function Standby Read: Word Read: Lower Byte RAS H L L CASL CASH H→X H→X L L L H WE X H H OE X L L ADDRESS High-Z DQs Notes ROW/COL Data Out ROW/COL Lower Byte,DataOut Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,DataOut ROW/COL Data-In ROW/COL Lower Byte,Data-In Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-In ROW/COL Data-Out,Data-In ROW/COL Data-Out COL Data-Out Read: Upper Byte L H L H L Write: Word(Early Write) Write: Lower Byte (Early) Write: Upper Byte (Early) Read Write EDO-PageMode Read EDO-PageMode Write EDO-PageMode ReadWrite Hidden Refresh 2nd Cycle Read Write RAS -Only Refresh CBR Refresh 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle 1st Cycle L L L L L L L L L L L H L H→L H→L H→L H→L H→L L H L L H→L H→L H→L H→L H→L L L L H→L H H L L H→L X X X L→H L L X X L→H 1,2 1 1 2 2 1,2 ROW/COL Data-In COL Data-In ROW/COL Data-Out,Data-In L L→H→L L→H→L L H→L H→L L L H L H→L L L H L H→L H L X X L→H L X X X COL Data-Out,Data-In 1,2 1 2,3 ROW/COL Data-Out ROW/COL Data-In ROW High-Z High-Z 4 Notes: 1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active). 2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active ( UCAS or LCAS ). G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -5- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified. Sym . ILI Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE Test Conditions 0V ≤ VIN ≤ 5.5V (All other pins not under test=0V) 0V ≤ Vout ≤ 5.5V Output is disabled (Hiz) tRC = tRC (min.) Access Time Min. -10 Typ Max. +10 Unit Notes µA µA ILO ICC1 -10 tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 45ns +10 180 170 160 150 4 mA 1,2 ICC2 Standby Current,(TTL) ICC3 Refresh Current, RAS -Only ICC4 Operating Current, EDO Page Mode RAS , UCAS , LCAS at VIH other inputs ≥VSS RAS cycling, UCAS , LCAS at VIH tRC = tRC (min.) RAS at VIL, UCAS , LCAS address cycling: tPC = tPC(min.) tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 45ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 45ns tRAC = 30ns tRAC = 35ns tRAC = 40ns tRAC = 45ns mA mA 2 ICC5 Refresh Current, CAS Before RAS RAS , UCAS , LCAS address cycling: tRC = tRC (min.) 180 170 160 150 180 170 160 150 180 170 160 150 2 mA 1,2 mA 1 ICC6 Standby Current, (CMOS) RAS ≥VCC-0.2V, UCAS ≥VCC-0.2V, LCAS ≥VCC-0.2V, All other inputs VSS VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage -1 2.4 IOL = 4.2mA IOH = -5mA 2.4 mA +0.8 VCC+1 0.4 V V V V 3 3 Notes: 1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC. G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -6- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) AC Characteristics TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V An initial pause of 100 µs and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up. 30 Parameter Read or Write Cycle Time Read Modify Write Cycle Time RAS Precharge Time RAS Pulse Width Access Time from RAS Access Time from CAS Access Time from Column Address CAS to Output Low-Z CAS to Output High-Z RAS Hold Time RAS Hold Time Referenced to OE CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Set-Up Time Row Address Hold Time Column Address Set-Up Time Column Address Hold Time Column Address to RAS Lead Time Column Address Hold Time Referenced to RAS Read Command Set-Up Time Read Command Hold Time Referenced to CAS 35 70 95 25 75 40 80 45 ns ns ns Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes tRC tRWC tRP tRAS tRAC tCAC tAA tCLZ tCEZ tRSH tROH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tAR tRCS tRCH t 0 3 10 7 25 6 13 10 5 0 6 0 6 15 26 0 0 0 0 6 6 10k 20 15 8 65 90 25 100 25 103 30 30 100k 35 100k 40 100k 45 100k ns 30 10 15 0 3 12 8 30 6 17 12 5 0 7 0 6 18 30 0 0 0 0 6 6 10k 24 17 8 35 11 18 0 3 12 8 34 6 18 13 5 0 8 0 6 20 34 0 0 0 0 6 6 10K 28 20 8 40 12 20 0 3 13 9 40 7 18 13 5 0 8 0 6 23 39 0 0 0 0 6 6 8 45 12 22 ns ns ns ns ns ns ns ns 10K ns 33 23 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 4 8,9 7 1,2,3 1,5,10 1,5,6 Read Command Hold Time Referenced to RAS RRH Write Command Set-Up Time tWCS Write Command Hold Time Write Command Pulse Width G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. tWCH tWP G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -7- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) AC Characteristics 30 Parameter Write Command to RAS Lead Time Write Command to CAS Lead Time Data Set-Up Time Data Hold Time Data Hold Time Referenced to RAS RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to CAS Precharge Time Access Time from CAS Precharge EDO Page Mode Cycle Time 35 11 11 40 12 12 45 12 12 Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes tRWL tCWL 10 10 ns ns tDS tDH tDHR tRWD tCWD tAWD tRPC tCPA tPC tCP tRASP tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tOCH tCHO tOEP tCSR tCHR tT tREF 0 6 26 44 22 25 0 17 12 43 5 0 7 31 49 23 30 0 20 13 47 5 0 8 36 54 24 32 0 22 15 50 5 0 8 41 59 24 34 0 24 18 52 7 ns ns ns ns ns ns ns ns ns ns ns EDO Page Mode Read-Modify-Write Cycle Time tPRWC CAS Precharge Time (EDO Page Mode) RAS Pulse Width (EDO Page Mode Only) Access Time from OE OE to Data Delay Time OE to Output High-Z OE Command Hold Time Data Output Hold after CAS low RAS to Output High-Z WE to Output High-Z OE to CAS Hold Time CAS Hold Time to OE OE Precharge Time CAS Set-Up Time for CAS -before- RAS Cycle CAS Hold Time for CAS -before- RAS Cycle Transition Time Refresh Period G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. 30 100k 35 100k 40 100k 45 100k ns 10 8 3 6 3 3 3 8 8 8 10 10 1.5 50 4 8 10 8 8 3 6 3 3 3 8 8 8 10 10 2 50 4 8 10 8 11 8 3 7 3 3 3 8 8 8 10 10 2 50 4 8 10 8 12 8 3 7 5 3 3 8 8 8 10 10 2 50 4 8 10 8 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ms G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -8- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Notes: 1. Measure with a load equivalent to two TTL inputs and 50 pF. 2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA dominant. 3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRCD (max.), access time will be controlled by tCAC. 4. Either tRRH or tRCH must be satisfied for a Read Cycle. 5. Access time is determined by the longest of tAA, tCAC and tCPA. 6. Assumes that tRAD ≥ tRAD (max.). 7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tAA and tCAC. 8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 9. tWCS (min.) must be satisfied in an Early Write Cycle. 10. tDS and tDH are referenced to the latter occurrence of CAS of WE . 11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns. G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. -9- G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Read CYCLE Note : DIN = OPEN G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 10 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Early Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 11 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) OE Controlled Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 12 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Read - Modify - Write Cycle G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 13 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) EDO Page Mode Read Cycle G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 14 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) EDO Page Mode Early Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 15 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) EDO Page Mode Read - Modify - Write Cycle NOTE : DOUT = OPEN G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 16 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) CAS - Before - RAS Refresh Cycle RAS-Only Refresh Cycle G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 17 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Hidden Refresh Cycle ( Read ) G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 18 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Hidden Refresh Cycle ( Write ) NOTE : DOUT = OPEN G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 19 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) CAS -Before- RAS Refresh Counter Test Cycle Read Cycle Write Cycle Read-Modify-Write Ordering Information G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 20 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Part Number GLT41016-30J4 GLT41016-35J4 GLT41016-40J4 GLT41016-45J4 GLT41016-30TC GLT41016-35TC GLT41016-40TC GLT41016-45TC SPEED 30ns 35ns 40ns 45ns 30ns 35ns 40ns 45ns POWER Normal Normal Normal Normal Normal Normal Normal Normal FEATURE EDO EDO EDO EDO EDO EDO EDO EDO PACKAGE SOJ 400mil 40L SOJ 400mil 40L SOJ 400mil 40L SOJ 400mil 40L TSOP 400mil 44L TSOP 400mil 44L TSOP 400mil 44L TSOP 400mil 44L Parts Numbers (Top Mark) Definition : GLT 4 10 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note 16 - 40 J4 CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP VOLTAGE Blank : 5V L : 3.3V M : Mix Voltage Note : CÙCDROM , HÙHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type. G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 21 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) Package Information 400mil 40 pin Small Outline J-form Package (SOJ) G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 22 - G -LINK GLT41016 64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Dec 1998 (Rev 2.1) 40/44 Lead Thin Small Outline Package TSOP(Type II) G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 2F, No.12, R&D Rd. II, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. - 23 -