SPLC100A1

SPLC100A1 40-CHANNEL SEG/COM LCD DRIVER GENERAL DESCRIPTION The SPLC100A1 is a Liquid Crystal Display driver that contains two sets of 20-bit bi-directional shift registers, 20 data latch flip-flops and 20 Liquid Crystal Display drivers. It also features 40-channel outputs that can be applied as common or segment driver. The SPLC100A1 receives serial display data from a display control LSI, converts it into parallel data and supplies liquid crystal display waveforms to the liquid crystal. FEATURES Liquid Crystal Display driver with serial/parallel BLOCK DIAGRAM Y1 Y20 conversion function. V1,V2 Serial transfer facilitates board design. Capable of interfacing to liquid crystal display controllers: HD43160AH, HD61830, HD44780, HD44790, SPLC780 40 internal LCD drivers. Internal serial/parallel conversion circuits: — 20-bit — 20-bit V3,V4 LCD Drivers Latch signal CL1 DL1 CL2 DL2 FCS M V1,V2 V5,V6 Data Shift signal 20-bit latch 20-bit bidirectional shift register Switching circuit 20-bit bidirectional shift register Data 20-bit latch LCD Drivers Shift direction Data Data Shift direction SHL1 DR1 DR2 SHL2 shift register latch 2 2 Y21 Y40 Power supply: — — Internal logic: 2.7V – 5.5V Liquid crystal display driver circuit: 3.0V – 11.0V CMOS process. Sunplus Technology Co., Ltd. 1 Rev.: 1.0 1999.10.04 SPLC100A1 FUNCTION DESCRIPTION SEGMENT DRIVER When SPLC100A1 is used as a segment driver, FCS is connected to VSS. In this case, both channel 1 and channel 2 shift data at the falling edge of CL2 and latch it at the falling edge of CL1. V3 and V5, V4 and V6 of the liquid crystal display driver power supply are short-circuited, respectively. 7 (FLM) M CL1 Output of latch (Y1 ~ Y40) Enlarged view M CL1 CL2 DL1/DR1 DL2/DR2 Latch Shift 8 1 2 3 4 5 6 7 8 1 2 Segment data waveforms ( A type waveforms, 1/8 duty cycle ) Sunplus Technology Co., Ltd. 2 Rev.: 1.0 1999.10.04 SPLC100A1 COMMON DRIVER In this case, channel 1 is used as a segment driver and channel 2 as common driver. When channel 2 of SPLC100A1 is used as common driver, FCS is connected to VDD. In this case, channel 2 shifts data at the rising edge of CL1 and latches it at the rising edge of CL2. 8 DL2/DR2(FLM) 1 Shift 2 3 4 5 6 7 8 1 2 CL1 Y21 (Y40) Y22 (Y33) to Y28 (Y33) Enlarged view DL2/DR2(FLM) M Shift CL1 Latch CL2 Y21 (Y40) Non-Select Select Select Select Non-Select Non-Select Select Select Select Common data waveforms ( A type waveforms of channel 2, 1/8 duty cycle ) Sunplus Technology Co., Ltd. 3 Rev.: 1.0 1999.10.04 SPLC100A1 Both Channel 1 and Channel 2 Used as Common Drivers ( FCS = VDD ) Common Drivers ( FCS = VDD ) When both of channel 1 and channel 2 are used common drives, FCS is connected to VDD and the signals (CL1, CL2, FLM) from the controller are connected as following. In this case, connection of the Liquid Crystal Display driver power supply is different from that of segment driver, V1,V2: Select level of segment and common V3,V4: Non-select level of segment V5,V6: Non-select level of common VDD SHL1 CL2 CL1 DL1 Common DR1 driver DL2 DR2 SPLC100A1 Y40 - 1 V1 V2 V3 V4 V5 V6 SPLC100A1 Segment driver V1 V2 V3 V4 V5 V6 Y40 - 1 SPLC100A1 Segment driver V1 V2 V3 V4 V5 V6 SHL2 FCS Y40 - 1 LCD Controller Drive voltage of liquid crystal Sunplus Technology Co., Ltd. display V1 V2 V3 V4 V5 V6 4 Rev.: 1.0 1999.10.04 SPLC100A1 PIN DESCRIPTION Mnemonic VDD VSS VEE Y6 – 1 Y20 – 7 Y27 – 21 Y40 – 28 V1, V2 V3, V4 V5, V6 SHL1 PIN No. Type 22 32 29 23-28 8-21 1-7 47-59 41,42 43,44 45,46 38 I I I I Power supply for liquid crystal display drive ( Select level ) Power supply for liquid crystal display drive (Non-select level for channel 1) Power supply for liquid crystal display drive (Non-select level for channel 2) Selection of the shift direction of channel 1 shift register SHL1 DL1 DR1 VDD Out In GND In Out Selection of the shift direction of channel 2 shift register SHL2 DL2 DR2 VDD Out In GND In Out Data Input / Output of channel 1 shift register Data Input / Output of channel 2 shift register Alternated signal for liquid crystal driver output Latch signal for channel 1 ( ) *1 O Liquid crystal driver output ( Channel 2 ) I I I O Description Positive power supply voltage input Ground input Power supply voltage for liquid crystal display drive Liquid crystal driver output ( Channel 1 ) SHL2 39 I DL1, DR1 DL2, DR2 M CL1 33,34 35,36 37 30 I/O I/O I I Used for channel 2 when FCS is GND CL2 31 I Shift signal for channel 1 ( ) *1 Used for channel 2 when FCS is GND FCS 40 I Mode select signal of channel 2. FCS signal exchanges the latch signal and the shift of channel 2 and inverts M for channel 2.Thus, this signal exchanges the function of channel 2. FCS Level Channel 2 Latch signal Shift signal VDD CL2 CL1 GND CL1 CL2 *1 *1 Notes: *1. and M Polarity M M Function For common drive For segment drive *2 indicate the latches at rise and fall times, respectively. *2. The output level relationship between channel 1 and channel 2 based on the FCS signal level as follows: Sunplus Technology Co., Ltd. 5 Rev.: 1.0 1999.10.04 SPLC100A1 Output Level FCS Data H VDD (H) (Select) L (Non-select) H (Select) GND (L) L (Non-select) H L V3 V4 V5 V6 M Channel 1(Y1 - Y20) H L H L H L V1 V2 V3 V4 V1 V2 Channel 2(Y21 - Y40) V2 V1 V6 V5 V1 V2 ABSOLUTE MAXIMUM RATINGS Characteristics Operating Voltage LCD Driver Supply Voltage Input Voltage 1 Input Voltage 2 ( V1 - V6 ) Operating Temperature Storage Temperature Symbol VDD *1 VEE *2 VIN1 VIN2 TOPR TSTG Ratings -0.3V to + 7.0V VDD - 13.5V to VDD+ 0.3V -0.3V to VDD + 0.3V VDD + 0.3V to VEE -0.3V -20 -55 to + 75 to + 125 Note: 1.It will cause damage to IC if the supply voltage is greater than above. 2.Connect a protection resistor of 220 5% to VEE. Sunplus Technology Co., Ltd. 6 Rev.: 1.0 1999.10.04 SPLC100A1 DC CHARACTERISTICS ( VDD = 5V 10%,VEE = -5V 10%, VSS = 0V, Ta = -20 to + 75 Characteristics Input Voltage (CL1, CL2, DL1, DL2, DR1, DR2, M, SHL1, SHL2, FCS) Output Voltage (DL1, DL2, DR1, DR2) LCD Driver Voltage Vi-Yj Voltage Descending V(V6 - 1)-Y(Y40 - 1) Input Leakage Current (CL1, CL2, DL1, DL2, DR1, DR2, M, SHL1, SHL2, FCS ) Vi Leakage Current V6 - 1 IVL ICC IEE SPLC100A vs. SPLC100A1 (1) The test condition has been improved from IOH = -0.35 mA (SPLC100A) to IOH = -0.4mA (SPLC100A1) (2) The minimum working voltage of SPLC100A is 4.5V. In contrast, the minimum working voltage of SPLC100A1 is improved to 3.0V. -10.0 10.0 1.0 10 A mA A VIN = VDD - VEE (Output Y40 - 1: floating ) FCL2 = 400KHz FCL1 = 1KHz IIL -5.0 5.0 A VIN = 0 to VDD VIL VOH VOL VLCD VD1 VD2 0 VDD-0.4 3.0 0.3VDD 0.4 11.0 1.1 1.5 V V V V V V IOH = -0.4mA IOL = +0.4mA VDD - V5 ION = 0.1mA for one of Yj ION = 0.05mA for each Yj Symbol VIH Min. 0.7VDD Typ. ) Max. VDD Unit V Test Condition Power Supply Current Sunplus Technology Co., Ltd. 7 Rev.: 1.0 1999.10.04 SPLC100A1 AC CHARACTERISTICS Characteristics Data Shift Frequency ( CL2 ) Clock Width High Level ( CL1, CL2 ) Low Level ( CL2 ) Symbol FCL tCWH tCWL tSU tSL tLS tPD tCT tDH Min. 800 800 300 500 500 300 Typ. Max. 400 500 200 Unit Test Condition KHz ns ns ns ns ns ns ns ns (CL2 CL1) (CL1 CL2) CL = 15pF Data Set-up Time ( DL1, DL2, DR1, DR2, FLM ) Clock Set-up Time ( CL1, CL2 ) Clock Set-up Time ( CL1, CL2 ) Date Delay Time ( DL1, DL2, DR1, DR2 ) Clock Rise/Fall Time ( CL1, CL2 ) Date Hold Time ( DL1, DL2, DR1, DR2, FLM ) CL2 VIH VIL tCT tCWH VIH VIL tpd tSU tCT tCWL tDH tSL VIH Data in (DL1,DL2,DR1,DR2) Data out (DL1,DL2,DR1,DR2) VOH VOL tLS CL1 VIH VIL tCT tCWH tSU tLS tCT FLM VIH VIL Sunplus Technology Co., Ltd. 8 Rev.: 1.0 1999.10.04 SPLC100A1 APPLICATION NOTES SEGMENT DRIVER COM16 - 1 Controller M CL2 CL1 D Common signal DL 1 FCS SPLC100A1 SHL 1 (segment SHL 2 driver) CL 1 CL 2 M 40 Y40 - 1 LCD Segment signal DR 1 DL 2 DR 2 40 DR 1 DL 2 DR 2 COMMON DRIVER VDD FCS SHL1 CL2 CL1 DL1 SPLC100A1 DR1 DL2 DR2 Common driver SHL2 CL2 CL1 FLM Controller Y40 - 1 LCD CL 1 CL 2 M Y40 - 1 Y40 - 1 DL 1 FCS SPLC100A1 SHL 1 (segment SHL 2 driver) Y40 - 1 SPLC100A1 Segment driver SPLC100A1 Segment driver Sunplus Technology Co., Ltd. 9 Rev.: 1.0 1999.10.04 SPLC100A1 SEGMENT / COMMON DRIVER D M CL2 CL1 FLM Controller Common signal 20 20 Y20 - 1 DL1 Y40 - 21 SPLC100A1 DL2 DR1 (segment FCS /common SHL 1 SHL 2 driver) CL 1 CL 2 M LCD Segment signal VDD Sunplus Technology Co., Ltd. 10 CL 1 CL 2 M DL 1 FCS SPLC100A1 SHL 1 (segment SHL 2 driver) 40 Y40 - 1 DR 1 DL 2 DR 2 Rev.: 1.0 1999.10.04 SPLC100A1 PAD ASSIGNMENT AND LOCATIONS PAD Assignment Chip Size: 2152 m x 2380 m This IC substrate should be connected to VDD Note: To ensure IC function properly, please bond all of the VDD, VSS AVDD and AVSS pins. Ordering Information Product Number SPLC100A1-nnnnV-C Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z). Package Type Chip form NOTE: SUNPLUS TECHNOLOGY GO., LTD reserves the right to make changes at any time without notice in order to improve the design and performance to supply the best possible product. Sunplus Technology Co., Ltd. 11 Rev.: 1.0 1999.10.04 SPLC100A1 PAD Locations Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pad Name Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y9 Y10 Y11 Y8 Y7 VDD Y6 Y5 Y4 Y3 Y2 Y1 VEE CL1 X -912 -910 -913 -913 -913 -913 -912 -912 -912 -910 -912 -912 -913 -912 -913 -912 -744 -614 -484 -358 -234 -109 16 139 265 390 513 642 772 908 Y 889 751 628 498 373 249 123 -2 -126 -249 -373 -500 -628 -756 -891 -1023 -1022 -1022 -1023 -1023 -1022 -1023 -1023 -1023 -1022 -1023 -1023 -1023 -1023 -958 Pad No 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Pad Name CL2 VSS DL1 DR1 DL2 DR2 M SHL1 SHL2 FCS V1 V2 V3 V4 V5 V6 Y40 Y39 Y38 Y37 Y36 Y35 Y30 Y31 Y32 Y33 Y34 Y29 Y28 X 907 907 907 907 908 906 907 907 907 907 907 907 907 907 908 774 644 513 388 264 139 14 -110 -235 -360 -484 -614 -744 -912 Y -826 -690 -565 -434 -312 -188 -63 61 186 309 433 561 687 825 970 1020 1021 1021 1021 1022 1021 1022 1021 1022 1021 1021 1022 1022 1022 Sunplus Technology Co., Ltd. 12 Rev.: 1.0 1999.10.04 SPLC100A1 PACKAGE Configuration QFP 64L Top View Y34 Y33 Y32 Y31 Y30 Y35 Y36 Y37 Y38 Y39 53 Y40 52 NC NC 58 64 63 62 61 60 59 57 56 55 54 NC 1 2 3 51 V6 V5 Y29 Y28 50 49 V4 V3 V2 Y27 Y26 4 5 48 47 46 Y25 Y24 6 7 V1 FCS SHL2 SHL1 45 44 43 Y23 Y22 8 9 10 11 Y21 Y20 SPLC100 42 M 41 40 39 NC DR2 DL2 Y19 Y18 12 13 Y17 14 15 16 38 37 DR1 Y16 Y15 DL1 36 35 34 33 VSS CL2 CL1 VEE Y14 Y13 Y12 17 18 19 Y11 22 20 Y10 21 23 24 VDD 25 26 27 28 29 30 NC Y8 Y7 Y6 Y5 Y4 Y3 Y2 31 Sunplus Technology Co., Ltd. 13 Y1 Y9 32 Rev.: 1.0 1999.10.04 SPLC100A1 PACKAGE Information QFP 64L Outline Dimensions Unit: inch/mm Sunplus Technology Co., Ltd. 14 Rev.: 1.0 1999.10.04 SPLC100A1 DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. reference purposes only. Please note that application circuits illustrated in this document are for Sunplus Technology Co., Ltd. 15 Rev.: 1.0 1999.10.04