TSL201R

t TSL201R 64 y 1 LINEAR SENSOR ARRAY t TAOS030B – AUGUST 2002 D D D D D D D D D 64 × 1 Sensor-Element Organization 200 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 2000:1 (66 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 5 MHz Single 5-V Supply Replacement for TSL201 DIP PACKAGE (TOP VIEW) SI 1 CLK 2 AO 3 VDD 4 8 NC 7 GND 6 GND 5 NC NC – No internal connection Description The TSL201R linear sensor array consists of a 64 × 1 array of photodiodes and associated charge amplifier circuitry. The pixels measure 120 µm (H) by 70 µm (W) with 125-µm center-to-center spacing and 55-µm spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. The TSL201R is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear and rotary encoding. Functional Block Diagram Pixel 1 Integrator Reset Pixel 2 Pixel 3 Pixel 64 Analog Bus Output Amplifier 3 AO Sample/ Output 6, 7 GND RL (External 330 W Load) 4 VDD _ + Switch Control Logic Gain Trim Q1 Q2 Q3 Q64 CLK SI 2 1 64-Bit Shift Register The LUMENOLOGY r Company t Copyright E 2002, TAOS Inc. Texas Advanced Optoelectronic Solutions Inc. 800 Jupiter Road, Suite 205 S Plano, TX 75074 S (972) 673-0759 t www.taosinc.com 1 TSL201R 64 y 1 LINEAR SENSOR ARRAY TAOS030B – AUGUST 2002 Terminal Functions TERMINAL NAME AO CLK GND SI VDD NO. 3 2 6, 7 1 4 Analog output. Clock. The clock controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to the substrate. Serial input. SI defines the start of the data-out sequence. Supply voltage. Supply voltage for both analog and digital circuits. DESCRIPTION Detailed Description The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The integration time is the interval between two consecutive output periods. The output and reset of the integrators is controlled by a 64-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)†. As the SI pulse is clocked through the 64-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 65th clock rising edge, the SI pulse is clocked out of the shift register and the output assumes a high-impedance state. Note that this 65th clock pulse is required to terminate the output of the 64th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented as early as the 66th clock pulse, thereby initiating another pixel output cycle. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee) (tint) where: Vout Vdrk Re Ee tint is is is is is the analog output voltage for white condition the analog output voltage for dark condition the device responsivity for a given wavelength of light given in V/(µJ/cm2) the incident irradiance in µW/cm2 integration time in seconds AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device is not in the output phase, AO is in a high impedance state. A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device. † For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. Copyright E 2002, TAOS Inc. t The LUMENOLOGY r Company t 2 www.taosinc.com TSL201R 64 y 1 LINEAR SENSOR ARRAY TAOS030B – AUGUST 2002 Absolute Maximum Ratings† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA to 40 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions (see Figure 1 and Figure 2) MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, λ Clock frequency, fclock Sensor integration time, tint Operating free-air temperature, TA Load resistance, RL Load capacitance, CL 4.5 0 2 0 400 5 0.017 0 300 NOM 5 MAX 5.5 VDD VDD 0.8 1000 5000 100 70 4700 470 UNIT V V V V nm kHz ms °C Ω pF The LUMENOLOGY r Company t Copyright E 2002, TAOS Inc. t www.taosinc.com 3 TSL201R 64 y 1 LINEAR SENSOR ARRAY TAOS030B – AUGUST 2002 Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms, RL = 330 Ω, Ee = 16.5 µW/cm2 (unless otherwise noted) PARAMETER Vout Vdrk PRNU Analog output voltage (white, average over 64 pixels) Analog output voltage (dark, average over 64 pixels) Pixel response nonuniformity Nonlinearity of analog output voltage Output noise voltage Re SE Vsat DSNU IL IDD IIH IIL Ci(SI) Ci(CLK) Responsivity Saturation exposure Analog output saturation voltage Dark signal nonuniformity Image lag Supply current, output idle High-level input current Low-level input current Input capacitance, SI Input capacitance, CLK VI = VDD VI = 0 5 5 All pixels, Ee = 0 See Note 7 See Note 6 See Note 5 2.5 Ee = 0 See Notes 2 & 3 See Note 3 See Note 4 18 TEST CONDITIONS see Note 1 MIN 1.6 0 TYP 2 50 ±4% ±0.4% 1 23 142 3.4 25 0.5% 3.4 4 1 1 mA µA µA pF pF 120 MAX 2.4 120 ± 7.5% FS mVrms V/ (µJ/cm 2) nJ/cm 2 V mV UNIT V mV NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 5. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re. 6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination. 7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL + V out (IL) * V drk V out (white) * V drk 100 Timing Requirements (see Figure 1 and Figure 2) MIN tsu(SI) th(SI) tw tr, tf Setup time, serial input (see Note 8) Hold time, serial input (see Note 8 and Note 9) Pulse duration, clock high or low Input transition (rise and fall) time 20 0 50 0 500 NOM MAX UNIT ns ns ns ns NOTES: 8. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 9. SI must go low before the rising edge of the next clock pulse. Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 2) PARAMETER ts Analog output settling time to ±1% TEST CONDITIONS RL = 330 Ω, CL = 10 pF MIN TYP 185 MAX UNIT ns Copyright E 2002, TAOS Inc. t The LUMENOLOGY r Company t 4 www.taosinc.com TSL201R 64 y 1 LINEAR SENSOR ARRAY TAOS030B – AUGUST 2002 TYPICAL CHARACTERISTICS CLK SI 65 Clock Cycles AO Hi-Z tw CLK 2.5 V tsu(SI) 5V SI 2.5 V 2.5 V 0V th(SI) ts ts AO Pixel 1 Pixel 64 The LUMENOLOGY r Company ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Hi-Z Figure 1. Timing Waveforms 1 2.5 V 2 64 65 5V 2.5 V 0V Figure 2. Operational Waveforms t Copyright E 2002, TAOS Inc. t www.taosinc.com 5 TSL201R 64 y 1 LINEAR SENSOR ARRAY TAOS030B – AUGUST 2002 TYPICAL CHARACTERISTICS PHOTODIODE SPECTRAL RESPONSIVITY 1 TA = 25°C 600 ANALOG OUTPUT SETTLING TIME vs LOAD CAPACITANCE AND RESISTANCE VDD = 5 V Vout = 1 V 500 ts — Settling Time to 1% — ns 220 pF 400 100 pF 300 10 pF 470 pF 0.8 Relative Responsivity 0.6 0.4 200 0.2 100 0 300 400 500 600 700 800 900 1000 1100 0 0 200 400 600 800 1000 1200 RL – Load Resistance – Ω λ – Wavelength – nm Figure 3 Figure 4 APPLICATION INFORMATION Power Supply Considerations For optimum device performance, power-supply lines should be decoupled by a 0.01-µF to 0.1-µF capacitor with short leads mounted close to the device package. Copyright E 2002, TAOS Inc. t The LUMENOLOGY r Company t 6 www.taosinc.com TSL201R 64 y 1 LINEAR SENSOR ARRAY TAOS030B – AUGUST 2002 MECHANICAL INFORMATION This dual-in-line package consists of an integrated circuit mounted on a lead frame and encapsulated in an electrically nonconductive clear plastic compound. 0.440 (11,18) 0.420 (10,67) Centerline of Pin 1 Nominally Lies On Pixel 2. 8 C 7L6 5 0.017 (0,43) C Pixels L 0.260 (6,60) 0.240 (6,61) C Package L 1 C Pin 1 L 2 3 4 j 0.30 (0,76) NOM 0.310 (7,87) 0.290 (7,37) 0.260 (6,60) 0.240 (6,10) 0.075 (1,91) 0.060 (1,52) 10° 0.130 (3,30) 0.120 (3,05) Seating Plane 100° 90° 0.016 (0,41) 0.014 (0,36) Die Thickness 0.10 (2,54) 8° 0.053 (1,35) 0.043 (1,09) 0.175 (9,78) 0.155 (7,75) 8° 8° 0.012 (0,30) 0.008 (0,20) 0.060 (1,52) 0.040 (1,02) 0.025 (0,64) 0.015 (0,38) 0.150 (3,81) 0.125 (3,18) NOTES: A. All linear dimensions are in inches and (millimeters). B. Index of refraction of clear plastic is 1.55. C. This drawing is subject to change without notice. Figure 5. Packaging Configuration The LUMENOLOGY r Company t Copyright E 2002, TAOS Inc. t www.taosinc.com 7 TSL201R 64 y 1 LINEAR SENSOR ARRAY TAOS030B – AUGUST 2002 PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK. LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated. Copyright E 2002, TAOS Inc. t The LUMENOLOGY r Company t 8 www.taosinc.com