WCMA2008U1B-FF70

WCMA2008U1B WCMA2008U1B 256K x 8 Static RAM Features • High Speed — 70ns availability • Voltage range — 2.7V–3.3V • Ultra low active power — Typical active current: 1 mA @ f = 1MHz — Typical active current: 7 mA @ f = fmax (70ns speed) • Low standby power • Easy memory expansion with CE1,CE2 ,and OE features • Automatic power-down when deselected • CMOS for optimum speed/power reduces power consumption by 80% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE 1 HIGH or CE2 LOW). Writing to the device is accomplished by taking Chip Enable (CE 1) and Write Enable (WE) inputs LOW and Chip Enable 2 (CE 2) HIGH. Data on the eight I/O pins (I/O0 through I/O7 ) is then written into the location specified on the address pins (A 0 through A17 ). Reading from the device is accomplished by taking Chip Enable (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE ) and Chip Enable 2 (CE2 ) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected ( E 1 C HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE 1 LOW and CE2 HIGH and WE LOW). The WCMA2008U1B is available in a 36-ball FBGA package. Functional Description The WCMA2008U1B is a high-performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is device is ideal for portable applications. The device also has an automatic power-down feature that significantly Logic Block Diagram Data in Drivers I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ROW DECODER S ENS E AMPS I/O2 I/O3 I/O4 I/O5 128K x 8 ARRAY CE 2 CE1 WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 A12 A13 A14 A15 A16 A17 W CMA2008U1B Pin Configurations FBGA (Top View) 1 A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9 OE A10 NC CE1 A11 A17 A16 A12 A 15 A13 2 A1 A2 3 CE 2 WE DNU 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 VCC VSS I/O2 I/O3 A 14 A B C D E F G H Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied...............................................55°C to +125°C Supply Voltage to Ground Potential..... ..........–0.5V to +4.6V DC Voltage Applied to Outputs in High Z State [1] ........................................0.5V to VCC + 0.5V DC Input Voltage [1] ..................................–0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................20 mA Static Discharge Voltage ..........................................>2001V (per MIL-STD-883, Method 3015) Latch-Up Current ......................................................>200 mA Operating Range Product WCMA2008U1B Range Industrial Ambient Temperature –40°C to +85°C VCC 2.7V to 3.3V Product Portfolio Power Dissipation (Industrial) Product Min. WCMA2008U1B 2.7V VCC Range Typ. [2] Speed Max. 3.3V 70 ns Operating, I CC f = 1 MHz Typ. [2] f = fmax Typ. [2] Standby (I SB2) Typ. [2] 2 µA Max. 10 µA Max. 3 mA Max. 15 mA 3.0V 1.5 mA 7 mA Notes: 1. VIL(min.) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.) , T A = 25°C. 2 W CMA2008U1B Electrical Characteristics Over the Operating Range WCMA2008U1B-70 Parameter VOH VO L VIH VIL I IX I OZ I CC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — CMOS Inputs Automatic CE Power-Down Current— CMOS Inputs GND < VI < VCC f =fMAX = 1/t RC f = 1 MHz VCC = 3.3V IOUT = 0 mA CMOS Levels Output Leakage Current GND < VO < VCC , Output Disabled Test Conditions IOH = –1.0 mA IO L = 2.1 mA VCC = 2.7V VCC = 2.7V 2.2 –0.3 –1 –1 7 1.5 2 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +1 15 3 10 µA Typ. [2] Max. Unit V V V V µA µA mA I SB1 CE1 > VCC – 0.2V or CE 2 < 0.2V VIN > VCC – 0.2V or V IN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE,WE) CE1 > VCC – 0.2V or CE 2 < 0.2V VIN > VCC − 0.2V or VIN < 0.2V, f = 0, V CC =3.3V I SB2 Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions T A = 25°C, f = 1 MHz,VCC = Vcc(typ) Max. 6 8 Unit pF pF Thermal Resistance Description Thermal Resistance (Junction to Ambient) [3] Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol ΘJA ΘJC BGA 55 16 Unit °C/W °C/W Thermal Resistance[3] (Junction to Case) Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 W CMA2008U1B AC Test Loads and Waveforms R1 V CC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 V CC Typ 10% GND Rise Time: 1 V/ns Fall time: 1 V/ns ALL INPUT PULSES 90% 90% 10% Equivalent to: OUTPUT THÉVENIN EQUIVALENT R TH V TH Parameters R1 R2 RTH VTH 3.3V 1105 1550 645 1.75 Unit Ohms Ohms Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR I CCDR t CDR[3] t R[4] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.5V CE1 > VCC – 0.2V or CE2 < 0.2V VIN > V CC − 0.2V or VIN < 0.2V 0 t RC Conditions Min. 1.5 1 Typ.[2] Max. Vccmax 6 Unit V µA ns ns Data Retention Waveform DATA RETENTION MODE VCC V CC(min) tCDR CE 1 VDR > 1.5 V V CC(min) tR or C E2 Note: 4. Full Device AC operation requires linear VCC ramp from V DR to VCC(min.) > 100 µs or stable at V CC(min.) > 100 µs. 4 W CMA2008U1B Switching Characteristics Over the Operating Range [5] WCMA2008U1B-70 Parameter READ CYCLE t RC t AA t OHA t ACE t DOE t LZOE t HZOE t LZCE t HZCE t PU t PD WRITE CYCLE t WC t SCE t AW t HA t SA t PWE t SD t HD t HZWE t LZWE [8,] Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE 1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] OE HIGH to High Z [6, 7] [6] Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 60 60 0 0 50 30 0 25 10 [6, 7] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE 1 LOW and CE2 HIGH to Low Z CE 1 HIGH or CE2 LOW to High Z CE 1 LOW and CE2 HIGH to Power-Up CE 1 HIGH or CE2 LOW to Power-Down Write Cycle Time CE 1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z [6, 7] WE HIGH to Low Z [6] Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to VCC(typ.) , and output loading of the specified IOL /I O H and 30 pF load capacitance. 6. At any given temperature and voltage condition, tH Z C E is less than t LZCE , t HZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. t HZOE, t HZCE, and t HZWE transitions are measured when the outputs enter a high impedance state. 8. The internal write time of the memory is defined by the overlap of WE, CE1 = V IL , and CE2 = VIH . All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 5 W CMA2008U1B Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [9, 1 0] tRC ADDRESS tAA tO H A DATA OUT PREVIOUS DATA VALID D ATA VALID Read Cycle No. 2 (OE Controlled) [10, 11] ADDRESS tRC CE 1 CE 2 tACE OE tHZOE tDOE tLZOE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tPD 50% ISB IC C tH Z C E HIGH IMPEDANCE Notes: 9. Device is continuously selected. OE , CE 1 = V IL, CE2 = VIH . 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 6 W CMA2008U1B Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [8, 12, 14] tWC ADDRESS tS C E CE1 CE2 tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 13 tHZOE DATA I N VALID tH D [8, 12, 14] Write Cycle No. 2 (CE1 or CE2 Controlled) tWC ADDRESS tS C E CE 1 tSA CE 2 tAW tPWE WE tH A OE tSD DATA I/O DATAIN VALID tHD Notes: 12. Data I/O is high impedance if OE = VIH . 13. During this period, the I/Os are in output state and input signals should not be applied. 14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 7 W CMA2008U1B Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [14] tWC ADDRESS tS C E CE 1 CE 2 tAW tSA WE tSD DATAI/O NOTE 13 tH Z W E DATAIN VALID tLZWE tHD tP W E tH A 8 W CMA2008U1B Truth Table CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H Inputs/Outputs High Z High Z Data Out Data In High Z Mode Deselect/Power-Down Deselect/Power-Down Read Write Output Disabled Power Standby (ISB) Standby (ISB) Active (ICC ) Active (ICC ) Active (ICC ) 9 W CMA2008U1B Ordering Information Speed (ns) 70 Ordering Code WCMA2008U1B-FF70 Package Name FB36A Package Type 36-ball Fine Pitch BGA (6.0 mm x 8.0 mm x 1.0 mm) Operating Range Industrial Package Diagrams 36-Lead VFBGA (6.0 mm x 8.0 mm x 1.0 mm) FB36A 51-85149-** 10 W CMA2008U1B Document Title: WCMA2008U1B, 256K x 8 Static RAM REV. ** Spec # 38-05321 ECN # 117495 Issue Date 3/18/2002 Orig. of Change CBD Description of Change New Data Sheet 11