ADS-930

® ® ADS-930 16-Bit, 500kHz Sampling A/D Converters INNOVATION and EXCELLENCE FEATURES • • • • • • • • • 16-bit resolution 500kHz sampling rate Functionally complete Excellent dynamic performance 83dB SNR, –89dB THD No missing codes Small, 40-pin, TDIP package 3.5 Watts power dissipation On-board FIFO PIN INPUT/OUTPUT CONNECTIONS FUNCTION +10V REF. OUT BIPOLAR ANALOG INPUT ANALOG GROUND OFFSET ADJUST GAIN ADJUST +15V SUPPLY COMP. BITS ENABLE FIFO READ ANALOG GROUND –15V SUPPLY ANALOG GROUND OVERFLOW EOC +5V SUPPLY START CONVERT DIGITAL GROUND FSTAT1 FSTAT2 PIN 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 FUNCTION BIT 1 (MSB) BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 ANALOG GROUND BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 DIGITAL GROUND FIFO/DIR BIT 15 BIT 16 (LSB) GENERAL DESCRIPTION The low-cost ADS-930 is a high-performance, 16-bit, 500kHz sampling A/D converter. This device accurately samples fullscale input signals up to Nyquist frequencies with no missing codes. The dynamic performance of the ADS-930 is optimized to achieve a THD of –89dB and an SNR of 83dB. Packaged in a small, 40-pin, ceramic TDIP, the functionally complete ADS-930 contains a fast-settling sample-hold amplifier, a subranging (three-pass) A/D converter, an internal reference, an on-board FIFO, timing and control logic, threestate outputs and error-correction circuitry. Digital inputs/ outputs are TTL. Requiring ±15V and +5V supplies, the ADS-930 typically dissipates 3.5 Watts. The unit is offered with a bipolar input range of ±5V or a unipolar input range of 0 to –10V. Models are available for use in either commercial (0 to +70°C) or military (–55 to +125°C) operating temperature ranges. Typical applications include radar, sonar, medical/graphic imaging, and FFT spectrum analysis. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 19 FSTAT1 20 FSTAT2 GAIN ADJUST 6 GAIN ADJUST CKT. 23 FIFO/DIR 10 FIFO READ 40 BIT 1 (MSB) 39 BIT 1 (MSB) +10V REF. OUT 1 POWER AND GROUNDING +5V SUPPLY +15V SUPPLY –15V SUPPLY ANALOG GROUND DIGITAL GROUND 16 7 12 4, 11, 13, 30 18, 24 BIPOLAR 2 OFFSET ADJUST 5 3-PASS ANALOG-TO-DIGITAL CONVERTER PRECISION +10V REFERENCE 38 BIT 2 37 BIT 3 36 BIT 4 CUSTOM GATE ARRAY 3-STATE OUTPUT REGISTER 35 BIT 5 34 BIT 6 33 BIT 7 32 BIT 8 31 BIT 9 29 BIT 10 28 BIT 11 27 BIT 12 26 BIT 13 25 BIT 14 22 BIT 15 21 BIT 16 (LSB) 9 ENABLE 14 OVERFLOW OFFSET ADJUST CKT. ANALOG INPUT 3 S/H START CONVERT 17 EOC 15 COMP. BITS 8 TIMING AND CONTROL LOGIC Figure 1. ADS-930 Functional Block Diagram DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048 (U.S.A.) • Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 • Email: datellit@mcimail.com ® ® ADS-930 ABSOLUTE MAXIMUM RATINGS PARAMETERS +15V Supply (Pin 7) –15V Supply (Pin 12) +5V Supply (Pin 16) Digital Inputs (Pin 8, 9, 10, 17, 23) Analog Input (Pin 3) Unipolar Bipolar Lead Temperature (10 seconds) LIMITS 0 to +16 0 to –16 0 to +6 –0.3 to +VDD +0.3 –12.5 to +12.5 –7.5 to +12.5 +300 UNITS Volts Volts Volts Volts Volts Volts °C PHYSICAL/ENVIRONMENTAL PARAMETERS Operating Temp. Range, Case ADS-930MC ADS-930MM Thermal Impedance θjc θca Storage Temperature Range Package Type Weight MIN. 0 –55 — — –65 TYP. — — MAX. +70 +125 UNITS °C °C 4 — °C/Watt 18 — °C/Watt — +150 °C 40-pin, metal-sealed, ceramic TDIP 0.56 ounces (16 grams) FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±VCC = ±15V, +VDD = +5V, 500kHz sampling rate, and a minimum 5 minute warmup Œ unless otherwise specified.) +25°C ANALOG INPUTS Input Voltage Range Bipolar Unipolar Input Resistance Input Capacitance DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0"  Start Convert Positive Pulse Width Ž STATIC PERFORMANCE Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Unipolar Zero Error (Tech Note 2) Bipolar Zero Error (Tech Note 2) Bipolar Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 100kHz 100kHz to 250kHz Total Harmonic Distortion (–0.5dB) dc to 100kHz 100kHz to 250kHz Signal–to–Noise Ratio (w/o distortion, –0.5dB) dc to 100kHz 100kHz to 250kHz Signal–to–Noise Ratio  (& distortion, –0.5dB) dc to 100kHz 100kHz to 250kHz Two–Tone Intermodulation Distortion (fin = 100kHz, 240kHz, fs = 500kHz, –0.5dB) Noise Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal (–0.5dB input) Feedthrough Rejection (fin = 250kHz) Slew Rate — — — — 81 — 78 — — — — — — — –91 –86 –89 –84 83 80 81 78 –82 150 2 1.1 92 ±80 — — –81 — — — — — — — — — — — — — — — 81 — 77 — — — — — — — –91 –86 –89 –84 83 80 81 78 –82 150 2 1.1 92 ±80 — — –81 — — — — — — — — — — — — — — — 75 — 72 — — — — — — — –87 –84 –85 –82 80 79 78 76 –81 150 2 1.1 92 ±80 — — –76 — — — — — — — — — — — dB dB dB dB dB dB dB dB dB µVrms MHz MHz dB V/µs — — — — — — — — 16 16 ±1.0 ±0.75 ±0.05 ±0.05 ±0.05 ±0.05 ±0.1 — — — — ±0.18 ±0.085 ±0.085 ±0.15 ±0.15 — — — — — — — — — 16 16 ±1.5 ±1.0 ±0.2 ±0.1 ±0.15 ±0.1 ±0.15 — — — — ±0.5 ±0.25 ±0.25 ±0.25 ±0.35 — — — — — — — — — 15 16 ±2.0 ±1.5 ±0.5 ±0.25 ±0.25 ±0.25 ±0.25 — — — — ±0.8 ±0.5 ±0.5 ±0.5 ±0.65 — Bits LSB LSB %FSR %FSR %FSR %FSR % Bits +2.0 — — — 175 — — — — 200 — +0.8 +20 –20 215 +2.0 — — — 175 — — — — 200 — +0.8 +20 –20 215 +2.0 — — — 175 — — — — 200 — +0.8 +20 –20 215 Volts Volts µA µA ns MIN. — — 1.4 — TYP. ±5 0 to –10 1.5 7 MAX. — — 1.7 15 MIN. — — 1.4 — 0 to +70°C TYP. ±5 0 to –10 1.5 7 MAX. — — 1.7 15 MIN. — — 1.4 — –55 to +125°C TYP. ±5 0 to –10 1.5 7 MAX. — — 1.7 15 UNITS Volts Volts kΩ pF 2 ® ® ADS-930 +25°C DYNAMIC PERFORMANCE (Cont.) Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to ±0.003%FSR, 10V step) Overvoltage Recovery Time A/D Conversion Rate ANALOG OUTPUT Internal Reference Voltage Drift External Current DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Delay, Falling Edge of ENABLE to Output Data Valid Output Coding POWER REQUIREMENTS Power Supply Ranges +15V Supply –15V Supply +5V Supply Power Supply Currents +15V Supply –15V Supply +5V Supply Power Dissipation Power Supply Rejection +14.5 –14.5 +4.75 — — — — — +15.0 –15.0 +5.0 +110 –100 +80 3.5 — +15.5 –15.5 +5.25 +130 –125 +90 4.25 ±0.02 +14.5 –14.5 +4.75 — — — — — +15.0 –15.0 +5.0 +110 –100 +80 3.5 — +15.5 –15.5 +5.25 +130 –125 +90 4.25 ±0.02 +14.5 –14.5 +4.75 — — — — — +15.0 –15.0 +5.0 +110 –100 +80 3.5 — +15.5 –15.5 +5.75 +130 –125 +90 4.25 ±0.02 Volts Volts Volts mA mA mA Watts %FSR/%V +2.4 — — — — — — — — — +0.4 –4 +4 +2.4 — — — — — — — — +0.4 –4 +4 +2.4 — — — — — — — — +0.4 –4 +4 Volts Volts mA mA ns +9.95 — — +10.0 ±10 — +10.05 — 1 +9.95 — — +10.0 ±10 — +10.05 — 1 +9.95 — — +10.0 ±10 — +10.05 — 1 Volts ppm/°C mA MIN. — — — — 500 TYP. ±10 5 460 600 — MAX. — — 545 1000 — MIN. — — — — 500 0 to +70°C TYP. ±10 5 460 600 — MAX. — — 545 1000 — MIN. — — — — 500 –55 to +125°C TYP. ±10 5 460 600 — MAX. — — 545 1000 — UNITS ns ps rms ns ns kHz — 10 — — 10 — — 10 Complementary Offset Binary; Complementary Two's Complement, Offset Binary, Two's Complement Footnotes: Œ All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warmup periods. The device must be continuously converting during this time.  When COMP. BITS (pin 8) is low, logic loading "0" will be –350µA. Ž A 200ns wide start convert pulse is used for all production testing. For 6.02 applications requiring less than a 500kHz sampling rate, wider start convert pulses can be used.  Effective bits is equal to: (SNR + Distortion) – 1.76 + 20 log Full Scale Amplitude Actual Input Amplitude TECHNICAL NOTES 1. Obtaining fully specified performance from the ADS-930 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (4, 11, 13, 18, 24 and 30) directly to a large analog ground plane beneath the package. Bypass all power supplies and the +10V reference output to ground with 4.7µF tantalum capacitors in parallel with 0.1µF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. 2. The ADS-930 achieves its specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the adjustment circuitry shown in Figure 2. When using this circuitry, or any similar offset and gain calibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not using offset and gain adjust circuits. 3. Pin 8 (COMP. BITS) is used to select the digital output coding format of the ADS-930. See Tables 3a and 3b. When this pin has a TTL logic "0" applied, it complements all of the ADS-930's digital outputs. When pin 8 has a logic "1" applied and the ADS-930 is operated within its unipolar (0 to –10V) input range, the output coding is straight binary. Applying a logic "0" to pin 8 under these conditions changes the output coding to complementary binary. When pin 8 has a logic "1" applied and the ADS-930 is operated within its bipolar (±5V) input range, the output coding is offset binary. Applying a logic "0" to pin 8 under these conditions changes the coding to complementary offset binary. Using the MSB output (pin 40) instead of the MSB output (pin 39) under these conditions changes the respective output codings to two's complement and complementary two's complement. Pin 8 is TTL-compatible and can be directly driven with digital logic in applications requiring dynamic control over its function. There is an internal pull-up resistor on pin 8 allowing 3 ® ® ADS-930 TECHNICAL NOTES cont. it to be either connected to +5V or left open when a logic "1" is required. 4. To enable the three-state outputs, connect ENABLE (pin 9) to a logic "0" (low). To disable, connect pin 9 to a logic "1" (high). 5. Applying a start convert pulse while a conversion is in progress (EOC = logic "1") will initiate a new and probably inaccurate conversion cycle. 6. Do not enable/disable or complement the output bits or read from the FIFO during the conversion process (from the falling edge of START CONVERT to the falling edge of EOC). FIFO immediately after the first conversion has been completed and remains there until the FIFO is read. If the output three-state register has been enabled (logic "0" applied to pin 9), data from the first conversion will appear at the output of the ADS-930. Attempting to write a 17th word to a full FIFO will result in that data, and any subsequent conversion data, being lost. Once the FIFO is full (indicated by FSTAT1 and FSTAT2 both = "1"), it can be read by dropping the FIFO READ line (pin 10) to a logic "0" and then applying a series of 15 rising edges to the read line. Since the first data word is already present at the FIFO output, the first read command (the first rising edge applied to FIFO READ) will bring data from the second conversion to the output. Each subsequent read command/rising edge brings the next word to the output lines. If a read command is issued after the FIFO has been emptied, the last word (the 16th conversion) will remain present at the outputs. FIFO Reset Feature At any time, the FIFO can be reset to an empty state by putting the ADS-930 into its "direct" mode (logic "0" applied to pin 23, FIFO/DIR) and also applying a logic "0" to the FIFO READ line (pin 10). The empty status of the FIFO will be indicated by FSTAT1 going to a "0" and FSTAT2 going to a "1". The status outputs will change 40ns after the control signals have been applied. FIFO Status, FSTAT1 and FSTAT2 The status of the data in the FIFO can be monitored by reading the two status pins, FSTAT1 (pin 19) and FSTAT2 (pin 20). CONTENTS Empty (0 words)