RSC-464-100LQFP

RSC-464 Speech Recognition Processor Preliminary Data Sheet General Description The RSC-464 is the newest member of Sensory’s RSC-4x Family of microcontrollers with on-chip speech I/O capabilities. The RSC-464 has many features of the RSC-4128, but reduced in cost by integrating less memory. The RSC-464 is designed to bring high performance speech I/O features to cost sensitive embedded and consumer products. Based on an 8-bit microcontroller, the RSC-464 integrates speech-optimized digital and analog processing blocks into a single chip solution capable of accurate speech recognition; high quality, low data-rate compressed speech; and advanced music. Products can use one or all features in a single application. The RSC-464 operates in tandem with the radically new FluentChip™ technology, offering the best speech recognition technologies in the industry. FluentChip™ includes Hidden Markov Model-Neural Net hybrid speech recognition. Accuracy in all kinds of noise is dramatically improved. New Speaker Verification technology is perfect for voice password security applications that must work in noisy environments. New high quality compressed speech technology reduces data rates by 5 times. New 8voice MIDI-compatible music includes drum tracks, effectively increasing instruments beyond 8. Simultaneous music and speech rounds out the FluentChip™ technology. FluentChip™ technology tools also support the revolutionary capability of creating speaker independent recognition sets by simply typing in the desired recognition vocabulary! A few keystrokes creates a recognition set in seconds without the wait or cost of recording sessions to train the recognizer, speeding time to sales. The Audio Wakeup feature listens while the RSC-464 is in power down mode. When an audio event such as a clap or whistle occurs, Audio Wakeup will wakeup the RSC-464 for speech or application tasks. Audio Wakeup is perfect for battery applications that require continuous listening and long battery life. The RSC-464 provides further on-chip integration of features. A complete speech I/O application can be built with as few additional parts as a clock crystal, speaker, microphone, and few resistors and capacitors. Moreover, the RSC-464 provides an unprecedented level of cost effective system-on-chip (SOC) integration, enabling many applications that require DSP and/or audio processing. The RSC-464 may be used as a general-purpose mixed signal processor platform for custom algorithms, technologies and applications. Features Full Range of FluentChip™ Capabilities Noise-robust Speaker Independent and Speaker Dependent recognition Many languages now available for international use Speaker Verification – voice password biometric security Word Spotting and Continuous Listening recognition options High quality, 2.4-10.8 kbps speech synthesis & sound effects, with Sensory SX™ synthesis technology 8 voice MIDI-compatible music synthesis coincident with speech; drum track feature enables additional voices Voice Record & Playback (voice memo) Audio Wake Up from sleep with whistles or claps Touch Tone (DTMF) output Integrated Single-Chip Solution 8-bit microcontroller 64K bytes ROM 16 bit ADC, 10 bit DAC & PWM, and microphone preamplifier; PWM 30% louder than before! Independent, programmable Digital Filter engine 2.8 KBytes total RAM (262 bytes “user” application RAM) Five timers (3 GP, 1 Watchdog, 1 Multi Tasking) Twin-DMA, Vector Math accelerator, and Multiplier Built-in Analog Comparator Unit (4 inputs) On chip storage for SD, SV, templates 16 configurable I/O lines with 10 mA (typical) outputs Uses low cost 3.58MHz crystal (internal PLL) Low EMI design for FCC and CE requirements Fully nested interrupt structure with up to 8 sources Optional Real Time Clock Long Battery Life 2.4 – 3.6V operation 10mA (typical) operating current at 3V during 2 low power modes; 1 µA typical sleep current Full Suite of Quick & Powerful Tools Quick Text-to-SI (T2SI) text entry to build noise robust SI recognition sets – low cost & push-button – no recording! Quick Synthesis for push-button speech compression Integrated Development Environment, C Compiler, Debugger & In Circuit Emulator from Phyton, Inc. © 2005 Sensory Inc. P/N 80-0282-A 1 RSC-464 Preliminary Data Sheet Table of Contents General Description ........................................................................................................................................................................ 1 Speech Technologies ..................................................................................................................................................................... 4 Speech Recognition .............................................................................................................................................................................................. 4 Speech and Music Synthesis ................................................................................................................................................................................ 4 Record and Playback ............................................................................................................................................................................................ 4 RSC-464 Architecture..................................................................................................................................................................... 5 Reference Schematics.................................................................................................................................................................... 7 Using the RSC-464......................................................................................................................................................................... 8 Instruction Set ....................................................................................................................................................................................................... 8 Stack ..................................................................................................................................................................................................................... 9 Register and User RAM ........................................................................................................................................................................................ 9 L1 Vector Accelerator/Multiplier .......................................................................................................................................................................... 10 Power and Wakeup Control ................................................................................................................................................................................ 10 General Purpose I/O ........................................................................................................................................................................................... 11 Memory Addressing ............................................................................................................................................................................................ 13 Oscillators ........................................................................................................................................................................................................... 13 Clocks ................................................................................................................................................................................................................. 14 Timers/Counters.................................................................................................................................................................................................. 15 Interrupts ............................................................................................................................................................................................................. 18 Audio Wakeup..................................................................................................................................................................................................... 21 Microphones........................................................................................................................................................................................................ 22 Reset................................................................................................................................................................................................................... 23 Digital-to-Analog-Converter (DAC) Output.......................................................................................................................................................... 23 Pulse Width Modulator (PWM) Analog Output.................................................................................................................................................... 25 Comparator Unit.................................................................................................................................................................................................. 26 Instruction Set Opcodes and Timing Details ................................................................................................................................. 28 MOVE Group Instructions ................................................................................................................................................................................... 28 ROTATE Group Instructions ............................................................................................................................................................................... 29 BRANCH Group Instructions............................................................................................................................................................................... 29 ARITHMETIC/LOGICAL Group Instructions ....................................................................................................................................................... 29 MISCELLANEOUS Group Instructions ............................................................................................................................................................... 30 Special Functions Registers (SFRs) Summary............................................................................................................................. 31 DC Characteristics........................................................................................................................................................................ 33 Absolute Maximum Ratings .......................................................................................................................................................... 33 Package Options .......................................................................................................................................................................... 34 Die Pad Ring ................................................................................................................................................................................ 37 RSC-464 Die Bonding Pad Locations........................................................................................................................................... 38 Mechanical Data ........................................................................................................................................................................... 39 Ordering Information..................................................................................................................................................................... 40 The Interactive Speech™ Product Line ........................................................................................................................................ 41 2 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 RSC-464 Overview The RSC-464 is a member of the Interactive Speech™ line of products from Sensory. It features a highperformance 8-bit microcontroller with on-chip ADC, DAC, preamplifier, RAM, ROM, and optimized audio processing blocks. The RSC-464 is designed to bring a high degree of integration and versatility into low-cost, power-sensitive applications. Various functional units have been integrated onto the CPU core in order to reduce total system cost and increase system reliability. The RSC-464 operates in tandem with FluentChip™ firmware, an ultra compact suite of recognition and synthesis technologies. This reduced software footprint enables, for example, products with 60 seconds of compressed speech, multiple speaker dependent and independent vocabularies, speaker verification, and all application code built into the RSC-464 as a single chip solution. Revolutionary Text-to-Speaker-Independent (T2SI) technology allows the creation of SI recognition sets by simply entering text. The CPU core embedded in the RSC-464 is an 8-bit, variable-length-instruction microcontroller. The instruction set is similar to the 8051 microcontroller, and has a variety of addressing mode, MOV and 16 bit instructions. The RSC464 processor avoids the limitations of dedicated A, B, and DPTR registers by having completely symmetrical sources and destinations for all instructions. The RSC-464 provides a high level of on-chip features and special DSP engines, providing a very cost effective mixed signal platform for general-purpose applications and development of custom algorithms. The full suite of industry standard tools for easy product development makes the RSC-464 an ideal platform for consumer electronics. RSC-464 Block Diagram 3 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Speech Technologies Speech Recognition The RSC-464 is designed to operate in tandem with the FluentChip™ technology library, including speaker independent (SI), speaker dependent (SD), and speaker verification (SV) speech recognition. Combinations of these technologies may used to create applications that are rich in features. These are described below: Speaker Independent recognition requires no user training. The RSC-464 can recognize up to 15 commands in an active set (number of sets is limited only by internal ROM size). Text-to-SI (T2SI), based on a hybrid of Hidden Markov Modeling and Neural Net technologies, allows creation of accurate SI recognition sets in seconds. SI requires on-chip ROM. Speaker Dependent recognition allows the user to create names for products or customize recognition sets. SD is implemented with DTW (dynamic time warping) pattern matching technology. SD requires programmable memory to store the personalized speech templates(trained patterns) that may be on-chip SRAM, or off-chip serial EEPROM, Flash Memory, or SRAM. Up to 50 templates can be recognized in an active set (the number of unique sets is limited only by programmable memory capacity). The RSC-464 can store 1 SD templates in onchip SRAM. Speaker Verification enables the RSC-464 to authenticate when a previously trained password is spoken by the target user. SV is also implemented with DTW technology. 1 SV template can be stored in on-chip SRAM, or more with external programmable memory such as delineated in SD above. Word Spotting enables the RSC-464 to spot a specific word surrounded by other speech within a phrase. This can be quite effective when the users response may vary (e.g. spotting “telephone” in the phrases “ummm telephone”, or “telephone call”). This option is available for SI and SD. Continuous Listening allows the chip to continuously listen for a specific word. This may be used as a trigger word to request a device to listen for a command. This option is available for SI and SD. Speech and Music Synthesis The RSC-464 provides high-quality speech compression using Sensory SX™ technology. One may select various data rates from approximately 2.4 to 10.8Kbps to manage speech quality versus allotted memory. The highest data rates use 16KHz sample rates to provide high quality reproduction of high pitched voices. Speech and sound effects may also be compressed using 8-bit PCM (64Kbps) or 4-bit ADPCM (32Kbps) technologies. The RSC-464 also provides eight-voice, wave table music synthesis which allows multiple, simultaneous instruments for harmonizing. The RSC-464 uses a MIDI-like system to generate music. One or more of the eight voices may be speech playback instead of music. One or more of the eight voices may be a drum track comprising multiple drums. In effect, drum tracks allow the number of simultaneous instruments to exceed 8. Speech and Music data may be stored in on-chip ROM. Speech data may alternatively be stored in off-chip serial data ROM or serial data Flash for extended durations. Easy to use tools allow the developer to record and compress their own voice talents and create with the push of a button, or to create their own MIDI scores and instruments. Record and Playback The RSC-464 can perform speech record and playback (sometimes called “voice memo”) using either 8 bits (64Kbps) or 4 bits (32Kbps) per sample, depending on the quantity and quality of playback desired. The record and playback technology also optionally performs silence removal to reduce memory requirements. External serial Flash or SRAM is required to store the compressed speech. 4 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 RSC-464 Architecture The RSC-464 is a highly integrated speech and analog I/O mixed signal processor that combines: 8-bit microcontroller with enhanced instructions and interrupt control, superior register architecture, independent Digital Filter engine and “L1” Vector Math Accelerator On-chip ROM and RAM (2.8 Kbytes). Input microphone preamp and 16 bit Analog-to-Digital Converter (ADC) for speech and audio/analog input 10 bit Digital-to-Analog Converter (DAC), and 10 bit Pulse Width Modulator (PWM) to directly drive a speaker or other analog device Low power Audio Wakeup from power down mode, when a selected audio event, such as clap or whistle, occurs RSC-464 Internal Block Diagram Two bi-directional ports provide 16 configurable, general-purpose I/O pins to communicate with or control external devices with a variety of source and sink currents. Up to 4 of these I/O may be used as programmable Analog Comparator inputs. 16 may be used as I/O wakeup. The RSC-464 has a high frequency (14.32 MHz) clock as well as a low frequency (32,768 Hz) clock. The processor clock can be selected from either source, with a selectable divider value. The device performs speech recognition when running at 14.32 MHz. OSC1 is a very low-cost 3.58 MHz crystal oscillator that is used by a 4X PLL to generate the 14.32MHz clock. The OSC2 oscillator provides the options of using an external crystal or its own internal RC devices (no external components required for the internal RC mode). There are three programmable, general-purpose 8-bit counters / timers – Timers 1 and 3 are derived from OSC1, and Timer2 from OSC2. There is also a Watchdog timer that may be used to exit an undesired condition in program flow, and Multi-tasking timer to allow chip operations to share resources in parallel. A single chip speech I/O solution may be created with the RSC-464. An external microphone passes an audio signal to the preamplifier and ADC to convert the incoming speech signal into digital data. Speech features are extracted using the Digital Filter engine. The microcontroller CPU processes these speech features using speech recognition algorithms in firmware, with the help of the “L1” Vector Accelerator and enhanced instruction set. The resulting speech recognition results may be used to control the consumer product application code, or to output 5 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet speech or audio in the form of a dialog with the user of the consumer product. If desired, the output speech or audio signal from the RSC-464 is generated by a DAC for external amplification into a speaker, or a PWM capable of directly driving a speaker at typical consumer product volumes. A typical product will require about $0.30 - $1.00 (in high volume) of additional components, in addition to the RSC-464. The RSC-464 also provides a very cost effective mixed signal platform for general-purpose applications and development of custom algorithms. A typical general-purpose application will require about $0.30 - $0.50 (in high volume) of additional components, in addition to the RSC-464. 6 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 Reference Schematics Schematic 1-1: RSC-464, Utilizing On-chip ROM and Optional External Serial Data Memory TBA 7 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Using the RSC-464 Creating applications using the RSC-464 requires the development of electronic circuitry, software code, and speech/music data files. Software code for the RSC-464 can be developed using a complete suite of RSC-464 development tools including In-Circuit Emulator, C Compiler, and “push button” tools for speech recognition and synthesis data files. Sensory provides free design reviews of customer applications to assist in the speech dialog and speech I/O design. Sensory also offers application development services. For more information about development tools and services, please contact Sensory. When using the RSC-464 macro blocks such as the AFE, digital filters, L1, etc, for purposes other than as intended in the FluentChip™ technology modules, in applications that will also use FluentChip™ technologies, care must be taken to avoid conflicts that may cause adverse impact on functionality. Contact Sensory Technical Support for help in avoiding these conflicts. Instruction Set The instruction set for the RSC-464 has 60 instructions comprising 13 move, 7 rotate, 11 branch, 22 arithmetic, and 7 miscellaneous instructions. All instructions are 3 bytes or fewer and no instruction requires more than 10 clock cycles (plus wait states) to execute. (see “Instruction Set Opcodes and Timing Details” for detailed descriptions) Flags The “flags” register (register FF) has bits that are set/cleared by arithmetic/logical instructions, a trap enable bit set under program control, a read-only stack overflow bit cleared at power on and set by stack wrap around, and the Global Interrupt Enable bit: 0FFH R/W Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 3: Bit 1: Bit 0: “flags” carry zero sign trap stkoflo stkfull (unused) gie (set = 1 when result of arith/log instruction is 0) (set = 1 when result of arith/log instruction has msb high) (read-only, initialized to 0, set to 1 on stack overflow) (read-only, initialized to 0, set to 1 on stack full) (Global Interrupt Enable) NOTE: The “trap” bit must be left written as “0”. Flags Hold The “flagsHold” register (register CF) stores the “flags” value when an interrupt occurs. Unlike previous RSC chips, the RSC-464 processor has read/write access to “flagsHold” for multi-tasking purposes. Since the “flags” register is restored from the “flagsHold” register upon return from interrupt, the “stkoflo” and “stkfull” bits are omitted from the “flagsHold” register to prevent inadvertent clearing of these bits. 0CFH R/W Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: “flagsHold” carry zero sign trap (unused – reads 0) (unused – reads 0) (unused – reads 0) gie NOTE: The “trap” bit must be left written as “0”. See the discussion in “Interrupts” section relating to the value of “gie” stored in the “flagsHold” register when an interrupt occurs during execution of an instruction that clears the “gie” bit. 8 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 Stack There is a 16-level, 16-bit stack for saving the program counter for subroutine calls and interrupt requests. The stack pointer wraps around on overflow or underflow. When the stack read and write pointers indicate that stack overflow has occurred, the “stkoflo” bit in the “flags” register is set. Once set, this bit can only be cleared by a processor reset. The bit may be tested by software, but it performs no other function. When the stack read and write pointers indicate that stack is full, the “stkfull” bit in the “flags” register is set. This bit will be reset once the stack is not full. Stack Pointers The 16-level stack has two 4-bit pointers, stack write and stack read. They are normally written by the processor upon execution of a “CALL” instruction or an interrupt. The stack also has a 6-bit index register “stkNdx” (register F6) and an 8-bit data port register “stkData” (register F7) that are used to access the stack contents as bytes in a register file under program control. The contents of the stack location selected by the “stkNdx” register may be read or written by the processor via MOV instructions at the “stkData” register. The stack register index must be written first, then the stack data can be read. The Stack read and write pointers (4 bits each) are also mapped to addresses accessible via the Stack Register Index. Stack contents accessed by value in stack register index (“stkNdx”, register F6) 00H Stack0 Lo 08H Stack4 Lo 10H Stack8 Lo 18H 01H Stack0 Hi 09H Stack4 Hi 11H Stack8 Hi 19H 02H Stack1 Lo 0AH Stack5 Lo 12H Stack9 Lo 1AH 03H Stack1 Hi 0BH Stack5 Hi 13H Stack9 Hi 1BH 04H Stack2 Lo 0CH Stack6 Lo 14H StackA Lo 1CH 05H Stack2 Hi 0DH Stack6 Hi 15H StackA Hi 1DH 06H Stack3 Lo 0EH Stack7 Lo 16H StackB Lo 1EH 07H Stack3 Hi 0FH Stack7 Hi 17H StackB Hi 1FH 20(unused) 30(unused) 3EH StackWritePtr 3FH 2FH 3DH (4bits only) StackC Lo StackC Hi StackD Lo StackD Hi StackE Lo StackE Hi StackF Lo StacKF Hi StackReadPtr (4bits only) Register and User RAM The RSC-464 has a physical register RAM space of 896 bytes. There is an additional RAM space of 64 bytes dedicated to Special Function Registers (SFRs), for a total register RAM space of 960 bytes. User RAM is assigned 262 bytes of this register RAM space, as detailed below. Logical register space addressing is architecturally limited to 8 bits (256 bytes). Therefore a banking scheme is used to provide the total of 960 bytes of register RAM space. The lower 128 bytes and the top 64 bytes of addressing are used to directly address register RAM. The remaining 64 bytes (080H-0BFH) are banked to provide the remaining 768 bytes of register RAM space. This 768 bytes of register RAM is divided into 12 banks of 64 bytes each. The “bank” register (register FC) is combined with logical addressing to access these 12 banks. Here is a table illustrating the breakdown of register RAM space: 000H-07FH 080H-0BFH 0C0H-0FFH unbanked register RAM banked register RAM unbanked register RAM (SFRs) Bits [4:0] of the “bank” register determine which physical bank of 64 bytes is logically mapped to addresses 080H0BFH. When a logical address falls in the range of 080H-0BFH, the lower 6 bits of the logical address (64 byte address) are combined with the “bank” register bits used as the upper 5 bits of an 11-bit physical address. This physical address is used to address 768 bytes (12 banks) of physical bank RAM. (Note: 4 bits are required by the “bank” register to address 12 banks, but 5 bits are provided to allow for possible increases in the register RAM for future RSC family members.) Here is a table that illustrates this banking scheme: 9 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Mapping of logical addresses 080H-0BFH (“bank” register FC is used) register FC [4:0] Physical Bank RAM register FC [4:0] 00H (Bank 0) 00-3FH 08H (Bank 8) 01H (Bank 1) 40-7FH 09H (Bank 9) 02H (Bank 2) 80-BFH 0AH (Bank A) 03H (Bank 3) C0-FFH 0BH (Bank B) 04H (Bank 4) 100-13FH 0CH 05H (Bank 5) 140-17FH 0DH 06H (Bank 6) 180-1BFH 0EH 07H (Bank 7) 1C0-1FFH 0FH Physical Bank RAM 200-23FH 240-27FH 280-2BFH 2C0-2FFH --- (unimplemented) --- (unimplemented) --- (unimplemented) --- (unimplemented) NOTE: If a value other than those indicated above is used in the “bank” register, an undefined state will result. User RAM is assigned both in directly addressed register RAM space and in banked register RAM space. Addresses 03AH-07FH (70 bytes) of directly addressed register RAM and Banks 0, A and B (192 bytes) of banked register RAM are assigned for a total of 262 bytes of User RAM. See the “Special Functions Registers Summary” for details on the contents of SFRs. L1 Vector Accelerator/Multiplier A variety of macros are provided by Sensory that manipulate the L1 Vector Accelerator to provide signed and unsigned multiplication functions. See the “FluentChip™ Technology Library Manual” for information on these macros and their application. The L1/Multiplier unit may be independently powered down by programming the register D6.Bit 4 to “0” (“clkExt” register, “L1clk_on” bit). Digital Filter The RSC-464 has a Digital Filter engine capable of dividing up a frequency range into several smaller ranges. It is also capable of reporting characteristics of each range to the RSC-464 processor. The configuration of the Digital Filter engine and access to signal characteristics generated are enabled by technology modules that are available from Sensory “Technology Support” upon request. Power and Wakeup Control The typical Active Supply Current is realized when operating with a main clock rate of 14.32 MHz at 3V and all I/O configured to the high-Z state. Lowering clock frequency reduces active power consumption, although FluentChip™ technology typically requires a 14.32 MHz clock. Two supply current power-down modes are available – Sleep and Idle modes. In Sleep mode everything is stopped, and only an I/O event can initiate a wake-up. In Idle mode OSC2 and Timer2 continue to run, and an Audio Wakeup, I/O Wakeup or Timer2 interrupt request caused by overflow can generate a wake-up. Sleep mode is entered by setting register E8.Bit7=1 (“ckCtl” register; “pdn” bit), register E8.Bit0=1 (“osc1_off”) and register E8.Bit1=0 (OSC2 off). Idle mode is entered by setting register E8.Bit7=1, register E8.Bit1=1 (“osc2_on”) and register E8.Bit0=1. Setting register E8.Bit7=1 (“pdn”) freezes the processor, but does not insure that the DAC, Audio Wakeup, and the PWM are placed in the lowest possible current-consumption state. Software control must power these blocks down prior to setting “pdn” to “1”, according to the procedures indicated in “DAC”, “Audio Wakeup”, and “Pulse Width Modulator Analog Output” Sections. The “FluentChip™ Technology Library Manual” provides sample code for achieving the lowest current-consumption state for Sleep and Idle modes. The state of “pdn” bit may be observed externally on the PDN pin (see pin definitions in “Package Options” section) and used to control power down of circuitry external to the RSC-464, if desired. NOTE: GPIO (Ports 0 & 2) should be put in input mode and a known state (e.g. light pull-up) whenever possible to conserve power, and especially in powerdown mode to achieve the specified minimum supply current consumption. 10 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 The external memory interface (A[19:0], D[7:0], -RDR, -WRC, -RDF and –WRD) automatically goes into a high-Z state and is pulled up by a 100 Kohm internal resistor when the “pdn” bit is set, to conserve current. Register E8 contains both the “pdn” bit and the processor clock selector (Bit2). The clock selector bit determines whether the 14.32 clock (“fast clock”) or the 32KHz clock (“slow clock”) will be used at wakeup time, independent of what clock rate was being used before or during power down mode. This allows the processor clock after wakeup to be the same or different from the processor clock used when the power-down flag was set. (see “Clock” section for complete explanation) To minimize power consumption, most operational blocks on the chip also have individual power controls that may be selectively enabled or disabled by the programmer. Wakeup from powerdown Note that a Wakeup event does not cause a reset. The processor, which was "frozen" when register E8.Bit7 was set, will be restarted without loss of context. A reset of the chip will also cancel a power down mode, but with a corresponding loss of processor context. Wakeup events terminate a power-down state. In Sleep mode, only an I/O Wakeup event can initiate a wake-up. In Idle mode, an Audio Wakeup, I/O Wakeup or Timer2 interrupt request caused by overflow can generate a wakeup. An I/O Wakeup is enabled by setting the bit(s) high in registers E9 corresponding to the desired I/O pin(s) to be used for wakeup. E9 controls P0 wakeup enable. The polarity of the wakeup event is controlled by putting the appropriate port pin in input mode and writing the appropriate bit in the output register for that pin to the desired polarity. (see “General Purpose I/O” section for complete explanation) When the value on the wakeup pin equals the value in the output register a wakeup will occur. When an I/O Wakeup occurs register FB.Bit1 will be set high. The user should clear this bit once the status is noted, so that it can indicate future wakeup events. A T2 Wakeup is enabled by setting register E8.Bit6 high. Then an overflow of timer T2 will generate an interrupt request, which in turn will trigger a wakeup event. Note that the Timer2 “irq” bit (register FE.Bit1) must be cleared prior to powering down to allow the wakeup interrupt request to occur. (the “Timers/Counters” section describes how timer T2 is configured) An Audio Wakeup is generated by special circuitry that can detect several classes of sounds, even while in powerdown mode. When the class of sound selected by the programmer is detected by this circuitry a wakeup event will occur. (see the “Audio Wakeup” section for more information) To determine the source of wakeup during powerdown, it is necessary to query FE.Bit1 and FB.Bit1. If FE.Bit1 is set, then the wakeup was caused by T2. If FB.Bit1 was set, it was caused by I/O. If a wakeup occurs and neither of these bits is set, then by process of elimination the wakeup was caused by Audio Wakeup. General Purpose I/O The RSC-464 has 16 general-purpose I/O pins (P0.0-P0.7 and P2.0-P2.7). Each pin can be programmed as an input with weak pull-up (~200kΩ equivalent device); input with strong pull-up (~10kΩ equivalent device); input without pull-up, or as an output with sufficient drive to light an LED. (See “DC Characteristics” section for I/O electrical characteristics.) This is accomplished by programming combinations of bits of configuration registers assigned to the I/O pins. NOTE: Port 1 on the RSC-4128 has been removed on the RSC-464 to reduce cost. If an application began as an RSC-4128 design, it should be reviewed to ensure Port 1 is not being used. Two control registers, A and B, are used to control the nature of inputs and outputs for each port. Registers E6 (“p0CtlA”) and E7 (“p0CtlB”), and DE (“p2CtlA”) and DF (“p2CtlB”), are the control registers A and B for ports P0 and P2, respectively. Each port pin’s I/O configuration may be controlled independently by the state of it’s corresponding bits in these registers. Control registers A and B together determine the function of the port pins as follows: 11 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet B bit 0 0 1 1 A bit 0 1 0 1 Port Pin Function Input - Weak Pull-up Input - Strong Pull-up Input - No pull-up Output (For example, if register E7.Bit 4 is set high, and register E6.Bit 4 is low, then pin P0.4 is an input without a pull-up device.) After reset, pins P0.0-P0.7 and P2.5-P2.7 are set to be digital inputs with weak pull-ups, and pins P2.0-P2.4 are configured as analog input pins with no pull-ups. Being reset as an input and lightly pulled to a known (high) state ensures minimum power consumption as a default beginning. Eight of these pins (Port P0) can also be configured as inputs to control IO Wakeup events. (see “Power and Wakeup Control” section). P2.0, P2.1, P2.3, and P2.4 can be configured as comparator inputs. P2.2 can be configured as a comparator reference. Some or all of P2.0-P2.4 can be configured as digital inputs by the use of the “cmpCtl” register (register D4) Bits[2:0] (see “Comparator Unit” section) Note: When configuring P2.0-P2.4 as digital inputs the associated weak pull-up should be selected as shown above. P0.0 and P0.2 can be configured as External Interrupts (see “Interrupts” section). P0.1 can be configured in input mode as a gate for an external event counter. (See “Timers/Counters” Section) Registers E5 (“p0In”) and E4 (“p0Out”), and DD (“p2In”) and DC (“p2Out”), provide paths for data input and data output on P0 and P2, respectively. The input registers are actually buffers that record the value at the ports at the time they are read. The output registers latch the data written to them and express it on the ports when the ports are configured as an output. Following is a summary of the general purpose I/O control registers: Register 0DCH Read/Write 0DDH Read 0DEH Read/Write 0DFH Read/Write P2[0:7] (port 2) output register. Cleared by reset. Port 2 input. Port 2 Control Register A. Cleared by reset. Port 2 Control Register B. Bits[7:5] cleared by reset. Bits[4:0] set by reset P0[0:7] (port 0) output register. Cleared by reset. Port 0 input. Port 0 Control Register A. Cleared by reset. Port 0 Control Register B. Cleared by reset. 0E4H 0E5H 0E6H 0E7H Read/Write Read Read/Write Read/Write GPIO during powerdown GPIO should be put in input mode and a known state (e.g. light pull-up) whenever possible to conserve power, and especially in powerdown mode to achieve the specified minimum supply current consumption. 12 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 Memory Addressing The RSC-464 can address up to 64Kbytes of default internal ROM providing Constant/Code Space. Constant/Code Space is read-only in the RSC-464 One may also interface to serial memory devices for storage and retrieval of speech data, by using the serial drivers for ROM, Flash, EEPROM, etc. provided in the FluentChip™ Technology Library. The serial memory option is useful for applications for which speech or music data exceed the storage capacity of on chip ROM. The specific I/O used by the serial interface are configurable. (See the “FluentChip™ Technology Library Manual” for more information). An example of the optional use of external serial Flash is provided in Reference Schematic 1-1. Constant/Code Space When reading Constant/Code Space, an application can access up to 64KBytes. The MOVC and MOVX instruction can read these first 64KBytes. However, the MOVC is more efficient for reading Constants within the current Code Bank. This 64KBytes is called Code Bank 0. NOTE: Constant Space may be referred to as “Const Space” in assemblers and compilers. M e m o r y M a p D ia g r a m C o d e /C o n s ta n t (C o n s t ) S p a c e R e a d : M O V C (-R D R ) W rite : M O V C (-W R C ) 000000H 00FFFFH C o d e b a n k 0 a n d /o r C o n s ta n ts (C o n s t) R e a d : M O V X (-R D R ), if D 2 .4 = 0 W rite : N o n e N /A Oscillators Two independent oscillators in the RSC-464 provide a high-frequency oscillator (OSC1), and a 32 KHz timekeeping and power-saving oscillator (OSC2). The oscillator characteristics are: OSC FREQ PLL PINS SOURCES Crystal 1 3.58 MHz 4X XI1 XO1 Ceramic resonator LC Crystal 2 32768 Hz N/A XI2 XO2 Internal RC 13 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet OSC1 OSC1 is enabled by programming register E8.Bit0 to “0”, which is the reset state for this bit. This bit is also programmed to “0” during a Wakeup Event, enabling OSC1, if register E8.Bit2 is programmed to “0”. (see “Power and Wakeup Control” section) In this case, a 10-20 millisecond delay will be forced to allow OSC1 to reach stable oscillation. OSC1 must run at 3.58 MHz when using the FluentChip™ technologies, but may be slower if the RSC464 is used as a general purpose platform for other applications. When OSC1 is disabled, the PLL which generates the 14.32MHz clock (CLK1) is also disabled. OSC2 OSC2 is enabled by programming register E8.Bit1 to “1”. The reset state for this bit is “0”, so this oscillator is disabled by reset. OSC2 will be enabled during a Wakeup Event if register E8.Bit2 is programmed to “1”. (see “Power and Wakeup Control” section) No delay will be forced, as OSC2 is assumed to be running during Idle mode. The OSC2 source may be set to an external 32 KHz crystal by programming register EF.Bit2 to “0” (Note: register EF.Bit7 must be “0” to enable writing EF.Bit2). The external 32 KHz crystal should be used when accurate timing and/or time-keeping is essential. In this mode, OSC2 is capable of achieving errors as low as 20ppm, depending on the quality of the crystal and crystal circuit design. A typical value for the crystal bias capacitors is 27pF, but this will vary depending on the crystal quality and stray capacitance inherent in the application board layout. The OSC2 source may be set to an on-chip RC by programming register EF.Bit2 to “1” (Note: register EF.Bit7 must be “0” to enable writing EF.Bit2). When using the on-chip RC, no external components are required for OSC1. The on-chip RC value will vary due to process, temperature and supply voltage variations, so this oscillator frequency will vary by +/- 30%. The on-chip RC mode should be used for low power modes where timing is not critical and minimum system cost is important. Oscillator Stabilization When exiting Sleep mode (see “Power and Wakeup Control” section) OSC1 will have a forced 10-20millisecond delay for stabilization if it is enabled. If OSC2 is enabled, it may require several seconds to stabilize, after which the RSC4128 will begin running. Therefore, for fast response out of Sleep mode OSC1 should be enabled. Clocks The RSC-464 uses a fully static core – the processor can be stopped (by removing the clock source) and restarted without causing a reset or losing contents of internal registers. Dynamic operation is guaranteed from ~1KHz to 14.32 MHz. Fast Clock The 3.58 MHz OSC1 frequency is quadrupled by an on-chip PLL to produce a 14.32 MHz internal clock (CLK1). Creating the internal clock in this way avoids an expensive high frequency crystal, substantially reducing overall system cost. When used as the processor clock (see below), the 14.32 MHz internal clock creates internal RAM cycles of 70 nsec duration, and internal or external Code/Data memory cycles of 140 nsec duration. Careful design may allow operation with memories having access times as slow as 140 nsec. Slow Clock OSC2 generates an internal clock (CLK2) with an equivalent frequency to OSC2. When used as the processor clock (see below), the RAM access cycles are one CLK2 cycle and Code/Data access cycles are two CLK2 cycles. Processor Clock Either CLK1 or CLK2 can be selected as the processor clock (PCLK) on the fly by changing the value of register E8.Bit2. The reset state defaults to CLK1. (NOTE: it is possible to select a disabled clock as the processor clock. It is the responsibility of the programmer not to select a clock until the corresponding oscillator has been enabled and allowed to stabilize.) Power savings may result by using CLK2 when the processor is a lower activity mode and using CLK1 when in a higher activity mode. If the use of an external clock driver is desired, the output of that driver should be connected to the XI1 pin. 14 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet After source selection, the processor clock can be divided-down in order to limit power consumption. E8.Bits 4 and 3 determine the divisor: E8.Bit4 0 0 1 1 E8.Bit3 0 1 0 1 Processor Clock Divisor 1/2 1/1 (reset default) 1/8 1/256 RSC-464 Register A Processor Clock divisor of 1/1 is typically required for FluentChip™ technology. The processor clock is gated by the Wake-up delay and also gated by “pdn”=0 (register E8.Bit7), in such a way that the processor is stopped in a zero-power state with no loss of context. Other System Clocks The following functional clocks are generated from OSC1: CLK1, the digital filter clock, the analog front end (AFE) master clock, the L1 clock, Timer1 clock, Timer3 clock, and the Multi-Task timer clock. The Timer2 clock and the Watchdog timer clock are generated from OSC2. (see each block’s section for clocking details) All clocks except the Timer2 and Audio Wakeup clocks are gated with the pdn = 0, to assure they are disabled during IDLE and SLEEP modes. Timer2 and Audio Wakeup can run during Idle mode to produce a T2 Wakeup or Audio Wakeup. (see “Power and Wakeup Control” section) Timers/Counters Four programmable timers and one fixed timer in the RSC-464 provide a variety of timing/counting options. Timers 1, 2, 3 and the Multi-Tasking timer can all generate interrupts upon overflow. (See “Interrupts” section) Timers 1 and 3 Each of Timer1 (T1) and Timer3 (T3) consists of an 8-bit reload value register, an 8-bit up-counter, and a 4-bit decoded prescaler register. Each is clocked by CLK1 divided by 16. The reload register is readable and writeable by the processor. The counter is readable with precaution taken against a counter change in the middle of a read. NOTE: If the processor writes to the counter, the data is ignored. Instead, the act of writing to the counter causes the counter to preset to the reload register value. When the timer overflows from FFH, a pulse is generated that sets register FE.Bit 0 (“irq” register; T1 bit) or register FE. Bit 4(T3 bit). The width of the pulse is the pre-scaled counter clock period. Instead of overflowing to 00, the counter is automatically reloaded on each overflow. For example, if the reload value is 0FAH, the counter will count as follows: 0FAH, 0FBH, 0FCH, 0FDH, 0FEH, 0FFH, 0FAH, 0FBH etc. The overflow pulse is generated during the period after the counter value reaches 0FFH. A separate 4-bit decoded prescaler register is between the clock source and the up-counter for each of T1 and T3. The 4bits represent the power of 2 used to divide the timer clock before applying it to the up-counter. For example, a prescaler value of 0 passes the timer clock directly through (divides by 2^0 = 1). A prescaler value of 5 divides the timer clock by 2^5 = 32. 15 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Prescaler value 0000 0001 0010 0011 0100 0101 0110 0111 Divisor 1 2 4 8 16 32 64 128 Prescaler value 1000 1001 1010 1011 1100 1101 1110 1111 Divisor 256 512 1024 2048 4096 8192 16384 32768 The resolution of T1 and T3 is 8 bits, but the range is 23 bits. The longest interval that can be timed by T1 or T3 is 2^15*256 clocks = 9.3 seconds. The 4-bit prescaler for T1 is in the Clock Extensions Register, (register D6.Bits[3:0]). The 4-bit prescaler for T3 is in the Timer3 Control Register (register D9.Bits[3:0]). In addition to its timing capability, T3 can also be configured as a counter of external events. In this configuration it uses either the rising or falling edge of a signal applied to I/O pin P0.1. The selected transition is internally synchronized to CLK1. The maximum external count rate for T3 is 447KHz. The Timer3 Control Register contains the counting/timing options for T3. The register is write-only. Bits[6:4] provide configuration control. Bit6 x 0 1 0 1 Bit5 0 0 0 1 1 Bit4 0 1 1 x x timer source T3CLK T3CLK T3CLK P0.1 P0.1 Configuration timer timer gated by P0.1 LOW timer gated by P0.1 HIGH count P0.1 events, rising edge count P0.1 events, falling edge Bit 7 0: disable T3 and prescaler from counting/timing 1: enable T3 cleared by reset. 0: use rising edge for external event counting use LOW state on pin P0.1 for timer gating 1: use falling edge for external event counting use HIGH state on pin P0.1 for timer gating cleared by reset 0: use internal T3CLK for source (timing) 1: use external events on pin P0.1 for source (counting) cleared by reset 0: normal operation 1: T3 is gated by pin P0.1 according to Bit6 cleared by reset. Encoded prescaler for T3. (See prescaler table above). cleared by reset. Bit 6 Bit 5 Bit 4 Bit 3:0 16 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 T1 and T3 can generate interrupts upon overflow by setting register FD.Bit0=1 and Bit4=1, respectively. (see “Interrupts” section) Timer2 Timer2 (T2) is clocked by CLK2 divided by 128. The overflow pulse from T2 can cause an interrupt request which in turn will cause a T2 Wake-up from power-down, if register E8.Bit6=1. (see “Power and Wakeup Control” section). Note that the Timer2 “irq” bit (register FE.Bit1) must be cleared prior to powering down to allow the wakeup interrupt request to occur. T2 can also generate a standard interrupt request by setting register FD.Bit1=1. (see “Interrupts” section) Timers 1, 2 and 3 Timer Reload and Counter Registers All are cleared to zero on reset. Register t1r t1v t2r t2v t3r t3v addr EBH ECH EDH EEH DAH DBH Read/Write Read Write Read/Write Read Write Read/Write Read Write Timer1 Counter Reload (2's complement of period) Timer1 current counter value Force load of Timer1 counter from reload register Timer2 Counter Reload (2's complement of period) Timer2 current counter value Force load of Timer2 counter from reload register Timer3 Counter Reload (2's complement of period) Timer3 current counter value Force load of Timer3 counter from reload register Multi-Task Timer The multi-tasking (MT) timer is intended to count a fixed interval of 858.1 microseconds. This provides a “heartbeat” for multi-tasking in the FluentChip™ technology library. Other applications may find this useful for similar purposes. This interval is obtained by dividing the CLK1 rate, when running at 14.32 MHz, by a fixed factor of 12288. There is no configurability to the MT timer. One bit in the Clock Extension Register (D6.Bit6) enable this timer’s clock. The MT timer overflow can generate an interrupt by setting register FD.Bit7=1. (see “Interrupts” section) Watchdog Timer Due to static electricity, voltage glitches, or other environmental conditions (or program bugs!), a software program can begin to operate incorrectly. The watchdog timer provides protection from such errant operation. The Watchdog Timer (WDT) unit comprises two control bits in the System Control Register (D5), a special instruction, two status bits, and a 17-bit counter. The counter, driven by OSC2, produces a toggle rate of approximately 4 seconds at the 17th bit. A 2-bit decoded mux in the “sysCtl” register (register D5) allows selecting the WDT timeout pulse from bit 9, 13, 15, or 17 of the counter. This selection sets the timeout in the range of approximately 15.6 msec to 4 seconds. The accuracy of these times will depend on whether the OSC2 source is a 32 KHz crystal or the on-chip RC. The WDT is enabled by register FB.Bit4=1. This bit can only be set by execution of the “WDC” instruction. This bit is cleared by reset, so the WDT is disabled by reset. The bit is also cleared when E8.Bit7=1 (pdn), so the WDT is disabled in either SLEEP or IDLE mode. It is not automatically re-enabled on Wakeup. Program control cannot write to register FB.Bit4 to enable or disable the WDT. That is, FB.Bit4 is a read-only bit for normal register access instructions. Since the WDT needs OSC2 for its operation, once the WDC instruction has been executed and register FB.Bit4=1 to enable the WDT, OSC2 cannot be disabled by programming register E8.Bit1 =0 unless the “pdn” bit (register E8.Bit7) is also set simultaneously. This allows disabling the WDT only when entering a power down mode and is intended to reduce the probability of accidental software disabling of the WDT in active mode. 17 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Executing the WDC instruction clears the WDT counter, sets register FB.Bit4=1, clears register FB.Bit5=0 (wd_timed-out), and starts a new timeout period. The OSC2 oscillator may also be enabled by executing the WDC instruction. If the oscillator is stopped, executing this instruction also sets register E8.Bit1=1 to enable OSC2. In this case, timing will not begin until the oscillator is active. Once the WDT is started, software must execute the WDC instruction at a rate faster than the timeout period. Otherwise the watchdog circuit sets the “watch dog timed out” bit (register FB.Bit5) and generates a Timed Out Reset, which resets the RSC-464. A Timed Out Reset disables the WDT. (See “Reset” section) Software in the reset routine can detect that the WDT timed out (FB.Bit5=1), since that is preserved during the Timed Out Reset. Placing the chip in Sleep or Idle mode disables the WDT operation. Timer Powerdown Some timers have independent power down control, while others may only be powered down by turning off their clock source, setting the “pdn” bit, or resetting. It is not required for the application to do this for full chip power down, as long as it complies with directions in the “Power and Wakeup Control” section. However, one may choose to reduce power consumption in active mode by turning off individual timers. Timer 3 and MT Timer may be independently powered down by setting the register D9.Bit 7 to “0” (“t3Ctl” register, “t3_on” bit) and register D6.Bit 6 to “0” (“clkExt” register, “MTclk_on” bit), respectively. Timer 1, Timer 2 and the WDT require special circumstances to powerdown, which are appropriate for their application. See their respective descriptions for more detail. Interrupts The RSC-464 allows for 8 interrupt request sources, as selected by software. All are asynchronous positive edge activated except the two external requests, which have programmable edges. Each has its own mask bit and request bit in the “imr” and “irq” registers respectively. There is a Global Interrupt Enable flag in the “flags” registers. The “imr” and “irq” bits are listed below with the RSC-464 interrupt source shown in parenthesis: 0FDH “imr” Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: 0FEH “irq” Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: 1=interrupt request #7 (Overflow of MT Timer) 1= interrupt request #6 (Edge of P0.2) 1=interrupt request #5 (Block End)(Reserved for Technology code) 1= interrupt request #4 (Overflow of Timer3) 1= interrupt request #3 (Edge of P0.0) 1= interrupt request #2 (Filter End Marker)(Reserved for Technology code) 1= interrupt request #1 (Overflow of Timer2) 1= interrupt request #0 (Overflow of Timer1) 1= enable interrupt request #7 (Overflow of MT timer) 1= enable interrupt request #6 (Edge of P0.2) 1= enable interrupt request #5 (Block End)(Reserved for Technology code) 1= enable interrupt request #4 (Overflow of Timer3) 1= enable interrupt request #3 (Edge of P0.0) 1= enable interrupt request #2 (Filter End Marker)(Reserved for Technology code) 1= enable interrupt request #1 (Overflow of Timer2) 1= enable interrupt request #0 (Overflow of Timer1) 18 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 If an “irq” bit is set high and the corresponding “imr” bit is set high and the Global Interrupt Enable (“gie”; register FF.bit0) bit is set high, an interrupt will occur. Interrupts may be nested if software handles saving and restoring the “flagsHold” register (register CF). The “flags” register is copied to the “flagsHold” register and then the Global Interrupt Enable is cleared, preventing subsequent interrupts until the IRET instruction is executed. The IRET instruction will restore the “flags” register from the “flagsHold” register. The Global Interrupt Enable bit in the “flags” register must not be re-enabled during the period after an interrupt has been acknowledged and before an IRET instruction has been executed unless interrupt nesting is desired. If an interrupt occurs during an instruction that clears the Global Interrupt Enable bit (typically the CLI instruction) the value of the “gie” bit will be 0 upon completion of the Interrupt Service Routine and Return From Interrupt to the instruction following the one that cleared the “gie” bit. (NOTE: This is a change from the operation of the RSC-364.) The “flagsHold” register is accessible under program control at address CF in order to improve multi-tasking operation. External interrupts may be enabled on pins P0.0 (1st external interrupt request) and P0.2 (2nd external interrupt request), by setting register FD.Bit3=1 and register FD.Bit6=1, respectively. The polarity of the edges to trigger an external interrupt request for P0.0 and are controlled by register D5.Bits[1:0]. Setting D5.Bit0=0 will cause a positive going edge on P0.0 to generate and interrupt and D5.Bit0=1 will cause a negative going edge to generate an interrupt. The same controls for P0.2 are possible with D5.Bit1. The corresponding external “irq” flag will be set if the transition matches the interrupt edge control bit. NOTE: If P0.0 or P0.2 are configured as outputs, writing to those outputs can trigger external interrupt requests if the proper edge polarities occur. The user must be careful to avoid this, unless it is intended to use this as a way of generating interrupt requests under internal software control. An interrupt is disabled by writing a zero to the corresponding bit in the imr register (register 0FDH). However, an active interrupt request can still be pending. To be certain that an interrupt does not happen, you should clear the interrupt request flag in the irq register (register 0FEH) as well. For example: ; Disable timer 1 interrupt cli and mov sti imr,#0FEH irq,#0FEH ; mask new interrupt requests ; clear any pending interrupt request For each interrupt, execution begins at a different address: Interrupt #0 Interrupt #1 Interrupt #2 Interrupt #3 Interrupt #4 Interrupt #5 Interrupt#6 Interrupt#7 Address 04H Address 08H Address 0CH Address 10H Address 14H Address 18H Address 1CH Address 20H (Overflow of Timer 1) (Overflow of Timer 2) (Filter End Marker)(Reserved for Technology code) (Edge of P00) (Overflow of Timer 3) (Block End)(Reserved for Technology code) (Edge of P02) (Overflow of MT timer) The interrupt vector is generated as a 20-bit address. The low 16 bits are derived from the execution table above, and the high 4 bits are selected as a normal code fetch as described in the “Memory Addressing” section. Specifically, the “cb1” bit is not touched by the interrupt. If the corresponding mask register bit is clear, the “irq” bit will not cause an interrupt. However, it can be polled by reading the “irq” register. 19 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet “irq” bits can be cleared by writing a “0” to the corresponding bit at register FE (the “irq” register). “irq” bits cannot be set by writing to register FE. Writing a “1” to that register is a NO-OP. The “irq” bits must be cleared within the interrupt handler by an explicit write to the “irq” register rather than by an implicit interrupt acknowledge. PLEASE NOTE: Clear interrupts this way – mov irq, #bitmask Not this way – And irq, #bitmask ; INCORRECT ; CORRECT The “and” instruction is not atomic. The “and” instruction is a read-modify-write action. If an interrupt occurs during an “and irq” operation the interrupt will be cleared before it is seen, possibly disabling the interrupt until the system is reset. Because one cannot directly set or clear bits in the “irq” register, use “mov irq” as a safe, effective and atomic way to clear bits in the “irq” register. Use it the way you would use an “and” instruction to operate on other registers. NOTE: Bit2 and Bit5 of the “irq” register should always be written as “1” when clearing other “irq” bits, to avoid conflicts with the Technology code use of these bits. In Idle mode, Timer2 continues to operate even when the rest of the RSC-464 is powered-down. An overflow from Timer2 will set the corresponding “irq” flag even when there is no clock input to the processor. Note that the Timer2 “irq” bit (register FE.Bit1) must be cleared prior to powering down to allow the wakeup interrupt request to occur. This may also lead to normal interrupt processing once the processor is active, if the Timer 2 “imr” bit is set (register FD.Bit1). This interrupt response is unique from, and may be in addition to, the T2 Wakeup. Analog input The analog front end (AFE) for the RSC-464 consists of a preamplifier with gain control, a 16-bit analog-to-digital converter, digital decimator and channel filters, and associated references. A single analog input can be processed through the AFE. All of this circuitry can be powered down to conserve battery life by programming register EF.Bit0 to “0”. Setting this bit to “1” powers up the circuitry, requiring a settling time of approximately 10milliseconds. The analog front end (AFE) performs analog to digital conversions on a low-level signals, which may be derived from an electret microphone. The microphone signal is amplified by a preamp that provides four levels of gain, which are selected by programming register D5.Bits[4:3]. Full-scale output for the four settings corresponds to input signals of 100, 50, 25, and 12.5 millivolts Vpeak-peak, as shown in the table below. Gain “sysCtl” Bits[4:3] 00 01 10 11 Input Referred Noise µVrms 5.2* 4.9* 4.6* 4.4 Max Input Signal mVp-p 100 50 25 12.5 mVrms 35.4 17.7 8.8 4.4 Input signals higher than specified will produce a saturated full scale output with no wrap around. A line level audio input must be attenuated to the range shown above for use with the AFE. 20 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet Digital Transfer Functions RSC-464 Lowpass response Detail of passband Frequency Below 8 kHz 9.395 kHz 20 kHz Above 20 kHz Attenuation Min Max 0 1.18 3 dB 87.82 53 NOTE: A 1uF capacitor should be connected to AMPCOM and tied to GND, a 2.2uF should be connected to VCM and tied to GND, and a 0.1uF capacitor should be connected to VREF and tied to GND. Failure to connect this capacitors will substantially degrade ADC performance, and FluentChip™ technology. A/D Conversion The amplified signal is processed by a delta-sigma A/D converter that provides a 1-bit over-sampled digital signal. This digital stream is filtered and decimated to produce 16-bit samples at the fixed rate of 18,636 samples per second. The 16 bit signal will have about 12.5 bits of dynamic range, with about 10 bits above the noise level. These samples are then provided to the RSC-464 digital filter unit formatted as signed two’s-complement 16-bit values. The samples are stored in the digital filter input registers “adcSampleHi” (register F5) and “adcSampleLo” (register F4). Note: Using the AFE for general purposes other than as intended in FluentChip™ technology modules may conflict with FluentChip™. Such conflicts may adversely impact FluentChip™ functionality and/or the functionality of the general purpose application. Care should be taken to avoid such conflicts. Contact Sensory Technical Support for help in this area. Audio Wakeup The Audio Wakeup unit is an analog/digital circuit that can be configured to wakeup from one of four specific audio events: 1) Two handclaps, or any two sharp, closely spaced sounds 2) Three handclaps, or any three sharp, closely spaced sounds 3) A whistle 4) Any “loud” sound above a specified amplitude, with duration options of 1 or 2 seconds 21 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Because it is intended to “listen” continuously at very low power levels, the Audio Wakeup unit must detect each of these events without any processor interaction. The processor configures and enables the unit under program control before going into Idle mode. Audio Wakeup is not available in Sleep mode because the unit requires the CLK2 signal. The detection signal from the Audio Wakeup unit can trigger a wakeup event, which starts the processor and allows further audio processing. The processor inputs to the Audio Wakeup are an enable signal and control signals to select for which sound to listen. See schematic 1-3 for details on this implementation. Schematic 1-3 NOTES: 1. Optional. This capacitor MAY reduce noise coupled into the mic input on a noisy PCB. 2. If used, this capacitor MUST be placed close to the RSC-4128 AGND and MIC1IN pads. 3. Place close to MICIN1. 4. Place close to MICIN2. RSC-4x Example using one microphone for both Audio Wakeup and normal operation MK1 1 2 1.2K MICROPHONE C5 .1 100 -> 220uF AVdd C8 100 AVdd R2 R1 Px.n MICIN2 AMPCOM (Px.n is any available port I/O pin) MICIN1 VCM AVss Vdd Vdd C7 .1 NOTE 1 NOTE 2 C9 3300pF 2.2uF NOTE 4 C6 .047 C4 C1 .1 NOTE 3 .1 VREF GND C2 C3 1uF example 1 RSC-4x Example using one microphone for normal operation only AVdd MK1 1 2 1.2K MICROPHONE C5 .1 100 -> 220uF AVdd C7 100 AVdd R2 R1 Px.n MICIN2 AMPCOM 1 (Px.n is any available port I/O pin) MICIN1 VCM AVss Vdd VREF GND Vdd BT1 3V 2 GND C6 .1 NOTE 1 C8 NOTE 3 C1 .1 .1 C2 2.2uF C4 C3 1uF 3300pF NOTE 2 The RSC-464 FluentChip™ library contains routines for detecting each of the four audio events listed above. These routines also manage powerdown appropriately. See the “FluentChip™ Technology Library Manual” for reference code to invoke these routines. Microphones A single electret microphone may be used both for the analog front-end input (for recognition purposes) and as the sound source for the Audio Wakeup unit. The current consumption and frequency response requirements are different for the two uses, so two microphone input pads are provided: MICIN1 for the normal recognition input to the analog front-end, and MICIN2 for the Audio Wakeup analog front end. A common microphone ground is used for both the normal recognition analog front-end and the Audio Wakeup analog front end. During normal recognition and Audio Wakeup operation, the microphone would typically be powered from a source with an impedance in the range of 1-3 Kohms. If both the normal recognition and Audio Wakeup front ends are used, they must be isolated from each other by capacitors and may share one microphone and microphone bias circuit. The switching of the microphone input source is under program control. See schematic 1-3 for details on this implementation. The recommended value for the microphone filter capacitor (labeled “C5” in Schematic 1-3) is in the range of 100uF-220uF. Using a capacitor at the upper end of this range will reduce low frequency noise. Low frequency noise on the microphone input typically won’t affect recognition, but could affect the quality of speech playback when using Record and Playback technology in an application. (see the “FluentChip™ Technology Library Manual” for more information on Record and Playback) Typical low frequency noise sources include 60 Hz hum, “motor 22 P/N 80-0282-A © 2005 Sensory Inc. AVss Vdd Preliminary Data Sheet RSC-464 boating” or cyclical fluctuations in the system power supply from “sagging” due to flash writes during speech recording, and LED blinking during recording of speech. All of these effects are reduced in speech playback by using a capacitor closer to 220uF. NOTE: See Design Notes - “Microphone Housing” and “Selecting Microphone” on the RSC-4x Demo/Evaluation CD. Improper microphone circuit and/or enclosure design will result in poor recognition performance. Reset An external reset is generated by applying a low condition for at least two clock cycles on -RESET, an active low Schmitt trigger input. The output of the Schmitt trigger passes through a 10 nsec glitch blocking circuit, followed by an asynchronous flip-flop. The output of the flip-flop generates active high reset throughout RSC-464. The internal reset state is held for 20 msec (when clocked by a 14.32 MHz PCLK). The purpose is to allow the oscillator to stabilize and the PLL to lock before enabling the processor and the other RSC-464 circuits. External reset clears the Global Interrupt Enable flag and begins execution at address 0h. The special function registers will be cleared, set, or left as-is, as detailed in the “Special Function Registers Summary” section. Watchdog Timeout Reset A special Watchdog Timeout Reset is produced if the Watchdog Timer is enabled and the Watchdog counter times out. The only difference between the Watchdog Timeout Reset and an ordinary reset is that the “wd_timed” bit in the “sysStat” register (register FB.Bit5) is preserved as “1” for a Watchdog Timeout Reset Digital-to-Analog-Converter (DAC) Output The DAC consists of an R-2R network with 10 bits of resolution and an output impedance of approximately 11 Kohms. An external amplifier is required to drive a speaker when using the DAC. The specifications of that amplifier will determine the best choice of speaker impedance and the resulting volume. The 10-bit resolution corresponds to an analog voltage range between 0V and Vdd minus 1 LSB (represented as “Vdd-“). At Vdd=3V, one LSB of the R-2R network corresponds to about 3 mV. For example: R2R Value 000H = 0v 001H = 0v+ 200H = Vdd/2 3FFH = VddDAC output; Vdd=3V 0.000V 0.003V 1.500V 2.997V There are two DAC output modes, full-scale and half-scale. In full-scale mode the output voltage swings between 0v and Vdd-; in half-scale mode the output swings between Vdd/4 and 3Vdd/4 minus 1 LSB (roughly Vdd/2 +/Vdd/4). Values written into the DAC hold register and certain Analog Control register bits are converted into analog voltages. The DAC hold register (“dac”; register FA) presents an 8-bit signed value to the DAC unit. In full-scale mode, the 8 most significant bits are driven by the DAC hold register and the 2 least significant bits are driven by the LSB1 and LSB0 bits in the Analog Control register (“anCtl”; register EF.Bits[5:4]). This results in a total output range of –512 to +511. In half-scale mode the 8 middle bits of are driven by the DAC hold register, the most significant bit is generated automatically by sign extension, and the least significant bit is driven by bit LSB1 in the Analog Control register. This gives a total output range of –256 to +255. The half-scale mode is enabled by setting the mode bit (d2a_half) equal to “1” in register EF.Bit3. The tables below show a selection of values and the resulting output voltage. Note: Register EF.Bit7 (“-anctlen”) must be “0” in the value being written to register EF, when writing EF.Bit2. 23 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Full-Scale Mode (Output range 0v to Vdd- 1 LSB) Decimal DAC hold Analog Cntrl Digital input Equivalent reg[7:0] (hex) [5:4] (binary) -512 80H 00 000H -511 80H 01 001H -510 80H 10 002H -509 80H 11 003H -508 81H 00 004H -2 -1 0 +1 +2 +3 +4 +510 +511 FFH FFH 00H 00H 00H 00H 01H 7FH 7FH 10 11 00 01 10 11 00 10 11 1FEH 1FFH 200H 201H 202H 203H 204H 3FEH 3FFH Preliminary Data Sheet Analog Voltage output General 0-3V (approx) 0V 0.000V 0V+ 1 LSB 0.003V 0.006V 0.009V 0.012V Vdd/2- 1 LSB Vdd/2 Vdd/2+ 1LSB 1.497V 1.500V 1.503V Vdd- 1LSB 2.994V 2.997V The translation in Full-Scale mode is: R2R[9] = dac[7] inverted R2R[8:2] = dac[6:0] R2R[1:0] = anCtl[5:4] Half-Scale Mode (Output range Vdd/4 to 3Vdd/4- 1 LSB) Decimal DAC hold Analog Cntrl Digital Input Equivalent reg[7:0] (hex) [5:4] (binary) -256 80H 0x 100H -255 80H 1x 101H -254 81H 0x 102H -253 81H 1x 103H -252 82H 0x 104H -2 -1 0 +1 +2 +3 +4 +254 +255 FFH FFH 00H 00H 01H 01H 02H 7FH 7FH 0x 1x 0x 1x 0x 1x 0x 0x 1x 1FEH 1FFH 200H 201H 202H 203H 204H 2FEH 2FFH Analog Voltage output General 0-3V (approx) Vdd/4 0.750V Vdd/4+ 1 LSB 0.753V 0.756V 0.759V 0.762V Vdd/2- 1LSB Vdd/2 Vdd/2+ 1LSB 1.497V 1.500V 1.503V 3Vdd/4-1 LSB 2.244V 2.247V The translation in Half-Scale mode is: R2R[9] = dac[7] inverted R2R[8:1] = dac[7:0] R2R[0] = anCtl[5] DAC Power Control The DAC has no explicit power control. It is turned off (placed into lowest current mode) by loading the value 80H into the DAC hold register, and 0 into the LSB1 and LSB0 bits of the Analog Control Register (register EF.Bits[5:4]). Note: register EF.Bit7 (“-anCtl” must be “0” in the value being written to register EF, when writing EF.Bits[5:0]. 24 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 Pulse Width Modulator (PWM) Analog Output The PWM consists of circuitry to regulate the width of a pulse supplied to one of two outputs, PWM0 and PWM1, over a period of programmable duration. One or the other of the two outputs is held at ground and the other is driven with a pulse of programmable duration, giving “push-pull” drive. Both outputs have “low shoot-thru” transistors to reduce radiated EMI. Once programmed, the PWM produces outputs continuously until register values are changed. The PWM has both 8 and 10 bit modes. The PWM Control Register (‘pwmCtl”; register D7) contains the PWM on/off control (Bit0), the sample period (Bits[3:2]), sample size selection controls (Bit5), and the two least-significant bits of the 10-bit output value (Bits[7:6]). The sample size defaults to 8 bits, with register D7.Bit5=0 (“tenBits”). A sample size of 10 bits is selected by setting “tenBits” =1. The PWM output impedance is approximately 11 Ohms. Of the standard speaker impedances available, an 8 ohm speaker will provide optimal volume when driven by the PWM. The PWM contains two counters. The data value counter is programmed with the value programmed in the “pwmData” register (register D8) in 8-bit mode. In 10-bit mode the data value counter uses “pwmData” and appends Bits[7:6] of “pwmCtl” as the least significant two bits to create a 10 bit value. Output data always lags input by one PWM sample period. The sample period counter is fixed and counts to 128. The prescaler in the PWM control register (register D7.Bits[3:2]) determines the clock for both the data value counter and the sample period counter. The prescaler divides the 14.3 MHz clock by 4,6, or 7, resulting in a PWM frequency of 27.9 KHz, 18.6Khz and 15.97 KHz, respectively. The PWM restarts every sample period, at which time either PWM0 or PWM1 pulses high. The selected signal pulses high for a duration determined by the data value and then returns low. The nonselected signal remains low. The pulsed output selection is controlled by the sign of the data. When Bit 7 of the “pwmData” register is 0, PWM0 pulses high while PWM1 remains 0. When Bit 7 of the “pwmData” register is 1, PWM1 pulses high while PWM0 remains low. When the data value in “pwmData” is 0, both signals remain low. When the sample period count selected by programming Bits[3:2] of the “pwmCtl” register D7.Bit has been reached, the PWM restarts. The PWM hardware sample period and the software data value updating must be synchronized to avoid aliasing. The following table shows the rates and pulse durations obtained for 8-bit mode (“tenBits” programmed to “0”) SOFTWARE NOTE: “Full scale” output for all prescaler values is obtained by setting the data value to 7FH, so 8-bit signed data can be output at any of the three rates without amplitude adjustment. PWM timing for “tenBits”=0 Item prescaler=4 prescaler=6 nsec/clock (period clock) 280 420 CLK1 clocks per period 512 768 nsec/clock (sample 280 420 clock) PWM frequency 27.9 kHz 18.6 kHz pulse for data=01 4 H / 508 L 6 H / 762 L pulse for data=7F 508 H / 4L 762 H / 6 L prescaler=7 490 896 490 15.97 kHz 7 H / 889 L 889 H / 7 L For 10-bit mode (“tenBits” programmed to “1”), the sample period counter counts a full 7-bits (128 counts), exactly as when TenBits is 0. The 14.3 MHz clock is divided by the prescaler value and supplied to the sample period counter. The data value counter is clocked by the 14.3 clock divided by 2 for prescaler values 6 or 7, and is clocked directly by the 14.3 MHz clock when the prescaler value is 4. Table YY shows the rates and pulse durations obtained with TenBits set to 1. SOFTWARE NOTE: “Full scale” output is obtained with a different data value for each prescaler value. Only prescaler=4 supports a full 9-bit count (512), so true 10-bit signed data can be output only with prescaler=4. Otherwise the amplitudes must be adjusted to have maximum amplitude of 447 (prescaler=7) or 383 (prescaler=6). See “Additional considerations using the PWM for 10-bit Data” below. 25 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet PWM timing for TenBits=1 Item prescaler=4 prescaler=6 nsec/clock (period ctr) 280 420 CLK1 clocks per period 512 768 nsec/clock (data ctr) 70 140 PWM frequency 27.9 kHz 18.6 kHz pulse for data=001 1 H / 511 L 2 H / 766 L pulse for data=17F 383 H / 129 L 766 H / 2 L pulse for data=1BF 447 H / 65 L -- n/a -pulse for data=1FF 511 H / 1 L -- n/a -- prescaler=7 490 896 140 15.97 kHz 2 H / 894 L 766 H / 130 L 894 H / 2 L -- n/a -- Additional considerations using the PWM for 10-bit Data The 14.3 MHz CLK1 clock rate of the RSC-464 is not fast enough to provide PWM synchronization with 10-bit 8kHz or 9.3 kHz data. To understand this, consider a PWM rate of 8 kHZ (125 microsec). To output 10 bits (9 bits plus sign) during this interval, a source must provide 512 clocks, giving a source rate of 125000/512 = 244 nsec. The CLK1 period is 70 nsec, so the relationship between the source clock and CLK1 is 244/70 = 3.5, which is not an integer. So the source clock cannot be derived simply from CLK1. The RSC-464 application developer should address this issue by using a “near-10-bit” resolution, as follows. The TenBits bit is set in the “pwmCtl” register, and the prescaler is programmed to 7 to produce a PWM frequency of 15.98 kHz (62.57 microseconds). During this interval there will be 62570/70 = 894 CLK1 clocks, or 894/2 (=447) data counter clocks. The number 447 thus represents the largest possible count that can be loaded into the data value counter. The range of allowable values is from –447 to +447. Any larger value would produce the same output of the PWM pulse “on” for the entire duration of the PWM period. Thus 447 represents “full scale” of the PWM. If all 10-bit data values are then scaled to a maximum of +/-447, the PWM will provide full-scale swing and (close-enough) synchronization at 8 kHz. The actual number of bits in the data is log2(447 – (-447)) = 9.8 bits. The developer must ensure that the value programmed in the data value counter must not exceed the range of –447 to +447. FluentChip™ provides PWM output utilities for speech and music that manage the PWM for the developer, if so desired. (See “FluentChip™ Technology Library Manual”) PWM powerdown The PWM may be independently powered down by programming the register D7.Bit 0 to “0” (“pwmCtl” register, “pwm_on” bit). When the PWM is off, the PWM outputs PWM0 and PWM1 are in a high-Z state and pulled up by internal 10K resistors. The PWM must be explicitly turned off before setting “pdn” equal to 1 to achieve the lowest powerdown current. Comparator Unit The Comparator Unit consists of 2 analog comparators designated “A” and “B”, a programmable voltage reference, selection circuitry, and two registers – the Comparator Control register (“cmpCtl”) and the Comparator Reference (“cmpRef”). Register “cmpCtl” configures the comparator unit and provides the digital comparator outputs. Bits [2:0] are used to select from one of eight comparator configurations, in which some or all of P2.0-P2.4 may be analog or digital inputs. (See “RSC-464 Comparator Unit” figure; “A” denotes analog input and “D” denotes digital input) Bits [3:0] are read-write. Register “cmpRef” controls the Comparator Reference Voltage. The unit can provide level information under software control about 4 external analog signals. All external signals connected to the comparator inputs must be between Vss and Vdd. 26 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 Each comparator has two analog inputs, designated “+” and “-“, and one digital output. When the analog voltage on the “+” input is greater than the analog voltage on the “-“ input, the digital output is a high level. This is indicated by a “1” in the “cmpCtl” register (register D4) Bits 7 & 6 for Comparators A and B, respectively. When the analog voltage on the “+” input is less than the analog voltage on the “-“ input, the digital output is a low level. This is indicated by a “0” in the “cmpCtl” register (register D4) Bits 7 & 6 for Comparators A and B, respectively. Bits 7 and 6 are the comparator outputs and are “Read-Only” by the processor. Each comparator can be separately enabled or disabled. When a comparator is disabled, both inputs are isolated from any circuitry common to both comparators, the inputs are grounded, and the comparator power is turned off. Comparator Multiplexing Each comparator “+” input has an analog multiplexer that selects between one of two external signals. When Bit3 of “cmpCtl” is programmed to “0”, comparator input A+ is multiplexed to P2.0 and input B+ is multiplexed to P2.1. When Bit3 of “cmpCtl” is programmed to “1”, comparator input A+ is multiplexed to P2.3 and input B+ is multiplexed to P2.4. The “-“ inputs of both comparators are connected together. This common “-“ input can be multiplexed to either an external comparator reference signal input through P2.2, or the Comparator Reference Voltage (CRV). Comparator Reference Voltage CmpCtl=000 A P2.0 A P2.3 OFF A P2.1 A P2.4 OFF A P2.2 CmpCtl=001 A P2.0 A P2.3 A P2.1 A P2.4 iVREF D P2.2 CmpCtl=011 A P2.0 A P2.3 D P2.1 D P2.4 OFF iVREF D P2.2 CmpCtl=101 D P2.0 D P2.3 OFF A P2.1 A P2.4 iVREF D P2.2 A P2.2 B A P2.1 A P2.4 A D P2.0 D P2.3 A P2.2 B A A P2.0 A P2.3 D P2.1 D P2.4 A P2.2 B A A P2.0 A P2.3 A P2.1 A P2.4 D P2.2 B D P2.1 D P2.4 A D P2.0 D P2.3 CmpCtl=111 A OFF B OFF CmpCtl=010 A B CmpCtl=100 A B OFF CmpCtl=110 A OFF B RSC-464 Comparator Unit The internal Comparator Reference Voltage (CRV) is derived from a multi-tap resistive divider and a 4-bit analog multiplexer. Register “cmpRef” controls the Comparator Reference Voltage. The power for the Comparator Reference Voltage is provided by unregulated Vdd. This means that the CRV will track external voltages referenced from the system supply, giving consistent comparisons as the system supply drops. Power to the CRV is gated by decoding the comparator configuration. The voltage select value in “cmpRef” Bits[3:0] selects one of 16 outputs of an analog multiplexer connected to 16 equally spaced taps. The Comparator Reference Voltage covers the range from 0.15*Vdd to 0.90*Vdd in steps of 0.05*Vdd and is given by 0.15*Vdd + (D3[3:0]/20)*Vdd. In some configurations the Comparator Control register can be set up once and simply read thereafter. In many configurations it will be necessary to switch the input multiplexers and/or re-program the reference voltage repeatedly. These multiplexing and selection operations will have settling times of approximately 10 microseconds. When the “pdn” bit is set for Idle or Sleep mode the entire comparator unit is powered down, but the contents of the “cmpCtl” and “cmpRef” registers are preserved. When the RSC-464 wakes up the comparators resume normal operation. 27 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Instruction Set Opcodes and Timing Details The RSC-464 instruction set has 60 instructions comprising 13 move, 7 rotate/shift, 11 jump/branch, 13 register arithmetic, 9 immediate arithmetic, and 7 miscellaneous instructions. All instructions are 3 bytes or fewer, and no instruction requires more than 10 clock cycles (plus wait states) to execute. The column “Cycles” indicates the number of clock cycles required for each instruction when operating with zero wait states. Wait states may be added to lengthen all accesses to external addresses or to the internal ROM (but not internal SRAM). The column “+Cycles/Waitstate” shows the number of additional cycles added for each additional wait state. Opcodes are in HEX. MOVE Group Instructions Register-indirect instructions accessing code (MOVC), data (MOVX), technology (MOVY) or register (MOV) space locations use an 8-bit operand (“@source” or “@dest”) to designate an SRAM register pointer to the 16-bit target address. The “source” or “dest” indirect pointer register must be at an even address unless it is a 8-bit pointer (indirect MOV). The LOW byte of the target address is contained at the pointer address, and the HIGH byte of the target address is contained at the pointer address+1. Unless the flags register is the destination, the carry, sign, and zero flags are not affected by MOV instructions. Instruction MOV MOV MOV MOV MOVC MOVC MOVX MOVX POP Opcode 10 11 12 13 14 15 16 17 18 Operand 1 dest @dest dest dest dest @dest dest @dest dest Operand 2 Source Source @source #immed @source Source @source Source @++source Description register to register register to register-indirect register-indirect to register immediate data to register code space to register register to code space data space to register register to data space register to register data stack pop (source preincremented) register to register data stack push (dest postdecremented) RAMY to register, indirect Register to RAMY, indirect register to register, direct, 16-bit MOV Bytes 3 3 3 3 3 3 3 3 3 Cycles 5 5 6 4 7 8 7 8 10 +Cycles/Waitstate 3 3 3 3 4 4 4* 4* 3 PUSH 19 @dest-- Source 3 9 3 MOVY MOVY MOVD 1A 1B 1C dest @dest dest_pair @source source source_pair 3 3 3 7 7 7 3 3 3 * If register D6.Bit 5=1 (movX_4ws) and external read/write memory is selected by setting the “rw” bit (register D2.Bit4), MOVX instructions have four additional wait states. 28 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 ROTATE Group Instructions Rotate group instructions apply only directly to register space SRAM locations. The carry flag is affected by these instructions, but the sign and zero flags are unaffected. Instruction RL RR RLC RRC SHL SHR SAR Opcode 30 31 32 33 34 35 36 Operand 1 dest dest dest dest dest dest dest Operand 2 Description rotate left, c set from b7 rotate right, c set from b0 rotate left through carry rotate right through carry shift left, c set from b7, b0=0 shift right, c set from b0, b7=0 shift right arithmetic, c set from b0, b7 duplicated Bytes 2 2 2 2 2 2 2 Cycles 5 5 5 5 5 5 5 +Cycles/Waitstate 2 2 2 2 2 2 2 BRANCH Group Instructions The branch instructions use direct address values rather than offsets to define the target address of the branch. This implies that binary code containing branches is not relocatable. However, object code produced by the RSC464 assembler contains address references that are resolved at link time, so .OBJ modules are relocatable. The indirect jump instruction uses an 8-bit operand (“@dest”) to designate an SRAM register pointer to the 16-bit target address. The “dest” pointer register must be at an even address. The LOW byte of the target address is contained at the pointer address, and the HIGH byte of the target address is contained at the pointer address+1. Instruction JC JNC JZ JNZ JS JNS JMP CALL RET IRET JMPR Opcode 20 21 22 23 24 25 26 27 28 29 2A Operand 1 dest low dest low dest low dest low dest low dest low dest low dest low @dest Operand 2 dest high dest high dest high dest high dest high dest high dest high dest high Description jump on carry = 1 jump on carry = 0 jump on zflag = 1 jump on zflag = 0 jump on sflag = 1 jump on sflag = 0 jump unconditional direct subroutine call return from call return from interrupt jump indirect Bytes 3 3 3 3 3 3 3 3 1 1 2 Cycles 3 3 3 3 3 3 3 3 2 2 4 +Cycles/Waitstate 3 3 3 3 3 3 3 3 1 1 2 ARITHMETIC/LOGICAL Group Instructions Arithmetic and logical group instructions apply only to Register Space SRAM locations. The results of the instruction are always written directly to the SRAM “dest” register. The exceptions are TM and CP instructions, which do not write the result to the “dest” register and only update the flags register based on the operation’s outcome. All but the INCrement and DECrement instructions have both register source and immediate source forms. In each of the following instructions the sign and zero flags are updated based on the result of the operation. The carry flag is updated by the arithmetic operations (ADD, ADC, SUB, SUBC, CP, INC, DEC) but it is not affected by the logical operations (AND, TM, OR, XOR). Note: the carry is set high by SUB, CP, SUBC and DEC when a borrow is generated. 29 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Instruction Opcode Operand 1 Operand 2 Description AND 40 dest source logical and TM 41 dest source like AND, destination register unchanged OR 42 dest source logical or XOR 43 dest source exclusive or SUB 44 dest source subtract CP 45 dest source like SUB, destination register unchanged SUBC 46 dest source subtract w/carry ADD 47 dest source add ADC 48 dest source add w/carry INC 49 dest increment DEC 4A dest decrement AND 50 dest #immed logical and TM 51 dest #immed like AND, destination register unchanged OR 52 dest #immed logical or XOR 53 dest #immed exclusive or SUB 54 dest #immed subtract CP 55 dest #immed like SUB, destination register unchanged SUBC 56 dest #immed subtract w/carry ADD 57 dest #immed add ADC 58 dest #immed add w/carry INCD 69 dest_pair & register pair 16-bit source_pair increment CPD 66 dest_pair source_pair 16-bit compare Bytes 3 3 3 3 3 3 3 3 3 2 2 3 3 3 3 3 3 3 3 3 2 3 Cycles +Cycles/Waitstate 6 3 6 3 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 8 10 3 3 3 3 3 3 3 2 2 3 3 3 3 3 3 3 3 3 2 3 MISCELLANEOUS Group Instructions Instruction NOP CLC STC CMC CLI STI WDC Opcode 00 01 02 03 04 05 06 Operand 1 Operand 2 Description no operation clear carry set carry complement carry disable interrupts enable interrupts enable/restart Watchdog timer Bytes 1 1 1 1 1 1 1 Cycles 2 2 2 2 2 2 2 +Cycles/Waitstate 1 1 1 1 1 1 1 30 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 Special Functions Registers (SFRs) Summary Address FF FE FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CF CE R/W R/W R/W R/W R/W W R R/W R/W R/W R/W R/W W R W R R/W R/W W R R/W W R W R R/W W R R/W R/W R/W R/W R/W R/W R R/W Name flags ***** irq * imr **** bank RESERVED sysStat dac RESERVED RESERVED stkData stkNdx RESERVED adcSampleHi RESERVED adcSampleLo RESERVED RESERVED RESERVED RESERVED RESERVED anCtl *** t2v ** 0000 0000 t2r t1v ** 0000 0000 t1r wake1 wake0 ckCtl **** p0CtlB p0CtlA p0In p0Out RESERVED RESERVED RESERVED RESERVED p2CtlB p2CtlA p2In p2Out t3v ** Reset Bit 7 0000 0000 carry 0000 0000 MTtimer 0000 0000 MTtimer 1110 0000 ws2 0000 0000 0000 0000 0 dh7 Bit 6 zero p0.2 p0.2 ws1 1 dh6 Bit 5 sign block block ws0 wd_timed dh5 Bit 4 Bit 3 Bit 2 trap stkoflo stkfull timer3 p0.0 endmark timer3 p0.0 endmark (bank4) bank3 bank2 wd_on dh4 0 dh3 0 dh2 Bit 1 --timer2 timer2 bank1 fastClk dh1 Bit 0 gie timer1 timer1 bank0 0 dh0 0000 0000 0000 0000 0000 0000 0000 0000 stdk7 0 adc15 adc07 stkd6 0 adc14 adc06 stkd5 stkind5 adc13 adc05 stkd4 stkind4 adc12 adc04 stkd3 stkind3 adc11 adc03 stkd2 stkind2 adc10 adc02 stkd1 stkind1 adc09 adc01 stkd0 stkind0 adc08 adc00 0000 0000 -anctlen 0000 0000 -anctlen 0000 0000 x t2v7 0000 0000 t2r7 0000 0000 x t1v7 0000 0000 t1r7 0000 0000 w1.7 0000 0000 w0.7 0000 1000 pdn 0000 0000 ctlb0.7 0000 0000 ctla0.7 xxxx xxxx pin0.7 0000 0000 pout0.7 0 0 x t2v6 t2r6 x t1v6 t1r6 w1.6 w0.6 t2wake ctlb0.6 ctla0.6 pin0.6 pout0.6 lsb1 lsb1 x t2v5 t2r5 x t1v5 t1r5 w1.5 w0.5 fclk_on ctlb0.5 ctla0.5 pin0.5 pout0.5 lsb0 lsb0 x t2v4 t2r4 x t1v4 t1r4 w1.4 w0.4 clk_div1 ctlb0.4 ctla0.4 pin0.4 pout0.4 d2a_half rc_osc2 0 afe_on d2a_half rc_osc2 0 afe_on x x x x t2v3 t2v2 t2v1 t2v0 t2r3 y2r2 t2r1 t2r0 x x x x t1v3 t1v2 t1v1 t1v0 t1r3 t1r2 t1r1 t1r0 w1.3 w1.2 w1.1 w1.0 w0.3 w0.2 w0.1 w0.0 clk_div0 slow_pclk osc2_on osc1_off ctlb0.3 ctlb0.2 ctlb0.1 ctlb0.0 ctla0.3 ctla0.2 ctla0.1 ctla0.0 pin0.3 pin0.2 pin0.1 pin0.0 pout0.3 pout0.2 pout0.1 pout0.0 R/W R/W R R/W W R R/W W R/W R/W R/W R/W W R R/W R/W R/W R/W R/W W 0000 0000 xxxx 0000 0000 0000 t3r 0000 t3Ctl 0000 pwmData 0000 pwmCtl 0000 clkExt **** 0000 sysCtl 0000 cmpCtl 1100 1100 cmpRef 0000 extAdd 0000 RESERVED RESERVED flagsHold 0000 ***** awcCtl 0000 0000 0000 xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ctlb2.7 ctla2.7 pin2.7 pout2.7 x t3v7 t3r7 t3_on pwmd09 pwmd01 rom_0Ws wd_ps1 1 compA+ 0 0 ctlb2.6 ctlb2.5 ctlb2.4 ctlb2.3 ctla2.6 ctla2.5 ctla2.4 ctla2.3 pin2.6 pin2.5 pin2.4 pin2.3 pout2.6 pout2.5 pout2.4 pout2.3 x x x x t3v6 t3v5 t3v4 t3v3 t3r6 t3r5 t3r4 t3r3 polarity p0.1_src t3_gated t3_ps3 pwmd08 pwmd07 pwmd06 pwmd05 pwmd00 tenBits 0 period1 MTclk_on movx_4ws L1clk_on t1_ps3 wd_ps0 brnout_on afe_g1 afe_g0 1 0 0 mux_sel compB+ 0 0 mux_sel 0 0 0 crv03 0 cb1 rw eda19 ctlb2.2 ctla2.2 pin2.2 pout2.2 x t3v2 t3r2 t3_ps2 pwmd04 period0 t1_ps2 0 ccs2 ccs2 crv02 eda18 ctlb2.1 ctla2.1 pin2.1 pout2.1 x t3v1 t3r1 t3_ps1 pwmd03 0 t1_ps1 p02Edge ccs1 ccs1 crv01 eda17 ctlb2.0 ctla2.0 pin2.0 pout2.0 x t3v0 t3r0 t3_ps0 pwmd02 pwm_on t1_ps0 p00Edge ccs0 ccs0 crv00 eda16 0000 0000 carry pwrl zero 0 sign thrh2 trap thrh1 0 thrh0 0 thrl2 0 thrl1 gie thrl0 31 P/N 80-0282-A © 2005 Sensory Inc. RSC-464 Preliminary Data Sheet Address R/W R CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 Name Reset 0000 0000 Bit 7 pwrl Bit 6 detect Bit 5 thrh2 Bit 4 thrh1 Bit 3 thrh0 Bit 2 thrl2 Bit 1 thrl1 Bit 0 thrl0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Reset: “x” = unknown/don’t care, ‘-‘ = not implemented * Only “0” can be written to “irq” bits. “1” is a “nop” for the bit to which it is written. When using FluentChip™ technology, always write “1” to “block” and “endmark” in the “irq” register to avoid conflicting with technology code control of these bits. ** Write value is ignored and reload register value is written instead. *** -anctlen (Bit7) of values written to the “anCtl” register must be “0” to enable writing the other bits in the value to “anCtl”. **** When using FluentChip™ technology, “fclk_on”, “L1clk_on”, and “block” and “endmark” in the “imr” register should be left at the values programmed by the technology code. A read-modify-write action should be used to modify the registers to avoid changing these bits. ***** “trap” must always be written as “0” in the “flags” and “flagsHold” registers 32 P/N 80-0282-A © 2005 Sensory Inc. Preliminary Data Sheet RSC-464 DC Characteristics Operating Conditions (TO = 0°C to +70°C, VDD = 2.4V – 3.6V) SYMBOL VIL VIH IIL IACT IACT IIDLE ISLEEP RPU PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Supply Current, Active Supply Current, Active Supply Current, Idle Supply Current, Sleep Pull-up resistance P0.0-P0.7, P2.0- P2.7 PLLEN, -RESET PWM0, PWM1 Pull-down resistance TEST Output Low Current PDN P0.0-P0.7, P2.0-P2.7 PWM0, PWM1 Output High Current PDN P0.0-P0.7, P2.0-P2.7 PWM0, PWM1 MIN -0.1 0.8*Vdd TYP MAX 0.75 Vdd+0.3 10 20 7 4 UNITS V V µA mA mA µA µA kΩ kΩ kΩ kΩ TEST CONDITIONS