P06B03LVG

Logic Level Enhancement P06B03LVG NIKO-SEM Dual P-ChannelField Effect Transistor Mode SOP-8 Lead Free PRODUCT SUMMARY V(BR)DSS -30 RDS(ON) 50mΩ ID -6A G :GATE D :DRAIN S :SOURCE ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -30 ± 20 -6 -5 UNITS V V TC = 25 °C TC = 70 °C ID IDM A -30 2.5 1.3 W TC = 25 °C TC = 70 °C PD Tj, Tstg TL Operating Junction & Storage Temperature Range Lead Temperature (1/16” from case for 10 sec.) -55 to 150 275 °C THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Ambient 1 2 SYMBOL RθJA TYPICAL MAXIMUM 62.5 UNITS °C / W Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current 1 Drain-Source On-State Resistance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) VGS = 0V, ID = -250µA VDS = VGS, ID = -250µA VDS = 0V, VGS = ± 20V VDS = -24V, VGS = 0V VDS = -20V, VGS = 0V, TJ = 125 °C VDS = -5V, VGS = -10V VGS = -4.5V, ID = - 5A VGS = -10V, ID = -6A -30 65 40 80 50 -30 -0.9 -1.5 -3 ±100 1 10 A mΩ nA µA V LIMITS UNIT MIN TYP MAX May-04-2005 1 Logic Level Enhancement P06B03LVG NIKO-SEM Dual P-ChannelField Effect Transistor Mode SOP-8 Lead Free Forward Transconductance1 gfs VDS = -10V, ID = -6A DYNAMIC 16 S Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge2 Gate-Source Charge2 Gate-Drain Charge 2 Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) VDS = -15V, RL = 1Ω ID ≅ -1A, VGS = -10V, RGS = 6Ω VDS = 0.5V (BR)DSS, VGS = -10V, ID = -6A VGS = 0V, VDS = -15V, f = 1MHz 530 135 70 10 2.2 2 5.7 10 18 5 nS 14 nC pF Turn-On Delay Time2 Rise Time2 Turn-Off Delay Time2 Fall Time2 Continuous Current Pulsed Current 3 IS ISM VSD trr Qrr IF = -1A, VGS = 0V IF = -5A, dlF/dt = 100A / µS 15.5 7.9 -2.1 -4 -1.2 A V nS nC Forward Voltage1 Reverse Recovery Time Reverse Recovery Charge 1 2 Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％ . Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P06B03LVG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. May-04-2005 2 Logic Level Enhancement P06B03LVG NIKO-SEM Dual P-ChannelField Effect Transistor Mode SOP-8 Lead Free Typical Characteristics May-04-2005 3 Logic Level Enhancement P06B03LVG NIKO-SEM Dual P-ChannelField Effect Transistor Mode SOP-8 Lead Free May-04-2005 4 Logic Level Enhancement P06B03LVG NIKO-SEM Dual P-ChannelField Effect Transistor Mode SOP-8 Lead Free SOIC-8 (D) MECHANICAL DATA mm Dimension Min. A B C D E F G 1.35 0.1 4.8 3.8 5.8 0.38 Typ. 4.9 3.9 6.0 0.445 1.27 1.55 0.175 1.75 0.25 Max. 5.0 4.0 6.2 0.51 H I J K L M N 0° Dimension Min. 0.5 0.18 Typ. 0.715 0.254 0.22 4° 8° Max. 0.83 0.25 mm May-04-2005 5