BTS712N1XUMA1

PROFET® BTS712N1 Smart Four Channel Highside Power Switch Features • Overload protection • Current limitation • Short-circuit protection • Thermal shutdown • Overvoltage protection (including load dump) • Fast demagnetization of inductive loads • Reverse battery protection1) • Undervoltage and overvoltage shutdown Product Summary Overvoltage Protection Operating voltage active channels: On-state resistance RON Nominal load current IL(NOM) Current limitation IL(SCr) with auto-restart and hysteresis • Open drain diagnostic output • Open load detection in OFF-state • CMOS compatible input • Loss of ground and loss of Vbb protection • Electrostatic discharge (ESD) protection 43 V Vbb(AZ) Vbb(on) 5.0 ... 34 V two parallel four parallel one 200 100 50 mΩ 1.9 2.8 4.4 A 4 4 4 A P-DSO-20 Application • µC compatible power switch with diagnostic feedback for 12 V and 24 V DC grounded loads • All types of resistive, inductive and capacitive loads • Replaces electromechanical relays and discrete circuits General Description N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, monolithically integrated in Smart SIPMOS technology. Providing embedded protective functions. Pin Definitions and Functions Pin 1,10, 11,12, 15,16, 19,20 3 5 7 9 18 17 14 13 4 8 2 6 1) Symbol Function Vbb Positive power supply voltage. Design the wiring for the simultaneous max. short circuit currents from channel 1 to 4 and also for low thermal resistance IN1 Input 1 .. 4, activates channel 1 .. 4 in case of IN2 logic high signal IN3 IN4 OUT1 Output 1 .. 4, protected high-side power output OUT2 of channel 1 .. 4. Design the wiring for the OUT3 max. short circuit current OUT4 ST1/2 Diagnostic feedback 1/2 of channel 1 and channel 2, open drain, low on failure ST3/4 Diagnostic feedback 3/4 of channel 3 and channel 4, open drain, low on failure GND1/2 Ground 1/2 of chip 1 (channel 1 and channel 2) GND3/4 Ground 3/4 of chip 2 (channel 3 and channel 4) Pin configuration (top view) Vbb GND1/2 IN1 ST1/2 IN2 GND3/4 IN3 ST3/4 IN4 Vbb 1 2 3 4 5 6 7 8 9 10 • 20 19 18 17 16 15 14 13 12 11 Vbb Vbb OUT1 OUT2 Vbb Vbb OUT3 OUT4 Vbb Vbb With external current limit (e.g. resistor RGND=150 Ω) in GND connection, resistor in series with ST connection, reverse load current limited by connected load. Semiconductor Group 1 of 15 2004-Mar-11 BTS712N1 Block diagram Four Channels; Open Load detection in off state; Voltage source Overvoltage protection Current limit 1 Gate 1 protection + V bb Leadframe OUT1 18 OUT2 17 V Logic 3 IN1 5 IN2 4 ST1/2 Voltage Level shifter sensor Rectifier 1 Logic ESD Signal GND Chip 1 Current limit 2 Level shifter Rectifier 2 GND1/2 Channel 1 Temperature sensor 1 Open load Short to Vbb detection 1 Charge pump 1 Charge pump 2 2 Limit for unclamped ind. loads 1 Gate 2 protection Limit for unclamped ind. loads 2 Channel 2 Load Temperature sensor 2 Open load Short to Vbb detection 2 Chip 1 Load GND + V bb Logic and protection circuit of chip 2 Leadframe Channel 3 OUT3 14 Channel 4 OUT4 13 (equivalent to chip 1) 7 IN3 9 IN4 8 ST3/4 6 Load GND3/4 PROFET Signal GND Chip 2  Chip 2 Load GND Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20 Semiconductor Group 2 2004-Mar-11 BTS712N1 Maximum Ratings at Tj = 25°C unless otherwise specified Parameter Symbol Supply voltage (overvoltage protection see page 4) Supply voltage for full short circuit protection Tj,start = -40 ...+150°C Load current (Short-circuit current, see page 5) Load dump protection2) VLoadDump = UA + Vs, UA = 13.5 V RI3) = 2 Ω, td = 200 ms; IN = low or high, each channel loaded with RL = 7.1 Ω, Operating temperature range Storage temperature range Power dissipation (DC)5 Ta = 25°C: (all channels active) Ta = 85°C: Inductive load switch-off energy dissipation, single pulse Vbb = 12V, Tj,start = 150°C5), IL = 1.9 A, ZL = 66 mH, 0 Ω one channel: IL = 2.8 A, ZL = 66 mH, 0 Ω two parallel channels: IL = 4.4 A, ZL = 66 mH, 0 Ω four parallel channels: Vbb Vbb Values Unit 43 34 V V self-limited 60 A V Tj Tstg Ptot -40 ...+150 -55 ...+150 3.6 1.9 °C EAS 150 320 800 mJ VESD 1.0 kV -10 ... +16 ±2.0 ±5.0 V mA 16 44 35 K/W IL VLoad 4) dump W see diagrams on page 10 Electrostatic discharge capability (ESD) (Human Body Model) Input voltage (DC) Current through input pin (DC) Current through status pin (DC) VIN IIN IST see internal circuit diagram page 9 Thermal resistance junction - soldering point5),6) junction - ambient5) 2) 3) 4) 5) 6) each channel: one channel active: all channels active: Rthjs Rthja Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins, e.g. with a 150 Ω resistor in the GND connection and a 15 kΩ resistor in series with the status pin. A resistor for input protection is integrated. RI = internal resistance of the load dump test pulse generator VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839 Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb connection. PCB is vertical without blown air. See page 15 Soldering point: upper side of solder edge of device pin 15. See page 15 Semiconductor Group 3 2004-Mar-11 BTS712N1 Electrical Characteristics Parameter and Conditions, each of the four channels Symbol at Tj = 25 °C, Vbb = 12 V unless otherwise specified Load Switching Capabilities and Characteristics On-state resistance (Vbb to OUT) each channel, Tj = 25°C: RON IL = 1.8 A Tj = 150°C: two parallel channels, Tj = 25°C: four parallel channels, Tj = 25°C: Nominal load current one channel active: two parallel channels active: four parallel channels active: 5) Device on PCB , Ta = 85°C, Tj ≤ 150°C Output current while GND disconnected or pulled up; Vbb = 30 V, VIN = 0, see diagram page 10 Turn-on time to 90% VOUT: Turn-off time to 10% VOUT: RL = 12 Ω, Tj =-40...+150°C Slew rate on 10 to 30% VOUT, RL = 12 Ω, Tj =-40...+150°C: Slew rate off 70 to 40% VOUT, RL = 12 Ω, Tj =-40...+150°C: Operating Parameters Operating voltage7) Undervoltage shutdown Undervoltage restart Tj =-40...+150°C: Tj =-40...+150°C: Tj =-40...+25°C: Tj =+150°C: Undervoltage restart of charge pump see diagram page 14 Tj =-40...+150°C: Undervoltage hysteresis ∆Vbb(under) = Vbb(u rst) - Vbb(under) Overvoltage shutdown Tj =-40...+150°C: Overvoltage restart Tj =-40...+150°C: Overvoltage hysteresis Tj =-40...+150°C: 8 ) Overvoltage protection Tj =-40...+150°C: I bb = 40 mA 7) 8) Values min typ max -- Unit mΩ 165 320 200 400 1.7 2.6 4.1 83 42 1.9 2.8 4.4 100 50 -- A -- -- 10 mA ton toff 80 80 200 200 400 400 µs dV/dton 0.1 -- 1 V/µs -dV/dtoff 0.1 -- 1 V/µs Vbb(on) Vbb(under) Vbb(u rst) 5.0 3.5 -- ---- V V V Vbb(ucp) -- 5.6 34 5.0 5.0 7.0 7.0 ∆Vbb(under) -- 0.2 -- V Vbb(over) Vbb(o rst) ∆Vbb(over) Vbb(AZ) 34 33 -42 --0.5 47 43 ---- V V V V IL(NOM) IL(GNDhigh) V At supply voltage increase up to Vbb = 5.6 V typ without charge pump, VOUT ≈Vbb - 2 V see also VON(CL) in circuit diagram on page 9. Semiconductor Group 4 2004-Mar-11 BTS712N1 Parameter and Conditions, each of the four channels Symbol at Tj = 25 °C, Vbb = 12 V unless otherwise specified Standby current, all channels off Tj =25°C: Ibb(off) Tj =150°C: VIN = 0 9) Operating current , VIN = 5V, Tj =-40...+150°C IGND = IGND1/2 + IGND3/4, one channel on: IGND four channels on: Values min typ max Unit --- 180 160 300 300 µA --- 0.35 1.2 0.8 2.8 mA Protection Functions10) Initial peak short circuit current limit, (see timing diagrams, page 12) each channel, Tj =-40°C: IL(SCp) 5.5 9.5 13 4.5 7.5 11 Tj =25°C: 2.5 4.5 7 Tj =+150°C: two parallel channels twice the current of one channel four parallel channels four times the current of one channel Repetitive short circuit current limit, Tj = Tjt each channel IL(SCr) -4 --4 -two parallel channels -4 -four parallel channels A A (see timing diagrams, page 12) Initial short circuit shutdown time Tj,start =-40°C: toff(SC) Tj,start = 25°C: --- 5.5 4 --- ms -- 47 -- V 150 -- -10 --- °C K --- -610 32 -- V mV -2 30 3 -4 µA V (see page 11 and timing diagrams on page 12) Output clamp (inductive load switch off)11) at VON(CL) = Vbb - VOUT Thermal overload trip temperature Thermal hysteresis VON(CL) Tjt ∆Tjt Reverse Battery Reverse battery voltage 12) Drain-source diode voltage (Vout > Vbb) IL = - 1.9 A, Tj = +150°C Diagnostic Characteristics Open load detection current Open load detection voltage -Vbb -VON IL(off) Tj =-40..+150°C: VOUT(OL) 9) Add IST, if IST > 0 Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. 11) If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest VON(CL) 12) Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature protection is not active during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and circuit page 9). 10) Semiconductor Group 5 2004-Mar-11 BTS712N1 Parameter and Conditions, each of the four channels Symbol Values min typ max RI 2.5 3.5 6 kΩ VIN(T+) 1.7 -- 3.5 V VIN(T-) 1.5 -- -- V ∆ VIN(T) VIN = 0.4 V: IIN(off) -1 0.5 -- -50 V µA VIN = 5 V: IIN(on) 20 50 90 µA td(ST OL3) -- 220 -- µs Status output (open drain) Zener limit voltage Tj =-40...+150°C, IST = +1.6 mA: VST(high) ST low voltage Tj =-40...+25°C, IST = +1.6 mA: VST(low) Tj = +150°C, IST = +1.6 mA: 5.4 --- 6.1 --- -0.4 0.6 V at Tj = 25 °C, Vbb = 12 V unless otherwise specified Input and Status Feedback13) Input resistance (see circuit page 9) Unit Tj =-40..+150°C: Input turn-on threshold voltage Tj =-40..+150°C: Input turn-off threshold voltage Tj =-40..+150°C: Input threshold hysteresis Off state input current Tj =-40..+150°C: On state input current Tj =-40..+150°C: Delay time for status with open load (see timing diagrams, page 13) 13) If ground resistors RGND are used, add the voltage drop across these resistors. Semiconductor Group 6 2004-Mar-11 BTS712N1 Truth Table Channel 1 and 2 Channel 3 and 4 (equivalent to channel 1 and 2) Chip 1 Chip 2 Normal operation Open load Channel 1 (3) Channel 2 (4) Short circuit to Vbb Channel 1 (3) Channel 2 (4) Overtemperature both channel Channel 1 (3) Channel 2 (4) Undervoltage/ Overvoltage L = "Low" Level H = "High" Level IN1 IN3 IN2 IN4 OUT1 OUT3 OUT2 OUT4 L L H H L L H L H L H L H X L L H H Z Z H L H L H L H X L H X L L H L L H L H X L H X H H H Z Z H L H X L H X L X H L H X X X L L H L H X X X L H X L H X L L L L L X X L H H H L L L X X L L L ST1/2 ST3/4 ST1/2 ST3/4 BTS 711L1 BTS 712N1 H H H H H H H H L H H H(L14)) H L H(L14)) H L L15) H H(L16)) L15) H H(L16)) H L L H L H L H L H H L15) H H L15) H H H L L H L H L H X = don't care Z = high impedance, potential depends on external circuit Status signal valid after the time delay shown in the timing diagrams Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4 have to be configured as a 'Wired OR' function with a single pull-up resistor. 14) With additional external pull up resistor An external short of output to Vbb in the off state causes an internal current from output to ground. If RGND is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious. 16) Low resistance to V may be detected by no-load-detection bb 15) Semiconductor Group 7 2004-Mar-11 BTS712N1 Terms V Ibb bb I IN2 I ST1/2 V VON1 VON2 Leadframe I IN1 IN1 V IN2 VST1/2 3 5 4 V bb IN1 IN2 ST1/2 OUT1 PROFET Chip 1 OUT2 GND1/2 I L1 17 I L2 V 2 R 18 IGND1/2 V ON3 V ON4 Leadframe I IN3 I IN4 I ST3/4 V OUT1 IN3 V IN4 VST3/4 7 9 8 V bb IN3 IN4 ST3/4 OUT3 PROFET Chip 2 OUT4 GND3/4 R GND1/2 I L3 13 I L4 V 6 V OUT2 14 I GND3/4 OUT3 V OUT4 GND3/4 Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20 External RGND optional; two resistors RGND1/2 ,RGND3/4 = 150 Ω or a single resistor RGND = 75 Ω for reverse battery protection up to the max. operating voltage Semiconductor Group 8 2004-Mar-11 BTS712N1 Overvoltage protection of logic part Input circuit (ESD protection), IN1...4 GND1/2 or GND3/4 + V bb R IN I V RI IN Z2 IN ESD-ZD I I Logic I ST R ST GND V Z1 ESD zener diodes are not to be used as voltage clamp at DC conditions. Operation in this mode may result in a drift of the zener voltage (increase of up to 1 V). GND R GND Signal GND VZ1 = 6.1 V typ., VZ2 = 47 V typ., RI = 3.5 kΩ typ., RGND = 150 Ω Status output, ST1/2 or ST3/4 +5V R ST(ON) GND Reverse battery protection ST ± 5V R ST ESDZD IN - Vbb RI Logic ST ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 380 Ω at 1.6 mA, ESD zener diodes are not to be used as voltage clamp at DC conditions. Operation in this mode may result in a drift of the zener voltage (increase of up to 1 V). OUT Power Inverse Diode GND RGND Inductive and overvoltage output clamp, Power GND Signal GND OUT1...4 RL RGND = 150 Ω, RI = 3.5 kΩ typ, Temperature protection is not active during inverse current operation. +Vbb VZ Open-load detection, OUT1...4 V ON OFF-state diagnostic condition: VOUT > 3 V typ.; IN low OUT PROFET Power GND VON clamped to VON(CL) = 47 V typ. OFF I Logic unit L(OL) V OUT Open load detection Signal GND Semiconductor Group 9 2004-Mar-11 BTS712N1 Inductive load switch-off energy dissipation GND disconnect (channel 1/2 or 3/4) E bb E AS Ibb V bb Vbb IN1 IN OUT1 IN2 PROFET PROFET OUT2 ST = GND V V V IN1 IN2 ST ELoad Vbb OUT L ST GND ZL V GND { R EL ER L Any kind of load. In case of IN = high is VOUT ≈ VIN - VIN(T+). Due to VGND > 0, no VST = low signal available. Energy stored in load inductance: GND disconnect with GND pull up While demagnetizing load inductance, the energy dissipated in PROFET is (channel 1/2 or 3/4) 2 EL = 1/2·L·I L EAS= Ebb + EL - ER= ∫ VON(CL)·iL(t) dt, IN1 with an approximate solution for RL > 0 Ω: Vbb OUT1 V IN1 IN2 PROFET ST GND V IN2 OUT2 IL· L (V + |VOUT(CL)|) 2·RL bb ln (1+ |V IL·RL OUT(CL)| ) Maximum allowable load inductance for a single switch off (one channel)5) V GND V ST V bb EAS= L = f (IL ); Tj,start = 150°C, Vbb = 12 V, RL = 0 Ω L [mH] 1000 Any kind of load. If VGND > VIN - VIN(T+) device stays off Due to VGND > 0, no VST = low signal available. Vbb disconnect with energized inductive load IN1 Vbb IN2 PROFET ST GND 100 OUT1 high OUT2 10 V bb For an inductive load current up to the limit defined by EAS (max. ratings see page 3 and diagram on page 10) each switch is protected against loss of Vbb. Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load the whole load current flows through the GND connection. 1 1 1.5 2 2.5 3 IL [A] Semiconductor Group 10 2004-Mar-11 BTS712N1 Typ. on-state resistance Typ. ground pin operating current RON = f (Vbb,Tj ); IL = 1.8 A, IN = high IGND = f (Vbb,Tj ); VIN = high (one channel on) RON [mOhm] IGND [mA] 500 1.5 450 1.25 400 350 Tj = 150°C 1 85°C 0.75 25°C 0.5 300 250 200 150 Tj = -40°C 25°C 85°C 150°C -40°C 0.25 100 50 0 0 0 0 10 20 30 10 20 30 40 50 40 Vbb [V] Vbb [V] Typ. initial short circuit shutdown time Typ. standby current toff(SC) = f (Tj,start ); Vbb =12 V Ibb(off) = f (Tj ); Vbb = 9...34 V, IN1...4 = low toff(SC) [msec] 6 Ibb(off) [µA] 250 5 200 4 150 3 100 2 50 0 -50 1 0 50 100 150 0 -50 200 Tj [°C] 0 50 100 150 200 Tj,start [°C] Ibb(off) includes four times the current IL(off) of the open load detection current sources. Semiconductor Group 11 2004-Mar-11 BTS712N1 Timing diagrams Timing diagrams are shown for chip 1 (channel 1/2). For chip 2 (channel 3/4) the diagrams are valid too. The channels 1 and 2, respectively 3 and 4, are symmetric and consequently the diagrams are valid for each channel as well as for permuted channels Figure 2b: Switching an inductive load, Figure 1a: Vbb turn on: IN1 IN IN2 V bb ST V OUT1 V OUT V OUT2 I L ST open drain t t Figure 3a: Turn on into short circuit: shut down by overtemperature, restart by cooling Figure 2a: Switching a lamp: IN1 IN other channel: normal operation ST I L1 I V OUT L(SCp) I I L(SCr) L ST t off(SC) t t The initial peak current should be limited by the lamp and not by the initial short circuit current IL(SCp) = 7.5 A typ. of the device. Heating up of the chip may require several milliseconds, depending on external conditions (toff(SC) vs. Tj,start see page 11) Semiconductor Group 12 2004-Mar-11 BTS712N1 Figure 5a: Open load: detection in OFF-state, turn on/off to open load Figure 3b: Turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2) IN1 IN1/2 IN2 I +I L1 channel 2: normal operation L2 I L(SCp) VOUT1 I L(SCr) I L1 channel 1: open load t ST1/2 off(SC) t d(ST OL3) t d(ST OL3) ST t t td(ST,OL3) depends on external circuitry because of high impedance *) IL = 30 µA typ Figure 4a: Overtemperature: Reset if Tj