CYW43340XKUBG

The following document contains information on Cypress products. Although the document is marked with the name “Broadcom”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. Cypress continues to support existing part numbers. To order these products, please use only the Cypress Ordering Part Number listed in the table. Broadcom Ordering Part Number BCM43340XKUBGT BCM43340HKUBG BCM43340XKUBG BCM43340HKUBGT Cypress Ordering Part Number CYW43340XKUBGT CYW43340HKUBG CYW43340XKUBG CYW43340HKUBGT Please visit our website at www.cypress.com or contact your local sales office for additional information about Cypress products and services. Cypress is for true innovators – in companies both large and small. Our customers are smart, aggressive, out-of-the-box thinkers who design and develop game-changing products that revolutionize their industries or create new industries with products and solutions that nobody ever thought of before. Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. Cypress’s programmable systems-on-chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn more, go to www.cypress.com. Cypress Semiconductor Corporation Document Number: 002-14943 Rev. *I 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised October 18, 2016 Data Sheet BCM43340 Single-Chip, Dual-Band (2.4 GHz/5 GHz) IEEE 802.11 a/b/ g/n MAC/Baseband/Radio with Integrated Bluetooth 4.0 and FM Receiver GE NE R AL DE S C RI PT ION F E A T U RE S ® The Broadcom BCM43340 single–chip quad–radio device provides the highest level of integration for a mobile or handheld wireless system, with integrated dual band (2.4 GHz / 5 GHz) IEEE 802.11 a/b/g and single–stream IEEE 802.11n MAC/baseband/radio, Bluetooth 4.0, and FM radio receiver. The BCM43340 includes integrated power amplifiers and LNAs for the 2.4 GHz and 5 GHz WLAN bands, and an integrated 2.4 GHz T/R switch. This greatly reduces the external part count, PCB footprint, and cost of the solution. The BCM43340 implements the highly sophisticated Enhanced Collaborative Coexistence algorithms and hardware mechanisms, allowing for an extremely collaborative Bluetooth coexistence scheme along with coexistence support for external radios (such as cellular and LTE, GPS, WiMAX, and Ultra–Wideband) and a single shared 2.4 GHz antenna for Bluetooth and WLAN. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. Using advanced design techniques and process technology to reduce active and idle power, the BCM43340 is designed to address the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which simplifies the system power topology and allows for operation directly from a mobile platform battery while maximizing battery life. For the WLAN section, two host interface options are included: an SDIO v2.0 interface (including gSPI) and a High-Speed Inter-Chip (HSIC) interface (a USB 2.0 derivative for short-distance on-board connections). An independent, high-speed UART is provided for the Bluetooth host interface. Figure 1: Functional Block Diagram VIO WLAN Host I/F VBAT WL_REG_ON 5 GHz WLAN Tx WL_IRQ SDIO*/SPI 5 GHz WLAN Rx FEM or T/R Switch HSIC CLK_REQ BT_REG_ON Bluetooth Host I/F BCM43340 2.4 GHz WLAN + Bluetooth Tx/Rx CBF 2 PCM/I S BT_DEV_WAKE BT_HOST_WAKE UART FM Rx Host I/F FM Rx I2S Stereo Analog Out 43340-DS109-R 5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 January 28, 2015 BCM43340 Data Sheet Revision History F E A T U RE S F E A T U RE S IEEE 802.11x Key Features • Dual–band 2.4 GHz and 5 GHz IEEE 802.11 a/b/g/n • Single–stream IEEE 802.11n support for 20 MHz and 40 MHz channels provides PHY layer rates up to 150 Mbps for typical upper– layer throughput in excess of 90 Mbps. • Supports the IEEE 802.11n STBC (space– time block coding) RX and LDPC (low– density parity check) TX options for improved range and power efficiency. • Supports a single 2.4 GHz antenna shared between WLAN and Bluetooth. • Shared Bluetooth and 2.4 GHz WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN. • Internal fractional nPLL allows support for a wide range of reference clock frequencies • Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co–located wireless technologies such as GPS, WiMAX, or UWB • Supports standard SDIO v2.0 and gSPI (48 MHz) host interfaces. • Alternative host interface supports HSIC v1.0 (short–distance USB device) • Integrated ARM® Cortex–M3™ processor and on–chip memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. On–chip memory includes 512 KB SRAM and 640 KB ROM. • OneDriver™ software architecture for easy migration from existing embedded WLAN and Bluetooth devices as well as future devices. Bluetooth and FM Key Features • Complies with Bluetooth Core Specification Version 4.0 with provisions for supporting future specifications. • Bluetooth Class 1 or Class 2 transmitter operation • Supports extended Synchronous Connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets. • Adaptive Frequency Hopping (AFH) for reducing radio frequency interference • Interface support: Host Controller Interface (HCI) using a high-speed UART interface and PCM for audio data • The FM receiver unit supports HCI for communication. • Low power consumption improves battery life of handheld devices. • FM receiver: 76 MHz to 108 MHz FM bands; supports the European Radio Data Systems (RDS) and the North American Radio Broadcast Data System (RBDS) standards • Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound. • Automatic frequency detection for standard crystal and TCXO values Broadcom® January 28, 2015 • 43340-DS109-R General Features • Supports battery voltage range from 2.9V to 4.8V supplies with internal switching regulator. • Programmable dynamic power management • 3072-bit OTP for storing board parameters • Routable on low–cost 1x1 PCB stack–ups • 141-ball WLBGA package(5.67 mm × 4.47 mm, 0.4 mm pitch) • Security: – WPA™ and WPA2™ (Personal) support for powerful encryption and authentication – AES in WLAN hardware for faster data encryption and IEEE 802.11i compatibility – Reference WLAN subsystem provides Cisco® Compatible Extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0) – Reference WLAN subsystem provides Wi–Fi Protected Setup (WPS) • Worldwide regulatory support: Global products supported with worldwide homologated design BROADCOM CONFIDENTIAL Page 2 BCM43340 Data Sheet Revision History Revision History Revision Date Change Description 43340-DS109-R 01/28/15 43340-DS107-R 07/07/14 43340-DS107-R 04/07/14 43340-DS106-R 03/04/14 43340-DS105-R 02/14/14 43340-DS104-R 12/03/13 Updated: • Table 18: “WLBGA Signal Descriptions,” on page 85 Updated: • Figure 65: “WLBGA Keep-Out Areas for PCB Layout — Bottom View,” on page 177 Updated: • Table 28: “WLAN GPIO Functions and Strapping Options (Advance Information),” on page 144 • Title change (2.5 GHz to 2.4 GHz) for Figure 55 on page 169 Figure 39: “141-Bump BCM43340 WLBGA Ball Map (Bottom View),” on page 84 and Table 18: “WLBGA Signal Descriptions,” on page 85: Updated signal names for No Connect, VDDC, VDDIO, VSS, VSSC, and WRF_PA5G_VBAT_GND3P3 pins. Updated: • Section 26: “Ordering Information,” on page 194. Updated: • Proprietary protocols in “Standards Compliance” on page 21. • Table 24: “ESD Specifications,” on page 102. • Table 33: “WLAN 2.4 GHz Transmitter Performance Specifications,” on page 124. • Table 35: “WLAN 5 GHz Transmitter Performance Specifications,” on page 129. 43340-DS103-R 08/30/13 Broadcom® January 28, 2015 • 43340-DS109-R Removed ‘Preliminary’ from the document type. BROADCOM CONFIDENTIAL Page 3 BCM43340 Data Sheet Revision History Revision Date Change Description 43340-DS102-R 04/22/13 Updated: • Figure 1: “Functional Block Diagram,” on page 1. • AES feature description on page 5. • VBAT voltage range changed from 2.3–4.8V to 2.9–4.8V. • Figure 4: “Typical Power Topology,” on page 29. • “Link Control Layer” on page 51: substates. • Table 33: “Bluetooth Receiver RF Specifications,” on page 131. • Figure 52: “WLAN Port Locations (5 GHz),” on page 142. • Table 34: “Bluetooth Transmitter RF Specifications,” on page 135: Power control step. • Table 36: “BLE RF Specifications,” on page 136: Rx sense. • Table 37: “FM Receiver Specifications,” on page 137. • Table 39: “WLAN 2.4 GHz Receiver Performance Specifications,” on page 144. • Table 40: “WLAN 2.4 GHz Transmitter Performance Specifications,” on page 148. • Table 42: “WLAN 5 GHz Transmitter Performance Specifications,” on page 153. • Table 50: “Typical WLAN Power Consumption,” on page 162. 43340-DS101-R 12/21/12 43340–DS100-R 7/9/12 Updated: • HCI high-speed UART: H4+ mode no longer supported. • General Description on page 1. • “IEEE 802.11x Key Features” on page 5: shared Bluetooth and 2.4 GHz WLAN signal path. • Figure 11: “Startup Signaling Sequence,” on page 54. • “External Coexistence Interface” on page 80. • Table 26: “WLBGA and WLCSP Signal Descriptions,” on page 127. • Table 27: “WLAN GPIO Functions and Strapping Options (Advance Information),” on page 140. • Table 31: “I/O States,” on page 145 . • Table 32: “Absolute Maximum Ratings,” on page 149. • Table 36: “Bluetooth Receiver RF Specifications,” on page 154. • Table 37: “Bluetooth Transmitter RF Specifications,” on page 158. • Table 53: “Typical WLAN Power Consumption,” on page 185. • Table 54: “Bluetooth and FM Current Consumption,” on page 187. Initial Release Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 4 Broadcom Corporation 5300 California Avenue Irvine, CA 92617 © 2015 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom®, the pulse logo, OneDriver™, Smart Audio®, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. BCM43340 Data Sheet Table of Contents Table of Contents About This Document ................................................................................................................................ 15 Purpose and Audience .......................................................................................................................... 15 Acronyms and Abbreviations................................................................................................................. 15 Technical Support ...................................................................................................................................... 15 Section 1: Introduction ..................................................................................................... 16 Overview...................................................................................................................................................... 16 Features....................................................................................................................................................... 17 Standards Compliance............................................................................................................................... 18 Mobile Phone Usage Model ....................................................................................................................... 20 Section 2: Power Supplies and Power Management ..................................................... 21 Power Supply Topology............................................................................................................................. 21 BCM43340 PMU Features .................................................................................................................... 21 WLAN Power Management ........................................................................................................................ 23 PMU Sequencing ........................................................................................................................................ 24 Power-Off Shutdown .................................................................................................................................. 25 Power-Up/Power-Down/Reset Circuits..................................................................................................... 25 Section 3: Frequency References.................................................................................... 26 Crystal Interface and Clock Generation ................................................................................................... 26 TCXO............................................................................................................................................................ 27 Frequency Selection .................................................................................................................................. 29 External 32.768 kHz Low-Power Oscillator .............................................................................................. 30 Section 4: Bluetooth + FM Subsystem Overview ........................................................... 31 Features....................................................................................................................................................... 31 Bluetooth Radio.......................................................................................................................................... 33 Transmit ................................................................................................................................................ 33 Digital Modulator ................................................................................................................................... 33 Digital Demodulator and Bit Synchronizer............................................................................................. 33 Power Amplifier ..................................................................................................................................... 33 Receiver ................................................................................................................................................ 34 Digital Demodulator and Bit Synchronizer............................................................................................. 34 Receiver Signal Strength Indicator........................................................................................................ 34 Local Oscillator Generation ................................................................................................................... 34 Calibration ............................................................................................................................................. 34 Section 5: Bluetooth Baseband Core .............................................................................. 35 Bluetooth 4.0 Features............................................................................................................................... 35 Link Control Layer...................................................................................................................................... 36 Broadcom® January 28, 2015 • 43340-DS109-R Page 6 BROADCOM CONFIDENTIAL BCM43340 Data Sheet Table of Contents Test Mode Support ..................................................................................................................................... 36 Bluetooth Power Management Unit .......................................................................................................... 37 RF Power Management ........................................................................................................................ 37 Host Controller Power Management ..................................................................................................... 37 BBC Power Management...................................................................................................................... 39 FM Power Management ........................................................................................................................ 39 Wideband Speech ................................................................................................................................. 39 Packet Loss Concealment..................................................................................................................... 40 Audio Rate-Matching Algorithms........................................................................................................... 40 Codec Encoding .................................................................................................................................... 41 Multiple Simultaneous A2DP Audio Stream .......................................................................................... 41 FM Over Bluetooth ................................................................................................................................ 41 Burst Buffer Operation........................................................................................................................... 41 Adaptive Frequency Hopping.................................................................................................................... 41 Advanced Bluetooth/WLAN Coexistence................................................................................................. 42 Fast Connection (Interlaced Page and Inquiry Scans) ........................................................................... 42 Section 6: Microprocessor and Memory Unit for Bluetooth.......................................... 43 RAM, ROM, and Patch Memory ................................................................................................................. 43 Reset............................................................................................................................................................ 43 Section 7: Bluetooth Peripheral Transport Unit ............................................................. 44 PCM Interface.............................................................................................................................................. 44 Slot Mapping ......................................................................................................................................... 44 Frame Synchronization ......................................................................................................................... 44 Data Formatting..................................................................................................................................... 44 Wideband Speech Support ................................................................................................................... 45 Multiplexed Bluetooth and FM Over PCM ............................................................................................. 45 Burst PCM Mode ................................................................................................................................... 46 PCM Interface Timing............................................................................................................................ 46 Short Frame Sync, Master Mode ................................................................................................... 46 Short Frame Sync, Slave Mode ..................................................................................................... 47 Long Frame Sync, Master Mode.................................................................................................... 48 Long Frame Sync, Slave Mode...................................................................................................... 49 Short Frame Sync, Burst Mode...................................................................................................... 50 Long Frame Sync, Burst Mode ...................................................................................................... 51 UART Interface............................................................................................................................................ 52 I2S Interface................................................................................................................................................. 54 I2S Timing.............................................................................................................................................. 55 Broadcom® January 28, 2015 • 43340-DS109-R Page 7 BROADCOM CONFIDENTIAL BCM43340 Data Sheet Table of Contents Section 8: FM Receiver Subsystem ................................................................................. 58 FM Radio ..................................................................................................................................................... 58 Digital FM Audio Interfaces ....................................................................................................................... 58 Analog FM Audio Interfaces ...................................................................................................................... 58 FM Over Bluetooth ..................................................................................................................................... 58 eSCO............................................................................................................................................................ 59 Wideband Speech Link .............................................................................................................................. 59 A2DP ............................................................................................................................................................ 59 Autotune and Search Algorithms ............................................................................................................. 59 Audio Features ........................................................................................................................................... 60 RDS/RBDS................................................................................................................................................... 62 Section 9: WLAN Global Functions ................................................................................. 63 WLAN CPU and Memory Subsystem........................................................................................................ 63 One-Time Programmable Memory ............................................................................................................ 63 GPIO Interface............................................................................................................................................. 64 External Coexistence Interface ................................................................................................................. 64 UART Interface............................................................................................................................................ 65 JTAG Interface ............................................................................................................................................ 65 Section 10: WLAN Host Interfaces................................................................................... 66 SDIO v2.0..................................................................................................................................................... 66 SDIO Pin Descriptions........................................................................................................................... 66 Generic SPI Mode ....................................................................................................................................... 68 SPI Protocol .......................................................................................................................................... 69 Command Structure ....................................................................................................................... 70 Write............................................................................................................................................... 70 Write/Read ..................................................................................................................................... 70 Read............................................................................................................................................... 70 Status ............................................................................................................................................. 71 gSPI Host-Device Handshake............................................................................................................... 73 Boot-Up Sequence ................................................................................................................................ 73 HSIC Interface ............................................................................................................................................. 76 Section 11: Wireless LAN MAC and PHY ........................................................................ 77 MAC Features ............................................................................................................................................. 77 MAC Description ................................................................................................................................... 77 PSM ............................................................................................................................................... 78 WEP ............................................................................................................................................... 79 TXE ................................................................................................................................................ 79 RXE................................................................................................................................................ 79 Broadcom® January 28, 2015 • 43340-DS109-R Page 8 BROADCOM CONFIDENTIAL BCM43340 Data Sheet Table of Contents IFS.................................................................................................................................................. 80 TSF ................................................................................................................................................ 80 NAV................................................................................................................................................ 80 MAC-PHY Interface........................................................................................................................ 80 WLAN PHY Description.............................................................................................................................. 81 PHY Features........................................................................................................................................ 81 Section 12: WLAN Radio Subsystem .............................................................................. 83 Receiver Path.............................................................................................................................................. 83 Transmit Path.............................................................................................................................................. 83 Calibration................................................................................................................................................... 83 Section 13: Pinout and Signal Descriptions ................................................................... 84 Signal Assignments ................................................................................................................................... 84 Signal Descriptions .................................................................................................................................... 85 WLAN GPIO Signals and Strapping Options ........................................................................................ 93 CIS Select Options ................................................................................................................................ 94 I/O States ..................................................................................................................................................... 95 Section 14: DC Characteristics ........................................................................................ 98 Absolute Maximum Ratings ...................................................................................................................... 98 Environmental Ratings .............................................................................................................................. 99 Electrostatic Discharge Specifications .................................................................................................... 99 Recommended Operating Conditions and DC Characteristics ........................................................... 100 Section 15: Bluetooth RF Specifications ...................................................................... 102 Section 16: FM Receiver Specifications........................................................................ 109 Section 17: WLAN RF Specifications ............................................................................ 114 Introduction............................................................................................................................................... 114 2.4 GHz Band General RF Specifications............................................................................................... 115 WLAN 2.4 GHz Receiver Performance Specifications .......................................................................... 116 WLAN 2.4 GHz Transmitter Performance Specifications ..................................................................... 120 WLAN 5 GHz Receiver Performance Specifications ............................................................................. 122 WLAN 5 GHz Transmitter Performance Specifications ........................................................................ 125 General Spurious Emissions Specifications ......................................................................................... 126 Section 18: Internal Regulator Electrical Specifications ............................................. 127 Core Buck Switching Regulator.............................................................................................................. 127 3.3V LDO (LDO3P3) .................................................................................................................................. 129 2.5V LDO (LDO2P5) .................................................................................................................................. 130 HSICDVDD LDO ........................................................................................................................................ 131 CLDO ......................................................................................................................................................... 132 Broadcom® January 28, 2015 • 43340-DS109-R Page 9 BROADCOM CONFIDENTIAL BCM43340 Data Sheet Table of Contents LNLDO ....................................................................................................................................................... 133 Section 19: System Power Consumption...................................................................... 134 WLAN Current Consumption................................................................................................................... 134 Bluetooth, BLE, and FM Current Consumption..................................................................................... 135 Section 20: Interface Timing and AC Characteristics .................................................. 136 SDIO/gSPI Timing ..................................................................................................................................... 136 SDIO Default Mode Timing ................................................................................................................. 136 SDIO High-Speed Mode Timing.......................................................................................................... 138 gSPI Signal Timing.............................................................................................................................. 139 HSIC Interface Specifications.................................................................................................................. 140 JTAG Timing ............................................................................................................................................. 141 Section 21: Power-Up Sequence and Timing ............................................................... 142 Sequencing of Reset and Regulator Control Signals ........................................................................... 142 Description of Control Signals ............................................................................................................. 142 Control Signal Timing Diagrams.......................................................................................................... 143 Section 22: Package Information ................................................................................... 145 Package Thermal Characteristics ........................................................................................................... 145 Junction Temperature Estimation and PSIJT Versus THETAJC ........................................................... 145 Environmental Characteristics................................................................................................................ 145 Section 23: Mechanical Information .............................................................................. 146 Section 24: Ordering Information .................................................................................. 148 Broadcom® January 28, 2015 • 43340-DS109-R Page 10 BROADCOM CONFIDENTIAL BCM43340 Data Sheet List of Figures List of Figures Figure 1: Functional Block Diagram................................................................................................................... 1 Figure 2: BCM43340 Block Diagram ............................................................................................................... 16 Figure 3: Mobile Phone System Block Diagram .............................................................................................. 20 Figure 4: Typical Power Topology ................................................................................................................... 22 Figure 5: Recommended Oscillator Configuration ........................................................................................... 26 Figure 6: Recommended Circuit to Use with an External Dedicated TCXO .................................................... 27 Figure 7: Recommended Circuit to Use with an External Shared TCXO......................................................... 27 Figure 8: Startup Signaling Sequence ............................................................................................................. 38 Figure 9: CVSD Decoder Output Waveform Without PLC ............................................................................... 40 Figure 10: CVSD Decoder Output Waveform After Applying PLC................................................................... 40 Figure 11: Functional Multiplex Data Diagram................................................................................................. 45 Figure 12: PCM Timing Diagram (Short Frame Sync, Master Mode) .............................................................. 46 Figure 13: PCM Timing Diagram (Short Frame Sync, Slave Mode) ................................................................ 47 Figure 14: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 48 Figure 15: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 49 Figure 16: PCM Burst Mode Timing (Receive Only, Short Frame Sync) ......................................................... 50 Figure 17: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 51 Figure 18: UART Timing .................................................................................................................................. 53 Figure 19: I2S Transmitter Timing .................................................................................................................... 56 Figure 20: I2S Receiver Timing........................................................................................................................ 57 Figure 21: Example Blend/Switch Usage......................................................................................................... 60 Figure 22: Example Blend/Switch Separation.................................................................................................. 61 Figure 23: Example Soft Mute Characteristic .................................................................................................. 61 Figure 24: LTE Coexistence Interface ............................................................................................................. 64 Figure 25: Signal Connections to SDIO Host (SD 4-Bit Mode) ........................................................................ 67 Figure 26: Signal Connections to SDIO Host (SD 1-Bit Mode) ........................................................................ 67 Figure 27: SDIO Pull-Up Requirements........................................................................................................... 67 Figure 28: Signal Connections to SDIO Host (gSPI Mode) ............................................................................. 68 Figure 29: gSPI Write Protocol ........................................................................................................................ 69 Figure 30: gSPI Read Protocol ........................................................................................................................ 69 Figure 31: gSPI Command Structure............................................................................................................... 70 Figure 32: gSPI Signal Timing Without Status (32-bit big endian shown) ....................................................... 71 Figure 33: gSPI Signal Timing with Status (Response Delay = 0) (32-bit big endian shown) ......................... 72 Figure 34: WLAN Boot-Up Sequence .............................................................................................................. 75 Figure 35: HSIC Device Block Diagram........................................................................................................... 76 Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 11 BCM43340 Data Sheet List of Figures Figure 36: WLAN MAC Architecture ................................................................................................................ 78 Figure 37: WLAN PHY Block Diagram............................................................................................................. 82 Figure 38: STBC Implementation in the Receive Path .................................................................................... 82 Figure 39: 141-Bump BCM43340 WLBGA Ball Map (Bottom View)................................................................ 84 Figure 40: RF Port Location for Bluetooth Testing......................................................................................... 102 Figure 41: WLAN Port Locations (5 GHz)...................................................................................................... 114 Figure 42: WLAN Port Locations (2.4 GHz)................................................................................................... 114 Figure 43: SDIO Bus Timing (Default Mode) ................................................................................................. 136 Figure 44: SDIO Bus Timing (High-Speed Mode).......................................................................................... 138 Figure 45: gSPI Timing .................................................................................................................................. 139 Figure 46: WLAN = ON, Bluetooth = ON ....................................................................................................... 143 Figure 47: WLAN = OFF, Bluetooth = OFF.................................................................................................... 143 Figure 48: WLAN = ON, Bluetooth = OFF ..................................................................................................... 144 Figure 49: WLAN = OFF, Bluetooth = ON ..................................................................................................... 144 Figure 50: 141-Ball WLBGA Package Mechanical Information ..................................................................... 146 Figure 51: WLBGA Keep-Out Areas for PCB Layout—Bottom View ............................................................ 147 Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 12 BCM43340 Data Sheet List of Tables List of Tables Table 1: Power-Up/Power-Down/Reset Control Signals.................................................................................. 25 Table 2: Crystal Oscillator and External Clock – Requirements and Performance.......................................... 28 Table 3: External 32.768 kHz Sleep Clock Specifications ............................................................................... 30 Table 4: Power Control Pin Description ........................................................................................................... 37 Table 5: PCM Interface Timing Specifications (Short Frame Sync, Master Mode).......................................... 46 Table 6: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)............................................ 47 Table 7: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) .......................................... 48 Table 8: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) ............................................ 49 Table 9: PCM Burst Mode (Receive Only, Short Frame Sync) ........................................................................ 50 Table 10: PCM Burst Mode (Receive Only, Long Frame Sync) ...................................................................... 51 Table 11: Example of Common Baud Rates.................................................................................................... 52 Table 12: UART Timing Specifications ............................................................................................................ 53 Table 13: Timing for I2S Transmitters and Receivers ...................................................................................... 55 Table 14: External Coexistence Interface ........................................................................................................ 64 Table 15: SDIO Pin Description ....................................................................................................................... 66 Table 16: gSPI Status Field Details ................................................................................................................. 72 Table 17: gSPI Registers ................................................................................................................................. 73 Table 18: WLBGA Signal Descriptions ............................................................................................................ 85 Table 19: WLAN GPIO Functions and Strapping Options (Advance Information) ........................................... 93 Table 20: CIS Select ........................................................................................................................................ 94 Table 21: I/O States ......................................................................................................................................... 95 Table 22: Absolute Maximum Ratings ............................................................................................................. 98 Table 23: Environmental Ratings ..................................................................................................................... 99 Table 24: ESD Specifications .......................................................................................................................... 99 Table 25: Recommended Operating Conditions and DC Characteristics ...................................................... 100 Table 26: Bluetooth Receiver RF Specifications............................................................................................ 103 Table 27: Bluetooth Transmitter RF Specifications........................................................................................ 107 Table 28: Local Oscillator Performance......................................................................................................... 108 Table 29: BLE RF Specifications ................................................................................................................... 108 Table 30: FM Receiver Specifications ........................................................................................................... 109 Table 31: 2.4 GHz Band General RF Specifications...................................................................................... 115 Table 32: WLAN 2.4 GHz Receiver Performance Specifications .................................................................. 116 Table 33: WLAN 2.4 GHz Transmitter Performance Specifications .............................................................. 120 Table 34: WLAN 5 GHz Receiver Performance Specifications ..................................................................... 122 Table 35: WLAN 5 GHz Transmitter Performance Specifications ................................................................. 125 Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 13 BCM43340 Data Sheet List of Tables Table 36: General Spurious Emissions Specifications .................................................................................. 126 Table 37: Core Buck Switching Regulator (CBUCK) Specifications .............................................................. 127 Table 38: LDO3P3 Specifications .................................................................................................................. 129 Table 39: LDO2P5 Specifications .................................................................................................................. 130 Table 40: HISCDVDD LDO Specifications..................................................................................................... 131 Table 41: CLDO Specifications ...................................................................................................................... 132 Table 42: LNLDO Specifications .................................................................................................................... 133 Table 43: Typical WLAN Power Consumption ............................................................................................... 134 Table 44: Bluetooth and FM Current Consumption ....................................................................................... 135 Table 45: SDIO Bus Timing Parameters (Default Mode) ............................................................................... 136 Table 46: SDIO Bus Timing Parameters (High-Speed Mode) ....................................................................... 138 Table 47: gSPI Timing Parameters ................................................................................................................ 139 Table 48: HSIC Timing Parameters ............................................................................................................... 140 Table 49: JTAG Timing Characteristics ......................................................................................................... 141 Table 50: Package Thermal Characteristics .................................................................................................. 145 Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 14 About This Document BCM43340 Data Sheet About This Document Purpose and Audience This document provides details of the functional, operational, and electrical characteristics of the Broadcom® BCM43340. It is intended for hardware design, application, and OEM engineers. Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php. Technical Support Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering support representative. In addition, Broadcom provides other product support through its Downloads & Support site (http://www.broadcom.com/support/). Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 15 Introduction BCM43340 Data Sheet Se c t i o n 1 : I n t ro d u c t i o n Overview The Broadcom® BCM43340 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.1 a/b/g/n MAC/baseband/radio, Bluetooth 4.0, and FM RX. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 shows the interconnect of all the major physical blocks in the BCM43340 and their associated external interfaces, which are described in greater detail in the following sections. Figure 2: BCM43340 Block Diagram PMU Controller FLL Analog PMU Clk rst JTAG From To WLAN WLAN BT/FM BT BT CLB WLAN PMU XTAL/Radio/Pads etc BT GCI BT LTE LTE AXI2APB Port Control To WLAN From WLAN UART I2S PCM RAM SoCSRAM ROM RAM512KB ROM640KB ARMCM3 ARMCM3 AHB Bridge Registers RAM ROM DMA JTAG Master AHB Bus Matrix ARM CM0 WLAN Master Slave RX/TX BLE Timers SWP DIG WD AHB2APB LCU GPIO APU WLAN BT Access AXI2AHB AXI Backplane SDIOD USB20D HSIC AHB2AXI To GCI CLB Chip To CLB Common UPI DOT11MAC (D11) Shared LNA Control BlueRF Pause To CLB 1x1 11N PHY Modem FM Receiver 2.4 GHz / 5 GHz Dualband Radio BT RF Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 16 Features BCM43340 Data Sheet Features The BCM43340 supports the following WLAN, Bluetooth, and FM features: • IEEE 802.11a/b/g/n dual-band radio with internal Power Amplifiers, LNAs, and T/R switches • Bluetooth v4.0 with integrated Class 1 PA • Concurrent Bluetooth, FM (RX) RDS/RBDS, and WLAN operation • On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality • Single- and dual-antenna support – Single antenna with shared LNA – Simultaneous BT/WLAN receive with single antenna • WLAN host interface options: – SDIO v2.0, including default and high-speed timing. – gSPI—up to 48 MHz clock rate – HSIC (USB device interface for short distance on-board applications) • BT host digital interface (can be used concurrently with above interfaces): – UART (up to 4 Mbps) • ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receives • I2S/PCM for FM/BT audio, HCI for FM block control • HCI high-speed UART (H4, H5) transport support • Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air coding, both through I2S and PCM interface) • Bluetooth SmartAudio® technology improves voice and music quality to headsets • Bluetooth low power inquiry and page scan • Bluetooth Low Energy (BLE) support • Bluetooth Packet Loss Concealment (PLC) • Bluetooth Wideband Speech (WBS) • FM advanced internal antenna support • FM auto search/tuning functions • FM multiple audio routing options: I2S, PCM, eSCO, A2DP • FM mono-stereo blend and switch, and soft mute support • FM audio pause detect support • Audio rate-matching algorithms • Multiple simultaneous A2DP audio stream • FM over Bluetooth operation and on-chip stereo headset emulation Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 17 Standards Compliance BCM43340 Data Sheet Standards Compliance The BCM43340 supports the following standards: • Bluetooth 4.0 (including Bluetooth Low Energy) • 76 MHz to 108 MHz FM bands (US, Europe, and Japan) • IEEE 802.11n—Handheld Device Class (Section 11) • IEEE 802.11a • IEEE 802.11b • IEEE 802.11g • IEEE 802.11d • IEEE 802.11h • IEEE 802.11i The BCM43340 will support the following future drafts/standards: • IEEE 802.11r—Fast Roaming (between APs) • IEEE 802.11k—Resource Management • IEEE 802.11w—Secure Management Frames • IEEE 802.11 Extensions: – IEEE 802.11e QoS Enhancements (as per the WMM® specification is already supported) – IEEE 802.11h 5 GHz Extensions – IEEE 802.11i MAC Enhancements – IEEE 802.11r Fast Roaming Support – IEEE 802.11k Radio Resource Measurement The BCM43340 supports the following security features and proprietary protocols: • Security: – WEP – WPA™ Personal – WPA2™ Personal – WMM – WMM-PS (U-APSD) – WMM-SA – WAPI – AES (Hardware Accelerator) – TKIP (host-computed) – CKIP (SW Support) Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 18 Standards Compliance BCM43340 Data Sheet • Proprietary Protocols: – CCXv2 – CCXv3 – CCXv4 – CCXv5 • IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 19 Mobile Phone Usage Model BCM43340 Data Sheet Mobile Phone Usage Model The BCM43340 incorporates a number of unique features to simplify integration into mobile phone platforms. Its flexible PCM and UART interfaces enable it to transparently connect with the existing circuits. In addition, the TCXO and LPO inputs allow the use of existing handset features to further minimize the size, power, and cost of the complete system. • The PCM interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing to single or multiple external codec devices. • The UART interface supports hardware flow control with tight integration to power control sideband signaling to support the lowest power operation. • The TCXO interface accommodates any of the typical reference frequencies used by cell phones. • FM digital interfaces can use either I2S, PCM, or stereo analog output (an analog FM receiver interface is available for legacy systems.) • The highly linear design of the radio transceiver ensures that the device has the lowest spurious emissions output regardless of the state of operation. It has been fully characterized in the global cellular bands. • The transceiver design has excellent blocking (eliminating desensitization of the Bluetooth receiver) and intermodulation performance (distortion of the transmitted signal caused by the mixing of the cellular and Bluetooth transmissions) in the presence of a any cellular transmission (GSM®, GPRS, CDMA, WCDMA, or iDEN). Minimal external filtering is required for integration inside the handset. The BCM43340 is designed to provide direct interface with new and existing handset designs as shown in Figure 3. Figure 3: Mobile Phone System Block Diagram VIO WLAN Host I/F VBAT WL_REG_ON 5 GHz WLAN Tx WL_IRQ SDIO*/SPI 5 GHz WLAN Rx FEM or T/R Switch HSIC CLK_REQ BT_REG_ON Bluetooth Host I/F BCM43340 2.4 GHz WLAN + Bluetooth Tx/Rx CBF 2 PCM/I S BT_DEV_WAKE BT_HOST_WAKE UART FM Rx Host I/F FM Rx I2 S Stereo Analog Out Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 20 Power Supplies and Power Management BCM43340 Data Sheet Section 2: Power Supplies and Power Management Power Supply Topology One Buck regulator, multiple LDO regulators, and a Power Management Unit (PMU) are integrated into the BCM43340. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth, WLAN, and FM in embedded designs. A single VBAT (2.9–4.8V) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the BCM43340. Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic demands of the digital baseband. The BCM43340 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNDLO regulators. When in this state, LPLDO1 and LPLDO2 (which are low-power linear regulators that are supplied by the system VIO supply) provide the BCM43340 with all the voltages it requires, further reducing leakage currents. BCM43340 PMU Features • VBAT to 1.35Vout (372 mA maximum) Core-Buck (CBUCK) switching regulator • VBAT to 3.3Vout (450 mA maximum) LDO3P3 (external-capacitor) • VBAT to 2.5Vout (70 mA maximum) LDO2P5 (external-capacitor) • 1.35V to 1.2Vout (100 mA maximum) LNLDO (external-capacitor) • 1.35V to 1.2Vout (150 mA maximum) CLDO (external-capacitor) • 1.35V to 1.2Vout (80 mA maximum) HSICDVDD LDO (external-capacitor) • Additional internal LDOs (not externally accessible) Figure 4 on page 22 shows the regulators and a typical power topology. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 21 Power Supply Topology BCM43340 Data Sheet Figure 4: Typical Power Topology VIO 1.8–3.3V VDDIO (sdio/spi, uart, coex, gpio, jtag, bt-pcm, bt-uart LDO2P5 Max. 70 mA 2.5V VBAT 2.9–4.8V Shaded areas are internal to the BCM43340. BT Class 1 PA VDDIO_RF for RF Switches LDO3P3 Max. 450 mA 3.3V OTP (3.3V) iPA, iPAD Core Buck Regulator Max. 372 mA 1.35V WLBGA conĮŐƵƌĂƟŽŶ shown. WL_REG_ON Internal LNLDO WL RF – AFE Internal LNLDO WL RF – TX Internal LNLDO WL RF – VCO, LOGEN Internal LNLDO BT_REG_ON LNLDO Max 100 mA 1.2V WL RF – LNA ^ĞĐƟŽŶ ^ĞŶƐŝƟǀĞ to Power Supply Noise WL RF – Rx, Rcal FM LNA, Mixer XO WL RF – Synth/RF PLL WL RF – BG BT RF VIO 1.8–3.3V Internal LPLDO1 1.2V Internal LNLDO HSIC-DVDD/SDIO Internal LNLDO HSIC-AVDD (DFLL) WL OTP (1.2V) CLDO Max 150 mA 1.2V Internal LPLDO2 Broadcom® January 28, 2015 • 43340-DS109-R WL BB PLL WL Digital and Mem BT Digital and Mem Always On/State Ret. Island CLPO/Ext. LPO Buīer Loads Not ^ĞŶƐŝƟǀĞ to Power Supply Noise Page 22 BROADCOM CONFIDENTIAL WLAN Power Management BCM43340 Data Sheet WLAN Power Management The BCM43340 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM43340 integrated RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the BCM43340 includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the BCM43340 into various power management states appropriate to the current environment and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power up sequences are fully programmable. Configurable, freerunning counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. The BCM43340 WLAN power states are described as follows: • Active mode— All WLAN blocks in the BCM43340 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. • Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the BCM43340 remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. • Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. Logic states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a host resume through the HSIC or SDIO bus, logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW re-initialization. • Power-down mode—The BCM43340 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 23 PMU Sequencing BCM43340 Data Sheet PMU Sequencing The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Resource requests may come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that contains 0 when the resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. During each clock cycle, the PMU sequencer performs the following actions: 1. Computes the required resource set based on requests and the resource dependency table. 2. Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. 3. Compares the request with the current resource status and determines which resources must be enabled or disabled. 4. Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents. 5. Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 24 Power-Off Shutdown BCM43340 Data Sheet Power-Off Shutdown The BCM43340 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the BCM43340 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the BCM43340 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. During a low-power shut-down state, provided VDDIO remains applied to the BCM43340, all outputs are tristated, and most inputs signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the BCM43340 to be fully integrated in an embedded device and take full advantage of the lowest power-savings modes. Two signals on the BCM43340, the frequency reference input (WRF_XTAL_CAB_OP) and the LPO_IN input, are designed to be high-impedance inputs that do not load down the driving signal even if the chip does not have VDDIO power applied to it. When the BCM43340 is powered on from this state, it is the same as a normal power-up and the device does not retain any information about its state from before it was powered down. Power-Up/Power-Down/Reset Circuits The BCM43340 has two signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 21: “Power-Up Sequence and Timing,” on page 142. Table 1: Power-Up/Power-Down/Reset Control Signals Signal Description WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal BCM43340 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal BCM43340 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 25 Frequency References BCM43340 Data Sheet S e c t i o n 3 : F re q u e n c y R e f e r e n c e s An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. Note: The crystal and TCXO implementations have different power supplies (WRF_XTAL_VDD1P2 for crystal, WRF_TCXO_VDD for TCXO). Crystal Interface and Clock Generation The BCM43340 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator including all external components is shown in Figure 5. Consult the reference schematics for the latest configuration. Figure 5: Recommended Oscillator Configuration C WRF_XTAL_OP 12–27 pF C X ohms* WRF_XTAL_ON 12–27 pF * Resistor value determined by crystal drive level. See reference schematics for details. A fractional-N synthesizer in the BCM43340 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. For SDIO and HSIC applications the default frequency reference is a 37.4 MHz crystal or TCXO. The signal characteristics for the crystal interface are listed in Table 2 on page 28. Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 26 TCXO BCM43340 Data Sheet TCXO As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the Phase Noise requirements listed in Table 2. When the clock is provided by an external TCXO, there are two possible connection methods, as shown in Figure 6 and Figure 7: 1. If the TCXO is dedicated to driving the BCM43340, it should be connected to the WRF_XTAL_OP pin through an external 1000 pF coupling capacitor, as shown in Figure 6. The internal clock buffer connected to this pin will be turned OFF when the BCM43340 goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance variation. If the TCXO is to be shared with another device, such as a GPS receiver, and impedance variation is not allowed, a dedicated external clock buffer will be needed. Power must be supplied to the WRF_XTAL_VDD1P2 pin. 2. For 2.4 GHz operation only, an alternative is to DC-couple the TCXO to the WRF_TCXO_CK pin, as shown in Figure 7. Use this method when the same TCXO is shared with other devices and a change in the input impedance is not acceptable because it may cause a frequency shift that cannot be tolerated by the other device sharing the TCXO. This pin is connected to a clock buffer powered from WRF_TCXO_VDD. If the power supply to this buffer is always on (even in sleep mode), the clock buffer is always on, thereby ensuring a constant input impedance in all states of the device. The maximum current drawn from WRF_TCXO_VDD is approximately 500 µA. Figure 6: Recommended Circuit to Use with an External Dedicated TCXO 1000 pF TCXO WRF_XTAL_OP NC WRF_XTAL_ON WRF_TCXO_CK WRF_TCXO_VDD Figure 7: Recommended Circuit to Use with an External Shared TCXO To other devices TCXO W RF_TCXO_CK To always present 1.8V supply W RF_TCXO_VDD W RF_XTAL_OP NC Broadcom® January 28, 2015 • 43340-DS109-R W RF_XTAL_ON BROADCOM CONFIDENTIAL Page 27 TCXO BCM43340 Data Sheet Table 2: Crystal Oscillator and External Clock – Requirements and Performance Crystala Parameter Conditions/Notes Frequency – Crystal load capacitance ESR Drive level – Input impedance (WRF_XTAL_OP) Input impedance (WRF_TCXO_IN) WRF_XTAL_OP Input low level WRF_XTAL_OP Input high level WRF_XTAL_OP input voltage WRF_TCXO_IN Input voltage Frequency tolerance over the lifetime of the equipment, including temperature Duty cycle Phase Noise (802.11b/g) Phase Noise (802.11a) Phase Noise (802.11n, 2.4 GHz) Phase Noise (802.11n, 5 GHz) Min Typ Max External Frequency Referenceb,c Min Typ Between 19.2 MHz and 52 MHz – 12 – – – – External crystal requirement – f Max Units – pF d,e – – 60 – – – – – – – Ω µW Resistive Capacitive Resistive Capacitive DC-coupled digital signal 200 30k – – – – 100k – – – – – 7.5 – – – 30k – 30k – 0 100k – 100k – – – 7.5 – 4 0.2 Ω pF Ω pF V DC-coupled digital signal – – – 1.0 – 1.26 V AC-coupled analog signal (see Figure 6) DC-coupled analog signal (see Figure 7) Without trimming – – – 400 – 1200 mVp-p – – – 400 – 1980 mVp-p –20 – 20 –20 – 20 ppm 37.4 MHz clock 37.4 MHz clock at 10 kHz offset 37.4 MHz clock at 100 kHz or greater offset 37.4 MHz clock at 10 kHz offset 37.4 MHz clock at 100 kHz or greater offset 37.4 MHz clock at 10 kHz offset 37.4 MHz clock at 100 kHz or greater offset 37.4 MHz clock at 10 kHz offset 37.4 MHz clock at 100 kHz or greater offset – – – – – – – – – 40 – – 50 – – 60 –131 –138 % dBc/Hz dBc/Hz – – – – – – – – – – –139 –146 dBc/Hz dBc/Hz – – – – – – – – – – –136 –143 dBc/Hz dBc/Hz – – – – – – – – – – –144 –151 dBc/Hz dBc/Hz a. (Crystal) Use WRF_XTAL_OP and WRF_XTAL_ON, internal power to pin WRF_XTAL_VDD1P2. b. (TCXO) See “TCXO” on page 27 for alternative connection methods. c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high. Note that 52 MHz is not an auto-detected frequency using the LPO clock. e. The frequency step size is approximately 80 Hz resolution. f. The crystal should be capable of handling a 200uW drive level from the BCM43340. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 28 Frequency Selection BCM43340 Data Sheet Frequency Selection Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard handset reference frequencies of 19.2, 19.44, 19.68, 19.8, 20, 26, 37.4, and 52 MHz, but also other frequencies in this range, with approximately 80 Hz resolution. The BCM43340 must have the reference frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all bit timing is derived from the reference frequency. Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. Contact Broadcom for further details. The reference frequency for the BCM43340 may be set in the following ways: • Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. • Auto-detect any of the standard handset reference frequencies using an external LPO clock. For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard frequencies commonly used, the BCM43340 automatically detects the reference frequency and programs itself to the correct reference frequency. In order for auto frequency detection to work correctly, the BCM43340 must have a valid and stable 32.768 kHz LPO clock that meets the requirements listed in Table 3 on page 30 and is present during power-on reset. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 29 External 32.768 kHz Low-Power Oscillator BCM43340 Data Sheet External 32.768 kHz Low-Power Oscillator The BCM43340 uses a secondary low frequency clock for low-power-mode timing. Either the internal lowprecision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, a trade-off caused by this wide LPO tolerance is a small current consumption increase during WLAN power save mode that is incurred by the need to wake up earlier to avoid missing beacons. Whenever possible, the preferred approach for WLAN is to use a precision external 32.768 kHz clock that meets the requirements listed in Table 3. Note: BTFM operations require the use of an external LPO that meets the requirements listed in Table 3. Table 3: External 32.768 kHz Sleep Clock Specifications Parameter LPO Clock Units Nominal input frequency 32.768 kHz Frequency accuracy ±200 ppm Duty cycle 30–70 % Input signal amplitude 200–1800 mV, p-p Signal type Square-wave or sine-wave – Input impedancea >100k 0.35T VH = 2.0V SCK VL = 0.8V thtr > 0 totr < 0.8T SD and WS T = Clock period Ttr = Minimum allowed clock period for transmitter T = Ttr * tRC is only relevant for transmitters in slave mode. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 56 I2S Interface BCM43340 Data Sheet Figure 20: I2S Receiver Timing T tLC > 0.35T tHC > 0.35 VH = 2.0V SCK VL = 0.8V tsr > 0.2T thr > 0 SD and WS T = Clock period Tr = Minimum allowed clock period for transmitter T > Tr Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 57 FM Receiver Subsystem BCM43340 Data Sheet Section 8: FM Receiver Subsystem FM Radio The BCM43340 includes a completely integrated FM radio receiver with RDS/RBDS covering all FM bands from 76 MHz to 108 MHz. The receiver is controlled through commands on the HCI. FM received audio is available as a stereo analog output or in digital form through I2S or PCM. The FM radio operates from the external clock reference. Digital FM Audio Interfaces The FM audio can be transmitted via the shared PCM and I2S pins, and the sampling rate is programmable. The BCM43340 supports a three-wire PCM or I2S audio interface in either master or slave configuration. The master or slave configuration is selected using vendor specific commands over the HCI interface. In addition, multiple sampling rates are supported, derived from either the FM or Bluetooth clocks. In master mode, the clock rate is either of the following: • 48 kHz x 32 bits per frame = 1.536 MHz • 48 kHz x 50 bits per frame = 2.400 MHz In slave mode, any clock rate is supported up to a maximum of 3.072 MHz. Analog FM Audio Interfaces The demodulated FM audio signal is available as line-level analog stereo output, generated by twin internal high SNR audio DACs. FM Over Bluetooth The BCM43340 can output received FM audio onto Bluetooth using one of following three links: eSCO, WBS, and A2DP. In all of the above modes, once the link has been set up, the host processor can enter sleep mode while the BCM43340 continues to stream FM audio to the remote Bluetooth device, allowing the system current consumption to be minimized. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 58 eSCO BCM43340 Data Sheet eSCO In this use case, the stereo FM audio is downsampled to 8 kHz and a mono or stereo stream is then sent through the Bluetooth eSCO link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo. Wideband Speech Link In this case, the stereo FM audio is downsampled to 16 kHz and a mono or stereo stream is then sent through the Bluetooth wideband speech link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo. A2DP In this case, the stereo FM audio is encoded by the on-chip SBC encoder and transported as an A2DP link to a remote Bluetooth device. Sampling rates of 48 kHz, 44.1 kHz, and 32 kHz joint stereo are supported. An A2DP lite stack is implemented in the BCM43340 to support this use case, which eliminates the need to route the SBCencoded audio back to the host to create the A2DP packets. Autotune and Search Algorithms The BCM43340 supports a number of FM search and tune functions that allows the host to implement many convenient user functions, which are accessed through the Broadcom FM stack. • Tune to Play—Allows the FM receiver to be programmed to a specific frequency. • Search for SNR > Threshold—Checks the power level of the available channel and the estimated SNR of the channel to help achieve precise control of the expected sound quality for the selected FM channel. Specifically, the host can adjust its SNR requirements to retrieve a signal with a specific sound quality, or adjust this to return the weakest channels. • Alternate Frequency Jump—Allows the FM receiver to automatically jump to an alternate FM channel that carries the same information, but has a better SNR. For example, when traveling, a user may pass through a region where a number of channels carry the same station. When the user passes from one area to the next, the FM receiver can automatically switch to another channel with a stronger signal to spare the user from having to manually change the channel to continue listening to the same station. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 59 Audio Features BCM43340 Data Sheet Audio Features A number of features are implemented in the BCM43340 to provide the best possible audio experience for the user. • Mono/Stereo Blend or Switch—The BCM43340 provides automatic control of the stereo or mono settings based on the FM signal carrier-to-noise ratio (C/N). This feature is used to maintain the best possible audio SNR based on the FM channel condition. Two modes of operation are supported: – Blend—In this mode, fine control of stereo separation is used to achieve optimal audio quality over a wide range of input C/N. The amount of separation is fully programmable. In Figure 21, the separation is programmed to maintain a minimum 50 dB SNR across the blend range. – Switch—In this mode, the audio switches from full stereo to full mono at a predetermined level to maintain optimal audio quality. The stereo-to-mono switch point and the mono-to-stereo switch points are fully programmable to provide the desired amount of audio SNR. In Figure 22, the switch point is programmed to switch to mono to maintain a 40 dB SNR. Figure 21: Example Blend/Switch Usage Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 60 Audio Features BCM43340 Data Sheet Figure 22: Example Blend/Switch Separation • Soft Mute—Improves the user experience by dynamically muting the output audio proportionate to the FM signal C/N. This prevents the user from being assaulted with a blast of static. The mute characteristic is fully programmable to accommodate fine tuning of the output signal level. An example mute characteristic is shown in Figure 23. Figure 23: Example Soft Mute Characteristic Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 61 RDS/RBDS BCM43340 Data Sheet • High Cut—A programmable high-cut filter is provided to reduce the amount of high-frequency noise caused by static in the output audio signal. Like the soft mute circuit, it is fully programmable to allow for any amount of high cut based on the FM signal C/N. • Audio Pause Detect—The FM receiver monitors the magnitude of the audio signal and notifies the host through an interrupt when the magnitude of the signal has fallen below the threshold set for a programmable period. This feature can be used to provide alternate frequency jumps during periods of silence to minimize disturbances to the listener. Filtering techniques are used within the audio pause detection block to provide more robust presence-to-silence detection and silence-to-presence detection. • Automatic Antenna Tuning—The BCM43340 has an on-chip automatic antenna tuning network. When used with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching component to obtain the highest signal strength for the desired frequency. The high-Q nature of this matching network simultaneously provides out-of-band blocking protection as well as a reduction of radiated spurious emissions from the FM antenna. It is designed to accommodate a wide range of external wire antennas. RDS/RBDS The BCM43340 integrates a RDS/RBDS modem, the decoder includes programmable filtering and buffering functions. The RDS/RBDS data can be read out through the HCI interface. In addition, the RDS/RBDS receive functionality supports the following: • Block decoding, error correction and synchronization • Flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and loss of sync. (It is possible to set up the BCM43340 such that synch is achieved when a minimum of two good blocks (error free) are decoded in sequence. The number of good blocks required for sync is programmable.) • Storage capability up to 126 blocks of RDS data • Full or partial block B match detect and interrupt to host • Audio pause detection with programmable parameters • Program Identification (PI) code detection and interrupt to host • Automatic frequency jump • Block E filtering • Soft mute • Signal dependent mono/stereo blend Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 62 WLAN Global Functions BCM43340 Data Sheet Section 9: WLAN Global Functions WLAN CPU and Memory Subsystem The BCM43340 includes an integrated ARM Cortex-M3™ processor with internal RAM and ROM. The ARM Cortex-M3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. It is intended for deeply embedded applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for Thumb®-2 instruction set. ARM Cortex-M3 delivers 30% more performance gain over ARM7TDMI®. At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit devices on MIPS/µW. It supports integrated sleep modes. ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM Cortex-M3 supports extensive debug features including real time trace of program execution. On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM. One-Time Programmable Memory Various hardware configuration parameters may be stored in an internal 3072-bit One-Time Programmable (OTP) memory, which is read by the system software after device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC address can be stored, depending on the specific board design. The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 63 GPIO Interface BCM43340 Data Sheet GPIO Interface On the WLBGA package, there are 8 GPIO pins available on the WLAN section of the BCM43340 that can be used to connect to various external devices. Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. External Coexistence Interface An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such as GPS, WiMAX, LTE, or UWB, to manage wireless medium sharing for optimum performance. The coexistence signals in Figure 24 and Table 14 can be enabled by software on the indicated GPIO pins. Figure 24: LTE Coexistence Interface GPIO5 WLAN ERCX WLAN_PRIORITY GPIO3 LTE_TX GPIO2 LTE_RX BT/FM BCM4334X LTE Chip Table 14: External Coexistence Interface Coexistence Signal GPIO Name Type Comment ERCX_TX_CONF/ WLAN_PRIORITY GPIO_5 Output Notify LTE of request to sleep ERCX_FREQ/LTE_TX GPIO_3 Input Notify WLAN RX of requirement to sleep ERCX_RF_ACTIVE/LTE_RX GPIO_2 Input Notify WLAN TX to reduce TX power Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 64 UART Interface BCM43340 Data Sheet UART Interface One UART interface can be enabled by software as an alternate function on pins WL_GPIO4 and WL_GPIO_5. Provided primarily for debugging during development, this UART enables the BCM43340 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART and provides a FIFO size of 64 × 8 in each direction. JTAG Interface The BCM43340 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 65 WLAN Host Interfaces BCM43340 Data Sheet Section 10: WLAN Host Interfaces SDIO v2.0 The BCM43340 WLAN section supports SDIO version 2.0, including the following modes: DS: Default speed up to 25 MHz, including 1- and 4-bit modes (3.3V signaling) HS: High speed up to 50 MHz (3.3V signaling) It also has the ability to map the interrupt signal onto a GPIO pin for applications requiring an interrupt different than what is provided by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided. SDIO mode is enabled using the strapping option pins strap_host_ifc_[3:1]. Three functions are supported: • Function 0 standard SDIO function (Max BlockSize/ByteCount = 32B) • Function 1 backplane function to access the internal system-on-chip (SoC) address space (Max BlockSize/ ByteCount = 64B) • Function 2 WLAN function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount = 512B) SDIO Pin Descriptions Table 15: SDIO Pin Description SD 4-Bit Mode SD 1-Bit Mode DATA0 Data line 0 Data line DO Data output DATA1 Data line 1 or Interrupt IRQ Interrupt IRQ Interrupt DATA2 Data line 2 or Read Wait RW Read Wait NC Not used DATA3 Data line 3 N/C Not used CS Card select CLK Clock CLK Clock SCLK Clock CMD Command line CMD Command line DI Data input Broadcom® January 28, 2015 • 43340-DS109-R DATA gSPI Mode BROADCOM CONFIDENTIAL Page 66 SDIO v2.0 BCM43340 Data Sheet Figure 25: Signal Connections to SDIO Host (SD 4-Bit Mode) CLK SD Host CMD BCM43340 DAT[3:0] Figure 26: Signal Connections to SDIO Host (SD 1-Bit Mode) CLK CMD SD Host DATA BCM43340 IRQ RW Figure 27: SDIO Pull-Up Requirements VDDIO_SD 47k (see note) 47k (see note) CLK SD Host CMD BCM43340 DATA[3:0] Note: Per Section 6 of the SDIO specification, 10 to 100 kohm pull-ups are required on the four DATA lines and the CMD line . This requirement must be met during all operating states by using external pull -up resistors or properly programming internal SDIO Host pull-ups. The BCM43340 does not have internal pull-ups on these lines. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 67 Generic SPI Mode BCM43340 Data Sheet Generic SPI Mode In addition to the full SDIO mode, the BCM43340 includes the option of using the simplified generic SPI (gSPI) interface/protocol. Characteristics of the gSPI mode include: • Supports up to 48 MHz operation • Supports fixed delays for responses and data from device • Supports alignment to host gSPI frames (16 or 32 bits) • Supports up to 2 KB frame size per transfer • Supports little endian (default) and big endian configurations • Supports configurable active edge for shifting • Supports packet transfer through DMA for WLAN gSPI mode is enabled using the strapping option pins strap_host_ifc_[3:1]. Figure 28: Signal Connections to SDIO Host (gSPI Mode) SCLK DI SD Host DO BCM43340 IRQ CS Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 68 Generic SPI Mode BCM43340 Data Sheet SPI Protocol The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianness is supported in both modes. Figure 29 and Figure 30 show the basic write and write/read commands. Figure 29: gSPI Write Protocol Figure 30: gSPI Read Protocol Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 69 Generic SPI Mode BCM43340 Data Sheet Command Structure The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure 31. Figure 31: gSPI Command Structure BCM_SPID Command Structure 31 30 29 28 C A F0 F1 27 11 10 Ad dres s – 17 bits 0 P acket length - 11b its * * 11’ h0 = 204 8 by tes F unction N o: 00 01 10 11 – – – – F unc F unc F unc F unc 0 Ϭ͗ůů^W/ƐƉĞĐŝĮĐƌĞŐŝƐƚĞƌƐ 1 1: Registers and meories belonging to other blocks in the chip (64 bytes max) 2 2: DMA channel 1. WLAN packets up to 2048 bytes. 3 ϯ͗DĐŚĂŶŶĞůϮ;ŽƉƟŽŶĂůͿ͘WĂĐŬĞƚƐƵƉƚŽϮϬϰϴďLJƚĞƐ͘ Acce ss : 0 – F ixed add ress 1 – Incremental add res s C ommand : 0 – R ead 1 – W rite Write The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge. Write/Read The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising clock edge of the clock burst for the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows data to be ready for the first clock edge without relying on asynchronous delays. Read The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data and b) the time interval between the command/address is not fixed. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 70 Generic SPI Mode BCM43340 Data Sheet Status The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information about any packet errors, protocol errors, information about available packet in the RX queue, etc. The status information helps in reducing the number of interrupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus timing for read/write transactions with and without status notification are as shown in Figure 32 and Figure 33 on page 72. See Table 16 on page 72 for information on status field details. Figure 32: gSPI Signal Timing Without Status (32-bit big endian shown) Write cs sclk mosi C31 C31 C30 C30 C1 C1 C0 C0 D31 D31 D30 D30 Command 32 bits Write-Read D1 D1 D0 D0 Write Data 16*n bits cs sclk mosi C31 C31 C30 C30 C0 C0 miso D31 D31 D30 D30 Response Delay Command 32 bits Read D1 D1 D0 D0 Read Data 16*n bits cs sclk mosi C31 C31 C30 C30 C0 C0 miso D31 D31 D30 D30 Command 32 bits Broadcom® January 28, 2015 • 43340-DS109-R Response Delay BROADCOM CONFIDENTIAL D0 D0 Read Data 16*n bits Page 71 Generic SPI Mode BCM43340 Data Sheet Figure 33: gSPI Signal Timing with Status (Response Delay = 0) (32-bit big endian shown) cs Write sclk mosi C31 C31 C1 C1 C0 C0 D31 D31 D1 D1 D0 D0 S31 S31 miso Command 32 bits Write-Read Write Data 16*n bits S1 S1 S0 S0 Status 32 bits cs sclk mosi C31 C31 C0 C0 miso D31 D31 D0 D0 Read Data 16*n bits Command 32 bits Read D1 D1 S31 S31 S0 S0 Status 32 bits cs sclk mosi C31 C31 C0 C0 miso D31 D31 Command 32 bits D1 D1 D0 D0 Read Data 16*n bits S31 S31 S0 S0 Status 32 bits Table 16: gSPI Status Field Details Bit Name Description 0 Data not available The requested read data is not available 1 Underflow FIFO underflow occurred due to current (F2, F3) read command 2 Overflow FIFO overflow occurred due to current (F1, F2, F3) write command 3 F2 interrupt F2 channel interrupt 4 F3 interrupt F3 channel interrupt 5 F2 RX Ready F2 FIFO is ready to receive data (FIFO empty) 6 F3 RX Ready F3 FIFO is ready to receive data (FIFO empty) 7 Reserved – 8 F2 Packet Available Packet is available/ready in F2 TX FIFO 9:19 F2 Packet Length Length of packet available in F2 FIFO 20 F3 Packet Available Packet is available/ready in F3 TX FIFO 21:31 F3 Packet Length Length of packet available in F3 FIFO Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 72 Generic SPI Mode BCM43340 Data Sheet gSPI Host-Device Handshake To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the BCM43340 is ready for data transfer. The device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of interrupt and then take necessary actions. Boot-Up Sequence After power-up, the gSPI host needs to wait 150 ms for the device to be out of reset. For this, the host needs to poll with a read command to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wakeup-WLAN bit (F0 reg 0x00 bit 7). The wakeup-WLAN issues a clock request to the PMU. For the first time after power-up, the host must wait for the availability of low power clock inside the device. Once that is available, the host must write to a PMU register to set the crystal frequency, which turns on the PLL. After the PLL is locked, the chipActive interrupt is issued to the host. This interrupt indicates the device awake/ready status. See Table 17 for information on gSPI registers. In Table 17, the following notation is used for register access: • R: Readable from host and CPU • W: Writable from host • U: Writable from CPU Table 17: gSPI Registers Address Register Bit Access Default Description x0000 Word length 0 R/W/U 0 0: 16 bit word length 1: 32 bit word length Endianness 1 R/W/U 0 0: Little Endian 1: Big Endian High-speed mode 4 R/W/U 1 0: Normal mode. RX and TX at different edges. 1: High speed mode. RX and TX on same edge (default). Interrupt polarity 5 R/W/U 1 0: Interrupt active polarity is low 1: Interrupt active polarity is high (default) Wake-up 7 R/W A write of 1 will denote a wake-up command from the host to the device. This will be followed by an F2 Interrupt from the gSPI device to the host, indicating device awake status. Response delay 7:0 R/W/U 8‘h04 x0001 Broadcom® January 28, 2015 • 43340-DS109-R 0 Configurable read response delay in multiples of 8 bits BROADCOM CONFIDENTIAL Page 73 Generic SPI Mode BCM43340 Data Sheet Table 17: gSPI Registers (Cont.) Address Register Bit Access Default Description x0002 Status enable 0 R/W 1 0: no status sent to host after read/write 1: status sent to host after read/write Interrupt with status 1 R/W 0 0: do not interrupt if status is sent 1: interrupt host even if status is sent Response delay for all 2 R/W 0 0: response delay applicable to F1 read only 1: response delay applicable to all function read x0003 Reserved – – – – x0004 Interrupt register 0 R/W 0 Requested data not available; Cleared by writing a 1 to this location 1 R 0 F2/F3 FIFO underflow due to last read 2 R 0 F2/F3 FIFO overflow due to last write 5 R 0 F2 packet available 6 R 0 F3 packet available 7 R 0 F1 overflow due to last write 5 R 0 F1 Interrupt 6 R 0 F2 Interrupt 7 R 0 F3 Interrupt x0005 Interrupt register x0006– x0007 Interrupt enable register 15:0 R/W/U 16'hE0E7 Particular Interrupt is enabled if a corresponding bit is set x0008– x000B Status register R x000C– x000D F1 info register x000E– x000F F2 info register 31:0 32'h0000 Same as status bit definitions 0 R 1 F1 enabled 1 R 0 F1 ready for data transfer 13:2 R/U 12'h40 F1 max packet size 0 R/U 1 F2 enabled 1 R 0 F2 ready for data transfer 15:2 R/U 14'h800 F2 max packet size 0 R/U 1 F3 enabled 1 R 0 F3 ready for data transfer F3 max packet size x0010– x0011 F3 info register R/U 14'h800 x0014– x0017 Test–Read only register 31:0 R 32'hFEE This register contains a predefined pattern, DBEAD which the host can read and determine if the gSPI interface is working properly. x0018– x001B Test–R/W register R/W/U 32'h0000 This is a dummy register where the host can 0000 write some pattern and read it back to determine if the gSPI interface is working properly. 15:2 Broadcom® January 28, 2015 • 43340-DS109-R 31:0 BROADCOM CONFIDENTIAL Page 74 Generic SPI Mode BCM43340 Data Sheet Figure 34 shows the WLAN boot-up sequence from power-up to firmware download. Figure 34: WLAN Boot-Up Sequence VBAT* VDDIO W L_REG_ON < 1.5 m s VDDC (from internal PM U ) < 104 m s Internal POR < 4 ms After a fixed delay following Internal POR and W L_REG _ON going high, the device responds to host F0 (address 0x14) reads. Device requests for reference clock 8 ms After 8 m s the reference clock is assum ed to be up. Access to PLL registers is possible . Host Interaction: Host polls F0 (address 0x14) until it reads a predefined pattern. Host sets wake-up-wlan bit and waits 8 ms, the maximum tim e for reference clock availability. After 8 m s, host program s PLL registers to set crystal frequency Chip active interrupt is asserted after the PLL locks Host downloads code. *N otes: 1. VBAT should not rise faster than 40 m icroseconds or slow er than 100 m illiseconds. 2. VBAT should be up before or at the sam e tim e as VD D IO . V DD IO should N O T be present first or be held high before VBAT is high . Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 75 HSIC Interface BCM43340 Data Sheet HSIC Interface As an alternative to SDIO, an HSIC host interface can be enabled using the strapping option pins strap_host_ifc_[3:1]. HSIC is a simplified derivative of the USB2.0 interface designed to replace a standard USB PHY and cable for short distances (up to 10 cm) on board point-to-point connections. Using two signals, a bidirectional data strobe (STROBE) and a bidirectional DDR data signal (DATA), it provides high-speed serial 480 Mbps data transfers that are 100% host driver compatible with traditional USB 2.0 cable-connected topologies. Figure 35 shows the blocks in the HSIC device core. Key features of HSIC include: • High-speed 480 Mbps data rate • Source-synchronous serial interface using 1.2V LVCMOS signal levels • No power consumed except when a data transfer is in progress • Maximum trace length of 10 cm. • No Plug-n-Play support, no hot attach/removal Figure 35: HSIC Device Block Diagram 32-Bit On-Chip Communication System DMA Engines RX FIFO TXFIFOs FIFOs TX FIFOs TX FIFOs TX FIFOs TX TX FIFOs Endpoint Management Unit USB 2.0 Protocol Engine HSIC PHY Strobe Broadcom® January 28, 2015 • 43340-DS109-R Data BROADCOM CONFIDENTIAL Page 76 Wireless LAN MAC and PHY BCM43340 Data Sheet S e c t i o n 11 : Wi r e l e s s L A N M A C a n d P H Y MAC Features The BCM43340 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The salient features are listed below: • Transmission and reception of aggregated MPDUs (A-MPDU) • Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP) and multiphase PSMP operation • Support for immediate ACK and Block-ACK policies • Interframe space timing support, including RIFS • Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges • Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification • Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT) generation in hardware • Hardware offload for AES-CCMP, legacy WEP ciphers, WAPI, and support for key management • Support for coexistence with Bluetooth and other external radios • Programmable independent basic service set (IBSS) or infrastructure basic service set functionality • Statistics counters for MIB support MAC Description The BCM43340 WLAN MAC is designed to support high-throughput operation with low-power consumption. It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 36 on page 78. The following sections provide an overview of the important modules in the MAC. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 77 MAC Features BCM43340 Data Sheet Figure 36: WLAN MAC Architecture Embedded CPU Interface Host Registers, DMA Engines TX-FIFO 32 KB PMQ RX-FIFO 10 KB PSM PSM UCODE Memory IFS Backoff, BTCX WEP TKIP, AES, WAPI TSF SHM BUS IHR NAV EXT- IHR BUS RXE RX A-MPDU TXE TX A-MPDU Shared Memory 6 KB MAC-PHY Interface PSM The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control to the hardware, to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications. The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratchpad memory (similar to a register bank) to store frequently accessed and temporary variables. The PSM exercises fine-grained control over the hardware engines, by programming internal hardware registers (IHR). These IHRs are co-located with the hardware functions they control, and are accessed by the PSM via the IHR bus. The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. For ALU operations the operands are obtained from shared memory, scratchpad, IHRs, or instruction literals, and the results are written into the shared memory, scratchpad, or IHRs. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 78 MAC Features BCM43340 Data Sheet There are two basic branch instructions: conditional branches and ALU based branches. To better support the many decision points in the IEEE 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condition signals are available to the PSM without polling the IHRs), or on the results of ALU operations. WEP The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, and MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2 AES-CCMP. The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to be used. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the TXE to encrypt and compute the MIC on transmit frames, and the RXE to decrypt and verify the MIC on receive frames. TXE The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the frames across the MAC-PHY interface at the appropriate time determined by the channel access mechanisms. The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a precise timing trigger received from the IFS module. The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed. RXE The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The decrypted data is stored in the RXFIFO. The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria such as receiver address, BSSID, and certain frame types. The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate them into component MPDUS. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 79 MAC Features BCM43340 Data Sheet IFS The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple backoff engines required to support prioritized access to the medium as specified by WMM. The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a TXOP). The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the backoff counters. When the backoff counters reach 0, the TXE gets notified, so that it may commence frame transmission. In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the PSM. The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power save mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer expires the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration ensuring that the TSF is synchronized to the network. The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions. TSF The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink transmission times used in PSMP. NAV The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard. The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames. This timing information is provided to the IFS module, which uses it as a virtual carriersense indication. MAC-PHY Interface The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is an programming interface, which can be controlled either by the host or the PSM to configure and control the PHY. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 80 WLAN PHY Description BCM43340 Data Sheet WLAN PHY Description The BCM43340 WLAN Digital PHY is designed to comply with IEEE 802.11a/b/g/n single-stream to provide wireless LAN connectivity supporting data rates from 1 Mbps to 150 Mbps for low-power, high-performance handheld applications. The PHY has been designed to work with interference, radio nonlinearity, and impairments. It incorporates efficient implementations of the filters, FFT and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has been tuned to provide high throughput for IEEE 802.11g/11b hybrid networks with Bluetooth coexistence. It has also been designed for shared single antenna systems between WL and BT to support simultaneous RX-RX. PHY Features • Supports IEEE 802.11a, 11b, 11g, and 11n single-stream PHY standards. • IEEE 802.11n single-stream operation in 20 MHz and 40 MHz channels • Supports Optional Short GI and Green Field modes in TX and RX. • Supports optional space-time block code (STBC) receive of two space-time streams. • TX LDPC for improved range and power efficiency • Supports IEEE 802.11h/k for worldwide operation. • Advanced algorithms for low power, enhanced sensitivity, range, and reliability • Algorithms to improve performance in presence of Bluetooth • Simultaneous RX-RX (WL-BT) architecture • Automatic gain control scheme for blocking and non blocking application scenario for cellular applications • Closed loop transmit power control • Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities • On-the-fly channel frequency and transmit power selection • Supports per packet RX antenna diversity. • Designed to meet FCC and other worldwide regulatory requirements. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 81 WLAN PHY Description BCM43340 Data Sheet Figure 37: WLAN PHY Block Diagram CCK/DSSS Demodulate Filters and Radio Comp Frequency and Timing Synch OFDM Demodulate Viterbi Decoder Descramble and Deframe Carrier Sense, AGC, and Rx FSM Buffers Radio Control Block MAC Interface FFT/IFFT AFE and Radio Tx FSM Modulation and Coding Common Logic Block Frame and Scramble Filters and Radio Comp PA Comp Modulate/Spread COEX One of the key features of the PHY is its space-time block coding (STBC) capability. The STBC scheme can obtain diversity gains in a fading channel environment. On a connection with an access point that uses multiple transmit antennas and supports STBC, the BCM43340 can process two space-time streams to improve receiver performance. Figure 38 is a block diagram showing the STBC implementation in the receive path. Figure 38: STBC Implementation in the Receive Path FFT of 2 Symbols Equalizer Demod Combine Demapper Descramble and Deframe Viterbi hold Transmitter Channel h hupd Symbol Memory Weighted Averaging hnew Estimate Channel In STBC mode, symbols are processed in pairs. Equalized output symbols are linearly combined and decoded. The channel estimate is refined on every pair of symbols using the received symbols and reconstructed symbols. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 82 WLAN Radio Subsystem BCM43340 Data Sheet Section 12: WLAN Radio Subsystem The BCM43340 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Receiver Path The BCM43340 has a wide dynamic range, direct conversion receiver. It employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. Control signals are available that can support the use of optional external low noise amplifiers (LNA), which can increase the receive sensitivity by several dB. Transmit Path Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5-GHz U-NII bands, respectively. The BCM43340 includes an on-chip regulator which regulates VBAT down to 3.3V for the BCM43340 on-chip linear Power Amplifiers. Closed-loop output power control is provided by means of internal a-band and g-band power detectors. Calibration The BCM43340 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations across components. This enables the BCM43340 to be used in high-volume applications, because calibration routines are not required during manufacturing testing. These calibration routines are performed periodically in the course of normal radio operation. Examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance and LOFT calibration for carrier leakage reduction. In addition, I/Q Calibration, R Calibration, and VCO Calibration are performed on-chip. No per-board calibration is required in manufacturing test, which helps to minimize test time and cost during large volume production. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 83 Pinout and Signal Descriptions BCM43340 Data Sheet Section 13: Pinout and Signal Descriptions Signal Assignments Figure 39 shows the WLBGA ball map. Table 18 on page 85 contains the signal description for all packages. Figure 39: 141-Bump BCM43340 WLBGA Ball Map (Bottom View) 11 10 9 8 7 6 5 4 FM_LNAVCOVDD FM_RFIN BT_VCOVDD BT_LNAVDD BT_RF BT_PAVDD WRF_RFIN_2G B FM_VCOVSS BT_VCOVSS BT_PLLVDD BT_PAVSS BT_IFVSS WRF_PA2G_VBAT_VDD3P3 C FM_AOUT2 FM_PLLVSS BT_IFVDD BT_PLLVSS BT_I2S_WS BT_I2S_CLK WRF_LNA_2G_GND1P2 WRF_PADRV_VBAT_VDD3P3 WRF_PADRV_VBAT_GND3P3 VDDC_E9 BT_PCM_OUT BT_I2S_DO WRF_RX_GND1P2 WRF_TX_GND1P2 BT_PCM_CLK BT_PCM_SYNC WRF_AFE_GND1P2 WRF_BUCK_VDD1P5 WL_GPIO_1 FM_LNAVSS WRF_RFOUT_2G 3 A D FM_AOUT1 FM_PLLVDD E CLK_REQ BT_DEV_WAKE F LPO_IN BT_HOST_WAKE BT_PCM_IN G BT_UART_CTS_N BT_UART_TXD NC_G9 RF_SW_CTRL_3 VSSC_G7 RF_SW_CTRL_2 WL_GPIO_6 WL_GPIO_2 H BT_UART_RTS_N BT_UART_RXD VDDIO_H9 RF_SW_CTRL_4 VDDC_H7 RF_SW_CTRL_1 WL_GPIO_5 J NC_J11 VSS_J10 NC_J9 VSS_J8 WL_GPIO_4 VDDIO_RF WL_GPIO_12 K VSS_K11 VSS_K10 NC_K9 VSS_K8 NC_K7 L VSS_L11 VSS_L10 VSS_L9 VSS_L8 M VSS_M11 VSS_M10 VSS_M9 N VSS_N11 VSS_N10 P VSS_P11 VSS_P10 10 11 2 WRF_RFOUT_5G WRF_CBUCK_PAVDD1P5 WRF_PA2G_VBAT_GND3P3 VSSC_D6 WRF_PAPMU_VOUT_LDO3P3 1 WRF_PAPMU_VBAT_VDD5P0 A WRF_PAPMU_GND B WRF_PA5G_VBAT_GND3P3_C3 WRF_PA5G_VBAT_GND3P3_C2 WRF_RFIN_5G WRF_LNA_5G_GND1P2 D WRF_VCO_GND1P2 E WRF_SYNTH_VDD1P2 WRF_XTAL_CAB_VDD1P2 F WL_GPIO_0 WRF_SYNTH_GND1P2 WRF_XTAL_CAB_XOP G WL_GPIO_3 WRF_TCXO_VDD1P8 WRF_XTAL_CAB_GND1P2 WRF_XTAL_CAB_XON H VDDIO_J4 WRF_TCXO_CKIN2V BT_REG_ON WL_REG_ON J SDIO_DATA_2 SDIO_DATA_3 RREFHSIC HSIC_DATA VDDC_K1 K NC_L7 RF_SW_CTRL_0 SDIO_DATA_0 SDIO_DATA_1 HSIC_DVDD1P2_OUT HSIC_STROBE HSIC_AGND12PLL L VSS_M8 NC_M7 SDIO_CLK JTAG_SEL VSSC_M2 PMU_AVSS M VSS_N9 VSS_N8 VSS_N7 VSSC_N6 N VSS_P9 VSS_P8 VSS_P7 VSS_P6 9 8 7 6 SDIO_CMD VDDC_P5 5 WRF_GPIO_OUT C VOUT_2P5 VOUT_CLDO SR_VDDBATA5V SR_VLX VOUT_LNLDO LDO_VDD1P5 SR_VDDBATP5V SR_PVSS 4 3 2 P 1 Top layer metal restrict Depopulated Broadcom® January 28, 2015 • 43340-DS109-R Page 84 BROADCOM CONFIDENTIAL Signal Descriptions BCM43340 Data Sheet Signal Descriptions The signal name, type, and description of each pin in the BCM43340 is listed in Table 18. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. See also Table 19 on page 93 for resistor strapping options. Table 18: WLBGA Signal Descriptions WLBGA Ball Signal Name Type Description WLAN RF Signal Interface A5 C1 A4 A2 D2 WRF_RFIN_2G WRF_RFIN_5G WRF_RFOUT_2G WRF_RFOUT_5G WRF_GPIO_OUT I I O O I/O 2.4G RF input 5G RF input 2.4G RF output 5G RF output – RF_SW_CTRL_0 RF_SW_CTRL_1 RF_SW_CTRL_2 RF_SW_CTRL_3 RF_SW_CTRL_4 O O O O O RF switch enable RF switch enable RF switch enable RF switch enable RF switch enable M6 M5 L5 L4 SDIO_CLK SDIO_CMD SDIO_DATA_0 SDIO_DATA_1 I I/O I/O I/O K5 SDIO_DATA_2 I/O K4 SDIO_DATA_3 I/O SDIO clock input SDIO command line SDIO data line 0 SDIO data line 1. Also used as a strapping option (see Table 19 on page 93). SDIO data line 2. Also used as a strapping option (see Table 19 on page 93). SDIO data line 3 RF Control Signals L6 H6 G6 G8 H8 SDIO Bus Interface Note: Per Section 6 of the SDIO specification, 10 to 100 kohm pull-ups are required on the four DATA lines and the CMD line. This requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO Host pull-ups. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 85 Signal Descriptions BCM43340 Data Sheet Table 18: WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description JTAG_SEL I/O JTAG select: Connect this pin high (VDDIO) in order to use GPIO_2 through GPIO_5 and GPIO_12 as JTAG signals. Otherwise, if this pin is left as a NO_CONNECT, its internal pull-down selects the default mode that allows GPIOs 2, 3, 4, 5, and 12 to be used as GPIOs. Note: See “WLAN GPIO Interface” on page 86 for the JTAG signal pins. HSIC_STROBE HSIC_DATA RREFHSIC I I/O I HSIC Strobe HSIC Data HSIC reference resistor input. If HSIC is used, connect this pin to ground via a 51Ω 5% resistor. G3 WL_GPIO_0 I/O F3 WL_GPIO_1 I/O G4 WL_GPIO_2 I/O H4 WL_GPIO_3 I/O J7 WL_GPIO_4 I/O H5 WL_GPIO_5 I/O G5 WL_GPIO_6 I/O This pin can be programmed by software to be a GPIO. This pin can be programmed by software to be a GPIO or an AP_READY or HSIC_HOST_READY input from the host indicating that it is awake. This pin can be programmed by software to be a GPIO, the JTAG TCK or an HSIC_READY output to the host, indicating that the device is ready to respond with a CONNECT when it sees IDLE on the HSIC bus. This pin can be programmed by software to be a GPIO or the JTAG TMS signal. This pin can be programmed by software to be a GPIO, the JTAG TDI signal, the UART RX signal, or as the WLAN_HOST_WAKE output indicating that host wake-up should be performed. This pin can be programmed by software to be a GPIO, the JTAG TDO signal or the UART TX signal. GPIO pin. Note: Some GPIOs are also used as strapping options (see Table 19 on page 93). JTAG Interface M4 HSIC Interface L2 K2 K3 WLAN GPIO Interface Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 86 Signal Descriptions BCM43340 Data Sheet Table 18: WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description J5 WL_GPIO_12 I/O This pin can be programmed by software to be a GPIO or the JTAG TRST_L signal. GPIO12 has an internal pull-down by default if JTAG_SEL is low. When JTAG_SEL is high, GPIO12 is used as JTAG_TRST_L and is pulled up. This pin is also used as WLAN_DEV_WAKE, an out-of- band wake-up signal when the host wants to wake WLAN from the deep sleep mode. Note: Some GPIOs are also used as strapping options (see Table 19 on page 93). H1 G1 J3 WRF_XTAL_CAB_XON WRF_XTAL_CAB_XOP WRF_TCXO_CKIN2V O I I E11 CLK_REQ O F11 LPO_IN I XTAL oscillator output XTAL oscillator input TCXO buffered input. When not using a TCXO this pin should be connected to ground. External system clock request—Used when the system clock is not provided by a dedicated crystal (for example, when a shared TCXO is used). Asserted to indicate to the host that the clock is required. Shared by BT, and WLAN. Can also be programmed as the BT_I2S_DI input pin if CLK_REQ functionality is not required. External sleep clock input (32.768 kHz) BT_RF FM_AOUT1 FM_AOUT2 FM_RFIN I/O O O I Bluetooth transceiver RF antenna port FM analog output 1 FM analog output 2 FM radio antenna port F8 BT_PCM_CLK I/O F9 E8 F7 BT_PCM_IN BT_PCM_OUT BT_PCM_SYNC I O I/O PCM clock; can be master (output) or slave (input) PCM data input sensing PCM data output PCM sync; can be master (output) or slave (input) Clocks Bluetooth/FM Receiver A7 D11 C11 A10 Bluetooth PCM Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 87 Signal Descriptions BCM43340 Data Sheet Table 18: WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description Bluetooth UART and Wake G11 BT_UART_CTS_N I UART clear-to-send. Active-low clearto-send signal for the HCI UART interface. H11 BT_UART_RTS_N O UART request-to-send. Active-low request-to-send signal for the HCI UART interface. H10 BT_UART_RXD I UART serial input. Serial data input for the HCI UART interface. G10 BT_UART_TXD O UART serial output. Serial data output for the HCI UART interface. E10 BT_DEV_WAKE I/O DEV_WAKE or general-purpose I/O signal F10 BT_HOST_WAKE I/O HOST_WAKE or general-purpose I/O signal Note: By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality. Through software configuration, the PCM interface can also be routed over the BT_WAKE/UART signals as follows: • PCM_CLK on the UART_RTS_N pin • PCM_OUT on the UART_CTS_N pin • PCM_SYNC on the BT_HOST_WAKE pin • PCM_IN on the BT_DEV_WAKE pin In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire UART Transport. D7 BT_I2S_CLK I/O I2S clock; can be master (output) or slave (input) E7 BT_I2S_DO I/O I2S data output D8 BT_I2S_WS I/O I2S WS; can be master (output) or slave (input) Bluetooth/FM I2S Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 88 Signal Descriptions BCM43340 Data Sheet Table 18: WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description J1 WL_REG_ON I J2 BT_REG_ON I Miscellaneous Used by PMU to power up or power down the internal BCM43340 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Used by PMU to power up or power down the internal BCM43340 regulators used by the Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/FM section in reset. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Integrated Voltage Regulators N2 P2 N1 SR_VDDBATA5V SR_VDDBATP5V SR_VLX I I O P3 LDO_VDD1P5 I P4 N3 VOUT_LNLDO VOUT_CLDO O O Quiet VBAT Power VBAT CBUCK switching regulator output. See Table 37 on page 127 for details of the inductor and capacitor required on this output. Input for the LNLDO, CLDO, and HSIC LDOs. It is also the voltage feedback pin for the CBUCK regulator. Output of low-noise LNLDO Output of core LDO I I I I I Bluetooth PA power supply Bluetooth LNA power supply Bluetooth IF block power supply Bluetooth RF PLL power supply Bluetooth RF power supply I I FM PLL power supply FM VCO and receiver power supply pin Bluetooth Power Supplies A6 A8 C8 B8 A9 BT_PAVDD BT_LNAVDD BT_IFVDD BT_PLLVDD BT_VCOVDD FM Receiver Power Supplies D10 A11 FM_PLLVDD FM_LNAVCOVDD Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 89 Signal Descriptions BCM43340 Data Sheet Table 18: WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description F4 WRF_BUCK_VDD1P5 I B3 B5 D4 A1 A3 F2 H3 WRF_CBUCK_PAVDD1P5 WRF_PA2G_VBAT_VDD3P3 WRF_PADRV_VBAT_VDD3P3 WRF_PAPMU_VBAT_VDD5P0 WRF_PAPMU_VOUT_LDO3P3 WRF_SYNTH_VDD1P2 WRF_TCXO_VDD1P8 I I I I O I I F1 WRF_XTAL_CAB_VDD1P2 I WLAN Power Supplies Internal LDO supply from CBUCK for VCO, AFE, TX, and RX NO_CONNECT 2G PA 3.3V Supply 3.3V supply for A/G band PAD PAPMU VBAT power supply PAPMU 3.3V LDO output voltage Synth VDD 1.2V input Supply to the WRF_TCXO_CKIN input buffer. When not using a TCXO, this pin should be connected to ground. XTAL oscillator supply Miscellaneous Power Supplies L3 HSIC_DVDD1P2_OUT O 1.2V supply for HSIC interface. This pin can be NO_CONNECT when HSIC is not used. Core supply for WLAN and BT. E9 H7 K1 P5 H9 J4 VDDC_E9 VDDC_H7 VDDC_K1 VDDC_P5 VDDIO_H9 VDDIO_J4 I I I I I I J6 VDDIO_RF I N4 VOUT_2P5 O I/O supply (1.8–3.3V). For the WLBGA package, this is the supply for both SDIO and other I/O pads. I/O supply for RF switch control pads (3.3V) 2.5V LDO output BT_PAVSS BT_IFVSS BT_PLLVSS BT_VCOVSS FM_VCOVSS FM_LNAVSS FM_PLLVSS HSIC_AGND12PLL PMU_AVSS SR_PVSS I I I I I I I I I I Bluetooth PA ground 1.2V Bluetooth IF block ground Bluetooth RF PLL ground 1.2V Bluetooth RF ground FM VCO ground FM receiver ground FM PLL ground HSIC PLL ground Quiet ground Power ground Ground B7 B6 C7 B9 B11 B10 C9 L1 M1 P1 Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 90 Signal Descriptions BCM43340 Data Sheet Table 18: WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description D6 G7 M2 N6 G2 F5 D5 D1 C4 C2 C3 B1 D3 E5 E4 E1 H2 J8 J10 K8 K10 K11 L8 L9 L10 L11 M8 M9 M10 M11 N7 N8 N9 N10 N11 P6 P7 P8 P9 P10 VSSC_D6 VSSC_G7 VSSC_M2 VSSC_N6 WRF_SYNTH_GND1P2 WRF_AFE_GND1P2 WRF_LNA_2G_GND1P2 WRF_LNA_5G_GND1P2 WRF_PA2G_VBAT_GND3P3 WRF_PA5G_VBAT_GND3P3_C2 WRF_PA5G_VBAT_GND3P3_C3 WRF_PAPMU_GND WRF_PADRV_VBAT_GND3P3 WRF_RX_GND1P2 WRF_TX_GND1P2 WRF_VCO_GND1P2 WRF_XTAL_CAB_GND1P2 VSS_J8 VSS_J10 VSS_K8 VSS_K10 VSS_K11 VSS_L8 VSS_L9 VSS_L10 VSS_L11 VSS_M8 VSS_M9 VSS_M10 VSS_M11 VSS_N7 VSS_N8 VSS_N9 VSS_N10 VSS_N11 VSS_P6 VSS_P7 VSS_P8 VSS_P9 VSS_P10 I I I I I I I I I I Synth ground AFE ground 2 GHz internal LNA ground 5 GHz internal LNA ground 2.4 GHz PA ground 5 GHz PA ground I I I I I I I I I I I I I I I I I I I I I I I I I I I I I PMU ground PA driver ground RX ground TX ground VCO/LOGEN ground XTAL ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Broadcom® January 28, 2015 • 43340-DS109-R Core ground for WLAN and BT BROADCOM CONFIDENTIAL Page 91 Signal Descriptions BCM43340 Data Sheet Table 18: WLBGA Signal Descriptions (Cont.) WLBGA Ball Signal Name Type Description P11 VSS_P11 I Ground NC_G9 NC_J9 NC_J11 NC_K7 NC_K9 NC_L7 NC_M7 – – – – – – – No Connect No Connect G9 J9 J11 K7 K9 L7 M7 Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 92 Signal Descriptions BCM43340 Data Sheet WLAN GPIO Signals and Strapping Options The pins listed in Table 19 on page 93 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kΩ resistor or less. Note: Refer to the reference board schematics for more information. Table 19: WLAN GPIO Functions and Strapping Options (Advance Information) Pin Name WLBG A Pin # Default Function Description SDIO_DATA_1 F9 0 The three strap pins strap_host_ifc_[3:1] select the host interfacea to enable: • 0XX: SDIO SDIO_DATA_2 strap_host_ifc_1 • 10X: gSPI • 110: normal HSIC • 111: bootloader-less HSIC 0: select gSPI mode G8 0 strap_host_ifc_2 • • 1: select SDIO mode GPIO_6/ J6 SPI_MODE_SEL 0 strap_host_ifc_3 • 0: select SDIO mode • 1: select HSIC mode JTAG_SEL N/A • JTAG select: Connect this pin high (VDDIO) in order to use GPIO_2 through GPIO_5 and GPIO_12 as JTAG signals. Otherwise, if this pin is left as a NO_CONNECT, its internal Pull-down selects the default mode that allows GPIOs 2, 3, 4, 5, and 12 to be used as GPIOs. M4 JTAG select Note: See “WLAN GPIO Interface” on page 86 for the JTAG signal pins. a. The unused host interface is tristated. However, the SDIO lines have internal pulls activated when in HSIC mode (see Table 21: “I/O States,” on page 95). There are no bus-keepers on the HSIC interface when it is not in use. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 93 Signal Descriptions BCM43340 Data Sheet CIS Select Options CIS select options are defined in Table 20. Table 20: CIS Select OTPEnabled CIS Source OTP State ChipID Source 0 Default OFF Default 1 OTP if programmed, else default ON OTP if programmed, else default Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 94 I/O States BCM43340 Data Sheet I/O States The following notations are used in Table 21: • I: Input signal • O: Output signal • I/O: Input/Output signal • PU = Pulled up • PD = Pulled down • NoPull = Neither pulled up nor pulled down Table 21: I/O States Low Power State/ Sleep (All Power Present) Power-down (BT_REG_ON and WL_REG_ON Held Low) Out-of-Reset; Before SW Download (WL_REG_ON=1 and BT_REG_ON=0) and (BT_REG_ON=1; VDDIOs Are Present WL_REG_ON=1) (WL_REG_ON=0 and BT_REG_ON=1) and VDDIOs Are Present Power Rail Name I/O Keeper Active Mode WL_REG_ON I N Input; PD (pull-down can Input; PD (pull-down can Input; PD (of 200K) be disabled) be disabled) Input; PD (of 200k) Input; PD (of 200k) – – BT_REG_ON I N Input; PD (pull down can Input; PD (pull down can Input; PD (of 200K) be disabled) be disabled) Input; PD (of 200k) Input; PD (of 200k) – – CLK_REQ I/O Y Open drain or push-pull Open drain or push-pull PD (programmable). Active (programmable). Active high. high Open drain. Active high. Open drain. Active high. – BT_VDDO BT_HOST_WAK I/O Y E I/O; PU, PD, NoPull (programmable) I/O; PU, PD, NoPull (programmable) High-Z, NoPull Input, PD Input, PD – BT_VDDO BT_DEV_WAKE I/O Y I/O; PU, PD, NoPull (programmable) Input; PU, PD, NoPull (programmable) High-Z, NoPull Input, PD Input, PD – BT_VDDO BT_UART_CTS I Y Input; NoPull Input; NoPull High-Z, NoPull Input; PU Input; PU – BT_VDDO BT_UART_RTS O Y Output; NoPull Output; NoPull High-Z, NoPull Input; PU Input; PU – BT_VDDO BT_UART_RXD I Y Input; PU Input; NoPull High-Z, NoPull Input; PU Input; PU – BT_VDDO BT_UART_TXD O Y Output; NoPull Output; NoPull High-Z, NoPull Input; PU Input; PU – BT_VDDO SDIO_DATA_0 I/O N HSIC MODE -> PU; SDIO MODE -> NoPull HSIC MODE -> PU; SDIO MODE -> NoPull HSIC MODE -> NoPull; HSIC MODE -> PU; HSIC MODE -> PU; SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull – WL_VDDI O Broadcom® January 28, 2015 • 43340-DS109-R Page 95 BROADCOM CONFIDENTIAL I/O States BCM43340 Data Sheet Table 21: I/O States (Cont.) Low Power State/ Sleep (All Power Present) Power-down (BT_REG_ON and WL_REG_ON Held Low) Out-of-Reset; Before SW Download (WL_REG_ON=1 and BT_REG_ON=0) and (BT_REG_ON=1; VDDIOs Are Present WL_REG_ON=1) (WL_REG_ON=0 and BT_REG_ON=1) and VDDIOs Are Present Power Rail Name I/O Keeper Active Mode SDIO_DATA_1 I/O N HSIC MODE -> PD; SDIO MODE -> NoPull HSIC MODE -> PD; SDIO MODE -> NoPull HSIC MODE -> NoPull; HSIC MODE -> PD; SDIO MODE -> NoPull SDIO MODE -> PD HSIC MODE -> PD; SDIO MODE -> NoPull – WL_VDDI O SDIO_DATA_2 I/O N HSIC MODE -> PU; SDIO MODE -> NoPull HSIC MODE -> PU; SDIO MODE -> NoPull HSIC MODE -> NoPull; HSIC MODE -> PU; SDIO MODE -> NoPull SDIO MODE -> PD HSIC MODE -> PU; SDIO MODE -> NoPull – WL_VDDI O SDIO_DATA_3 I/O N HSIC MODE -> PU; SDIO MODE -> NoPull HSIC MODE -> PU; SDIO MODE -> NoPull HSIC MODE -> NoPull; HSIC MODE -> PU; HSIC MODE -> PU; SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull – WL_VDDI O SDIO_CMD I/O N HSIC MODE -> PU; SDIO MODE -> NoPull HSIC MODE -> PU; SDIO MODE -> NoPull HSIC MODE -> NoPull; HSIC MODE -> PU; HSIC MODE -> PU; SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull – WL_VDDI O SDIO_CLK I HSIC MODE -> PD; SDIO MODE -> NoPull HSIC MODE -> PD; SDIO MODE -> NoPull HSIC MODE -> NoPull; HSIC MODE -> PD; HSIC MODE -> PD; SDIO MODE -> NoPull SDIO MODE -> NoPull SDIO MODE -> NoPull – WL_VDDI O BT_PCM_CLK I/O Y Input; NoPull (Note 4) Input; NoPull (Note 4) High-Z, NoPull Input, PD Input, PD – BT_VDDO BT_PCM_IN I/O Y Input; NoPull (Note 4) Input; NoPull (Note 4) High-Z, NoPull Input, PD Input, PD – BT_VDDO BT_PCM_OUT I/O Y Input; NoPull (Note 4) Input; NoPull (Note 4) High-Z, NoPull Input, PD Input, PD – BT_VDDO BT_PCM_SYNC I/O Y Input; NoPull (Note 4) Input; NoPull (Note 4) High-Z, NoPull Input, PD Input, PD – BT_VDDO BT_I2S_WS I/O Y Input; NoPull (Note 5) Input; NoPull (Note 5) High-Z, NoPull Input, PD Input, PD – BT_VDDO BT_I2S_CLK I/O Y Input; NoPull (Note 5) Input; NoPull (Note 5) High-Z, NoPull Input, PD Input, PD – BT_VDDO BT_I2S_DO I/O Y Input; NoPull (Note 5) Input; NoPull (Note 5) High-Z, NoPull Input, PD Input, PD – BT_VDDO JTAG_SEL I Y PD PD PD PD PD PD WL_VDDI O GPIO_0 I/O Y PD PD NoPull PD PD PD WL_VDDI O GPIO_1 I/O Y NoPull NoPull NoPull NoPull NoPull NoPull WL_VDDI O GPIO_2 I/O Y PU PU NoPull PU PU PU WL_VDDI O GPIO_3 I/O Y JTAG_SEL = 1 PU; jtag_sel=0 PD jtag_sel=1 PU; jtag_sel=0 PD NoPull jtag_sel=1 PU; jtag_sel=0 PD jtag_sel=1 PU; jtag_sel=0 PD jtag_sel = 1 PU; WL_VDDI O jtag_sel=1 PU; jtag_sel=0 PD jtag_sel=1 PU; jtag_sel=0 PD NoPull jtag_sel=1 PU; jtag_sel=0 PD jtag_sel=1 PU; jtag_sel=0 PD jtag_sel = 1 PU; GPIO_4 N I/O Y Broadcom® January 28, 2015 • 43340-DS109-R jtag_sel = 0 PD jtag_sel = 0 PD WL_VDDI O Page 96 BROADCOM CONFIDENTIAL I/O States BCM43340 Data Sheet Table 21: I/O States (Cont.) Power-down (BT_REG_ON and WL_REG_ON Held Low) Out-of-Reset; Before SW Download (WL_REG_ON=1 and BT_REG_ON=0) and (BT_REG_ON=1; VDDIOs Are Present WL_REG_ON=1) (WL_REG_ON=0 and BT_REG_ON=1) and VDDIOs Are Present Name I/O Keeper Active Mode Low Power State/ Sleep (All Power Present) GPIO_5 I/O Y NoPull NoPull NoPull NoPull NoPull NoPull WL_VDDI O GPIO_6 I/O Y PD PD NoPull PD PD PD WL_VDDI O GPIO_12 I/O Y jtag_sel=1 PU; jtag_sel=0 PD jtag_sel=1 PU; jtag_sel=0 PD NoPull jtag_sel=1 PU; jtag_sel=0 PD jtag_sel=1 PU; jtag_sel=0 PD PU WL_VDDI O Power Rail Note: 1. Keeper column: N=pad has no keeper. Y=pad has a keeper. Keeper is always active except in Power-down state. 2. If there is no keeper, and it is an input and there is Nopull, then the pad should be driven to prevent leakage due to floating pad (e.g., SDIO_CLK). 3. In the Power-down state (xx_REG_ON=0): High-Z; NoPull => the pad is disabled because power is not supplied. 4. Depending on whether the PCM interface is enabled and the configuration of PCM is in master or slave mode, it can be either output or input. 5. Depending on whether the I2S interface is enabled and the configuration of I2S is in master or slave mode, it can be either output or input. 6. GPIO_6 is input-only during the Low-Power and Deep-Sleep modes. 7. GPIO_0 through GPIO_5 and GPIO_12 can be configured to operate as inputs or outputs in Deep-Sleep mode before entering the mode. 8. The GPIO pull states for the Active and Low-Power states are hardware defaults. They can all be subsequently programmed as pull-ups or pull-downs. 9. Regarding GPIO pins, the following are the pull-up and pull-down values for both 3.3V and 1.8V VDDIO: Minimum (kΩ) 3.3V VDDIO, Pull-downs: 51.5 3.3V VDDIO, Pull-ups: 37.4 1.8V VDDIO, Pull-downs: 64 1.8V VDDIO, Pull-ups: 65 Typical (kΩ) 44.5 39.5 83 86 Broadcom® January 28, 2015 • 43340-DS109-R Maximum (kΩ) 38 44.5 116 118 Page 97 BROADCOM CONFIDENTIAL DC Characteristics BCM43340 Data Sheet S e c t i o n 1 4 : D C C h a r a c t e ri s t i c s Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 22 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. Table 22: Absolute Maximum Ratings Rating Symbol Value Unit DC supply for VBAT and PA driver supply: VBAT –0.5 to +6.0 V DC supply voltage for digital I/O VDDIO –0.5 to 3.9 V DC supply voltage for RF switch I/Os VDDIO_RF –0.5 to 3.9 V DC input supply voltage for – CLDO and LNLDO1 –0.5 to 1.575 V DC supply voltage for RF analog –0.5 to 1.32 V VDDRF DC supply voltage for core VDDC –0.5 to 1.32 V WRF_TCXO_VDD – –0.5 to 3.63 V Maximum undershoot voltage for I/O Vundershoot –0.5 V Maximum overshoot voltage for I/O Vovershoot 0.5 V Maximum Junction Temperature Tj 125 °C Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 98 Environmental Ratings BCM43340 Data Sheet Environmental Ratings The environmental ratings are shown in Table 23. Table 23: Environmental Ratings Characteristic Value Units Conditions/Comments Ambient Temperature (TA) –30 to +85 °C Functional operationa Storage Temperature –40 to +125 °C – Relative Humidity Less than 60 % Storage Less than 85 % Operation a. Functionality is guaranteed but specifications require derating at extreme temperatures; see the specification tables for details. Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging. Table 24: ESD Specifications Pin Type Symbol Condition ESD Rating Unit ESD_HAND_HBM Human body model contact discharge per ESD, Handling JEDEC EID/JESD22-A114 Reference: NQY00083, Section 3.4, Group D9, Table B 2000 V Machine Model (MM) ESD_HAND_MM Machine model contact 100 V CDM ESD_HAND_CDM Charged device model contact discharge per JEDEC EIA/JESD22-C101 500 V Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 99 Recommended Operating Conditions and DC Characteristics BCM43340 Data Sheet Recommended Operating Conditions and DC Characteristics Caution! Functional operation is not guaranteed outside of the limits shown in Table 25 and operation outside these limits for extended periods can adversely affect long-term reliability of the device. Table 25: Recommended Operating Conditions and DC Characteristics Value Parameter Symbol Minimum Typical Maximum Unit DC supply voltage for VBAT VBAT 2.9a – 4.8b V DC supply voltage for core VDD 1.14 1.2 1.26 V 1.14 1.2 1.26 V DC supply voltage for TCXO input buffer WRF_TCXO_VD 1.62 D 1.8 1.98 V DC supply voltage for digital I/O VDDIO, VDDIO_SD 1.71 – 3.63 V DC supply voltage for RF switch I/Os VDDIO_RF 3.13 3.3 3.46 V Internal POR threshold Vth_POR 0.4 – 0.7 V Input high voltage VIH 1.27 – – V Input low voltage VIL – – 0.58 V DC supply voltage for RF blocks in chip VDDRF SDIO Interface I/O Pins For VDDIO_SD = 1.8V: Output high voltage @ 2 mA VOH 1.40 – – V Output low voltage @ 2 mA VOL – – 0.45 V VIH 0.625 × VDDIO – – V 0.25 × VDDIO V For VDDIO_SD = 3.3V: Input high voltage Input low voltage VIL – Output high voltage @ 2 mA VOH 0.75 × VDDIO – - Output low voltage @ 2 mA VOL – 0.125 × VDDIO V Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL – – V Page 100 Recommended Operating Conditions and DC Characteristics BCM43340 Data Sheet Table 25: Recommended Operating Conditions and DC Characteristics (Cont.) Value Parameter Symbol Minimum Input high voltage VIH Input low voltage VIL Typical Maximum Unit 0.65 × VDDIO – – V - 0.35 × VDDIO V Other Digital I/O Pins For VDDIO = 1.8V: – Output high voltage @ 2 mA VOH VDDIO – 0.45 – – V Output low voltage @ 2 mA VOL – – 0.45 V Input high voltage VIH 2.00 – – V Input low voltage VIL – – 0.80 V Output high voltage @ 2 mA VOH VDDIO – 0.4 – – V Output low voltage @ 2 mA VOL – – 0.40 V Output high voltage VOH VDDIO – 0.4 – – V Output low voltage VOL – – 0.40 V CIN – – 5 pF For VDDIO = 3.3V: RF Switch Control Output Pinsc For VDDIO_RF = 3.3V: Input capacitance a. The BCM43340 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3.0V < VBAT < 4.8V. b. The maximum continuous voltage is 4.8V. Voltages up to 5.5V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 101 Bluetooth RF Specifications BCM43340 Data Sheet S e c t i o n 1 5 : B l u e t o o t h R F Sp e c i f i c a t i o n s Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified in Table 23: “Environmental Ratings,” on page 99 and Table 25: “Recommended Operating Conditions and DC Characteristics,” on page 100. Typical values apply for the following conditions: • VBAT = 3.6V • Ambient temperature +25°C Figure 40: RF Port Location for Bluetooth Testing BCM43340 2.4 GHz WLAN + BT Tx/Rx Filter Chip Port Antenna Port Note: All Bluetooth specifications are measured at the Chip port unless otherwise specified. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 102 Bluetooth RF Specifications BCM43340 Data Sheet Table 26: Bluetooth Receiver RF Specifications Parameter Conditions Minimum Typical Maximum Unit Note: The specifications in this table are measured at the Chip port output unless otherwise specified. General Frequency range – RX sensitivity 2402 – 2480 MHz GFSK, 0.1% BER, 1 Mbps – –92.5 – dBm /4–DQPSK, 0.01% BER, 2 Mbps – –94.5 – dBm 8–DPSK, 0.01% BER, 3 Mbps – –88.5 – dBm Input IP3 – –16 – – dBm Maximum input at antenna – – – –20 dBm C/I co-channel GFSK, 0.1% BER – – 11 dB C/I 1-MHz adjacent channel GFSK, 0.1% BER – – 0.0 dB C/I 2-MHz adjacent channel GFSK, 0.1% BER – – –30 dB C/I  3-MHz adjacent channel GFSK, 0.1% BER – – –40 dB C/I image channel GFSK, 0.1% BER – – –9 dB C/I 1-MHz adjacent to image channel GFSK, 0.1% BER – – –20 dB C/I co-channel /4–DQPSK, 0.1% BER – – 13 dB C/I 1-MHz adjacent channel /4–DQPSK, 0.1% BER – – 0.0 dB C/I 2-MHz adjacent channel Interference Performancea /4–DQPSK, 0.1% BER – – –30 dB C/I  3-MHz adjacent channel /4–DQPSK, 0.1% BER – – –40 dB C/I image channel /4–DQPSK, 0.1% BER – – –7 dB C/I 1-MHz adjacent to image channel /4–DQPSK, 0.1% BER – – –20 dB C/I co-channel 8–DPSK, 0.1% BER – – 21 dB C/I 1 MHz adjacent channel 8–DPSK, 0.1% BER – – 5.0 dB C/I 2 MHz adjacent channel 8–DPSK, 0.1% BER – – –25 dB C/I  3-MHz adjacent channel 8–DPSK, 0.1% BER – – –33 dB C/I Image channel 8–DPSK, 0.1% BER – – 0.0 dB C/I 1-MHz adjacent to image channel 8–DPSK, 0.1% BER – – –13 dB Out-of-Band Blocking Performance (CW) 30–2000 MHz 0.1% BER – –10.0 – dBm 2000–2399 MHz 0.1% BER – –27 – dBm 2498–3000 MHz 0.1% BER – –27 – dBm 3000 MHz–12.75 GHz 0.1% BER – –10.0 – dBm Out-of-Band Blocking Performance, Modulated Interferer (LTE) Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 103 Bluetooth RF Specifications BCM43340 Data Sheet Table 26: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit GFSK (1 Mbps) 2310Mhz LTE band40 TDD 20M BW – –20 – dBm 2330MHz LTE band40 TDD 20M BW – –21 – dBm 2350MHz LTE band40 TDD 20M BW – –22 – dBm 2370MHz LTE band40 TDD 20M BW – –23 – dBm 2510MHz LTE band7 FDD 20M BW – –26 – dBm 2530MHz LTE band7 FDD 20M BW – –25 – dBm 2550MHz LTE band7 FDD 20M BW – –25 – dBm 2570MHz LTE band7 FDD 20M BW – –24 – dBm  /4 DPSK (2 Mbps) 2310Mhz LTE band40 TDD 20M BW – –20 – dBm 2330MHz LTE band40 TDD 20M BW – –20 – dBm 2350MHz LTE band40 TDD 20M BW – –22 – dBm 2370MHz LTE band40 TDD 20M BW – –23 – dBm 2510MHz LTE band7 FDD 20M BW – –26 – dBm 2530MHz LTE band7 FDD 20M BW – –25 – dBm 2550MHz LTE band7 FDD 20M BW – –25 – dBm 2570MHz LTE band7 FDD 20M BW – –24 – dBm 8DPSK (3 Mbps) 2310Mhz LTE band40 TDD 20M BW – –21 – dBm 2330MHz LTE band40 TDD 20M BW – –21 – dBm 2350MHz LTE band40 TDD 20M BW – –23 – dBm 2370MHz LTE band40 TDD 20M BW – –24 – dBm 2510MHz LTE band7 FDD 20M BW – –26 – dBm 2530MHz LTE band7 FDD 20M BW – –25 – dBm 2550MHz LTE band7 FDD 20M BW – –25 – dBm 2570MHz LTE band7 FDD 20M BW – –24 – dBm Out-of-Band Blocking Performance, Modulated Interferer (Non-LTE) GFSK (1 Mbps)a 698–716 MHz WCDMA – –13 – dBm 776–849 MHz WCDMA – –13 – dBm 824–849 MHz GSM850 – –13 – dBm 824–849 MHz WCDMA – –13 – dBm 880–915 MHz E-GSM – –13 – dBm 880–915 MHz WCDMA – –13 – dBm 1710–1785 MHz GSM1800 – –19 – dBm 1710–1785 MHz WCDMA – –19 – dBm 1850–1910 MHz GSM1900 – –20 – dBm Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 104 Bluetooth RF Specifications BCM43340 Data Sheet Table 26: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 1850–1910 MHz WCDMA – –20 – dBm 1880–1920 MHz TD-SCDMA – –20 – dBm 1920–1980 MHz WCDMA – –20 – dBm 2010–2025 MHz TD–SCDMA – –21 – dBm 2500–2570 MHz WCDMA – –23 – dBm  /4 DPSK (2 Mbps) a 698–716 MHz WCDMA – –11 – dBm 776–794 MHz WCDMA – –11 – dBm 824–849 MHz GSM850 – –12 – dBm 824–849 MHz WCDMA – –12 – dBm 880–915 MHz E-GSM – –12 – dBm 880–915 MHz WCDMA – –12 – dBm 1710–1785 MHz GSM1800 – –17 – dBm 1710–1785 MHz WCDMA – –17 – dBm 1850–1910 MHz GSM1900 – –19 – dBm 1850–1910 MHz WCDMA – –18 – dBm 1880–1920 MHz TD-SCDMA – –19 – dBm 1920–1980 MHz WCDMA – –19 – dBm 2010–2025 MHz TD-SCDMA – –21 – dBm 2500–2570 MHz WCDMA – –23 – dBm 8DPSK (3 Mbps) a 698–716 MHz WCDMA – –13 – dBm 776–794 MHz WCDMA – –12 – dBm 824–849 MHz GSM850 – –13 – dBm 824–849 MHz WCDMA – –13 – dBm 880–915 MHz E-GSM – –13 – dBm 880–915 MHz WCDMA – –13 – dBm 1710–1785 MHz GSM1800 – –18 – dBm 1710–1785 MHz WCDMA – –18 – dBm 1850–1910 MHz GSM1900 – –20 – dBm 1850–1910 MHz WCDMA – –19 – dBm 1880–1920 MHz TD-SCDMA – –20 – dBm 1920–1980 MHz WCDMA – –20 – dBm 2010–2025 MHz TD-SCDMA – –21 – dBm 2500–2570 MHz WCDMA – –24 – dBm – – –90.0 –80.0 dBm RX LO Leakage 2.4 GHz band Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 105 Bluetooth RF Specifications BCM43340 Data Sheet Table 26: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 30 MHz–1 GHz – –95 –62 dBm 1–12.75 GHz – –70 –47 dBm 869–894 MHz – –147 – dBm/Hz 925–960 MHz – –147 – dBm/Hz 1805–1880 MHz – –147 – dBm/Hz 1930–1990 MHz – –147 – dBm/Hz 2110–2170 MHz – –147 – dBm/Hz Spurious Emissions a. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 106 Bluetooth RF Specifications BCM43340 Data Sheet Table 27: Bluetooth Transmitter RF Specificationsa Parameter Conditions Minimum Typical Maximum Unit General Frequency range Basic rate (GFSK) TX power at Bluetooth QPSK TX Power at Bluetooth 8PSK TX Power at Bluetooth Power control step 2402 – – – 2 – 11.0 8.0 8.0 4 2480 – – – 8 MHz dBm dBm dBm dB – .93 1 MHz M – N = the frequency range for – which the spurious emission is – measured relative to the – transmit center frequency. –38 –31 –43 –26.0 –20.0 –40.0 dBc dBm dBm GFSK In-Band Spurious Emissions –20 dBc BW – EDR In-Band Spurious Emissions 1.0 MHz < |M – N| < 1.5 MHz 1.5 MHz < |M – N| < 2.5 MHz |M – N|  2.5 MHzb Out-of-Band Spurious Emissions 30 MHz to 1 GHz – – – –36.0 c,d dBm 1 GHz to 12.75 GHz – – – dBm 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz – – – – – – –30.0 d,e,f –47.0 –47.0 dBm dBm – – –103 – dBm FM RX CDMA2000 cdmaOne, GSM850 E-GSM GPS GSM1800 GSM1900, cdmaOne, WCDMA WCDMA – – – – – – – – –147 –147 –147 –147 –146 –145 –144 –141 – – – – – – – – dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBm/Hz GPS Band Spurious Emissions Spurious emissions Out-of-Band Noise Floorg 65–108 MHz 776–794 MHz 869–960 MHz 925–960 MHz 1570–1580 MHz 1805–1880 MHz 1930–1990 MHz 2110–2170 MHz a. Unless otherwise specified, the specifications in this table are measured at the chip output port, and output power specifications are with the temperature correction algorithm and TSSI enabled. b. Typically measured at an offset of ±3 MHz. c. The maximum value represents the value required for Bluetooth qualification as defined in the v4.0 specification. d. The spurious emissions during Idle mode are the same as specified in Table 27 on page 107. e. Specified at the Bluetooth Antenna port. f. Meets this specification using a front-end band-pass filter. g. Transmitted power in cellular and FM bands at the Bluetooth Antenna port. See Figure 40 on page 102 for location of the port. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 107 Bluetooth RF Specifications BCM43340 Data Sheet Table 28: Local Oscillator Performance Parameter Minimum Typical Maximum Unit LO Performance Lock time – 72 – s Initial carrier frequency tolerance – ±25 ±75 kHz DH1 packet – ±8 ±25 kHz DH3 packet – ±8 ±40 kHz DH5 packet – ±8 ±40 kHz Drift rate – 5 20 kHz/50 µs 00001111 sequence in payloada 140 155 175 kHz 10101010 sequence in payloadb 115 140 – kHz Channel spacing – 1 – MHz Frequency Drift Frequency Deviation a. This pattern represents an average deviation in payload. b. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. Table 29: BLE RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range – 2402 2480 MHz RX sensea GFSK, 0.1% BER, 1 Mbps – –94.5 – dBm TX powerb – – 8.5 – dBm – 225 255 275 kHz – 99.9 – – % – 0.8 0.95 – % Mod Char: delta f1 average Mod Char: delta f2 max Mod Char: ratio c a. The Bluetooth tester is set so that Dirty TX is on. b. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, and so forth). The output is capped at 12 dBm out. The BLE TX power at the antenna port cannot exceed the 10 dBm specification limit. c. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 108 FM Receiver Specifications BCM43340 Data Sheet S e c t i o n 1 6 : F M R e c e i v e r Sp e c i f i c a t i o n s Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified inTable 23: “Environmental Ratings,” on page 99 and Table 25: “Recommended Operating Conditions and DC Characteristics,” on page 100. Typical values apply for the following conditions: • VBAT = 3.6V • Ambient temperature +25°C Table 30: FM Receiver Specifications Parameter Conditionsa Minimum Typical Maximum Units RF Parameters Operating frequencyb Frequencies inclusive Sensitivityc Receiver adjacent channel selectivityc,d FM only, SNR ≥ 26 dB 65 – 108 MHz – –0.5 – dBµV EMF – 0.95 – µV EMF – –6.5 – dBµV Measured for 30 dB SNR at audio output. Signal of interest: 23 dBµV EMF (14.1 µV EMF) At ±200 kHz. – 51 – dB At ±300 kHz. – 62 – dB 45 53 – dB Intermediate signal Vin = 20 dBµV (10 µV EMF) plus noise-to-noise ratio (S + N)/N, stereoc Intermodulation performancec,d Blocker level increased until desired at – 30 dB SNR Wanted Signal: 33 dBµV EMF (45 µV EMF) Modulated Interferer: At fWanted + 400 kHz and +4 MHz CW Interferer: At fWanted + 800 kHz and + 8 MHz 55 – dBc AM suppression, monoc Vin = 23 dBµV EMF (14.1 µV EMF). 40 AM at 400 Hz with m = 0.3. No A-weighted or any other filtering applied. – – dB Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 109 FM Receiver Specifications BCM43340 Data Sheet Table 30: FM Receiver Specifications (Cont.) Parameter Conditionsa Minimum Typical Maximum Units RDS deviation = 1.2 kHz – 16 – dBµV EMF – 6.3 – µV EMF RDS RDS sensitivitye,f RDS deviation = 2 kHz RDS selectivity f – 10 – dBµV – 12 – dBµV EMF – 4 – µV EMF – 6 – dBµV Wanted Signal: 33 dBµV EMF (45 µV EMF), 2 kHz RDS deviation Interferer: Δf = 40 kHz, fmod = 1 kHz ±200 kHz – 49 – dB ±300 kHz – 52 – dB ±400 kHz – 52 – dB RF Input RF input impedance – 1.5 – – kΩ Antenna tuning cap – 2.5 – 30 pF Maximum input levelc SNR > 26 dB – – 113 dBµV EMF – – 446 mV EMF – – 107 dBµV Local oscillator breakthrough measured on – the reference port – –55 dBm 869–894 MHz, 925–960 MHz, 1805–1880 MHz, and 1930–1990 MHz. GPS. – –90 dBm RF conducted emissions Broadcom® January 28, 2015 • 43340-DS109-R – BROADCOM CONFIDENTIAL Page 110 FM Receiver Specifications BCM43340 Data Sheet Table 30: FM Receiver Specifications (Cont.) Parameter Conditionsa RF blocking levels at the FM antenna input with a 40 dB SNR (assumes a 50Ω input and excludes spurs) GSM850, E-GSM (standard); BW = 0.2 MHz. – 824–849 MHz, 880–915 MHz. 7 – dBm GSM 850, E-GSM (edge); BW = 0.2 MHz. 824–849 MHz, 880–915 MHz. – 0 – dBm GSM DCS 1800, PCS 1900 (standard, edge); BW = 0.2 MHz. 1710–1785 MHz, 1850–1910 MHz. – 12 – dBm WCDMA: II (I), III (IV,X); BW = 5 MHz. 1710–1785 MHz (1710–1755 MHz, 1710–1770 MHz), 1850–1980 MHz (1920–1980 MHz). – 12 – dBm WCDMA: V (VI), VIII, XII, XIII, XIV; BW = 5 MHz. 824–849 MHz (830–840 MHz), 880–915 MHz. – 5 – dBm CDMA2000, CDMA One; BW = 1.25 MHz. 776–794 MHz, 824–849 MHz, 887–925 MHz. – 0 – dBm CDMA2000, CDMA One; BW= 1.25 MHz. 1750–1780 MHz, 1850–1910 MHz, 1920–1980 MHz. – 12 – dBm Bluetooth; BW = 1 MHz. 2402–2480 MHz. – 11 – dBm LTE, Band 38, Band 40, XGP Band – 11 – dBm WLAN-g/b; BW = 20 MHz. 2400–2483.5 MHz. – 11 – dBm WLAN-a; BW = 20 MHz. 4915–5825 MHz. – 6 – dBm Frequency step – 10 – – kHz Settling time Single frequency switch in any direction to a – frequency within the 88–108 MHz or 76–90 MHz bands. Time measured to within 5 kHz of the final frequency. 150 – µs Search time Total time for an automatic search to sweep – from 88–108 MHz or 76–90 MHz (or in the reverse direction) assuming no channels are found. – 8 sec Minimum Typical Maximum Units Tuning Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 111 FM Receiver Specifications BCM43340 Data Sheet Table 30: FM Receiver Specifications (Cont.) Conditionsa Minimum Typical Maximum Units Audio output levelg – –14.5 – –12.5 dBFS Maximum audio output levelh – – – 0 dBFS DAC audio output level Conditions: Vin = 66 dBµV EMF (2 mV EMF), Δf = 22.5 kHz, fmod = 1 kHz, Δf Pilot = 6.75 kHz 72 – 88 mVrms Maximum DAC audio – output levelh – 333 – mVrms Audio DAC output level differencei –1 – 1 dB Left and right AC mute FM input signal fully muted with DAC enabled 60 – – dB Left and right hard mute 80 – – dB Parameter General Audio – FM input signal fully muted with DAC disabled Soft mute attenuation Muting is performed dynamically, proportional to the desired FM input signal C/N. The and start level muting characteristic is fully programmable. See “Audio Features” on page 60. Maximum signal plus – noise-to-noise ratio (S + N)/N, monoi – 69 – dB Maximum signal plus – noise-to-noise ratio (S + N)/N, stereog – 64 – dB Δf = 75 kHz, fmod = 400 Hz. – – 0.8 % Δf = 75 kHz, fmod = 1 kHz. – – 0.8 % Δf = 75 kHz, fmod = 3 kHz. – – 0.8 % Total harmonic distortion, mono Vin = 66 dBµV EMF(2 mV EMF): Δf = 100 kHz, fmod = 1 kHz. – – 1.0 % Total harmonic distortion, stereo Vin = 66 dBµV EMF (2 mV EMF), Δf = 67.5 kHz, fmod = 1 kHz, ∆f pilot = 6.75 kHz, L = R – – 1.5 % Audio spurious productsi Range from 300 Hz to 15 kHz with respect to a 1 kHz tone. – – –60 dBc Audio bandwidth, upper (–3 dB point) Vin = 66 dBµV EMF (2 mV EMF) Δf = 8 kHz, for 50 µs 15 – – kHz – – 20 Hz Audio bandwidth, lower (–3 dB point) Audio in-band ripple 100 Hz to 13 kHz, Vin = 66 dBµV EMF (2 mV EMF), Δf = 8 kHz, for 50 µs. –0.5 – 0.5 dB Deemphasis time constant tolerance With respect to 50 and 75 µs. – – ±5 % Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 112 FM Receiver Specifications BCM43340 Data Sheet Table 30: FM Receiver Specifications (Cont.) Parameter Conditionsa Minimum Typical Maximum Units RSSI range With 1 dB resolution and ±5 dB accuracy at room temperature. 3 – 83 dBµV EMF 1.41 – 1.41E+4 µV EMF –3 – 77 dBµV – 48 – dB Stereo Decoder Stereo channel separation Forced Stereo mode Vin = 66 dBµV EMF (2 mV EMF), Δf = 67.5 kHz, fmod = 1 kHz, ∆f Pilot = 6.75 kHz, R = 0, L = 1 Mono stereo blend and switching Dynamically proportional to the desired FM input signal C/N. The blending and switching characteristics are fully programmable. See “Audio Features” on page 60. Pilot suppression Vin = 66 dBµV EMF (2 mV EMF), Δf = 75 kHz, fmod = 1 kHz. 46 – – dB Audio level at which a pause is detected Relative to 1-kHz tone, Δf = 22.5 kHz. – – – – 4 values in 3 dB steps –21 – –12 dB Audio pause duration 4 values 20 – 40 ms Pause Detection a. The following conditions are applied to all relevant tests unless otherwise indicated: Preemphasis and deemphasis of 50 µs, R = L for mono, BAF = 300 Hz to 15 kHz, A-weighted filtering applied. b. Contact your Broadcom representative for applications operating between 65–76 MHz. c. Signal of interest: Δf = 22.5 kHz, fmod = 1 kHz. d. Interferer: Δf = 22.5 kHz, fmod = 1 kHz. e. RDS sensitivity numbers are for 87.5–108 MHz only. f. Vin = Δf = 32 kHz, fmod = 1 kHz, Δf pilot = 7.5 kHz, and with an interferer for 95% of blocks decoded with no errors after correction, over a sample of 5000 blocks. g. Vin = 66 dBµV EMF (2 mV EMF), Δf = 22.5 kHz, fmod = 1 kHz, Δf pilot = 6.75 kHz. h. Vin = 66 dBµV EMF (2 mV EMF), Δf = 100 kHz, fmod = 1 kHz, Δf pilot = 6.75 kHz. i. Vin = 66 dBµV EMF (2 mV EMF), Δf = 22.5 kHz, fmod = 1 kHz. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 113 WLAN RF Specifications BCM43340 Data Sheet S e c t i o n 1 7 : W L A N R F Sp e c i f i c a t i o n s Introduction The BCM43340 includes an integrated dual-band direct conversion radio that supports either the 2.4 GHz band or the 5 GHz band. The BCM43340 does not provide simultaneous 2.4 GHz and 5 GHz operation. This section describes the RF characteristics of the 2.4 GHz and 5 GHz portions of the radio. Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified inTable 23: “Environmental Ratings,” on page 99 and Table 25: “Recommended Operating Conditions and DC Characteristics,” on page 100. Typical values apply for the following conditions: • VBAT = 3.6V • Ambient temperature +25°C Figure 41: WLAN Port Locations (5 GHz) BCM43340 FEM or T/R Switch 5 GHz WLAN Chip Port Antenna Port Figure 42: WLAN Port Locations (2.4 GHz) BCM43340 2.4 GHz WLAN + BT Tx/Rx Filter Chip Port Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Antenna Port Page 114 2.4 GHz Band General RF Specifications BCM43340 Data Sheet Note: All WLAN specifications are measured at the chip port, unless otherwise specified. 2.4 GHz Band General RF Specifications Table 31: 2.4 GHz Band General RF Specifications Item Condition TX/RX switch time Including TX ramp down – RX/TX switch time Including TX ramp up Power-up and power-down ramp time Broadcom® January 28, 2015 • 43340-DS109-R Minimum Typical Maximum Unit – 5 µs – – 2 µs DSSS/CCK modulations – – 90% duty cycle, OFDM)a – 76–108 MHz 776–794 MHz 869–960 MHz 4900 – – – – < –168 –168 –170 5845 – – – MHz dBm/Hz dBm/Hz dBm/Hz – – – – –170 –168 –169 –169 – – – – dBm/Hz dBm/Hz dBm/Hz dBm/Hz – – – – –169 –166 –167 –48.6 – – – – dBm/Hz dBm/Hz dBm/Hz dBm/MHz – – – – – – 19 17 19.5 16.5 16.5 16.5 – – – – – – dBm dBm dBm dBm dBm dBm – 16.5 – dBm – 0.7 – Degrees 30 – – dB 15 – – – 0.25 6 – – – dBc dB dB Harmonic level (at 17 dBm) TX power at chip port for highest power level setting at 25°C, VBAT = 3.6V, spectral mask and EVM complianceb 925–960 MHz 1570–1580 MHz 1805–1880 MHz 1930–1990 MHz 2110–2170 MHz 2400–2483 MHz 2300–2690 9.8–11.570 GHz FM RX – cdmaOne, GSM850 E-GSM GPS GSM1800 GSM1900, cdmaOne, WCDMA WCDMA BT/WLAN LTE 2nd harmonic 6 Mbps 54 Mbps MCS0 (20 MHz) MCS7 (20 MHz) MCS7 (40 MHz) MCS7 (20 MHz, SGI) MCS7 (40 MHz, SGI) Phase noise 37.4 MHz crystal, Integrated from 10 kHz to 10 MHz TX power control dynamic – range Carrier suppression – Gain control step – Return loss Zo = 50Ω a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands. b. Derate by 2 dB for –30°C to –10°C and 55°C to 85°C. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 125 General Spurious Emissions Specifications BCM43340 Data Sheet General Spurious Emissions Specifications Table 36: General Spurious Emissions Specifications Parameter Condition/Notes Min Typ Max Unit Frequency range – 2400 – 2500 MHz – – –62 dBm 1 GHz < f < 12.75 GHz RBW = 1 MHz – – –47 dBm 1.8 GHz < f < 1.9 GHz RBW = 1 MHz – – –53 dBm 5.15 GHz < f < 5.3 GHz RBW = 1 MHz – – –53 dBm 30 MHz < f < 1 GHz – –78 –63 dBm 1 GHz < f < 12.75 GHz RBW = 1 MHz – –68.5a –53 dBm 1.8 GHz < f < 1.9 GHz RBW = 1 MHz – –96 –53 dBm 5.15 GHz < f < 5.3 GHz RBW = 1 MHz – –96 –53 dBm General Spurious Emissions TX Emissions RX/standby Emissions 30 MHz < f < 1 GHz RBW = 100 kHz RBW = 100 kHz a. For frequencies other than 3.2 GHz, the emissions value is –96 dBm. The value presented in table is the result of LO leakage at 3.2 GHz. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 126 Internal Regulator Electrical Specifications BCM43340 Data Sheet Section 18: Internal Regulator Electrical Sp e c i f ic a t i o n s Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Functional operation is not guaranteed outside of the specification limits provided in this section. Core Buck Switching Regulator Table 37: Core Buck Switching Regulator (CBUCK) Specifications Specification Notes Min Typ Max Units Input supply voltage (DC), VBAT PWM mode switching frequency, Fsw DC voltage range inclusive of disturbances. Forced PWM without FLL enabled. Forced PWM with FLL enabled. – 2.9 3.6 4.8a V 2.8 3.6 – 4 4 – 5.2 4.4 – Programmable, 30 mV steps. Default = 1.35V (bits = 0000). Includes load and line regulation. Forced PWM mode. Total DC accuracy after trim. Measure with 20 MHz BW limit. Static Load. Max ripple based on: VBAT < 4.8V, Vout = 1.35V, Fsw = 4 MHz, 2.2 µH inductor, L > 1.05 µH, capacitor + Board total-ESR < 20 mΩ, Cout > 1.9 µF, ESL < 200 pH. 2.5 x 2 mm LQM2HPN2R2NG0, L = 2 µH, DCR = 80 mΩ ±25%, ACR < 1Ω. 0805-size LQM21PN2R2NGC, L = 2.1 µH, DCR=230 mΩ ±25%, ACR < 2Ω. 0603-size MIPSTZ1608D2R2B, L = 1 µH, DCR = 240 mΩ ±25%, ACR < 2Ω. – 1.2 1390 1.35 372b – 1.5 MHz MHz mA –4 – 4 % –2 – – 7 2 20 % mVpp 79 85 – % 78 84 – % 74 81 – % PWM output current Output current limit Output voltage range PWM output voltage DC accuracy PWM ripple voltage, static PWM mode peak efficiency (Peak efficiency is at 200 mA load. The following conditions apply to all inductor types: Forced PWM, 200 mA, Vout = 1.35V, VBAT = 3.6V, Fsw = 4 MHz, at 25°C.) Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL mA Volts Page 127 Core Buck Switching Regulator BCM43340 Data Sheet Table 37: Core Buck Switching Regulator (CBUCK) Specifications (Cont.) Specification Notes Min Typ Max Units PFM mode efficiency 10 mA load current, Vout = 1.35V, VBAT = 3.6V, 20C Cap + Board total-ESR < 20 mΩ, Cout = 4.7 µF, ESL < 200 pH, FLL= OFF 0603-size MIPSTZ1608D2R2B, L = 2.2 µH, DCR = 240 mΩ ±25%, ACR < 2Ω. 1 mA load current, Vout = 1.35V, VBAT = 3.6V, 20C Cap + board total-ESR < 20 mΩ, Cout = 4.7 µF, ESL < 200 pH, FLL = OFF 0603-size MIPSTZ1608D2R2B, L = 2.2 µH, DCR = 240Ω ±25%, ACR < 2Ω. VIO already on and steady. Time from REG_ON rising edge to CLDO reaching 1.2V. Includes 256 µsec typical Vddc_ok_o delay. – 67 77 – % 55 65 – % – 903 1106 µs – 2.2 – µH 2d 4.7 – µF 0.67d 4.7 – µF 40 – 100,000 µs LPOM efficiency Start-up time from power down External inductor, Lc External output capacitor, Coutc Ceramic, X5R, 0402, ESR < 30 mΩ at 4 MHz, ±20%, 6.3V, 4.7 µF, Murata® GRM155R60J475M For SR_VDDBATP5V pin. External input capacitor, Cinc Ceramic, X5R, 0603, ESR < 30 mΩ at 4 MHz, ±20%, 6.3V, 4.7 µF, Murata GRM155R60J475M. Input supply voltage ramp-up 0 to 4.3V time a. The maximum continuous voltage is 4.8V. Voltages up to 5.5V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. At junction temperature 125°C. c. Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details. d. The minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, DCbias, temperature, and aging. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 128 3.3V LDO (LDO3P3) BCM43340 Data Sheet 3.3V LDO (LDO3P3) Table 38: LDO3P3 Specifications Parameters Conditions Min. Typ. Max. Units Input supply voltage, Minimum = Vo+0.2V = 3.5V (for Vo = 3.3V) 2.9 Vin dropout voltage requirement must be met under max load for performance specs. 3.6 4.8 V Nominal output voltage, Vo Default = 3.3V – 3.3 – V Output voltage programmability Range Accuracy at any step (including Line/Load regulation), load > 0.1 mA 2.4 –5 – 3.4 +5 V % Dropout voltage At maximum load – – 200 mV Output current – 0.001 – 450 mA Quiescent current No load; Vin = Vo + 0.2V Maximum load @ 450mA; Vin = Vo + 0.2V – 66 4 85 4.5 µA mA Leakage current Powerdown mode (at 85°C junction temperature) – 1.5 5 µA Line regulation Vin from (Vo + 0.2V) to 4.8V, maximum load – 3.5 mV/V Load regulation load from 1–450 mA, Vin = 3.6V – 0.3 0.45 mV/mA Load step error Load from 1mA-200mA-400mA in 1 q5s and 400mA-200mA-1mA in 1 µs; Vin ≥ (Vo + 0.2V); Co = 4.7 µF – – 70 mV PSRR VBAT ≥ 3.6V, Vo = 3.3V, Co = 4.7 µF, maximum load, 100 Hz to 100 kHz 20 – – dB 250 LDO turn-on time LDO turn-on time when rest of chip is up – 160 Output current limit – – 800 In-rush current Vin = Vo + 0.2V to 4.8V, Co = 4.7 µF, no load – External output capacitor, Co Ceramic, X5R, 0402, (ESR: 5m-240mohm), ±10%, 10V 1.0 External input capacitor For SR_VDDBATA5V pin (shared with Bandgap) ceramic, X5R, 0402, ±10%, 10V. Not needed if sharing VBAT cap 4.7 µF with SR_VDDBATP5V. – Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL µs mA 280 mA 4.7 5.64 µF 4.7 – µF Page 129 2.5V LDO (LDO2P5) BCM43340 Data Sheet 2.5V LDO (LDO2P5) Table 39: LDO2P5 Specifications Specification Notes Input supply voltage Min= 2.52+0.15=2.67V Dropout voltage requirement must be met under the maximum load for performance specifications. Min. Typ. Max. Unit 2.9 3.6 4.8 V Output current – – – 70 mA Output voltage, Vo default = 2.52V 2.4 2.52 3.4 V Dropout voltage at max load 150 mV Output voltage DC Accuracy include Line/Load regulation –5 +5 % Quiescent current No load – – µA Line regulation Vin from (Vo + 0.15V) to 4.8V, maximum load –11 11 mV Load Regulation Load from 1–70 mA (subject to parasitic resistance of package and board). Vin = 2.52 + 0.15V to 4.8V – 15 31 mV Leakage current Powerdown mode. At Junction Temp 85°C – – 5 µA PSRR VBAT ≥ 3.6V, Vo = 2.52V, Co = 2.2 µF, maximum load, 100 Hz to 100 kHz 20 – – dB LDO turn-on time LDO turn-on time when rest of chip is up – – 260 µs In-rush current during turn-on from its output capacitor in fully-discharged state – – 100 mA External output capacitor, Co Ceramic, X5R, 0402, (ESR: 5m-240mohm), ±20%, 6.3V 0.7a 2.2 2.64 µF External input capacitor For SR_VDDBATA5V pin (shared with Bandgap) ceramic, X5R, 0402, ±10%, 10V. Not needed if sharing the VBAT capacitor 4.7 µF with SR_VDDBATP5V. – 1 – µF 8 a. Minimum cap value refers to residual cap value after taking into account part–to–part tolerance, DC–bias, temperature, aging Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 130 HSICDVDD LDO BCM43340 Data Sheet HSICDVDD LDO Table 40: HISCDVDD LDO Specifications Specification Notes Min Typ Max Units Input supply voltage Min = 1.2V + 0.1V = 1.3V. Dropout voltage requirement must be met under maximum load for performance specifications. – Step size 25 mV. Default = 1.2V. 1.3 1.35 1.5 V – 1.1 – 1.2 80 1.275 mA V – 100 mV – 182 4 – % µA – – Output current Output voltage, Vo Dropout voltage Output voltage DC accuracy Quiescent current PSRR at 1 kHz PSRR at 10 kHz PSRR at 100 kHz At maximum load. Includes 100 mΩ – routing resistors at input and output. Including line/load regulation. –4 No load. Dependent on programming. – ldo_cntl_i[43], ldo_cntl_i[41] to support different external capacitor loads. Input ≥ 1.35V, 50 to 300 pF, Vo = 1.2V 24 Load: 80 mA 39 Load: 40 mA Input ≥ 1.35V, 50 to 300 pF, Vo = 1.2V Load: 80 mA Load: 40 mA Input ≥ 1.35V, 50 to 300 pF, Vo = 1.2V dB dB – – 24 38 dB dB – – dB dB 15 27 Output Capacitor, Co Broadcom® January 28, 2015 • 43340-DS109-R Load: 80 mA Load: 40 mA Internal capacitor = Sum of supply – decoupling caps and supply-to-ground routing parasitic capacitance. Output capacitor dependent on programming. BROADCOM CONFIDENTIAL 1000 – pF Page 131 CLDO BCM43340 Data Sheet CLDO Table 41: CLDO Specifications Specification Notes Min Typ Max Units Input supply voltage, Vin Min = 1.2 + 0.1V = 1.3V. Dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 V Output current – 0.1 – 150 mA Output voltage, Vo Programmable in 25 mV steps. Default = 1.2V, load from 0.1–150 mA 1.1 1.2 1.275 V Dropout voltage At max load – – 100 mV Output voltage DC accuracya Includes line/load regulation –4 – +4 % After trim, load from 0.1–150 mA, includes line/load regulation. Vin > Vo + 0.1V. –2 – +2 % Quiescent current No load – 10 – µA Line regulation Vin from (Vo + 0.1V) to 1.5V, maximum load – – 7 mV/V Load regulation Load from 1 mA to 150 mA – 15 25 µV/mA Leakage current Power-down – – 10 µA PSRR @1 kHz, Vin ≥ 1.5V, Co = 1 µF 20 – dB Start-up time of PMU VIO up and steady. Time from the REG_ON – rising edge to the CLDO reaching 1.2V. Includes 256 µs vddc_ok_o delay. – 1106 µs LDO turn-on time Chip already powered up. – – 180 µs In-rush current during turn-on From its output capacitor in a fully-discharged – state – 150 mA External output capacitor, Cob Total ESR: 30 mΩ–200 mΩ – µF External input capacitor Only use an external input capacitor at the – VDD_LDO pin if it is not supplied from the CBUCK output. Total ESR (trace/capacitor): 30 mΩ–200 mΩ – µF 0.67c 1 1 a. Load from 0.1 to 150 mA. b. Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details. c. The minimum value refers to the residual capacitor value after taking into account the part-to-part tolerance, DCbias, temperature, and aging. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 132 LNLDO BCM43340 Data Sheet LNLDO Table 42: LNLDO Specifications Specification Notes Min Typ Max Units Input supply voltage, Vin Min = 1.2Vo + 0.1V = 1.3V. 1.3 1.35 1.5 V Dropout voltage requirement must be met under maximum load. Output current – 0.1 – 104 mA Output voltage, Vo Programmable in 25 mV steps. Default = 1.2V 1.1 1.2 1.275 V Dropout voltage At maximum load – – 100 mV Output voltage DC accuracya includes line/load regulation, load from 0.1 –4 to 150 mA – +4 % Quiescent current No load – 44 – µA Line regulation Vin from (Vo + 0.1V) to 1.5V, max load – – 7 mV/V Load regulation Load from 1 mA to 104 mA – 15 25 µV/mA Leakage current Power-down – – 10 µA Output noise @30 kHz, 60 mA load, Co = 1 µF – – 60 35 nV/root-Hz nV/root-Hz 20 – – dB VIO up and steady. Time from the REG_ON rising edge to the LNLDO reaching 1.2V. Includes 256 µs vddc_ok_o delay. – – 1106 µs LDO turn-on time Chip already powered up. – – 180 µs In-rush current during turnon From its output capacitor in a fullydischarged state – – 150 mA External output capacitor, Co b Total ESR (trace/capacitor): 30–200 mΩ 0.67c 1 – µF External input capacitor Only use an external input capacitor at the – VDD_LDO pin if it is not supplied from the CBUCK output. Total ESR (trace/capacitor): 30–200 mΩ 1 – µF @100 kHz, 60 mA load, Co = 1 µF PSRR @ 1kHz, input > 1.3V, Co= 1 µF, Vo = 1.2V Start-up time of PMU a. Load from 0.1 to 104 mA. b. Refer to PCB Layout Guidelines and Component Selection for Optimized PMU Performance (4334-AN200-R) for component selection details. c. The minimum value refers to the residual capacitor value after taking into account the part-to-part tolerance, DCbias, temperature, and aging. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 133 System Power Consumption BCM43340 Data Sheet Section 19: System Power Consumption Note: • • Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, these values apply for the conditions specified in Table 25: “Recommended Operating Conditions and DC Characteristics,” on page 100. WLAN Current Consumption The WLAN current consumption measurements are shown in Table 43. All values in Table 43 are with the Bluetooth core in reset (that is, Bluetooth and FM are off). Table 43: Typical WLAN Power Consumption VBAT = 3.6V, VDDIO = 1.8V, TA 25°C Bandwidt Band h (MHz) (GHz) VBAT (mA) Vioa (µA) – – – – 0.004 0.005 220 220 IEEE Power Save, DTIM 1c – – 1.06 220 IEEE Power Save DTIM 3d – – 0.321 220 RX (Listen)e, f – – 44.4 200 RX (Active)f, g, h – – 57.7 200 TX CCK, 11 Mbps (20.5 dBm @ chip)h, i, j HT20 2.4 325 200 TX, MCS7 (17.5 dBm @ chip)h, i, j HT20 2.4 254 200 h, i, j HT40 2.4 270 200 TX OFDM, 54 Mbps (18 dBm @ chip)h, i, j HT20 2.4 263 200 TX, MCS7 (15 dBm @ chip)h, i, j HT20 5 261 200 TX, MCS7 (15 dBm @ chip)h, i, j HT40 5 283 200 TX OFDM, 54 Mbps (16 dBm @ chip)h, i, j HT20 5 271 200 Mode Sleep Modes Leakage (OFF) SLEEP b Active Modes TX, MCS7 (17.5 dBm @ chip) a. b. c. d. e. f. Vio is specified with all pins idle and not driving any loads. Idle between beacons. Beacon interval = 100 ms; beacon duration = 1.9 ms @ 1Mbps (Integrated Sleep + wakeup + beacon) Beacon interval = 300 ms; beacon duration = 1.9 ms @ 1Mbps (Integrated Sleep + wakeup + beacon) Carrier sense (CCA) when no carrier present. Carrier sense (CS) detect/packet RX. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 134 Bluetooth, BLE, and FM Current Consumption BCM43340 Data Sheet g. h. i. j. Applicable to all supported rates. Duty Cycle = 100% TX output power is measured at the chip-out side. The items of active modes are measured under the real association/throughput with the wireless AP. Bluetooth, BLE, and FM Current Consumption The Bluetooth and FM current consumption measurements are shown in Table 44. Note: • • • The WLAN core is in reset (WL_REG_ON = low) for all measurements provided in Table 44. For FM measurements, the Bluetooth core is in Sleep mode. The BT current consumption numbers are measured based on GFSK TX output power = 8 dBm. Table 44: Bluetooth and FM Current Consumption Operating Mode VBAT (3.6V) VDDIO (1.8V) Unit Sleep 6 133 µA SCO HV3 master 10.1 – mA 3DH5/3DH1 master 18.1 – mA DM1/DH1 master 22.9 – mA DM3/DH3 master 27.0 – mA DM5/DH5 master 28.3 – mA 2EV3 7.5 0.1 mA FMRX I2S audio 6.7 – mA BLE scana 169 131 µA BLE connected (1 second) 43 132 µA a. No devices present; 1.28 second interval with a scan window of 11.25 ms. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 135 Interface Timing and AC Characteristics BCM43340 Data Sheet S e c t i o n 2 0 : I n t e r f a c e Ti m i n g a n d A C C h a r a c t e ri s t i c s SDIO/gSPI Timing SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 43 and Table 45. Figure 43: SDIO Bus Timing (Default Mode) fPP tWL tWH SDIO_CLK tTHL tTLH tISU tIH Input Output tODLY tODLY (max) (min) Table 45: SDIO Bus Timinga Parameters (Default Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (All values are referred to minimum VIH and maximum VILb) Frequency – Data Transfer mode fPP 0 – 25 MHz Frequency – Identification mode fOD 0 – 400 kHz Clock low time tWL 10 – – ns Clock high time tWH 10 – – ns Clock rise time tTLH – – 10 ns Clock low time tTHL – – 10 ns Inputs: CMD, DAT (referenced to CLK) Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 136 SDIO/gSPI Timing BCM43340 Data Sheet Table 45: SDIO Bus Timinga Parameters (Default Mode) (Cont.) Parameter Symbol Minimum Typical Maximum Unit Input setup time tISU 5 – – ns Input hold time tIH 5 – – ns Output delay time – Data Transfer mode tODLY 0 – 14 ns Output delay time – Identification mode tODLY 0 – 50 ns Outputs: CMD, DAT (referenced to CLK) a. Timing is based on CL  40pF load on CMD and Data. b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 137 SDIO/gSPI Timing BCM43340 Data Sheet SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 44 and Table 46. Figure 44: SDIO Bus Timing (High-Speed Mode) fPP tWL tWH 50% VDD SDIO_CLK tTHL tTLH tIH tISU Input Output tODLY tOH Table 46: SDIO Bus Timinga Parameters (High-Speed Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (all values are referred to minimum VIH and maximum VILb) Frequency – Data Transfer Mode fPP 0 – 50 MHz Frequency – Identification Mode fOD 0 – 400 kHz Clock low time tWL 7 – – ns Clock high time tWH 7 – – ns Clock rise time tTLH – – 3 ns Clock low time tTHL – – 3 ns Input setup Time tISU 6 – – ns Input hold Time tIH 2 – – ns Inputs: CMD, DAT (referenced to CLK) Outputs: CMD, DAT (referenced to CLK) Output delay time – Data Transfer Mode tODLY – – 14 ns Output hold time tOH 2.5 – – ns Total system capacitance (each line) CL – – 40 pF a. Timing is based on CL  40pF load on CMD and Data. b. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 138 SDIO/gSPI Timing BCM43340 Data Sheet gSPI Signal Timing The gSPI host and device always use the rising edge of clock to sample data. Figure 45: gSPI Timing Table 47: gSPI Timing Parameters Parameter Symbol Minimum Maximum Units Note Clock period T1 20.8 – ns Clock high/low T2/T3 (0.45 × T1) – T4 (0.55 × T1) – T4 ns – Clock rise/fall timea T4/T5 – 2.5 ns Measured from 10% to 90% of VDDIO Input setup time T6 5.0 – ns Setup time, SIMO valid to SPI_CLK active edge Input hold time T7 5.0 – ns Hold time, SPI_CLK active edge to SIMO invalid Output setup time T8 5.0 – ns Setup time, SOMI valid before SPI_CLK rising Output hold time T9 5.0 – ns Hold time, SPI_CLK active edge to SOMI invalid CSX to clockb – 7.86 – ns CSX fall to 1st rising edge Clock to CSXa – – – ns Last falling edge to CSX high Fmax = 48 MHz a. Limit applies when SPI_CLK = Fmax. For slower clock speeds, longer rise/fall times are acceptable provided that the transitions are monotonic and the setup and hold time limits are complied with. b. SPI_CSx remains active for entire duration of gSPI read/write/write-read transaction (overall words for multipleword transaction) Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 139 HSIC Interface Specifications BCM43340 Data Sheet HSIC Interface Specifications Table 48: HSIC Timing Parameters Parameter Symbol Minimum Typical Maximum Unit Comments HSIC signaling voltage VDD 1.1 1.2 1.3 V – I/O voltage input low VIL –0.3 – 0.35 × VDD V – I/O Voltage input high VIH 0.65 × VDD – VDD + 0.3 V – I/O voltage output low VOL – – 0.25 × VDD V – I/O voltage output high VOH 0.75 × VDD – – V – I/O pad drive strength OD 40 – 60 Ω Controlled output impedance driver I/O weak keepers IL 20 – 70 μA – I/O input impedance ZI 100 – – kΩ – Total capacitive loada CL 3 – 14 pF – Characteristic trace impedance TI 45 50 55 Ω – Circuit board trace length TL – – 10 cm – Circuit board trace propagation skewb TS – – 15 ps – STROBE frequencyc FSTROBE 239.988 240 240.012 MHz ± 500 ppm Slew rate (rise and fall) STROBE and DATAC Tslew 0.60 × VDD 1.0 1.2 V/ns Averaged from 30% ~ 70% points Receiver data setup time Ts (with respect to STROBE)c 300 – – ps Measured at the 50% point Tb Receiver data hold time (with respect to STROBE)c 300 – – ps Measured at the 50% point a. Total Capacitive Load (CL), includes device Input/Output capacitance, and capacitance of a 50Ω PCB trace with a length of 10 cm. b. Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be matched between STROBE and DATA to ensure that the signal timing is within specification limits at the receiver. c. Jitter and duty cycle are not separately specified parameters, they are incorporated into the values in the table above. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 140 JTAG Timing BCM43340 Data Sheet JTAG Timing Table 49: JTAG Timing Characteristics Signal Name Period Output Maximum Output Minimum Setup Hold TCK 125 ns – – – – TDI – – – 20 ns 0 ns TMS – – – 20 ns 0 ns TDO – 100 ns 0 ns – – JTAG_TRST 250 ns – – – – Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 141 Power-Up Sequence and Timing BCM43340 Data Sheet Section 21: Power-Up Sequence and Ti m i n g Sequencing of Reset and Regulator Control Signals The BCM43340 has three signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 46, Figure 47 on page 143, and Figure 48 and Figure 49 on page 144). The timing values indicated are minimum required values; longer delays are also acceptable. Note: • • • • The WL_REG_ON and BT_REG_ON signals are ORed in the BCM43340. The diagrams show both signals going high at the same time (as would be the case if both REG signals were controlled by a single host GPIO). If two independent host GPIOs are used (one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the BCM43340 regulators. The reset requirements for the Bluetooth core are also applicable for the FM core. In other words, if FM is to be used, then the Bluetooth core must be enabled. The BCM43340 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold (see Table 25: “Recommended Operating Conditions and DC Characteristics,” on page 100). Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses. VBAT should not rise faster than 40 µs. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Description of Control Signals • WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal BCM43340 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. • BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM43340 regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT section is in reset. Note: For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 msec time delay between consecutive toggles (where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 142 Sequencing of Reset and Regulator Control Signals BCM43340 Data Sheet Control Signal Timing Diagrams Figure 46: WLAN = ON, Bluetooth = ON 32.678 kHz Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise faster than 40 microseconds or slower than 100 milliseconds. 2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Figure 47: WLAN = OFF, Bluetooth = OFF 32.678 kHz Sleep Clock VBAT* VDDIO WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise faster than 40 microseconds or slower than 100 milliseconds. 2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 143 Sequencing of Reset and Regulator Control Signals BCM43340 Data Sheet Figure 48: WLAN = ON, Bluetooth = OFF 32.678 kH z Sleep Clock V BAT 90% of V H VD D IO ~ 2 Sleep cycles W L_REG _O N BT_REG _O N *N otes: 1. VBAT should not rise faster than 40 m icroseconds or slow er than 100 m illiseconds. 2. VBAT should be up before or at the sam e tim e as VDDIO . VD D IO should N O T be pre sent first or be held high before VBAT is high. Figure 49: WLAN = OFF, Bluetooth = ON 3 2.6 78 kH z Sleep Clo ck VBAT 9 0% of V H V D D IO ~ 2 Sleep cy cles W L_R EG _O N B T_REG _O N *N otes: 1. V B A T sho u ld no t rise faster th an 4 0 m icroseco n ds or slow er th an 10 0 m illisecon d s. 2. V B A T sho u ld be u p before o r at th e sam e tim e as V D D IO . V D D IO sh o uld N O T b e present first or b e held h ig h b efo re V B A T is h igh . Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 144 Package Information BCM43340 Data Sheet Section 22: Package Information Package Thermal Characteristics Table 50: Package Thermal Characteristicsa Characteristic WLBGA JA (°C/W) (value in still air) 36.8 JB (°C/W) 5.93 JC (°C/W) 2.82 JT (°C/W) 9.26 JB (°C/W) 16.93 Maximum Junction Temperature Tj 114.08 Maximum Power Dissipation (W) 1.198 a. No heat sink, TA = 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm × 101.6 mm × 1.6 mm) and P = 1.198W continuous dissipation. Junction Temperature Estimation and PSIJT Versus THETAJC Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is: TJ = TT + P x JT Where: • TJ = Junction temperature at steady-state condition (°C) • TT = Package case top center temperature at steady-state condition (°C) • P = Device power dissipation (Watts) • JT = Package thermal characteristics; no airflow (°C/W) Environmental Characteristics For environmental characteristics data, see Table 23: “Environmental Ratings,” on page 99. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 145 Mechanical Information BCM43340 Data Sheet Section 23: Mechanical Information Figure 50: 141-Ball WLBGA Package Mechanical Information Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 146 Mechanical Information BCM43340 Data Sheet Figure 51: WLBGA Keep-Out Areas for PCB Layout—Bottom View Note: No top-layer metal is allowed in keep-out areas. Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 147 Ordering Information BCM43340 Data Sheet S e c t i o n 2 4 : O rd e r i n g I n f o r m a t i o n Part Number Package Description Operating Ambient Temperature BCM43340XKUBG 141 ball WLBGA (5.67 mm × 4.47 mm, 0.4 mm pitch) Dual-band 2.4 GHz and 5 GHz –30°C to +85°C WLAN + BT 4.0 + FM BCM43340HKUBG 141 ball WLBGA (5.67 mm × 4.47 mm, 0.4 mm pitch) Dual-band 2.4 GHz and 5 GHz –30°C to +85°C WLAN + BT 4.0 + FM + BSP Broadcom® January 28, 2015 • 43340-DS109-R BROADCOM CONFIDENTIAL Page 148 BCM43340 Data Sheet Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. ® Broadcom Corporation 5300 California Avenue Irvine, CA 92617 © 2015 by BROADCOM CORPORATION. All rights reserved. 43340-DS109-R January 28, 2015 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: info@broadcom.com Web: www.broadcom.com