IPP80N08S2L07AKSA1

IPB80N08S2L-07 IPP80N08S2L-07 OptiMOS™ Power-Transistor Product Summary Features • N-channel Logic Level - Enhancement mode • Automotive AEC Q101 qualified • MSL1 up to 260°C peak reflow V DS 75 V R DS(on),max (SMD version) 6.8 mW ID 80 A • 175°C operating temperature PG-TO263-3-2 • Green package (lead free) PG-TO220-3-1 • Ultra low Rds(on) • 100% Avalanche tested Type Package Ordering Code Marking IPB80N08S2L-07 PG-TO263-3-2 SP0002-19051 2N08L07 IPP80N08S2L-07 PG-TO220-3-1 SP0002-19050 2N08L07 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions Value T C=25 °C, V GS=10 V1) 80 T C=100 °C, V GS=10 V2) Unit A 80 Pulsed drain current2) I D,pulse T C=25 °C 320 Avalanche energy, single pulse2) E AS I D=80A 810 mJ Gate source voltage V GS ±20 V Power dissipation P tot 300 W Operating and storage temperature T j, T stg -55 ... +175 °C T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.1 55/175/56 page 1 2014-03-07 IPB80N08S2L-07 IPP80N08S2L-07 Parameter Symbol Values Conditions Unit min. typ. max. Thermal characteristics2) Thermal resistance, junction - case R thJC - - 0.5 Thermal resistance, junction ambient, leaded R thJA - - 62 SMD version, device on PCB R thJA minimal footprint - - 62 6 cm2 cooling area3) - - 40 75 - - K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D= 1 mA Gate threshold voltage V GS(th) V DS=V GS, I D=250 µA 1.2 1.6 2.0 Zero gate voltage drain current I DSS V DS=75 V, V GS=0 V, T j=25 °C - 0.01 1 - 1 100 V DS=75 V, V GS=0 V, T j=125 °C2) V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 1 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=80 A - 6.6 9 mW V GS=4.5 V, I D=80 A, SMD version - 6.3 8.7 V GS=10 V, I D=80 A - 5.1 7.1 V GS=10 V, I D=80 A, SMD version - 4.8 6.8 Drain-source on-state resistance Rev. 1.1 RDS(on) page 2 mΩ 2014-03-07 IPB80N08S2L-07 IPP80N08S2L-07 Parameter Symbol Values Conditions Unit min. typ. max. - 5400 - - 1300 - Dynamic characteristics2) pF Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 590 - Turn-on delay time t d(on) - 19 - Rise time tr - 55 - Turn-off delay time t d(off) - 85 - Fall time tf - 22 - Gate to source charge Q gs - 18 23 Gate to drain charge Q gd - 69 83 Gate charge total Qg - 183 233 Gate plateau voltage V plateau - 3.4 - V - - 80 A - - 320 - 0.9 1.3 V - 95 120 ns - 240 300 nC V GS=0 V, V DS=25 V, f =1 MHz V DD=40 V, V GS=10 V, I D=80 A, R G=1.1 W ns Gate Charge Characteristics2) V DD=60 V, I D=80 A, V GS=0 to 10 V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD Reverse recovery time2) t rr Reverse recovery charge2) Q rr T C=25 °C V GS=0 V, I F=80 A, T j=25 °C V R=40 V, I F=I S, di F/dt =100 A/µs 1) Current is limited by bondwire; with an R thJC = 0.5K/W the chip is able to carry 135A at 25°C. 2) Defined by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.1 page 3 2014-03-07 IPB80N08S2L-07 IPP80N08S2L-07 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 4 V I D = f(T C); V GS ≥ 10 V 350 80 300 250 200 I D [A] P tot [W] 60 150 40 100 20 50 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 100 1000 1 µs 0.5 10 µs 100 µs 1 ms 10-1 0.1 I D [A] Z thJC [K/W] 100 0.05 10 10-2 1 -3 0.01 single pulse 10 0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.1 10-7 page 4 2014-03-07 IPB80N08S2L-07 IPP80N08S2L-07 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C R DS(on) = (I D); T j = 25 °C parameter: V GS parameter: V GS 300 20 10 V 5V 3V 4.5 V 3.5 V 4.5 V 4V 18 250 16 R DS(on) [mW] 200 I D [A] 4V 150 14 12 10 100 3.5 V 8 5V 50 6 3V 10 V 2.5 V 0 4 0 2 4 6 0 100 200 300 400 150 200 I D [A] V DS [V] 7 Typ. transfer characteristics 8 Typ. Forward transconductance I D = f(V GS); V DS = 6V g fs = f(I D); T j = 25°C parameter: T j parameter: g fs 400 250 200 300 g fs [S] I D [A] 150 200 100 100 50 175 °C 25 °C -55 °C 0 0 1 2 3 4 0 Rev. 1.1 50 100 I D [A] V GS [V] page 5 2014-03-07 IPB80N08S2L-07 IPP80N08S2L-07 9 Typ. Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(ON) = f(T j) V GS(th) = f(T j); V GS = V DS parameter: I D = 80 A; VGS = 10 V parameter: I D 12 2.5 10 2 8 1.5 V GS(th) [V] R DS(on) [mW] 1250µA 6 4 250µA 1 0.5 2 0 -60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180 T j [°C] T j [°C] 11 Typ. capacitances 12 Typical forward diode characteristicis C = f(V DS); V GS = 0 V; f = 1 MHz IF = f(VSD) parameter: T j 104 103 Ciss 102 I F [A] C [pF] Coss 103 175 °C Crss 25 °C 101 102 100 0 5 10 15 20 25 30 V DS [V] Rev. 1.1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 V SD [V] page 6 2014-03-07 IPB80N08S2L-07 IPP80N08S2L-07 13 Typical avalanche energy 14 Typ. gate charge E AS = f(T j) V GS = f(Q gate); I D = 80 A pulsed parameter: I D parameter: V DD 3500 12 20 A 15V 3000 60V 10 2500 8 V GS [V] E AS [mJ] 2000 40 A 1500 6 4 1000 80 A 2 500 0 0 25 75 125 0 175 40 80 120 160 200 Q gate [nC] T j [°C] 15 Typ. drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS) = f(T j); I D = 1 mA 86 V GS Qg V BR(DSS) [V] 81 76 71 Q gate Q gs Q gd 66 -60 -20 20 60 100 140 180 T j [°C] Rev. 1.1 page 7 2014-03-07 IPB80N08S2L-07 IPP80N08S2L-07 Published by Infineon Technologies AG Am Campeon 1-12 D-85579 Neubiberg © Infineon Technologies AG 2014 All Rights Reserved. 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If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.1 page 8 2014-03-07 IPB80N08S2L-07 IPP80N08S2L-07 Revision History Version Date Changes Revision 1.0 03.03.2006 Final Data Sheet Revision 1.1 07.03.2014 SOA extended Rev. 1.1 page 9 2014-03-07