IRFS3507TRLPBF

PD - 95935B IRFB3507PbF IRFS3507PbF IRFSL3507PbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits l Lead-Free HEXFET® Power MOSFET D G S Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability VDSS RDS(on) typ. max. ID S GD S D G D2Pak IRFS3507PbF TO-262 IRFSL3507PbF S D G TO-220AB IRFB3507PbF 75V 7.0m: 8.8m: 97A Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS Parameter d Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw f dv/dt TJ TSTG Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy c Max. Units 97 69 390 190 1.3 ± 20 5.0 -55 to + 175 A c c Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V W W/°C V V/ns °C 300 x x 10lb in (1.1N m) e 280 See Fig. 14, 15, 16a, 16b g mJ A mJ Thermal Resistance Symbol RθJC RθCS RθJA RθJA www.irf.com Parameter k Junction-to-Case Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220 k Junction-to-Ambient (PCB Mount) , D2Pak jk Typ. Max. ––– 0.50 ––– ––– 0.77 ––– 62 40 Units °C/W 1 01/20/06 IRFB/S/SL3507PbF Static @ TJ = 25°C (unless otherwise specified) Symbol Parameter V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Input Resistance RG Min. Typ. Max. Units 75 ––– ––– 2.0 ––– ––– ––– ––– ––– ––– ––– 0.070 ––– 7.0 8.8 ––– 4.0 ––– 20 ––– 250 ––– 200 ––– -200 1.3 ––– Conditions V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 58A V VDS = VGS, ID = 100µA µA VDS = 75V, VGS = 0V VDS = 75V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Ω f = 1MHz, open drain d g Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Min. Typ. Max. Units Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 86 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Effective Output Capacitance (Energy Related) ––– ––– Effective Output Capacitance (Time Related) h ––– 88 24 36 20 81 52 49 3540 340 210 460 520 ––– 130 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC ns pF Conditions VDS = 50V, ID = 58A ID = 58A VDS = 60V VGS = 10V VDD = 48V ID = 58A RG = 5.6Ω VGS = 10V VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 60V VGS = 0V, VDS = 0V to 60V g g i, See Fig.11 h, See Fig. 5 Diode Characteristics Symbol IS Parameter Min. Typ. Max. Units Continuous Source Current VSD trr (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM d ––– 97 c A MOSFET symbol ––– ––– 390 A showing the integral reverse D G p-n junction diode. TJ = 25°C, IS = 58A, VGS = 0V TJ = 25°C VR = 64V, TJ = 125°C IF = 58A di/dt = 100A/µs TJ = 25°C S g ––– ––– 1.3 V ––– 37 56 ns ––– 45 68 ––– 32 48 nC TJ = 125°C ––– 51 77 ––– 1.7 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. ‚ Repetitive rating; pulse width limited by max. junction temperature. ƒ Limited by TJmax, starting TJ = 25°C, L = 0.17mH, RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use above this value. „ ISD ≤ 58A, di/dt ≤ 390A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. … Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 Conditions ––– g † Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . ‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS . ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. ‰ Rθ is measured at TJ approximately 90°C. www.irf.com IRFB/S/SL3507PbF 1000 1000 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 100 10 4.5V 1 ≤60µs PULSE WIDTH BOTTOM 4.5V 10 ≤60µs PULSE WIDTH Tj = 25°C Tj = 175°C 0.1 1 0.1 1 10 100 1000 0.1 V DS, Drain-to-Source Voltage (V) 10 100 1000 Fig 2. Typical Output Characteristics 2.5 RDS(on) , Drain-to-Source On Resistance (Normalized) 1000 ID, Drain-to-Source Current (Α) 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 100 T J = 175°C 10 T J = 25°C 1 VDS = 25V ≤60µs PULSE WIDTH ID = 97A VGS = 10V 2.0 1.5 1.0 0.5 0.1 2 4 6 8 10 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (°C) VGS, Gate-to-Source Voltage (V) Fig 4. Normalized On-Resistance vs. Temperature Fig 3. Typical Transfer Characteristics 100000 12.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS, Gate-to-Source Voltage (V) ID= 58A C oss = C ds + C gd C, Capacitance(pF) VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 10000 Ciss 1000 Coss Crss 100 10.0 VDS= 60V VDS= 38V VDS= 15V 8.0 6.0 4.0 2.0 0.0 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com 0 20 40 60 80 100 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFB/S/SL3507PbF 10000 100 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 T J = 175°C 10 T J = 25°C 1 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100µsec 100 1msec 10 10msec 1 DC Tc = 25°C Tj = 175°C Single Pulse 0.1 VGS = 0V 0.1 0.01 0.0 0.4 0.8 1.2 1.6 2.0 1 VSD, Source-to-Drain Voltage (V) Limited By Package ID, Drain Current (A) 80 60 40 20 0 75 100 125 150 175 V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 100 50 90 85 80 75 70 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Temperature ( °C ) Fig 10. Drain-to-Source Breakdown Voltage Fig 9. Maximum Drain Current vs. Case Temperature 1.6 EAS , Single Pulse Avalanche Energy (mJ) 1200 1.4 1.2 Energy (µJ) 1000 95 T C , Case Temperature (°C) 1.0 0.8 0.6 0.4 0.2 0.0 ID 8.9A 12A BOTTOM 58A TOP 1000 800 600 400 200 0 0 10 20 30 40 50 60 70 VDS, Drain-to-Source Voltage (V) 4 100 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 25 10 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 80 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRFB/S/SL3507PbF Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 τJ 0.02 0.01 0.01 SINGLE PULSE ( THERMAL RESPONSE ) 0.001 R1 R1 τJ τ1 R2 R2 τC τ2 τ1 τ Ri (°C/W) τi (sec) 0.2963 0.000504 0.4738 τ2 0.013890 Ci= τi/Ri Ci i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse) Avalanche Current (A) Duty Cycle = Single Pulse 100 0.01 0.05 10 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 300 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max) is exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1% Duty Cycle ID = 58A 250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav 5 VGS(th) Gate threshold Voltage (V) IRFB/S/SL3507PbF 4.5 14 4.0 12 3.5 10 2.5 2.0 IRRM (A) 3.0 ID = 100µA ID = 250µA ID = 1.0mA ID = 1.0A 6 4 1.5 IF = 19A VR = 64V 2 1.0 -75 -50 -25 0 25 50 T = 25°C _____ J T = 125°C ---------J 0 75 100 125 150 175 200 100 200 300 400 500 600 700 800 900 1000 T J , Temperature ( °C ) dif/dt (A/µs) Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt 14 350 12 300 10 250 8 200 Qrr (nC) IRRM (A) 8 6 4 100 IF = 39A VR = 64V 2 150 I = 19A F V = 64V R TJ = 25°C _____ 50 T = 25°C _____ J T = 125°C ---------J TJ = 125°C ---------- 0 0 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs) dif/dt (A/µs) Fig. 19 - Typical Stored Charge vs. dif/dt Fig. 18 - Typical Recovery Current vs. dif/dt 300 250 Qrr (nC) 200 150 100 I = 39A F V = 64V R TJ = 25°C _____ 50 TJ = 125°C ---------- 0 100 200 300 400 500 600 700 800 900 1000 dif/dt (A/µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFB/S/SL3507PbF D.U.T Driver Gate Drive ƒ - ‚ „ - - * D.U.T. ISD Waveform Reverse Recovery Current +  RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V D.U.T RG VGS 20V DRIVER L VDS tp + V - DD IAS tp A 0.01Ω I AS Fig 21a. Unclamped Inductive Test Circuit LD Fig 21b. Unclamped Inductive Waveforms VDS VDS 90% + VDD - 10% D.U.T VGS VGS Pulse Width < 1µs Duty Factor < 0.1% td(on) Fig 22a. Switching Time Test Circuit tr td(off) tf Fig 22b. Switching Time Waveforms Id Vds Vgs L DUT 0 VCC Vgs(th) 1K Qgs1 Qgs2 Fig 23a. Gate Charge Test Circuit www.irf.com Qgd Qgodr Fig 23b. Gate Charge Waveform 7 IRFB/S/SL3507PbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information (;$03/( 7+,6,6$1,5) /27&2'( $66(0%/('21:: ,17+($66(0%/