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IRL2703STRL

IRL2703STRL

  • 厂商:

    EUPEC(英飞凌)

  • 封装:

    SOT404

  • 描述:

    MOSFET N-CH 30V 24A D2PAK

  • 数据手册
  • 价格&库存
IRL2703STRL 数据手册
PD - 9.1360 IRL2703S PRELIMINARY HEXFET® Power MOSFET l l l l l l Logic-Level Gate Drive Advanced Process Technology Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Fully Avalanche Rated D VDSS = 30V RDS(on) = 0.04Ω G ID = 24A S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D2PAK is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. D 2 Pak Absolute Maximum Ratings ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG Parameter Max. Continuous Drain Current, VGS @ 10V… Continuous Drain Current, VGS @ 10V… Pulsed Drain Current  Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy ‚… Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt ƒ… Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds 24 17 96 45 0.30 ±16 77 14 4.5 3.5 -55 to + 175 Units A W W/°C V mJ A mJ V/ns °C 300 (1.6mm from case) Thermal Resistance Parameter RθJC RθJA Junction-to-Case Junction-to-Ambient (PCB Mount,steady-state)** Min. Typ. Max. Units –––– –––– –––– –––– 3.3 40 °C/W 11/18/96 IRL2703S Electrical Characteristics @ TJ = 25°C (unless otherwise specified) ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. 30 ––– ––– ––– 1.0 6.4 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current LS Internal Source Inductance ––– Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance ––– ––– ––– V(BR)DSS I GSS Typ. ––– 0.030 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 8.5 140 12 20 Max. Units Conditions ––– V VGS = 0V, I D = 250µA ––– V/°C Reference to 25°C, I D = 1mA… 0.040 VGS = 10V, ID = 14A „ Ω 0.060 VGS = 4.5V, I D = 12A „ ––– V VDS = VGS , ID = 250µA ––– S VDS = 25V, I D = 14A… 25 VDS = 30V, VGS = 0V µA 250 VDS = 24V, VGS = 0V, TJ = 150°C 100 V GS = 16V nA -100 VGS = -16V 15 ID = 14A 4.6 nC VDS = 24V 9.3 V GS = 4.5V, See Fig. 6 and 13 „… ––– VDD = 15V ––– I D = 14A ns ––– RG = 12Ω, VGS = 4.5V ––– RD = 1.0Ω, See Fig. 10 „… Between lead, nH 7.5 ––– and center of die contact 450 ––– VGS = 0V 210 ––– pF VDS = 25V 110 ––– ƒ = 1.0MHz, See Fig. 5… Source-Drain Ratings and Characteristics IS ISM VSD t rr Q rr t on Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)  Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions MOSFET symbol ––– ––– 24 showing the A G integral reverse ––– ––– 96 p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 14A, VGS = 0V „ ––– 65 97 ns TJ = 25°C, IF = 14A ––– 140 210 nC di/dt = 100A/µs „… Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Repetitive rating; pulse width limited by ƒ ISD ≤ 14A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS, max. junction temperature. ( See fig. 11 ) TJ ≤ 175°C ‚ VDD = 15V, starting TJ = 25°C, L = 570µH „ Pulse width ≤ 300µs; duty cycle ≤ 2%. … Uses IRL2703 data and test conditions. RG = 25Ω, IAS = 14A. (See Figure 12) ** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. D S IRL2703S 1000 1000 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTT OM 2.5V 100 10 1 2.5V 20 µ s PU LSE W ID TH T J = 2 5°C 0.1 0.1 1 10 100 10 0.1 R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce (N o rm a li ze d ) I D , D r ain- to-S ourc e C urre nt (A ) T J = 2 5 °C T J = 1 7 5 °C 10 1 V DS = 1 5 V 2 0 µ s P U L S E W ID T H 5 6 7 8 9 V G S , Ga te-to-S o urce V oltage (V ) Fig 3. Typical Transfer Characteristics 10 A 100 Fig 2. Typical Output Characteristics 2.0 4 1 V D S , Drain-to-S ource Voltage (V ) 100 3 2 0µ s PU L SE W ID TH T J = 1 75 °C 0.1 A 100 Fig 1. Typical Output Characteristics 0.1 2.5V 1 V D S , Drain-to-Source V oltage (V ) 2 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP ID , D ra in -to -S o u rce C u rre n t (A ) ID , D ra in -to -S o u rc e C u rre n t (A ) TOP 10 A I D = 24 A 1.5 1.0 0.5 V G S = 10 V 0.0 -60 -40 -20 0 20 40 60 80 A 100 120 140 160 180 T J , Junction T emperature (°C) Fig 4. Normalized On-Resistance Vs. Temperature IRL2703S V GS C is s C rss C oss C , C a p a c ita n c e (p F ) 800 15 = 0 V, f = 1M H z = C gs + C gd , Cds SH OR TE D = C gd = C d s + C gd V G S , G a te -to -S o u rce V o lta g e (V ) 1000 C i ss 600 C o ss 400 C rs s 200 0 10 V DS = 2 4V V DS = 1 5V 12 9 6 3 FO R TEST CIR CU IT SEE FIG UR E 13 0 A 1 I D = 14A 0 100 V D S , D rain-to-S ource Voltage (V ) 8 12 16 A 20 Q G , T otal Gate C harge (nC ) Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 100 1000 OPE R ATIO N IN TH IS A RE A LIMITE D BY R D S(o n) I D , D ra in C u rre n t (A ) I S D , R e v e rse D ra in C u rre n t (A ) 4 TJ = 1 75 °C T J = 25° C 10 100 10µ s 10 0µs 10 1 ms VG S = 0 V 1 0.4 0.8 1.2 1.6 2.0 V S D , S ource-to-Drain Voltage (V ) Fig 7. Typical Source-Drain Diode Forward Voltage A 2.4 T C = 25 °C T J = 17 5°C S ing le Pulse 1 1 1 0m s A 10 V D S , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area 100 IRL2703S 24 RD VDS I D , D ra in C u rre n t (A m p s) 20 VGS D.U.T. RG + -VDD 16 5.0V 12 Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 8 Fig 10a. Switching Time Test Circuit VDS 4 90% A 0 25 50 75 100 125 150 175 TC , Case Temperature (°C ) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Therm al Response (Z th JC ) 10 D = 0 .5 0 1 0.2 0 0 .1 0 0.05 0.1 PD M 0.02 0.0 1 t S ING L E P UL S E ( THE R M A L R E S P O N S E ) 1 t2 N o tes : 1 . D u ty fa c to r D = t 1 / t 2 0.01 0.00001 2 . P e a k TJ = P D M x Z th J C + T C 0.0001 0.001 0.01 0.1 t 1 , R e cta n g u la r P u ls e D u r a tio n ( se c ) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case A 1 IRL2703S D.U.T. RG + V - DD IAS 5.0 V tp 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS E A S , S in g le P u ls e A va la n c h e E n e rg y (m J) 160 L VDS TO P B OTTO M ID 5.7 A 9 .9A 14A 120 80 40 V D D = 1 5V 0 25 50 A 75 100 125 150 Starting TJ , Junction T emperature (°C) tp VDD Fig 12c. Maximum Avalanche Energy Vs. Drain Current VDS IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 4.5 V QGS D.U.T. QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 175 IRL2703S Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer ƒ + ‚ - - „ +  • • • • RG Driver Gate Drive Period P.W. + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test D= - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS ISD * IRL2703S Package Outline D2Pak Outline Dimensions are shown in millimeters (inches) 1 0 .5 4 (.4 15 ) 1 0 .2 9 (.4 05 ) 1 .4 0 (.0 5 5) M A X. 4.6 9 (.1 85 ) 4.2 0 (.1 65 ) -A - -B - 4 1 .3 2 (.0 5 2) 1 .2 2 (.0 4 8) 1 0 .1 6 (.40 0 ) R E F. 4 1 .7 8 (.0 7 0) 1 .2 7 (.0 5 0) 1 2 1 5 .4 9 (.61 0 ) 1 4 .7 3 (.58 0 ) 3 5 .2 8 (.2 0 8) 4 .7 8 (.1 8 8) 3X 1.4 0 (.0 55 ) 1.1 4 (.0 45 ) 2X 5 .0 8 ( .20 0) 0.5 5 (.0 22 ) 0.4 6 (.0 18 ) 0 .93 (.03 7 ) 0 .69 (.02 7 ) 0 .2 5 ( .0 1 0) 6.4 7 (.2 55 ) 6.1 8 (.2 43 ) 2.7 9 ( .1 10 ) 2.2 9 ( .0 90 ) M 2.6 1 (.1 0 3) 2.3 2 (.0 9 1) 1.39 (.0 55 ) 1.14 (.0 45 ) 8 .8 9 (.35 0 ) R E F. A M B N O TES: 1 DIMEN SIO NS AFTER SO LD ER D IP. 2 DIMEN SIO NIN G & TO LERAN CIN G PER ANSI Y14.5M, 1982 3 CO N TRO LLIN G D IMENSION : IN CH . 4 DIMEN SIO NS AR E SH OW N IN MILLIMETER S (IN CH ES). 5 HEATSIN K & LEAD D IMEN SIO N S D O NO T IN CLU D E BU R RS. A Part Marking Information D2Pak E XAM PL E : THIS IS A N IR F5 30 S W ITH AS SE MB LY L OT C OD E 9B 1M IN TER NA TIO NA L R EC TIF IER LO G O A SS EMB LY LOT C OD E A PAR T N UM BE R F 53 0S 92 46 9B 1M D ATE C OD E (YYW W ) Y Y = YE AR W W = W E EK IRL2703S Tape & Reel Information D2Pak Dimensions are shown in millimeters (inches) TRR 1.6 0 (.063 ) 1.5 0 (.059 ) 4.10 ( .1 61) 3.90 ( .1 53) F E E D D I R E C T IO N 1.85 (.0 73) 1.65 (.0 65) 1 . 6 0 (. 06 3 ) 1 . 5 0 (. 05 9 ) 1 1 .6 0 (.4 5 7 ) 1 1 .4 0 (.4 4 9 ) 0 .3 6 8 (.0 1 4 5 ) 0 .3 4 2 (.0 1 3 5 ) 1 5 .4 2 (.6 0 9 ) 1 5 .2 2 (.6 0 1 ) 2 4 . 3 0 (. 9 5 7 ) 2 3 . 9 0 (. 9 4 1 ) TR L 1 0 . 9 0 (. 4 2 9 ) 1 0 . 7 0 (. 4 2 1 ) 1 . 7 5 (. 0 6 9 ) 1 . 2 5 (. 0 4 9 ) 4 .7 2 (.1 3 6 ) 4 .5 2 (.1 7 8 ) 1 6 .1 0 ( .6 3 4 ) 1 5 .9 0 ( .6 2 6 ) F E E D D I R E C T IO N 1 3 .5 0 (. 5 32 ) 1 2 .8 0 (. 5 04 ) 2 7 .4 0 (1 .0 7 9) 2 3 .9 0 (.9 4 1 ) 4 330.00 (14.173) M AX. NOTES : 1. C O M F O R M S T O E IA - 41 8 . 2. C O N T R O LL IN G D IM E N S I O N : M IL L IM E T E R . 3. D IM E N S IO N M E A S U R E D @ H U B . 4. IN C L U D E S F LA N G E D I S T O R T IO N @ O U T E R E D G E . 6 0. 00 (2 .3 6 2) M IN . 26.40 (1.039) 24.40 (.961) 3 0. 4 0 (1 .1 9 7) MAX . 4 3 WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 11/96 Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/
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