Data Sheet No. PD60312B
1/02/2014
IRMCF311
Dual Channel Sensorless Motor Control IC
for Appliances
Features
Product Summary
Maximum crystal frequency
TM
MCE (Motion Control Engine) - Hardware based
computation engine for high efficiency sinusoidal
sensorless control of permanent magnet AC motor
Integrated Power Factor Correction control
Supports both interior and surface permanent
magnet motors
Built-in hardware peripheral for single shunt
current feedback reconstruction
No external current or voltage sensing operational
amplifier required
Dual channel three/two-phase Space Vector PWM
Two-channel analog output (PWM)
Embedded 8-bit high speed microcontroller (8051)
for flexible I/O and man-machine control
JTAG programming port for emulation/debugger
Two serial communication interface (UART)
2
I C/SPI serial interface
Watchdog timer with independent analog clock
Three general purpose timers
Two special timers: periodic timer, capture timer
60 MHz
Maximum internal clock (SYSCLK) frequency
Sensorless control computation time
TM
MCE
computation data range
128 MHz
11 μsec typ
16 bit signed
Program RAM loaded from external EEPROM 48K bytes
Data RAM
8K bytes
GateKill latency (digital filtered)
2 μsec
PWM carrier frequency counter
16 bits/ SYSCLK
A/D input channels
6
A/D converter resolution
12 bits
A/D converter conversion speed
2 μsec
8051 instruction execution speed
Analog output (PWM) resolution
UART baud rate (typ)
Number of I/O (max)
Package (lead-free)
2 SYSCLK
8 bits
57.6K bps
14
QFP64
External EEPROM and internal RAM facilitate
debugging and code development
Pin compatible with IRMCK311, OTP-ROM version
1.8V/3.3V CMOS
Description
IRMCF311 is a high performance RAM based motion control IC designed primarily for appliance applications. IRMCF311 is
designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control.
TM
IRMCF311 contains two computation engines. One is Motion Control Engine (MCE ) for sensorless control of permanent
magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one
TM
monolithic chip. The MCE contains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle
estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by
connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as
the Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital
circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2cycle instruction execution (60MIPS at 120MHz). The MCE and 8051 microcontroller are connected via dual port RAM to
TM
process signal monitoring and command input. An advanced graphic compiler for the MCE is seamlessly integrated into the
MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments.
IRMCF311 comes with a small QFP64 pin lead-free package.
Rev C
IRMCF311
TABLE OF CONTENTS
1
2
3
4
Overview...................................................................................................................................... 4
IRMCF311 Block Diagram and Main Functions......................................................................... 5
Pinout ........................................................................................................................................... 7
Input/Output of IRMCF311 ......................................................................................................... 8
4.1 8051 Peripheral Interface Group ........................................................................................... 8
4.2 Motion Peripheral Interface Group ....................................................................................... 9
4.3 Analog Interface Group ....................................................................................................... 10
4.4 Power Interface Group ........................................................................................................ 11
4.5 Test Interface Group............................................................................................................ 11
5 Application Connections ........................................................................................................... 12
6 DC Characteristics ..................................................................................................................... 13
6.1 Absolute Maximum Ratings ............................................................................................... 13
6.2 System Clock Frequency and Power Consumption ............................................................ 13
6.3 Digital I/O DC Characteristics ............................................................................................ 14
6.4 PLL and Oscillator DC Characteristics ............................................................................... 15
6.5 Analog I/O DC Characteristics ........................................................................................... 15
6.6 Analog I/O DC Characteristics ........................................................................................... 16
6.7 Under Voltage Lockout DC Characteristics........................................................................ 17
6.8 CMEXT and AREF Characteristics .................................................................................... 17
7 AC Characteristics ..................................................................................................................... 18
7.1 PLL AC Characteristics ...................................................................................................... 18
7.2 Analog to Digital Converter AC Characteristics................................................................. 19
7.3 Op amp AC Characteristics ................................................................................................. 20
7.4 Op Amp AC Characteristics................................................................................................ 20
7.5 SYNC to SVPWM and A/D Conversion AC Timing ......................................................... 21
7.6 GATEKILL to SVPWM AC Timing .................................................................................. 22
7.7 Interrupt AC Timing ........................................................................................................... 22
7.8 I2C AC Timing .................................................................................................................... 23
7.9 SPI AC Timing.................................................................................................................... 24
7.9.1 SPI Write AC timing .................................................................................................... 24
7.9.2 SPI Read AC Timing .................................................................................................... 25
7.10
UART AC Timing ........................................................................................................... 26
7.11
CAPTURE Input AC Timing .......................................................................................... 27
7.12
JTAG AC Timing ............................................................................................................ 28
8 I/O Structure .............................................................................................................................. 29
9 Pin List ....................................................................................................................................... 32
10
Package Dimensions ............................................................................................................... 35
11
Part Marking Information ....................................................................................................... 36
2
IRMCF311
TABLE OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Typical Application Block Diagram Using IRMCF311 .................................................. 4
IRMCF311 Internal Block Diagram................................................................................. 5
IRMCF311 Pin Configuration.......................................................................................... 7
Input/Output of IRMCF311 ............................................................................................. 8
Application Connection of IRMCF311.......................................................................... 12
Clock Frequency vs. Power Consumption ..................................................................... 13
All digital I/O and PWM outputs .................................................................................... 29
RESET, GATEKILL I/O ................................................................................................. 29
Analog input .................................................................................................................... 30
Analog operational amplifier output and AREF I/O structure ...................................... 30
VSS, AVSS and PLLVSS pin structure ........................................................................ 30
VDD1, VDD2, AVDD and PLLVDD pin structure ..................................................... 31
XTAL0/XTAL1 pins structure ...................................................................................... 31
TABLE OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Absolute Maximum Ratings............................................................................................ 13
System Clock Frequency ................................................................................................. 13
Digital I/O DC Characteristics ........................................................................................ 14
PLL DC Characteristics ................................................................................................... 15
Analog I/O DC Characteristics ........................................................................................ 15
Analog I/O DC Characteristics ........................................................................................ 16
UVcc DC Characteristics ................................................................................................ 17
CMEXT and AREF DC Characteristics .......................................................................... 17
PLL AC Characteristics ................................................................................................... 18
A/D Converter AC Characteristics ................................................................................ 19
Current Sensing OP Amp AC Characteristics ............................................................... 20
Voltage sensing OP Amp AC Characteristics ............................................................... 20
SYNC AC Characteristics ............................................................................................. 21
GATEKILL to SVPWM AC Timing ............................................................................ 22
Interrupt AC Timing ...................................................................................................... 22
I2C AC Timing .............................................................................................................. 23
SPI Write AC Timing .................................................................................................... 24
SPI Read AC Timing..................................................................................................... 25
UART AC Timing ......................................................................................................... 26
CAPTURE AC Timing ................................................................................................. 27
JTAG AC Timing .......................................................................................................... 28
Pin List .......................................................................................................................... 34
3
IRMCF311
Overview
IRMCF311 is a new International Rectifier integrated circuit device primarily designed as a onechip solution for complete inverter controlled air conditioner motor control applications. Unlike a
traditional microcontroller or DSP, the IRMCF311 provides a built-in closed loop sensorless
control algorithm using the unique Motion Control Engine (MCETM) for permanent magnet
motors. The MCETM consists of a collection of control elements, motion peripherals, a dedicated
motion control sequencer and dual port RAM to map internal signal nodes. IRMCF311 also
employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital
circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is
achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM
development environment. Sequencing, user interface, host communication, and upper layer
control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051
microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1
shows a typical application schematics using IRMCF311.
IRMCF311 is intended for development purpose and contains 48K bytes of RAM, which can be
loaded from external EEPROM for 8051 program execution. For high volume production,
IRMCK311 contains OTP ROM in place of program RAM to reduce the cost. Both IRMCF311
and IRMCK311 come in the same 64-pin QFP package with identical pin configuration to facilitate
PC board layout and transition to mass production
RS232C
Serial Comm
Field Communication
Service to indoor unit
Galvanic
Isolation
Galvanic
Isolation
IGBT inverter
DC bus
Compressor
Motor
Motor PWM +
PFC+GF
7
AC input Passive
(100EMI
230V)
Filter
IRS2630D
IPM
Fault
IRMCF311
2
Temperature feedback
Analog actuators
Relay, Valves, Switches
User Parameter
Storage
EEPROM
User Program
Storage
EEPROM
Analog input
Analog output
60-100W
Fan Motor
1
Temp sense
2
6
Digital I/O
3
15V
3.3V
1.8V
SPM
Motor PWM
Fault
IRS2631D
Multple
Power
supply
FREDFET inveter
Figure 1. Typical Application Block Diagram Using IRMCF311
4
IRMCF311
2 IRMCF311 Block Diagram and Main Functions
IRMCF311 block diagram is shown in Figure 2.
MCE (Motion Control Engine)
8051 Microcontroller
D/A
(PWM)
Periodic
Timer
Timer
Counnter0
Timer
Counnter1
Timer
Counnter2
Watchdog
Timer
2
Host
Interface
EEPROM
Interface
2
8bit
CPU
Core
I2C / SPI
(4)
PORT 1
PORT 2
(4)
Local
RAM
2KBytes*
PORT 3
(4)
PORT 5
Dual Port
RAM
512 Bytes*
MCE
Program
RAM
5.5KBytes*
Motion
Control
Modules
Crystal
(4MHz)
2
6
To motor2 IGBT
gate drive
CGATEKILL
To PFC
IGBT gate drive
PFCGKILL
3
Motor1 shunt
resistor
3
Motor2 shunt
resistor
3
AC line volt
sensing
3
PFC current
sensing
AIN0
AIN1
Interrupt
Control
4
Single Shunt
Current
Sensing
A/D
MUX
S/H
&
OP Amp
* Sizes are
configurable
Emulator
Debugger
To motor1 IGBT
gate drive
PFC
PWM
Program
RAM
48KBytes
UART1
2/4
6
FGATEKILL
UART0
(2)
Digital
I/Os
Dual Channel
Low Loss
SVPWM
Motion Control Bus
3
8bit uP Address/Data bus
Monitoring
DC bus volt
sensing
Analog inputs
JTAG
Motion Control
Sequencer
PLL
120MHz
Figure 2. IRMCF311 Internal Block Diagram
IRMCF311 contains the following functions for sensorless AC motor control applications:
•
Motion Control Engine (MCETM)
o Proportional plus Integral block
o Low pass filter
o Differentiator and lag (high pass filter)
o Ramp
o Limit
o Angle estimate (sensorless control)
o Inverse Clark transformation
o Vector rotator
o Bit latch
5
IRMCF311
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
•
Peak detect
Transition
Multiply-divide (signed and unsigned)
Divide (signed and unsigned)
Adder
Subtractor
Comparator
Counter
Accumulator
Switch
Shift
ATAN (arc tangent)
Function block (any curve fitting, nonlinear function)
16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE)
MCETM program and data memory (6K byte). Note 1
MCETM control sequencer
8051 microcontroller
o Three 16-bit timer
o 16-bit periodic timer
o 16-bit analog watchdog timer
o 16-bit capture timer
o Up to 14 discrete I/Os
o Six-channel 12-bit A/D
Four buffered channels (0 – 1.2V input)
Two unbuffered channels (0 – 1.2V input)
o JTAG port (4 pins)
o Up to two channels of analog output (8-bit PWM)
o Two UART
o I2C/SPI port
o 48K byte program RAM loaded from external EEPROM
o 2K byte data RAM. Note 1
Note 1: Total size of RAM is 8K byte including MCE program, MCE data, and
8051 data. Different sizes can be allocated depending on applications.
6
IRMCF311
P5.0/PFCGKILL
PFCPWM
P3.2/INT0
P3.6/RXD1
P3.7/TXD1
VSS
SCL/SO-SI
SDA/CS0
P5.2/TMS
P5.3/TDO
P5.1/TDI
TCK
TSTMOD
RESET
PLLVDD
PLLVSS
3 Pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
XTAL0
1
48
P3.0/INT2/CS1
XTAL1
2
47
CPWMUH
P1.1/RXD
3
46
CPWMUL
P1.2/TXD
4
45
CPWMVH
P1.3/SYNC/SCK
5
44
CPWMVL
P1.4/CAP
6
43
CPWMWH
VDD2
7
42
CPWMWL
VSS
8
41
CGATEKILL
VDD1
9
40
VDD1
FGATEKILL
10
39
VSS
FPWMWL
11
38
IPFC-
FPWMWH
12
37
IPFC+
FPWMVL
13
36
IPFCO
FPWMVH
14
35
VACO
FPWMUL
15
34
VAC-
FPWMUH
16
33
VAC+
IRMCF311
(Top View)
IFBCO
IFBC+
IFBC-
AREF
CMEXT
AIN1
AVSS
AVDD
AIN0
IFBFO
IFBF+
IFBF-
VSS
VDD2
P2.7/AOPWM1
P2.6/AOPWM0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. IRMCF311 Pin Configuration
7
IRMCF311
4 Input/Output of IRMCF311
All I/O signals of IRMCF311 are shown in Figure 4. All I/O pins are 3.3V logic interface except
A/D interface pins.
XTAL0
Crystal
XTAL1
CPWMUH
CPWMUL
CPWMVH
Communication
Interface
P1.1/RXD
CPWMVL
P1.2/TXD
CPWMWH
CPWMWL
P3.6/RXD1
CGATEKILL
P3.7/TXD1
FPWMUH
SDA/CS0
SCL/SDI-SDO
FPWMUL
FPWMVH
FPWMVL
FPWMWH
P1.3/SYNC/SCK
Discrete I/O
Channel 1
PWM gate signal
Interface
Channel 2
PWM gate signal
Interface
FPWMWL
P1.4/CAP
FGATEKILL
P3.0/INT2/CS1
P3.2/INT0
PFCPWM
P5.0/PGATEKILL
System Reset
RESET
IRMCF311
P5.1/TDI
AVDD
AVSS
CMEXT
TCK
JTAG port
Power Factor Control
PWM gate signal
Interface
P5.2/TMS
AREF
P5.3/TDO
IFBC+
D/A Interface
(PWM output)
P2.6/AOPWM0
IFBC-
P2.7/AOPWM1
IFBCO
IFBF+
IFBFIFBFCO
Test mode
(must be tied VSS)
Digital power/
ground
TSTMOD
A/D Interface
VAC+
VACVACO
VSS
IPFC+
IPFCIPFCO
PLLVDD
AIN1
VDD1(3.3V)
VDD2(1.8V)
AIN0
PLL power/
ground
PLLVSS
Figure 4. Input/Output of IRMCF311
4.1
8051 Peripheral Interface Group
UART Interface
P1.1/RXD
Input, Receive data to IRMCF311
8
IRMCF311
P1.2/TXD
P3.6/RXD1
P3.7/TXD1
Output, Transmit data from IRMCF311
Input, 2nd channel Receive data to IRMCF311
Output, 2nd channel Transmit data from IRMCF311
Discrete I/O Interface
P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock,
needs to be pulled up to VDD1 in order to boot from I2C EEPROM
P1.4/CAP
Input/output port 1.4, can be configured as Capture Timer input
P3.0/INT2/CS1 Input/output port 3.0, can be configured as external interrupt 2 or SPI chip
select 1
P3.2/INT0
Input/output port 3.2, can be configured as external interrupt 0
Analog output Interface
P2.6/AOPWM0 Output, PWM output 0, 8-bit resolution, configurable carrier frequency
P2.7/AOPWM1 Output, PWM output 1, 8-bit resolution, configurable carrier frequency
Crystal Interface
XTAL0
XTAL1
Reset Interface
RESET
I2C/SPI Interface
SCL/SO-SI
SDA/CS0
P3.0/INT2/CS1
P1.3/SYNC/SCK
4.2
Input, connected to crystal
Output, connected to crystal
Inout, system reset, needs to be pulled up to VDD1 but doesn’t require
external RC time constant
Output, I2C clock output or SPI data
Input/output, I2C data line or SPI chip select 0
Input/output, INT2 or SPI chip select 1
Input/output, SYNC output or SPI clock, needs to be pulled up to VDD1
in order boot from I2C EEPROM
Motion Peripheral Interface Group
PWM
CPWMUH
CPWMUL
CPWMVH
CPWMVL
CPWMWH
Output, motor 1 PWM phase U high side gate signal
Output, motor 1 PWM phase U low side gate signal
Output, motor 1 PWM phase V high side gate signal
Output, motor 1 PWM phase V low side gate signal
Output, motor 1 PWM phase W high side gate signal
9
IRMCF311
CPWMWL
FPWMUH
FPWMUL
FPWMVH
FPWMVL
FPWMWH
FPWMWL
PFCPWM
Output, motor 1 PWM phase W low side gate signal
Output, motor 2 PWM phase U high side gate signal
Output, motor 2 PWM phase U low side gate signal
Output, motor 2 PWM phase V high side gate signal
Output, motor 2 PWM phase V low side gate signal
Output, motor 2 PWM phase W high side gate signal
Output, motor 2 PWM phase W low side gate signal
Output, PFC PWM
Fault
CGATEKILL
Input, upon assertion, this negates all six PWM signals for motor 1,
programmable logic sense
P5.0/PFCGKILL Input, upon assertion, this negates PFCPWM signal, programmable logic
sense, can be configured as discrete I/O in which case CGATEKILL
negates PFCPWM
FGATEKILL
Input, upon assertion, this negates all six PWM signals for motor 2,
programmable logic sense
4.3
Analog Interface Group
AVDD
AVSS
AREF
CMEXT
IFBC+
IFBCIFBCO
IFBF+
IFBFIFBFO
IPFC+
IPFCIPFO
VAC+
VACVACO
Analog power (1.8V)
Analog power return
Buffered 0.6V output
Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be
connected.
Input, Operational amplifier positive input for shunt resistor current
sensing of motor 1
Input, Operational amplifier negative input for shunt resistor current
sensing of motor 1
Output, Operational amplifier output for shunt resistor current sensing of
motor 1
Input, Operational amplifier positive input for shunt resistor current
sensing of motor 2
Input, Operational amplifier negative input for shunt resistor current
sensing of motor 2
Output, Operational amplifier output for shunt resistor current sensing of
motor 2
Input, Operational amplifier positive input for PFC current sensing
Input, Operational amplifier negative input for PFC current sensing
Output, Operational amplifier output for PFC current sensing
Input, Operational amplifier positive input for PFC AC voltage sensing
Input, Operational amplifier negative input for PFC AC voltage sensing
Output, Operational amplifier output for PFC AC voltage sensing
10
IRMCF311
AIN0
AIN1
4.4
Power Interface Group
VDD1
VDD2
VSS
PLLVDD
PLLVSS
4.5
Input, Analog input channel 0 (0 - 1.2V), typically configured for DC bus
voltage input
Input, Analog input channel 1 (0 - 1.2V), needs to be pulled down to
AVSS if unused
Digital power for I/O (3.3V)
Digital power for core logic (1.8V)
Digital common
PLL power (1.8V)
PLL ground return
Test Interface Group
TSTMOD
P5.1/TDI
P5.2/TMS
TCK
P5.3/TDO
Must be tied to VSS, used only for factory testing.
Input, JTAG test data input, or programmable discrete I/O
Input, JTAG test mode select, or programmable discrete I/O
Input, JTAG test clock
Output, JTAG test data output, or programmable discrete I/O
11
IRMCF311
5 Application Connections
Typical application connection is shown Figure 5. All components necessary to implement a
complete sensorless drive control algorithm are shown connected to IRMCF311.
System
Clock
XTAL0
4MHz
Crystal
XTAL1
PLLVDD
1.8V
PLLVSS
To indoor unit
Microcontroller
(RS232C)
P1.1/RXD
To other Host
(RS232C)
P3.7/TXD
P3.6/RXD
PLL
Logic
System
clock
Motion
Control
Modules
P1.2/TXD
SDA/CS0
SCL/SDI-SDO
Other Communication
(I2C)
RS232C
Dual
Port
Memory
(1kbyte)
&
MCE
Memory
(3kByte)
RS232C
I2C
3.3V
P1.3/SYNC/SCK
P1.4/CAP
Digital I/O
Control
PORT1
Motion
Control
Sequencer
CPWMUH
CPWMUL
CPWMVH
CPWMVL
CPWMWH
CPWMWL
CGATEKILL
Compressor
IGBT Gate
Drive
(i.e.IRS2630D)
FPWMUH
Low Loss
Space
Vector
PWM
PFC
PWM
FPWMUL
Fan motor
IGBT Gate
Drive
(i.e.IR21366)
FPWMVH
FPWMVL
FPWMWH
FPWMWL
FGATEKILL
PFC
IGBT
Gate drive
PFCPWM
PGATEKILL
0.6V
IFBC+
S/H
P3.0/INT2/CS1
Low Loss
Space
Vector
PWM
Compressor
DC bus shunt
resistor
IFBCIFBCO
PORT3
0.6V
IFBF+
S/H
Timer
RESET
Test
Mode
RESET
Watchdog
Timer
Test Mode
Circuit
Local
RAM
4kByte
PWM0
Analog Output
P2.7/AOPWM1
IFBFO
0.6V
IFBP+
System
Reset
TSTMOD
P2.6/AOPWM0
FAN motor
DC bus shunt
resistor
IFBF-
Program
RAM
(48kByte)
PWM1
S/H
FAN motor
DC bus shunt
resistor
IFBPIFBPO
VAC+
12bit
A/D
&
MUX
AC line
voltage
VACVACO
DC bus
voltage
AIN0
AIN1
AREF
Other analog input (0-1.2V)
Optional External Voltage
Reference (0.6V)
CMEXT
TCK
P5.1/TDI
P5.2/TMS
JTAG
Control
P5.3/TDO
3.3V
1.8V
JTAG
Interface
8051
CPU
AVDD
1.8V
AVSS
VDD1
VDD2
VSS
IRMCF311
Figure 5. Application Connection of IRMCF311
12
IRMCF311
6 DC Characteristics
6.1
Absolute Maximum Ratings
Symbol
VDD1
VDD2
VIA
VID
TA
TS
Parameter
Min
Typ
Max
Supply Voltage
-0.3 V
3.6 V
Supply Voltage
-0.3 V
1.98 V
Analog Input Voltage
-0.3 V
1.98 V
Digital Input Voltage
-0.3 V
3.65 V
Ambient Temperature
-40 ˚C
85 ˚C
Storage Temperature
-65 ˚C
150 ˚C
Table 1. Absolute Maximum Ratings
Condition
Respect to VSS
Respect to VSS
Respect to AVSS
Respect to VSS
Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only and function of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
System Clock Frequency and Power Consumption
Symbol
SYSCLK
Parameter
Min
Typ
Max
System Clock
32
128
Table 2. System Clock Frequency
Unit
MHz
240
200
160
Power (mW)
6.2
120
80
VDD2 (1.8V)
40
VDD1 (3.3V)
Total
0
0
50
100
Clock Frequency (MHz)
150
Figure 6. Clock Frequency vs. Power Consumption
13
IRMCF311
6.3
Digital I/O DC Characteristics
Symbol
VDD1
VDD2
VIL
VIH
CIN
IL
IOL1(2)
IOH1(2)
IOL2
(3)
IOH2(3)
Parameter
Min
Typ
Max
Supply Voltage
3.0 V
3.3 V
3.6 V
Supply Voltage
1.62 V
1.8 V
1.98 V
Input Low Voltage
-0.3 V
0.8 V
Input High Voltage
2.0 V
3.6 V
Input capacitance
3.6 pF
Input leakage current
±10 nA
±1 μA
Low level output
8.9 mA
13.2 mA
15.2 mA
current
High level output
12.4 mA
24.8 mA
38 mA
current
Low level output
17.9 mA
26.3 mA
33.4 mA
current
High level output
24.6 mA
49.5 mA
81 mA
current
Table 3. Digital I/O DC Characteristics
Condition
Recommended
Recommended
Recommended
Recommended
(1)
VO = 3.3 V or 0 V
VOL = 0.4 V
(1)
VOH = 2.4 V
(1)
VOL = 0.4 V
(1)
VOH = 2.4 V
(1)
Note:
(1) Data guaranteed by design.
(2) Applied to SCL/SO-SI, SDA/CS0 pins.
(3) Applied to P1.1/RXD, P1.2/TXD, P1.3/SYNC/SCK, P1.4/CAP, P2.6/AOPWM0,
P2.7/AOPWM1, P3.0/INT2/CS1, P3.2/INT0, P3.6/RXD1, P3.7/TXD1, P5.0/PFCGKILL,
P5.2/TMS, P5.3/TDO, P5.1/TDI, CGATEKILL, FGATEKILL, CPWMUL, CPWMUH,
CPWMVL, CPWMVH, CPWMWL, CPWMWH, FPWMUL, FPWMUH, FPWMVL,
FPWMVH, FPWMWL, FPWMWH, and PFCPWM pins.
14
IRMCF311
6.4
PLL and Oscillator DC Characteristics
Symbol
VPLLVDD
VIL OSC
VIH OSC
Parameter
Supply Voltage
Oscillator Input Low
Voltage
Oscillator Input High
Voltage
Table 4.
Min
1.62 V
VPLLVSS
Typ
1.8 V
-
Max
1.92 V
0.2*
VPLLVDD
VPLLVDD
0.8*
VPLLVDD
PLL DC Characteristics
Condition
Recommended
VPLLVDD = 1.8 V
(1)
VPLLVDD = 1.8 V
(1)
Note:
(1) Data guaranteed by design.
6.5
Analog I/O DC Characteristics
- OP amps for current sensing (IFBC+, IFBC-, IFBCO, IFBF+, IFBF-, IFBFO, IPFC+, IPFC-,
IPFCO)
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
VAVDD
Supply Voltage
1.71 V
1.8 V
VOFFSET
Input Offset Voltage
VI
Input Voltage Range
0V
VOUTSW
OP amp output
50 mV
(1)
operating range
CIN
Input capacitance
3.6 pF
RFDBK
OP amp feedback
5 kΩ
resistor
OP GAINCL
CMRR
ISRC
ISNK
Max
1.89 V
26 mV
1.2 V
1.2 V
Condition
Recommended
VAVDD = 1.8 V
Recommended
VAVDD = 1.8 V
20 kΩ
(1)
Operating Close loop
80 db
Gain
Common Mode
80 db
Rejection Ratio
Op amp output source
1 mA
current
Op amp output sink
100 μA
current
Table 5. Analog I/O DC Characteristics
(1)
Requested
between op amp
output and
negative input
(1)
VOUT = 0.6 V
(1)
VOUT = 0.6 V
(1)
Note:
(1) Data guaranteed by design.
15
IRMCF311
6.6
Analog I/O DC Characteristics
- OP amp for voltage sensing (VAC+,VAC-,VACO)
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
VAVDD
Supply Voltage
1.71 V
1.8 V
1.89 V
VOFFSET
Input Offset Voltage
26 mV
VI
Input Voltage Range
0V
1.2 V
VOUTSW
OP amp output
50 mV
1.2 V
(1)
operating range
CIN
Input capacitance
3.6 pF
OP GAINCL
Operating Close loop
80 db
Gain
CMRR
Common Mode
80 db
Rejection Ratio
ISRC
Op amp output source
5 mA
current
ISNK
Op amp output sink
500 μA
current
Table 6. Analog I/O DC Characteristics
Condition
VAVDD = 1.8 V
VAVDD = 1.8 V
(1)
(1)
(1)
VOUT = 0.6 V
(1)
VOUT = 0.6 V
(1)
Note:
(1) Data guaranteed by design.
16
IRMCF311
6.7
Under Voltage Lockout DC Characteristics
- Based on AVDD (1.8V)
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
UVCC+
UVcc positive going
1.53 V
1.66 V
1.71 V
Threshold
UVCCUVcc negative going
1.52 V
1.62 V
1.71 V
Threshold
UVCCH
UVcc Hysteresys
40 mV
Table 7. UVcc DC Characteristics
6.8
Condition
VDD1 = 3.3 V
VDD1 = 3.3 V
CMEXT and AREF Characteristics
CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C.
Condition
Symbol
Parameter
Min
Typ
Max
VCM
CMEXT voltage
495 mV
600 mV
700 mV
VAVDD = 1.8 V
VAREF
Buffer Output Voltage
495 mV
600 mV
700 mV
VAVDD = 1.8 V
(1)
Load
regulation
(V
1
mV
∆Vo
DC
0.6)
(1)
PSRR
Power Supply Rejection
75 db
Ratio
Table 8. CMEXT and AREF DC Characteristics
Note:
(1) Data guaranteed by design.
17
IRMCF311
7 AC Characteristics
7.1
PLL AC Characteristics
Symbol
FCLKIN
FPLL
FLWPW
JS
D
TLOCK
Parameter
Min
Typ
Max
Condition
(1)
Crystal input
3.2 MHz
4 MHz
60 MHz
frequency
(see figure below)
Internal clock
32 MHz
50 MHz
128 MHz (1)
frequency
(1)
Sleep mode output FCLKIN ÷ 256
frequency
(1)
Short time jitter
200 psec
(1)
Duty cycle
50 %
PLL lock time
500 μsec (1)
Table 9. PLL AC Characteristics
Note:
(1) Data guaranteed by design.
R1=1M
R2=10
Xtal
C1=30PF
C2=30PF
18
IRMCF311
7.2
Analog to Digital Converter AC Characteristics
Unless specified, Ta = 25˚C.
Symbol
Parameter
TCONV
Conversion time
THOLD
Sample/Hold
maximum hold time
Min
-
Typ
-
Max
2.05 μsec
10 μsec
Condition
(1)
Voltage droop ≤
15 LSB
(see figure below)
Table 10. A/D Converter AC Characteristics
Note:
(1) Data guaranteed by design.
Input Voltage
Voltage droop
S/H Voltage
tSAMPLE
THOLD
19
IRMCF311
7.3
Op amp AC Characteristics
- OP amps for current sensing (IFBC+, IFBC-, IFBCO, IFBF+, IFBF-, IFBFO, IPFC+, IPFC-,
IPFCO)
Unless specified, Ta = 25˚C.
Symbol
Parameter
OPSR
OP amp slew rate
OPIMP
TSET
Min
-
Typ
10 V/μsec
Max
-
-
108 Ω
400 ns
-
Min
Typ
2.5 V/μsec
Max
-
-
108 Ω
650 ns
-
OP input impedance
Settling time
Condition
VAVDD = 1.8 V,
CL = 33 pF (1)
(1)
VAVDD = 1.8 V,
CL = 33 pF (1)
Table 11. Current Sensing OP Amp AC Characteristics
Note:
(1) Data guaranteed by design.
7.4
Op Amp AC Characteristics
- OP amp for voltage sensing (VAC+,VAC-,VACO)
Unless specified, Ta = 25˚C.
Symbol
Parameter
OPSR
OP amp slew rate
OPIMP
TSET
OP input impedance
Settling time
Condition
VAVDD = 1.8 V,
CL = 33 pF (1)
(1)
VAVDD = 1.8 V,
CL = 33 pF (1)
Table 12. Voltage sensing OP Amp AC Characteristics
Note:
(1) Data guaranteed by design.
20
IRMCF311
7.5
SYNC to SVPWM and A/D Conversion AC Timing
twSYNC
SYNC
tdSYNC1
IU,IV,IW
tdSYNC2
AINx
tdSYNC3
PWMUx,PWMVx,PWMWx
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
twSYNC
SYNC pulse width
32
tdSYNC1
SYNC to current
100
feedback conversion
time
tdSYNC2
SYNC to AIN0-6
200
analog input
conversion time
tdSYNC3
SYNC to PWM output
2
delay time
Table 13. SYNC AC Characteristics
Unit
SYSCLK
SYSCLK
SYSCLK
(1)
SYSCLK
Note:
(1) AIN1 through AIN6 channels are converted once every 6 SYNC events
21
IRMCF311
7.6
GATEKILL to SVPWM AC Timing
twGK
GATEKILL
tdGK
PWMUx,PWMVx,PWMWx
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
twGK
GATEKILL pulse
32
width
tdGK
GATEKILL to PWM
100
output delay
Table 14. GATEKILL to SVPWM AC Timing
7.7
Unit
SYSCLK
SYSCLK
Interrupt AC Timing
twINT
P3.2/INT0
P3.3/INT1
tdINT
Internal
Program
Counter
Internal Vector Fetch
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
twINT
INT0, INT1 Interrupt
4
Assertion Time
tdINT
INT0, INT1 latency
4
Table 15. Interrupt AC Timing
Unit
SYSCLK
SYSCLK
22
IRMCF311
7.8
I2C AC Timing
TI2CLK
TI2CLK
SCL
tI2ST1
tI2WSETUP
tI2ST2
tI2WHOLD
tI2RSETUP
tI2EN1
tI2RHOLD
tI2EN2
SDA
Unless specified, Ta = 25˚C.
Symbol
Parameter
2
TI2CLK
I C clock period
tI2ST1
I2C SDA start time
tI2ST2
I2C SCL start time
tI2WSETUP
I2C write setup time
tI2WHOLD
I2C write hold time
tI2RSETUP
I2C read setup time
tI2RHOLD
I2C read hold time
Min
Typ
10
0.25
0.25
0.25
0.25
2
(1)
I C filter time
1
2
Table 16. I C AC Timing
Max
8192
-
Unit
SYSCLK
TI2CLK
TI2CLK
TI2CLK
TI2CLK
SYSCLK
SYSCLK
Note:
(1) I2C read setup time is determined by the programmable filter time applied to I2C
communication.
23
IRMCF311
7.9
SPI AC Timing
7.9.1 SPI Write AC timing
TSPICLK
P1.3/SYNC/SCK
tWRDELAY
SCL/SO-SI
Bit7(MSB)
tCSDELAY
tSPICLKHT
tSPICLKLT
Bit0(LSB)
tCSHOLD
tCSHIGH
SDA/CS0
P3.0/INT2/CS1
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
TSPICLK
SPI clock period
4
tSPICLKHT
SPI clock high time
1/2
tSPICLKLT
SPI clock low time
1/2
tCSDELAY
CS to data delay time
10
tWRDELAY
CLK falling edge to data
10
delay time
tCSHIGH
CS high time between two
1
consecutive byte transfer
tCSHOLD
CS hold time
1
Table 17. SPI Write AC Timing
Unit
SYSCLK
TSPICLK
TSPICLK
nsec
nsec
TSPICLK
TSPICLK
24
IRMCF311
7.9.2 SPI Read AC Timing
TSPICLK
P1.3/SYNC/SCK
tRDHOLD
tSPICLKHT
tSPICLKLT
tRDSU
SCL/SO-SI
Bit7(MSB)
tCSRD
Bit0(LSB)
tCSHOLD
tCSHIGH
SDA/CS0
P3.0/INT2/CS1
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
TSPICLK
SPI clock period
4
tSPICLKHT
SPI clock high time
1/2
tSPICLKLT
SPI clock low time
1/2
tCSRD
CS to data delay time
10
tRDSU
SPI read data setup time
10
tRDHOLD
SPI read data hold time
10
tCSHIGH
CS high time between two
1
consecutive byte transfer
tCSHOLD
CS hold time
1
Table 18. SPI Read AC Timing
Unit
SYSCLK
TSPICLK
TSPICLK
nsec
nsec
nsec
TSPICLK
TSPICLK
25
IRMCF311
7.10 UART AC Timing
TBAUD
TXD
Start Bit
Data and Parity Bit
Stop Bit
RXD
TUARTFIL
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
TBAUD
Baud Rate Period
57600
TUARTFIL
UART sampling filter
1/16
(1)
period
Table 19. UART AC Timing
Max
-
Unit
bit/sec
TBAUD
Note:
(1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of
1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated.
26
IRMCF311
7.11 CAPTURE Input AC Timing
TCAPCLK
tCAPHIGH
P1.4/CAP
tCAPLOW
tCRDELAY
CREV(H,L)
Internal
register
tCLDELAY
CLAST(H,L)
Internal
register
tINTDELAY
Interrupt
Vector Fetch
Interrupt
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
Max
TCAPCLK
CAPTURE input
8
period
tCAPHIGH
CAPTURE input high
4
time
tCAPLOW
CAPTURE input low
4
time
tCRDELAY
CAPTURE falling edge
4
to capture register latch
time
tCLDELAY
CAPTURE rising edge
4
to capture register latch
time
tINTDELAY
CAPTURE input
4
interrupt latency time
Table 20. CAPTURE AC Timing
Unit
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
27
IRMCF311
7.12 JTAG AC Timing
TJCLK
TCK
tJHIGH
tJLOW
tCO
TDO
tJSETUP
tJHOLD
TDI/TMS
Unless specified, Ta = 25˚C.
Symbol
Parameter
Min
Typ
TJCLK
TCK Period
tJHIGH
TCK High Period
10
tJLOW
TCK Low Period
10
tCO
TCK to TDO propagation
0
delay time
tJSETUP
TDI/TMS setup time
4
tJHOLD
TDI/TMS hold time
0
Table 21. JTAG AC Timing
Max
50
5
Unit
MHz
nsec
nsec
nsec
-
nsec
nsec
28
IRMCF311
8 I/O Structure
The following figure shows the PWM and digital I/O structure.
VDD1
(3.3V)
Internal digital circuit
Low true logic
70k Ω
6.0V
PIN
270 Ω
6.0V
Figure 7 All digital I/O and PWM outputs
The following figure shows RESET and GATEKILL I/O structure.
VDD1
(3.3V)
RESET
GATEKILL
circuit
70k Ω
6.0V
PIN
270 Ω
6.0V
VSS
Figure 8 RESET, GATEKILL I/O
29
IRMCF311
The following figure shows the analog input structure.
AVDD
Analog input
6.0V
PIN
1 Ω
Analog Circuit
6.0V
AVSS
Figure 9 Analog input
The following figure shows all analog operational amplifier output pins and AREF pin I/O
structure.
AVDD
Analog output
6.0V
PIN
Analog Circuit
6.0V
AVSS
Figure 10 Analog operational amplifier output and AREF I/O structure
The following figure shows the VSS, AVSS and PLLVSS pin structure
VDD1
AVDD
PLLVDD
PIN
6.0V
Figure 11 VSS, AVSS and PLLVSS pin structure
The following figure shows the VDD1, VDD2, AVDD and PLLVDD pin structure
30
IRMCF311
PIN
6.0V
VSS
AVSS
PLLVSS
Figure 12 VDD1, VDD2, AVDD and PLLVDD pin structure
The following figure shows the XTAL0 and XTAL1 pins structure
PLLVDD
6.0V
PIN
1 Ω
6.0V
PLLVSS
Figure 13 XTAL0/XTAL1 pins structure
31
IRMCF311
9 Pin List
Pin
Number
Pin Name
1
2
3
XTAL0
XTAL1
P1.1/RXD
4
P1.2/TXD
5
P1.3/SYNC/
SCK
6
P1.4/CAP
7
8
9
10
VDD2
VSS
VDD1
FGATEKILL
11
FPWMWL
12
FPWMWH
13
FPWMVL
14
FPWMVH
15
FPWMUL
16
FPWMUH
17
P2.6/
AOPWM0
P2.7/
AOPWM1
VDD2
VSS
IFBFIFBF+
IFBFO
18
19
20
21
22
23
Internal IC
Pull-up
/Pull-down
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
Pin
Type
Description
I
O
I/O
Crystal input
Crystal output
Discrete programmable I/O or UART receive input
I/O
Discrete programmable I/O or UART transmit
output
Discrete programmable I/O or SYNC output or SPI
clock, needs to be pulled up to VDD1 in order to
boot from I2C EEPROM
Discrete programmable I/O or Capture Timer input
I/O
I/O
P
P
P
I
O
O
O
O
O
O
I/O
P
P
I
I
O
1.8V digital power
Digital common
3.3V digital power
Fan PWM shutdown input, 2-μsec digital filter,
configurable either high or low true.
Fan PWM gate drive for phase W low side,
configurable either high or low true
Fan PWM gate drive for phase W high side,
configurable either high or low true
Fan PWM gate drive for phase V low side,
configurable either high or low true
Fan PWM gate drive for phase V high side,
configurable either high or low true
Fan PWM gate drive for phase U low side,
configurable either high or low true
Fan PWM gate drive for phase U high side,
configurable either high or low true
Discrete programmable I/O or analog output 0
(PWM)
Discrete programmable I/O or analog output 1
(PWM)
1.8V digital power
Digital common
Fan single shunt current sensing OP amp input (-)
Fan single shunt current sensing OP amp input (+)
Fan single shunt current sensing OP amp output
32
IRMCF311
Pin
Number
Pin Name
Internal IC
Pull-up
/Pull-down
Pin
Type
24
AIN0
I
25
26
27
AVDD
AVSS
AIN1
P
P
I
28
CMEXT
O
29
30
AREF
IFBC-
O
I
31
IFBC+
I
32
IFBCO
O
33
34
35
36
37
38
39
40
41
VACVAC+
VACO
IPFCO
IPFC+
IPFCVSS
VDD1
CGATEKILL
I
I
O
O
I
I
P
P
I
42
CPWMWL
43
CPWMWH
44
CPWMVL
45
CPWMVH
46
CPWMUL
47
CPWMUH
48
P3.0/INT2
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
O
O
O
O
O
O
I/O
Description
Analog input channel 0, 0-1.2V range, needs to be
pulled down to AVSS if unused
1.8V analog power
Analog common
Analog input channel 1, 0-1.2V range, needs to be
pulled down to AVSS if unused
Unbuffered analog reference voltage output (0.6V),
capacitor needs to be connected.
Analog reference voltage output (0.6V)
Compressor single shunt current sensing OP amp
input (-)
Compressor single shunt current sensing OP amp
input (+)
Compressor single shunt current sensing OP amp
output
AC input voltage sensing OP amp input (-)
AC input voltage sensing OP amp input (+)
AC input voltage sensing OP amp output
PFC shunt current sensing OP amp output
PFC shunt current sensing OP amp input (+)
PFC shunt current sensing OP amp input (-)
Digital common
3.3V digital power
Compressor PWM shutdown input, 2-μsec digital
filter, configurable either high or low true.
Compressor PWM gate drive for phase W low side,
configurable either high or low true
Compressor PWM gate drive for phase W high side,
configurable either high or low true
Compressor PWM gate drive for phase V low side,
configurable either high or low true
Compressor PWM gate drive for phase V high side,
configurable either high or low true
Compressor PWM gate drive for phase U low side,
configurable either high or low true
Compressor PWM gate drive for phase U high side,
configurable either high or low true
Discrete programmable I/O or INT2 digital input
33
IRMCF311
Pin
Number
Pin Name
49
P5.0/
PFCGKILL
50
PFCPWM
51
P3.2/INT0
52
P3.6/RXD1
53
P3.7/TXD1
54
55
VSS
SCL/SO-SI
56
SDA/CS0
57
P5.2/TMS
58
P5.3/TDO
59
P5.1/TDI
60
61
TCK
TSTMOD
62
RESET
63
64
PLLVDD
PLLVSS
Internal IC
Pull-up
/Pull-down
70 kΩ Pull
up
Pin
Type
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
O
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
70 kΩ Pull
up
58 kΩ pull
down
70 kΩ Pull
up
I
I/O
Description
Discrete programmable I/O or PFC PWM shutdown
input, 2-μsec digital filter, configurable either high
or low true.
PFC PWM gate drive, configurable either high or
low true
Discrete programmable I/O or INT0 input
P
I/O
Discrete programmable I/O or 2nd UART receive
input
Discrete programmable I/O or 2nd UART transmit
output
Digital common
I2C clock output or SPI data
I/O
I2C data or SPI chip select 0
I/O
I/O
Discrete programmable I/O or JTAG test mode
select
Discrete programmable I/O or JTAG port test data
output
Discrete programmable I/O or JTAG test data input
I
I
JTAG test clock
Test mode. Must be tied to VSS. Factory use only
I/O
Reset , low true, Schmitt trigger input
I/O
I/O
I/O
P
P
Table 22. Pin List
1.8 V PLL power
PLL ground
34
IRMCF311
10 Package Dimensions
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
IRMCF311
11 Part Marking Information
IRMCF311
Part Number
IR Logo
YWWP
Date Code
XXXXXX
Production Lot
Pin 1
Indentifier
Order Information
Lead-Free Part in 64-lead QFP
Moisture sensitivity rating – MSL3
Part number
IRMCF311TR
IRMCF311TY
Order quantities
1500 parts on tape and reel in dry pack
1600 parts on trays (160 parts per tray) in dry pack
The LQFP-64 is MSL3 qualified
This product has been designed and qualified for the industrial level
Qualification standards can be found at www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
Data and specifications subject to change without notice. 12/05/2006
www.irf.com
36
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