Wireless Components
ASK/FSK Single Conversion Receiver
TDA 5210 Version 3.0
Specification May 2001
Revision History
Current Version: 3.0 as of 18.05.01
Previous Version: 2.4, Dec. 2000
Page
(in previous
Version)
Page(s)
(in current
Version)
Subjects (major changes since last revision)
Product Info,
2-2
Product Info,
2-2
typ. supply current changed
3-12
3-12
Sec. 3.4.8: max. datarate changed, Sec. 3.4.9: max. output current changed
4-4
4-4
value of a changed to 1.414
4-8
4-8
FSK demodulator gain changed to 140µV/kHz
4-13
4-13
value for C2 changed to 22nF according to bill of materials, τ2 and T2 changed
5-3
5-3
min. supply current limits added, max. limits changed
5-4
5-4
supply current max. limit changed, min. limit added
5-5
5-5
NFLNA specification removed
5-6
5-6
3VOUT min. & max. limits changed, TAGC typ. & max. values changed, IFO:
NFmix and RF/IF isolation removed
5-7
5-7
Section “SLICER” reworked, max. datarate at given load capacitance quoted,
high output voltage limits changed, precharge current: min., max. limits
changed, PDO load and leakage currents limits and typ. values changed,
5-8
5-8
FSK demodulation gain min. limit changed
5-9
5-9
PDWN-current max. limit changed, supply currents min. limits added, max. limits changed, 3VOUT min. & max. limits changed, ITAGC_out limits changed
5-10
5-10
Section “SLICER” reworked, max. datarate at given load capacitance quoted,
high output voltage limits changed, precharge current: min., max. limits
changed, PDO output voltage removed
5-15
5-15
C18 value changed
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Edition 05.01
Published by Infineon Technologies AG,
Balanstraße 73,
81541 München
© Infineon Technologies AG May 2001.
All Rights Reserved.
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TDA 5210
Product Info
Product Info
General Description
Features
Application
The IC is a very low power consump- Package
tion single chip FSK/ASK Superheterodyne Receiver (SHR) for the
frequency bands 810 to 870 MHz and
400 to 440 MHz that is pin compatible
with the ASK Receiver TDA5200. The
IC offers a high level of integration and
needs only a few external components. The device contains a low noise
amplifier (LNA), a double balanced
mixer, a fully integrated VCO, a PLL
synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK
demodulator, a data filter, a data comparator (slicer) and a peak detector.
Additionally there is a power down feature to save battery life.
■
Low supply current (typ. at 868MHz
Is = 5.9mA in FSK mode,
Is = 5.2mA in ASK mode)
■
Selectable frequency ranges 810870 MHz and 400-440 MHz
■
Supply voltage range 5V ±10%
■
Limiter with RSSI generation,
operating at 10.7MHz
■
Power down mode with very low
supply current (50nA typ)
■
Selectable reference frequency
■
FSK and ASK demodulation capability
■
2nd order low pass data filter with
external capacitors
■
Fully integrated VCO and PLL
Synthesiser
■
Data slicer with self-adjusting
threshold
■
ASK sensitivity < –107dBm
■
FSK sensitivity Uth r es h o ld : Ilo a d =4.2µA
RSSI < Uth r es h o ld : Ilo a d = -1.5µA
4
UC
C
Uc :< 2.6V : Gain high
Uc :> 2.6V : Gain low
Uc ma x = VC C - 0.7V
Uc min = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal
(RSSI) generated by the Limiter with an externally provided threshold voltage
Uthres. As shown in the following figure the threshold voltage can have any
value between approximately 0.8 and 2.8V to provide a switching point within
the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage
can be generated by attaching a voltage divider between the 3VOUT pin
(Pin 24) which provides a temperature stable 3V output generated from the
internal bandgap voltage and the THRES pin. If the RSSI level generated by the
Limiter is higher than Uthres, the OTA generates a positive current Iload. This
yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a
negative current. These currents do not have the same values in order to
achieve a fast-attack and slow-release action of the AGC and are used to
charge an external capacitor which finally generates the LNA gain control voltage.
Wireless Components
4-2
Specification, May 2001
TDA 5210
Applications
LNA always
in high gain mode
3
2
RSSI Level Range
UTHRES Voltage Range
2.5
RSSI Level
1.5
1
LNA always
in low gain mode
0.5
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the optimum point is described in the accompanying
Application Note, a threshold voltage level of 1.8V is apparently a viable choice.
It should be noted that the output of the 3VOUT pin is capable of driving up to
50µA, but that the THRES pin input current is only in the region of 40nA. As the
current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. The
sum of R1 and R2 has to be 600kΩ in order to yield 3V at the 3VOUT pin. R1
can thus be chosen as 240kΩ, R2 as 360kΩ to yield an overall 3VOUT output
current of 5µA1 and a threshold voltage of 1.8V
Note: If the LNA gain shall be kept in either high or low gain mode this has to
be accomplished by tying the THRES pin to a fixed voltage. In order to achieve
high gain mode operation, a voltage higher than 2.8V shall be applied to the
THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain
mode operation a voltage lower than 0.7V shall be applied to the THRES, such
as a short to ground.
As stated above the capacitor connected to the TAGC pin is generating the gain
control voltage of the LNA due to the charging and discharging currents of the
OTA and thus is also responsible for the AGC time constant. As the charging
and discharging currents are not equal two different time constants will result.
The time constant corresponding to the charging process of the capacitor shall
be chosen according to the data rate. According to measurements performed
at Infineon the capacitor value should be greater than 47nF.
1. note the 20kΩ resistor in series with the 3.1V internal voltage source
Wireless Components
4-3
Specification, May 2001
TDA 5210
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100kΩ on-chip resistors a
2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as
depicted in the following figure and described in the following formulas1.
C1
Pins:
C2
22
21
R
R
100k
100k
19
Filter_Design.wmf
Figure 4-3
Data Filter Design
(1)(2)
b C2 = -------------------------4QRΠf 3dB
2Q b
C 1 = ---------------------R2Πf 3dB
with
Q = ------ba
(3)the quality factor of the poles
where
in case of a Bessel filter a = 1.3617, b = 0.618
and thus Q = 0.577
and in case of a Butterworth filter a = 1.414, b = 1
and thus Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100kΩ:
C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4-4
Specification, May 2001
TDA 5210
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is
operating at the intended frequency is determined by the reactive part of the
negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the
quartz specifications given by the quartz manufacturer.
CS
Pin 28
Crystal
Input
impedance
Z1-28
TDA5210
Pin 1
Quartz_load.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
CS =
1
1
+ 2π f X L
Cl
with Cl the load capacitance (refer to the quartz crystal specification).
Examples:
6.7 MHz: CL = 12 pFXL=695ΩCS = 8.9 pF
13.4 MHz: CL = 12 pFXL=1010 ΩCS = 5.9 pF
These values may be obtained in high accuracy by putting two capacitors in
series to the quartz, such as 22pF and 15pF in the 6.7MHz case and 22pF and
8.2pF in the 13.4MHz case.
Wireless Components
4-5
Specification, May 2001
TDA 5210
Applications
4.4 Quartz Frequency Calculation
As described in Section 3.4.3 the operating range of the on-chip VCO is 820 to
860 MHz with a nominal center frequency of 840MHz. This signal is divided by
2 before applied to the mixer in case of operation at 434 MHz. This local oscillator signal can be used to downconvert the RF signals both with high- or lowside injection at the mixer. The resulting receive frequency ranges then extend
between 810 and 870MHz or between 400 and 440MHz. Low-side injection of
the local oscillator has to be used for receive frequencies between 840 and
870MHz as well as high-side injection for receive frequencies below 840MHz.
Corresponding to that in the 400MHz region low-side injection is applicable for
receive frequencies above 420MHz, high-side injection below this frequency.
Therefore for operation both in the 868 and the 434 MHz ISM bands low-side
injection of the local oscillator has to be used. Then the local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz) from the RF
frequency (434 or 868 MHz). Please note that no sign-inversion occurs in case
of reception and demodulation of FSK-modulated signals.
The overall division ratios in the PLL are 64 or 128 in case of operation at
868 MHz or 32 and 64 in case of operation at 434 MHz, depending on the crystal frequency used as shown below. The quartz frequency in case of low-side
injection may be calculated by using the following formula:
ƒQU = (ƒRF - 10.7) / r
with
ƒRF
receive frequency
ƒLO
local oscillator (PLL) frequency (ƒRF - 10.7)
ƒQU
quartz oscillator frequency
r
ratio of local oscillator (PLL) frequency and quartz frequency as
shown in the subsequent table
Table 4-1 Dependence of PLL Overall Division Ratio on FSEL and CSEL
FSEL
CSEL
Ratio r = (fLO/fQU)
open
open
64
open
GND
32
GND
open
128
GND
GND
64
:
f QU = (868.4MHz − 10.7 MHz ) / 64 = 13.40156 MHz
f QU = (868 .4 MHz − 10.7 MHz ) / 128 = 6.7008 MHz
f QU = (434.2 MHz − 10.7 MHz ) / 32 = 13.23437 MHz
f QU = (434 .2 MHz − 10.7 MHz ) / 64 = 6.6172 MHz
Wireless Components
4-6
Specification, May 2001
TDA 5210
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated using an external R-C integrator as shown in Figure 4-5. The cut-off frequency of the R-C integrator has
to be lower than the lowest frequency appearing in the data signal. In order to
keep distortion low, the minimum value for R is 20kΩ.
R
C
Pins:
19
data out
25
20
Uthreshold
data
filter
data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use
the peak detector in connection with two resistors and one capacitor as shown
in the following figure. The component values are depending on the coding
scheme and the protocol used.
R
C
R
Pins:
peak detector
26
19
data out
25
20
Uthreshold
data slicer
data
filter
Data_slice2.wmf
Figure 4-6
Wireless Components
Data Slicer Threshold Generation Utilising the Peak Detector
4-7
Specification, May 2001
TDA 5210
Applications
4.6 ASK/FSK Switch Functional Description
The TDA5210 is containing an ASK/FSK switch which can be controlled via
Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that
are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of
the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to compensate for the DC-offset generated especially in case
of the FSK PLL demodulator there is a feedback connection between the
threshold voltage of the bit slicer comparator (Pin 20) to the negative input of
the FSK switch amplifier. This is shown in the following figure.
15
MSEL
RSSI (ASK signal)
ASK/FSK Switch
Data Filter
FSK PLL Demodulator
R1=100k
+ ASK
DATA Out
R2=100k
+
v=1
+ FSK
-
25
-
AC
0.18 mV/kHz
Comp
R3=300k
DC
typ. 2 V
1.5 V......2.5 V
R4=30k
FFB 22
21
OPP
SLP
19
20
SLN
ASK mode : v=1
FSK mode : v=11
C1
C2
R
C
ask_fsk_datapath.WMF
Figure 4-7
4.6.1
ASK/FSK mode datapath
FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown
above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is
determined by the external RC-combination. The upper cutoff frequency f3 is
determined by the data filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 140µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting
dynamic gain of this circuit is 2mV/kHz within the bandpass. The gain for the DC
content of FSK signal remains at 140µV/kHz. The cutoff frequencies of the
bandpass have to be chosen such that the spectrum of the data signal is influenced in an acceptable amount.
In case that the user data is containing long sequences of logical zeroes the
effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset
voltage inherent at the negative input of the slicer comparator (Pin20) is used.
The comparator has no hysteresis built in.
Wireless Components
4-8
Specification, May 2001
TDA 5210
Applications
This offset voltage is generated by the bias current of the negative input of the
comparator (i.e. 20nA) running over the external resistor R. This voltage raises
the voltage appearing at pin 20 (e.g. 1mV with R = 100kΩ). In order to obtain
benefit of this asymmetrical offset for the demodulation of long zeros the lower
of the two FSK frequencies should be chosen in the transmitter as the zerosymbol frequency.
In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v
v-3dB
20dB/dec
-40dB/dec
3dB
0dB
f
DC
f1
f2
0.18mV/kHz
f3
2mV/kHz
frequenzgang.WMF
Figure 4-8
Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
f1 =
1
R ⋅ 330kΩ
⋅C
2π
R + 330kΩ
f 2 = v ⋅ f1 = 11 ⋅ f1
f 3 = f 3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2.
Example:
R = 100kΩ, C = 47nF
This leads tof1 = 44Hzandf2 = 485Hz
Wireless Components
4-9
Specification, May 2001
TDA 5210
Applications
4.6.2
ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charactersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff
frequency is determined by the external capacitors C12 and C14 and the internal 100k resistors as described in Section 4.2
0dB
-3dB
-40dB/dec
f
f3dB
freq_ask.WMF
Figure 4-9
Wireless Components
Frequency charcteristic in case of ASK mode
4 - 10
Specification, May 2001
TDA 5210
Applications
4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network
as described in Section 4.5 it is necessary to use large values for the capacitor
C attached to the SLN pin (pin 20) in order to achieve long time constants. This
results also from the fact that the choice of the value for R connected between
the SLP and SLN pins (pins 19 and 20) is limited by the 330kΩ resistor appearing in parallel to R as can be seen in Figure 4-7. Apart from this a resistor value
of 100kΩ leads to a voltage offset of 1mv at the comparator input as described
in Section 4.6.1. The resulting startup time constant τ1 can be calculated with:
τ1 = (R // 330kΩ) · C
In case R is chosen to be 100kΩ and C is chosen as 47nF this leads to
τ1 = (100kΩ // 330kΩ) · 47nF = 77kΩ · 47nF = 3.6ms
When the device is turned on this time constant dominates the time necessary
for the device to be able to demodulate data properly. In the powerdown mode
the capacitor is only discharged by leakage currents.
In order to reduce the turn-on time in the presence of large values of C a precharge circuit was included in the TDA5210 as shown in the following figure.
C2
R1+R2=600k
R1
R2
C
R
Uth r es h o ld
24
20
23
Uc>Us
Uc 2.8V, high gain mode
1
2
Average Power Level
at BER = 2E-3
(Sensitivity) ASK
RFin
-110
Average Power Level
at BER = 2E-3
(Sensitivity) FSK
RFin
-103
dBm
Manchester enc.
datarate 4kBit,
280kHz IF Bandw.,
± 50kHz pk. dev.
■
■
3
Input impedance,
fRF=434 MHz
S11 LNA
0.873 / -34.7 deg
■
4
Input impedance,
fRF=869 MHz
S11 LNA
0.738 / -73.5 deg
■
5
Input level @ 1dB compression
P1dBLNA
-15
dBm
6
Input 3rd order intercept
point fRF=434 MHz
IIP3LNA
-10
dBm
matched input
■
7
Input 3rd order intercept
point fRF=869 MHz
IIP3LNA
-14
dBm
matched input
■
Wireless Components
5-4
■
Specification, May 2001
TDA 5210
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
min
8
LO signal feedthrough
at antenna port
typ
LOLNI
Unit
Test Conditions
L
Item
max
-73
■
dBm
Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode
1
Gain fRF=434 MHz
S21 LNA
1.509 / 138.2 deg
■
2
Gain fRF=869 MHz
S21 LNA
1.419 / 101.7 deg
■
3
Output impedance,
fRF=434 MHz
S22 LNA
0.886 / -12.9 deg
■
4
Output impedance,
fRF=869 MHz
S22 LNA
0.866 / -24.2 deg
■
5
Voltage Gain Antenna
to IFO fRF=434 MHz
GAntMI
42
dB
6
Voltage Gain Antenna
to IFO fRF=869 MHz
GAntMI
40
dB
Signal Input LNI, VTHRES = GND, low gain mode
1
Input impedance,
fRF=434 MHz
S11 LNA
0.873 / -34.7 deg
■
2
Input impedance,
fRF=869 MHz
S11 LNA
0.738 / -73.5 deg
■
3
Input level @ 1dB C. P
fRF = 434 MHz
P1dBLNA
-18
dBm
matched input
■
4
Input level @ 1dB C. P
fRF = 869 MHz
P1dBLNA
-6
dBm
matched input
■
5
Input 3rd order intercept
point fRF=434 MHz
IIP3LNA
-10
dBm
matched input
■
6
Input 3rd order intercept
point fRF=869 MHz
IIP3LNA
-5
dBm
matched input
■
Signal Output LNO, VTHRES = GND, low gain mode
1
Gain fRF=434 MHz
S21 LNA
0.183 / 140.6 deg
■
2
Gain fRF=869 MHz
S21 LNA
0.179 / 109.1deg
■
3
Output impedance,
fRF=434 MHz
S22 LNA
0.897 / -13.6 deg
■
4
Output impedance,
fRF=869 MHz
S22 LNA
0.868 / -26.3 deg
■
5
Voltage Gain Antenna
to MI fRF=434 MHz
GAntMI
22
dB
6
Voltage Gain Antenna
to MI fRF=869 MHz
GAntMI
19
dB
Wireless Components
5-5
Specification, May 2001
TDA 5210
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
min
typ
max
Unit
Test Conditions
L
Item
Signal 3VOUT (PIN 24)
1
Output voltage
V3VOUT
2.9
3.1
3.3
V
3VOUT Pin open
2
Current out
I3VOUT
-3
-5
-10
µA
see Section 4.1
VS-1V
V
see Section 4.1
Signal THRES (PIN 23)
1
Input Voltage range
VTHRES
0
2
LNA low gain mode
VTHRES
0
3
LNA high gain mode
VTHRES
2.8
4
Current in
ITHRES_in
V
3
VS
5
V
or shorted to Pin 24
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-3.6
-4.2
-5
µA
RSSI > VTHRES
2
Current in, LNA high
gain state
VTAGC_in
1
1.6
2.2
µA
RSSI>VTHRES
MIXER
Signal Input MI/MIX (PINS 8/9)
1
Input impedance,
fRF=434 MHz
S11 MIX
0.942 / -14.4 deg
■
2
Input impedance,
fRF=869 MHz
S11 MIX
0.918 / -28.1 deg
■
3
Input 3rd order intercept
point fRF=434 MHz
IIP3MIX
-28
dBm
■
4
Input 3rd order intercept
point fRF=869 MHz
IIP3MIX
-26
dBm
■
■
Signal Output IFO (PIN 12)
1
Output impedance
ZIFO
330
Ω
2
Conversion Voltage
Gain fRF=434 MHz
GMIX
+19
dB
3
Conversion Voltage
Gain fRF=869 MHz
GMIX
+18
dB
LIMITER
Signal Input LIM/X (PINS 17/18)
1
Input Impedance
ZLIM
264
2
RSSI dynamic range
DRRSSI
60
3
RSSI linearity
LINRSSI
4
Operating frequency
(3dB points)
Wireless Components
fLIM
330
396
Ω
80
dB
±1
5
10.7
5-6
23
■
dB
■
MHz
■
Specification, May 2001
TDA 5210
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
DATA FILTER
1
Useable bandwidth
2
RSSI Level at Data Filter Output SLP,
RFIN=-103dBm
RSSIlow
3
RSSI Level at Data Filter Output SLP,
RFIN=-30dBm
RSSIhigh
BWBB FILT
■
100
kHz
0.3
1
V
LNA in high gain
mode
1.8
3
V
LNA in high gain
mode
100
kBps
0.1
V
Slicer, Signal Output DATA (PIN 25)
1
Maximum Datarate
DRmax
2
LOW output voltage
VSLIC_L
0
3
HIGH output voltage
VSLIC_H
VS1.3V
VS-1V
VS0.7V
V
IPCH_SLN
-100
-220
-300
µA
Iload
-600
-950
-1300
µA
Ileakage
0
200
1000
nA
14
MHz
NRZ, 20pF capacitive loading
■
Slicer, Signal Output DATA (PIN 20)
1
Precharge Current Out
see Section 4.7
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
Load current
2
Leakage current
CRYSTAL OSCILLATOR
Signals CRSTL1, CRSTL 2, (PINS 1/28)
1
Operating frequency
2
Input Impedance
@ ~6MHz
Z1-28
-825
+j695
Ω
■
3
Input Impedance
@ ~13MHz
Z1-28
-600
+j1010
Ω
■
4
Serial Capacity
@ ~6MHz
CS 6=C1
8.9
pF
5
Serial Capacity
@ ~13MHz
CS13=C1
5.9
pF
fCRSTL
6
fundamental mode,
series resonance
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
ASK Mode
VMSEL
1.4
4
V
2
FSK Mode
VMSEL
0
0.2
V
Wireless Components
5-7
or open
Specification, May 2001
TDA 5210
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V (continued)
Parameter
Symbol
Limit Values
Unit
min
typ
max
Test Conditions
L
Item
FSK DEMODULATOR
1
Demodulation Gain
GFMDEM
85
140
225
µV/
kHz
2
Useable IF Bandwidth
BWIFPLL
10.2
10.7
11.2
MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1
Powerdown Mode On
PWDNON
0
0.8
V
2
Powerdown Mode Off
PWDNOff
2.8
VS
V
3
Input bias current
PDWN
4
Start-up Time until valid
signal is detected at IF
IPDWN
19
TSU
uA
1
ms
Power On Mode
VCO MULTIPLEXER
Signal FSEL (PIN 11)
1
fRF range 434 MHz
VFSEL
1.4
4
V
2
fRF range 869 MHz
VFSEL
0
0.2
V
3
Output bias current
FSEL
IFSEL
-160
-240
µA
FSEL tied to GND
or open
-200
or open
PLL DIVIDER
Signal CSEL (PIN 16)
1
fCRSTL range 6.xxMHz
VCSEL
1.4
4
V
2
fCRSTL range
13.xxMHz
VCSEL
0
0.2
V
3
Input bias current
CSEL
ICSEL
-3
-7
µA
-5
CSEL tied to GND
■ Measured only in lab.
Wireless Components
5-8
Specification, May 2001
TDA 5210
preliminary
Reference
5.1.4
AC/DC Characteristics at TAMB = -40 to 105°C
Currents flowing into the device are denoted as positive currents and vice versa
Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
min
Unit
Test Conditions
typ
max
50
400
nA
Pin 27 (PDWN)
open or tied to 0 V
L
Item
Supply
Supply Current
1
Supply current,
standby mode
IS PDWN
2
Supply current, device
operating in 868 MHz
range, FSK mode
ISF 868
4.1
5.9
7.7
mA
Pin 11 (FSEL) tied
to GND, Pin 15
(MSEL) tied to GND
3
Supply current, device
operating in 434 MHz
range, FSK mode
ISF 434
3.9
5.7
7.5
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) tied to GND
4
Supply current, device
operating in 868 MHz
range, ASK mode
ISA 868
3.4
5.2
7
mA
Pin 11 (FSEL) tied
to GND, Pin 15
(MSEL) open
5
Supply current, device
operating in 434 MHz
range, ASK mode
ISA 434
3.2
5
6.8
mA
Pin 11 (FSEL)
open, Pin 15
(MSEL) open
Signal 3VOUT (PIN 24)
1
Output voltage
V3VOUT
2.9
3.1
3.3
V
3VOUT Pin open
2
Current out
I3VOUT
-3
-5
-10
µA
see Section 4.1
see Section 4.1
Signal THRES (PIN 23)
1
Input Voltage range
VTHRES
0
VS-1V
V
2
LNA low gain mode
VTHRES
0
0.3
V
3
LNA high gain mode
VTHRES
3
VS
V
4
Current in
ITHRES_in
5
or shorted to Pin 24
nA
Signal TAGC (PIN 4)
1
Current out,
LNA low gain state
ITAGC_out
-1
-4.2
-8
µA
RSSI > VTHRES
2
Current in, LNA high
gain state
VTAGC_in
0.5
1.5
5
µA
RSSI>VTHRES
MIXER
1
Conversion Voltage
Gain fRF=434 MHz
GMIX
+19
dB
2
Conversion Voltage
Gain fRF=869 MHz
GMIX
+18
dB
LIMITER
Signal Input LIM/X (PINS 17/18)
1
RSSI dynamic range
Wireless Components
DRRSSI
60
80
5-9
dB
Specification, May 2001
TDA 5210
preliminary
Reference
Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
DATA FILTER
2
RSSI Level at Data Filter Output SLP,
RFIN=-103dBm
RSSIlow
0.3
1
V
LNA in high gain
mode
3
RSSI Level at Data Filter Output SLP,
RFIN=-30dBm
RSSIhigh
1.8
3
V
LNA in high gain
mode
100
kBps
0.1
V
Slicer, Signal Output DATA (PIN 25)
1
Maximum Datarate
DRmax
2
LOW output voltage
VSLIC_L
0
3
HIGH output voltage
VSLIC_H
VS1.5V
VS-1V
VS0.5V
V
IPCH_SLN
-100
-220
-300
µA
Iload
-400
-850
-1400
µA
Ileakage
0
700
2000
nA
NRZ, 20pF capacitive loading
■
Slicer, Signal Output DATA (PIN 20)
1
Precharge Current Out
see Section 4.7
PEAK DETECTOR
Signal Output PDO (PIN 26)
1
Load current
2
Leakage current
CRYSTAL OSCILLATOR
Signals CRSTL1, CRSTL 2, (PINS 1/28)
1
Operating frequency
fCRSTL
6
14
MHz
fundamental mode,
series resonance
ASK/FSK Signal Switch
Signal MSEL (PIN 15)
1
ASK Mode
VMSEL
1.4
4
V
2
FSK Mode
VMSEL
0
0.2
V
or open
FSK DEMODULATOR
1
Demodulation Gain
GFMDEM
105
140
245
µV/
kHz
2
Useable IF Bandwidth
BWIFPLL
10.2
10.7
11.2
MHz
POWER DOWN MODE
Signal PDWN (PIN 27)
1
Powerdown Mode On
PWDNON
0
0.8
V
2
Powerdown Mode Off
PWDNOff
2.8
VS
V
3
Start-up Time until valid
signal is detected at IF
1
ms
Wireless Components
TSU
5 - 10
Specification, May 2001
TDA 5210
preliminary
Reference
Table 5-4 AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V
Parameter
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
VCO MULTIPLEXER
Signal FSEL (PIN 11)
1
fRF range 434 MHz
VFSEL
1.4
4
V
2
fRF range 869 MHz
VFSEL
0
0.2
V
3
Output bias current
FSEL
IFSEL
-110
-340
µA
FSEL tied to GND
or open
-200
or open
PLL DIVIDER
Signal CSEL (PIN 16)
1
fCRSTL range 6.xxMHz
VCSEL
1.4
4
V
2
fCRSTL range
13.xxMHz
VCSEL
0
0.2
V
3
Input bias current
CSEL
ICSEL
-3
-7
µA
Wireless Components
-5
5 - 11
CSEL tied to GND
Specification, May 2001
TDA 5210
preliminary
Reference
5.2 Test Circuit
The device performance parameters marked with ■ in Section 5.1.3 were measured on an Infineon evaluation board. This evaluation board can be obtained
together with evaluation boards of the accompanying transmitter device
TDA5100 in an evaluation kit that may be ordered on the INFINEON RKE
Webpage www.infineon.com/rke. In case a matching codeword is received,
decoded and accepted by the decoder the on-board LED will turn on. This signal is also accessible on a 2-pole pin connector and can be used for simple
remote-control applications. More information on the kit is available on request.
TDA5210_testboard_20_schematic.WMF
Figure 5-1
Wireless Components
Schematic of the Evaluation Board
5 - 12
Specification, May 2001
TDA 5210
preliminary
Reference
5.3 Test Board Layouts
tda5210_testboard_20_top.WMF
Figure 5-2
Top Side of the Evaluation Board
tda5210_testboard_20_bot.WMF
Figure 5-3
Wireless Components
Bottom Side of the Evaluation Board
5 - 13
Specification, May 2001
TDA 5210
preliminary
Reference
tda5210_testboard_20_plc.EMF
Figure 5-4
Wireless Components
Component Placement on the Evaluation Board
5 - 14
Specification, May 2001
TDA 5210
preliminary
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5210 without
use of a Microchip HCS512 decoder.
Table 5-5 Bill of Materials
Ref
Value
Specification
R1
100kΩ
0805, ± 5%
R2
100kΩ
0805, ± 5%
R3
820kΩ
0805, ± 5%
R4
240kΩ
0805, ± 5%
R5
360kΩ
0805, ± 5%
R6
10kΩ
0805, ± 5%
L1
434 MHz: 15nH
869 MHz: 3.3nH
Toko, PTL2012-F15N0G
Toko, PTL2012-F3N3C
L2
434 MHz: 8.2pF
869 MHz: 3.9nH
0805, COG, ± 0.1pF
Toko, PTL2012-F3N9C
C1
1pF
0805, COG, ± 0.1pF
C2
434 MHz: 4.7pF
869 MHz: 3.9pF
0805, COG, ± 0.1pF
0805, COG, ± 0.1pF
C3
434 MHz: 6.8pF
869 MHz: 5.6pF
0805, COG, ± 0.1pF
0805, COG, ± 0.1pF
C4
100pF
0805, COG, ± 5%
C5
47nF
1206, X7R, ± 10%
C6
434 MHz: 10nH
869 MHz: 3.9pF
Toko, PTL2012-F10N0G
0805, COG, ± 0.1pF
C7
100pF
0805, COG, ± 5%
C8
434 MHz: 33pF
869 MHz: 22pF
0805, COG, ± 5%
0805, COG, ± 5%
C9
100pF
0805, COG, ± 5%
C10
10nF
0805, X7R, ± 10%
C11
10nF
0805, X7R, ± 10%
C12
220pF
0805, COG, ± 5%
C13
47nF
0805, X7R, ± 10%
C14
470pF
0805, COG, ± 5%
C15
47nF
0805, X7R, ± 5%
C16
8.2pF
0805, COG, ± 0.1pF
C17
22pF
0805, COG, ± 1%
C18
22nF
0805, X7R, ± 5%
Q1
(fRF – 10.7MHz)/32 or
(fRF – 10.7MHz)/64
HC49/U, fundamental mode, CL = 12pF,
e.g. 434.2MHz: Jauch Q 13,23437-S11-1323-12-10/20
e.g. 868.4MHz: Jauch Q 13,40155-S11-1323-12-10/20
Wireless Components
5 - 15
Specification, May 2001
TDA 5210
preliminary
Reference
Q2
SFE10.7MA5-A or
SKM107M1-A20-10
Murata
Toko
X2, X3
142-0701-801
Johnson
S1-S3, S6
X1, X3
2-pole pin connector
S4
3-pole pin connector, or not equipped
IC1
TDA 5210
Infineon
Please note that in case of operation at 434 MHz a capacitor has to be soldered
in place L2 and an inductor in place C6.
The following components are necessary in addition to the above mentioned
ones for evaluation of the TDA5210 in conjunction with a Microchip HCS512
decoder.
Table 5-6 Bill of Materials Addendum
Ref
Value
Specification
R7
100kΩ
0805, ± 5%
R8
10kΩ
0805, ± 5%
R9
100kΩ
0805, ± 5%
R10
22kΩ
0805, ± 5%
R11
100Ω
0805, ± 5%
R12
100Ω
0805, ± 5%
R13
100Ω
0805, ± 5%
R14
100Ω
0805, ± 5%
R21
22kΩ
0805, ± 5%
R22
10kΩ
0805, ± 5%
R23
22kΩ
0805, ± 5%
R24
820kΩ
0805, ± 5%
R25
560Ω
0805, ± 5%
C19
10pF
0805, COG, ± 5%
C21
100nF
1206, X7R, ± 10%
C22
100nF
1206, X7R, ± 10%
IC2
HCS512
Microchip
2-pole pin connector
S5, X4-X9
T1, T2
BC 847B
Infineon
D1
LS T670-JL
Infineon
Wireless Components
5 - 16
Specification, May 2001
TDA 5210
preliminary
Reference
Wireless Components
5 - 17
Specification, May 2001
TDA 5210
List of Figures
List of Figures
Figure 2-1
P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
Figure 3-1
IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
Figure 3-2
Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9
Figure 4-1
LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
Figure 4-3
Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . .
4-5
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . .
4-7
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . .
4-7
Figure 4-7
ASK/FSK mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8
Figure 4-8
Frequency characterstic in case of FSK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9
Figure 4-9
Frequency charcteristic in case of ASK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10
Figure 4-10 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11
Figure 4-11 Voltage appearing on C2 during precharging process . . . . . . . . . . . . . . . . . . . . . . . . .
4-12
Figure 4-12 Voltage transient on capacitor C attached to pin 20 . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-13
Figure 5-1
Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
Figure 5-2
Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13
Figure 5-3
Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13
Figure 5-4
Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14
Wireless Components
List of Figures - 1
Specification, May 2001
TDA 5210
List of Tables
List of Tables
Table 3-1
Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
Table 3-2
FSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10
Table 3-3
CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11
Table 3-4
MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-12
Table 3-5
PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-13
Table 4-1
Dependence of PLL Overall Division Ratio on FSEL and CSEL . . . . . . . . . . . . . . . . .
4-6
Table 5-1
Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 105°C . . . . . . . .
5-2
Table 5-2
Operating Range, Ambient temperature TAMB= -40°C ... + 105°C . . . . . . . . . . . . . . . .
5-3
Table 5-3
AC/DC Characteristics with TA 25 °C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . .
5-4
Table 5-4
AC/DC Characteristics with TAMB= -40°C ... + 105°C, VVCC = 4.5 ... 5.5 V . . . . . . . . .
5-9
Table 5-5
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15
Table 5-6
Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16
Wireless Components
List of Tables - 1
Specification, May 2001
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