OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
1
Overview
Features
•
Output voltage 5 V ± 2%
•
Output current up to 150 mA
•
Extreme low current consumption in ON state
•
Enable function: Below 1 µA current consumption In OFF state
•
Early warning
•
Power-on and undervoltage reset with programmable delay time
•
Reset low down to VQ = 1 V
•
Adjustable reset threshold
•
Very low dropout voltage
•
Output current limitation
•
Reverse polarity protection
•
Overtemperature protection
•
Suitable for use in automotive electronics
•
Wide temperature range from -40°C up to 150°C
•
Input voltage range from 5.5 V to 45 V
•
Green Product (RoHS compliant)
Potential applications
General automotive applications.
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100/101.
Description
The TLE42994 is a monolithic integrated low dropout voltage regulator, especially designed for automotive
applications that need to be in ON state during the car’s engine is turned off. An input voltage up to 45 V is
regulated to an output voltage of 5.0 V. The component is able to drive loads up to 150 mA. It is short-circuit
protected by the implemented current limitation and has an integrated overtemperature shutdown. A reset
Data Sheet
www.infineon.com/OPTIREG-Linear
1
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Overview
signal is generated for an output voltage VQ,rt of typically 4.65 V. This threshold can be decreased by an external
resistor divider. The power-on reset delay time can be programmed by the external delay capacitor. The
additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can be
monitored, an undervoltage condition is indicated by setting the comparator’s output to low. The
TLE42994GM (PG-DSO-14 package) and TLE42994E (PG-SSOP-14 exposed pad package) include additionally
an Enable function permitting enabling/disabling the regulator. In case the regulator is disabled it consumes
less current than 1 µA.
Dimensioning information on external components
The input capacitor CI is recommended for compensation of line influences. The output capacitor CQ is
necessary for the stability of the control loop.
Circuit description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and
drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents
any oversaturation of the power element. The component also has a number of internal circuits for protection
against:
•
Overload
•
Overtemperature
•
Reverse polarity
Type
Package
Marking
TLE42994E
PG-SSOP-14 exposed pad
42994E
TLE42994GM
PG-DSO-14
42994GM
TLE42994G
PG-DSO-8
42994G
Data Sheet
2
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block diagram
2
Block diagram
I
Q
Current
and
Saturation
Control
BandGapReference
RSO
RRO
SO
SI
Reference
RO
Reset
Control
RADJ
D
GND
AEB03103
Figure 1
Data Sheet
Block diagram TLE42994G (package PG-DSO-8)
3
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block diagram
TLE 4299
I
Q
Current
and
Saturation
Control
BandGapReference
EN
INH
RSO
RRO
Inhibit
Enable
Control
SO
SI
Reference
RO
Reset
Control
RADJ
D
GND
AEB03104
Figure 2
Data Sheet
Block diagram TLE42994GM, TLE42994E (packages PG-DSO-14, PG-SSOP-14 exposed pad)
4
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Pin configuration
3
Pin configuration
3.1
Pin assignment TLE42994G (PG-DSO-8)
Ι
SΙ
RADJ
D
1
2
3
4
8
7
6
5
Q
SO
RO
GND
AEP01668
Figure 3
Pin configuration (top view)
3.2
Pin definitions and functions TLE42994G (PG-DSO-8)
Pin
Symbol
Function
1
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
2
SI
Sense input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
3
RADJ
Reset threshold adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
4
D
Reset delay timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
5
GND
Ground
6
RO
Reset output
open collector output; internally linked to the output via a 20 kΩ pull-up resistor;
leave open if the reset function is not needed
7
SO
Sense output
open collector output; internally linked to the output via a 20 kΩ pull-up resistor;
leave open if the sense comparator is not needed
8
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values
given for its capacitance CQ and ESR in “Functional range” on Page 11
Data Sheet
5
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Pin configuration
3.3
Pin assignment TLE42994GM (PG-DSO-14)
RADJ
1
14
SI
D
2
13
I
GND
3
12
GND
GND
4
11
GND
GND
5
10
GND
EN
6
9
Q
RO
7
8
SO
PinConfig_PG-DSO-14.vsd
Figure 4
Pin configuration (top view)
3.4
Pin definitions and functions TLE42994GM (PG-DSO-14)
Pin
Symbol
Function
1
RADJ
Reset threshold adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
2
D
Reset delay timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
3, 4, 5
GND
Ground
connect all pins to PCB and heatsink area
6
EN
Enable
high signal enables the regulator;
low signal disables the regulator;
connect to I if the Enable function is not needed
7
RO
Reset output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the reset function is not needed
8
SO
Sense output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the sense comparator is not needed
9
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values
given for its capacitance CQ and ESR in the table “Functional range” on Page 11
10, 11, 12 GND
Data Sheet
Ground
connect all pins to PCB and heatsink area
6
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Pin configuration
Pin
Symbol
Function
13
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
14
SI
Sense input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
Data Sheet
7
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Pin configuration
3.5
Pin assignment TLE42994E (PG-SSOP-14 exposed pad)
RADJ
n.c.
D
GND
EN
n.c.
RO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SI
I
n.c.
Q
n.c.
n.c.
SO
PINCONFIG_SSOP-14.VSD
Figure 5
Pin configuration (top view)
3.6
Pin definitions and functions TLE42994E (PG-SSOP-14 exposed pad)
Pin
Symbol
Function
1
RADJ
Reset threshold adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
2, 6
n.c.
Not connected
leave open or connect to GND
3
D
Reset delay timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
4
GND
Ground
connect all pins to PCB and heatsink area
5
EN
Enable
high signal enables the regulator;
low signal disables the regulator;
connect to I if the Enable function is not needed
7
RO
Reset output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the reset function is not needed
8
SO
Sense output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the sense comparator is not needed
9, 10, 12
n.c.
Not connected
leave open or connect to GND
11
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values
given for its capacitance CQ and ESR in the table “Functional range” on Page 11
13
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
Data Sheet
8
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Pin configuration
Pin
Symbol
Function
14
SI
Sense input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
PAD
–
Exposed pad
attach the exposed pad on package bottom to the heatsink area on circuit board;
connect to GND
Data Sheet
9
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
General product characteristics
4
General product characteristics
4.1
Absolute maximum ratings
Table 1
Absolute maximum ratings1)
-40 °C ≤ Tj ≤ 150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol
Values
Typ.
Max.
Unit Note or
Test Condition
–
45
V
–
P_4.1.1
-0.3
–
7
V
–
P_4.1.2
VD, VRADJ
-0.3
–
7
V
–
P_4.1.3
Junction temperature
Tj
-40
–
150
°C
–
P_4.1.4
Storage temperature
Tstg
-50
–
150
°C
–
P_4.1.5
ESD absorption
VESD,HBM
-2
–
2
kV
Human body model
(HBM)2)
P_4.1.6
ESD absorption
VESD,CDM
-500
–
500
V
Charge device model
(CDM)3)
P_4.1.7
ESD absorption
VESD,CDM
-750
–
750
V
Charge device model
(CDM)3) at corner pins
P_4.1.8
Min.
Number
Input I, enable Input EN, sense input SI
Voltage
VI, VEN, VSI
-40
Output Q, reset output RO, sense output SO
Voltage
VQ, VRO, VSO
Reset delay D, reset threshold RADJ
Voltage
Temperature
ESD absorption
1) Not subject to production test, specified by design
2) ESD susceptibility human body model “HBM” according to AEC-Q100-002 - JESD22-A114
3) ESD susceptibility charged device model “CDM” according to ESDA STM5.3.1
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
10
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
General product characteristics
4.2
Functional range
Table 2
Functional range
Parameter
Symbol
Values
Min.
Typ. Max.
5.5
–
Input voltage
VI
Output capacitor’s
requirements for stability
CQ
22
–
–
Output capacitor’s
requirements for stability
ESR(CQ)
–
–
Junction temperature
Tj
-40
–
45
Unit
Note or
Test Condition
Number
V
–
P_4.2.1
µF
–
1)
P_4.2.2
3
Ω
–2)
P_4.2.3
150
°C
–
P_4.2.4
1) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
2) Relevant ESR value at f = 10 kHz
Note:
Data Sheet
Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
11
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
General product characteristics
4.3
Thermal resistance
Table 3
Thermal resistance
Parameter
Symbol
Values
Min.
Typ.
Max.
–
–
60
Unit
Note or Test Condition
Number
K/W
measured to pin 5
P_4.3.1
TLE42994G (PG-DSO-8)
Junction to soldering point1) RthJSP
Junction to ambient
1)
RthJA
–
113
–
K/W
FR4 2s2p board
Junction to ambient
1)
RthJA
–
185
–
K/W
FR4 1s0p board, footprint P_4.3.3
only3)
Junction to ambient1)
RthJA
–
142
–
K/W
FR4 1s0p board, 300mm2
heatsink area on PCB3)
P_4.3.4
Junction to ambient1)
RthJA
–
136
–
K/W
FR4 1s0p board, 600mm2
heatsink area on PCB3)
P_4.3.5
–
–
30
K/W
measured to all GND pins
P_4.3.6
P_4.3.7
2)
P_4.3.2
TLE42994GM (PG-DSO-14)
Junction to soldering point1) RthJSP
Junction to ambient1)
RthJA
–
63
–
K/W
FR4 2s2p board2)
1)
RthJA
–
112
–
K/W
FR4 1s0p board, footprint P_4.3.8
only3)
Junction to ambient1)
RthJA
–
73
–
K/W
FR4 1s0p board, 300mm2
heatsink area on PCB3)
P_4.3.9
Junction to ambient1)
RthJA
–
65
–
K/W
FR4 1s0p board, 600mm2
heatsink area on PCB3)
P_4.3.10
–
10
–
K/W
–
P_4.3.11
Junction to ambient
TLE42994E (PG-SSOP-14 exposed pad)
RthJC
Junction to case1)
1)
RthJA
–
47
–
K/W
FR4 2s2p board
Junction to ambient1)
RthJA
–
140
–
K/W
FR4 1s0p board, footprint P_4.3.13
only3)
Junction to ambient1)
RthJA
–
63
–
K/W
FR4 1s0p board, 300mm2
heatsink area on PCB3)
P_4.3.14
Junction to ambient1)
RthJA
–
53
–
K/W
FR4 1s0p board, 600mm2
heatsink area on PCB3)
P_4.3.15
Junction to ambient
2)
P_4.3.12
1) Not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
12
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
5
Block description and electrical characteristics
5.1
Voltage regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the
chip temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the
output capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table
“Functional range” on Page 11 have to be maintained. For details see also the typical performance graph
“Output capacitor series resistor ESR(CQ) versus output current IQ” on Page 16. As the output capacitor
also has to buffer load steps it should be sized according to the application’s needs.
An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to
the component’s terminals.
A protection circuitry prevents the IC as well as the application from destruction in case of catastrophic events.
These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal
shutdown in case of overtemperature.
To avoid excessive power dissipation that could never be handled by the pass element and the package, the
maximum output current is decreased at input voltages above VI = 22 V.
The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions
(e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled down,
the regulator restarts. This leads to an oscillatory behavior of the output voltage until the fault is removed.
However, junction temperatures above 150 °C are outside the maximum ratings and therefore significantly
reduce the IC’s lifetime.
The TLE42994 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC,
increasing its junction temperature. This has to be considered for the thermal design, respecting that the
thermal protection circuit is not operating during reverse polarity conditions.
Supply
II
I
Q
Regulated
Output Voltage
IQ
Saturation Control
Current Limitation
C
CI
Temperature
Shutdown
BlockDiagram_VoltageRegulator.vsd
Figure 6
Data Sheet
Bandgap
Reference
ESR
}
CQ
LOAD
GND
Voltage regulator
13
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
Table 4
Electrical characteristics voltage regulator
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or
Test Condition
Number
V
100 µA < IQ < 100 mA
6 V < VI < 18 V
P_5.1.1
100 µA < IQ < 150 mA
6 V < VI < 18 V
P_5.1.2
Output voltage
VQ
4.9
5.0
5.1
Output voltage
VQ
4.85
5.0
5.15
Output current limitation
IQ,max
150
400
500
mA
VQ = 4.8V
P_5.1.3
Load regulation
steady-state
ΔVQ, load
-30
-5
–
mV
IQ = 1 mA to 100 mA
VI = 6 V
P_5.1.4
Line regulation
steady-state
ΔVQ, line
–
10
25
mV
VI = 6 V to 32 V
IQ = 1 mA
P_5.1.5
Dropout voltage1)
Vdr = VI - VQ
Vdr
–
220
500
mV
IQ = 100 mA
P_5.1.6
Overtemperature
shutdown threshold
Tj,sd
151
–
200
°C
Tj increasing2)
P_5.1.7
Overtemperature
shutdown threshold
hysteresis
Tj,sdh
–
15
–
°C
Tj decreasing2)
P_5.1.8
Power supply ripple
rejection2)
PSRR
–
66
–
dB
fripple = 100 Hz
Vripple =1 Vpp
IQ = 100 mA
P_5.1.9
1) Measured when the output voltage VQ has dropped 100 mV from the nominal value obtained at VI = 13.5 V
2) Not subject to production test, specified by design
Data Sheet
14
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
5.2
Typical performance characteristics voltage regulator
Output voltage VQ versus
junction temperature TJ
Output current IQ versus
input voltage VI
01_VQ_TJ.VSD
5,20
02_IQ_VI.VSD
400
350
5,10
300
T j = -40 °C
IQ,max [mA]
V Q [V]
5,00
4,90
VI = 7 V
I Q = 5 mA
250
T j = 25 °C
T j = 150 °C
200
150
4,80
100
4,70
50
0
4,60
-40
0
40
80
120
0
160
10
20
Power supply ripple rejection PSRR versus
ripple frequency fr
T j = 150 °C
0,8
T j = 25 °C
0,7
T j = 150 °C
0,6
60
ΔV Q [mV]
PSRR [dB]
70
50
40
0,4
I Q = 10 mA
C Q = 10 µF
0,3
20
ceramic
V I = 13.5 V
0,2
10
V ripple = 0.5 Vpp
T j = -40 °C
0,1
0
0,1
1
10
100
0
1000
10
20
30
40
V I [V]
f [kHz]
Data Sheet
T j = 25 °C
0,5
30
0
0,01
04_DVQ_DVI.VSD
0,9
T j = -40 °C
80
50
Line regulation ΔVQ,line versus
input voltage change ΔVI
03_PSRR_FR.VSD
90
40
V I [V]
T j [°C]
100
30
15
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
Output capacitor series resistor ESR(CQ) versus
output current IQ
Load regulation ΔVQ,load versus
output current change ΔIQ
05_DVQ_DIQ.VSD
5
06_ESR_IQ_CORRECTED.VSD
100
VI = 6 V
0
Unstable
Region
ESR(C Q) [Ω ]
10
ΔV Q [mV]
-5
-10
T j = -40 °C
T j = 25 °C
-15
T j = 150 °C
C Q = 22 µF
T j = -40..150 °C
1
V I = 6..28 V
Stable
Region
0,1
-20
0,01
-25
0
50
100
0
150
I Q [mA]
50
100
150
I Q [mA]
Dropout voltage Vdr versus
junction temperature Ti
07_VDR_TJ.VSD
300
I Q = 100 mA
250
V DR [mV]
200
150
I Q = 25 mA
100
I Q = 5 mA
50
0
-40
0
40
80
120
160
T j [°C]
Data Sheet
16
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
5.3
Current consumption
Table 5
Electrical characteristics voltage regulator
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note or Test Condition Number
Current consumption
Iq = II - IQ
Iq
–
–
1
µA
VEN = 0 V
TLE42994GM and
TLE42994E only
Tj = 25 °C
P_5.4.1
Current consumption
Iq = II - IQ
Iq
–
65
100
µA
Enable HIGH
IQ = 100 µA, Tj = 25 °C
P_5.4.2
Current consumption
Iq = II - IQ
Iq
–
65
105
µA
Enable HIGH
IQ = 100 µA, Tj ≤ 85 °C
P_5.4.3
Current consumption
Iq = II - IQ
Iq
–
0.17
0.5
mA
Enable HIGH
IQ = 10 mA
P_5.4.4
Current consumption
Iq = II - IQ
Iq
–
0.7
2
mA
Enable HIGH
IQ = 50 mA
P_5.4.5
Data Sheet
17
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
5.4
Typical performance characteristics current consumption
Current consumption Iq versus
output current IQ
Current consumption Iq versus
output current IQ (IQ low)
08_IQ_IQ .VSD
6
09_IQ_IQ _IQLOW.VSD
1
V I = 13.5 V
V I = 13.5 V
0,9
T j = 150 °C
T j = 150 °C
5
0,8
T j = 25 °C
T j = 25 °C
0,7
4
I q [mA]
I q [mA]
0,6
3
2
0,5
0,4
0,3
0,2
1
0,1
0
0
0
50
100
150
0
I Q [mA]
10
20
30
40
50
I Q [mA]
Current consumption Iq versus
input voltage VI
10_IQ _VI.VSD
12
10
I q [mA]
8
6
R LOAD = 100 Ω
4
2
R LOAD = 50 k Ω
0
0
10
20
30
40
V I [V]
Data Sheet
18
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
5.5
Enable function (only TLE42994GM and TLE42994E)
Table 6
Electrical characteristics voltage regulator
VI = 13.5 V, -40 °C ≤ Tj ≤ 150°C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or Test Condition
Number
Enable OFF voltage range
VEN,OFF
–
–
0.8
V
–
P_5.6.1
Enable ON voltage range
VEN,ON
3.5
–
–
V
–
P_5.6.2
Enable OFF input current
IEN,OFF
–
0.5
2
µA
VEN = 0 V
P_5.6.3
Enable ON input current
IEN,ON
–
3
5
µA
VEN = 5 V
P_5.6.4
Data Sheet
19
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
5.6
Reset function
The reset function provides several features:
Output undervoltage reset:
An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be
used to reset a microcontroller during low supply voltage.
Power-on reset delay time:
The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time
frame from exceeding the reset switching threshold VRT until the reset is released by switching the reset output
“RO” from “low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD
connected to pin D charged by the delay capacitor charge current ID,ch starting from VD = 0 V.
If the application needs a power-on reset delay time trd different from the value given in Power-on reset
delay time, the delay capacitor’s value can be derived from the specified values in Power-on reset delay
time and the desired power-on delay time:
(5.1)
t rd, new
C D = ---------------- × 100nF
t rd
with
•
CD: capacitance of the delay capacitor to be chosen
•
trd,new: desired power-on reset delay time
•
trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
Reset reaction time:
The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The
reset reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the
external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction time
becomes:
(5.2)
t rr = t rd, int + t rr, d
with
•
trr: reset reaction time
•
trr,int: internal reset reaction time
•
trr,d: reset discharge
Optional reset output pull-up resistor RRO,ext:
The Reset Output RO is an open collector output with an integrated pull-up resistor. If needed, an external
pull-up resistor to the output Q can be added. In Table 7 “Electrical characteristics reset function” on
Page 23 a minimum value for the external resistor RRO,ext is given.
Data Sheet
20
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
Reset adjust function
The undervoltage reset switching threshold can be adjusted according to the application’s needs by
connecting an external voltage divider (RADJ1, RADJ2) at pin RADJ. For selecting the default threshold connect
pin RADJ to GND.
When dimensioning the voltage divider, take into consideration that there will be an additional current
constantly flowing through the resistors.
With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows:
(5.3)
V RT, new
R ADJ, 1 + R ADJ, 2
= ------------------------------------------ × V RADJ, th
R ADJ, 2
with
•
VRT,new: the desired new reset switching threshold
•
RADJ1, RADJ2: resistors of the external voltage divider
•
VRADJ,th: reset adjust switching threshold given in Table 7 “Electrical characteristics reset function” on
Page 23
I
Q
RRO
Int.
Supply
Control
CQ
RO
ID,ch
RRO,ext
Reset
I RO
VDST
VRADJ,th
VDD
optional
Supply
OR
RADJ,1
MicroController
RADJ
I RADJ
GND
optional
ID,dch
D
BlockDiagram_ResetAdjust.vsd
RADJ,2
GND
CD
Figure 7
Data Sheet
Block diagram reset function
21
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
VI
t
t < trr,total
VQ
VRT
1V
t
t rd
VD
V DU
V DRL
t
VRO
V RO,low
t rd
trr,total
trd
t rr,total
t rd
t rr,total
1V
t
Thermal
Shutdown
Figure 8
Data Sheet
Input
Voltage Dip
Undervoltage
Spike at
output
Overload
T i mi n g Di a g ra m_ Re se t . vs
Timing diagram reset
22
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
Table 7
Electrical characteristics reset function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Unit
Note or
Test Condition
Number
Min. Typ. Max.
Output undervoltage reset
Default output undervoltage reset VRT
Switching thresholds
4.5
4.65
4.8
V
VQ decreasing
P_5.7.1
Output undervoltage reset threshold adjustment
Reset adjust
Switching threshold
VRADJ,th
1.26
1.36
1.44
V
3.5 V ≤ VQ < 5 V
P_5.7.2
Reset adjustment range1)
VRT,range
3.50
–
4.65
V
–
P_5.7.3
Reset output low voltage
VRO,low
–
0.1
0.4
V
1 V ≤ VQ ≤ VRT
no external RRO,ext
P_5.7.4
Reset output internal
Pull-up resistor to VQ
RRO
10
20
40
kΩ
–
P_5.7.5
Optional reset output external
Pull-up resistor to VQ
RRO,ext
5.6
–
–
kΩ
1 V ≤ VQ ≤ VRT ;
VRO ≤ 0.4 V
P_5.7.6
Delay pin output voltage
VD
–
–
5
V
–
P_5.7.7
Power-on reset delay time
trd
17
28
35
ms
CD = 100 nF
Calculated value:
trd = CD * VDU / ID,ch
P_5.7.8
Upper delay
Switching threshold
VDU
–
1.85
–
V
–
P_5.7.9
Lower delay
Switching threshold
VDL
–
0.50
–
V
–
P_5.7.10
Delay capacitor
Charge current
ID,ch
–
8.0
–
µA
VD = 1 V
P_5.7.11
Delay capacitor
Reset discharge current
ID,dch
–
70
–
mA
VD = 1 V
P_5.7.12
Delay capacitor
Discharge time
trr, d
–
1.9
3.0
µs
Calculated Value:
trr, d = CD*(VDU - VDL)/
ID,dch
CD = 100 nF
P_5.7.13
Internal reset reaction time
trr, int
–
14
20
µs
CD = 0 nF 2)
P_5.7.14
Reset reaction time
trr, total
–
15.9
23
µs
Calculated value:
trr, total = trr, int + trr,d
CD = 100 nF
P_5.7.15
Reset output RO
Reset delay Ttming
1) VRT is scaled linearly, in case the Reset Switching Threshold is modified
2) Parameter not subject to production test; specified by design
Data Sheet
23
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
5.7
Typical performance characteristics reset
Undervoltage reset switching threshold VRT
versus junction temperature Tj
11_VRT_TJ.VSD
5
12_TRD_TJ.VSD
30
4,9
25
4,8
20
t rd [ m s ]
V RT [V]
Power-on reset delay time trd versus
junction temperature Tj
4,7
C D = 100 nF
15
10
4,6
5
4,5
0
-40
4,4
-40
0
40
80
120
10
Internal reset reaction time trr,int versus
junction temperature Tj
13_TRRINT _TJ.VSD
14_TRRD_TJ.VSD
2,5
2
15
1,5
t rr,d [µs]
t rr,int [µs]
160
Delay capacitor discharge time trr,d versus
junction temperature Tj
20
10
1
0,5
5
0
-40
0
-40
10
60
110
160
10
60
110
160
T j [°C]
T j [°C]
Data Sheet
110
T j [°C]
T j [°C]
25
60
160
24
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
5.8
Early warning function
The additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can
be monitored, an undervoltage condition is indicated by setting the comparator’s output to low.
Sense
Input
Voltage
VSI, High
VSI, Low
t
Sense
Output
High
Low
t
AED03049
Figure 9
Sense timing diagram
Table 8
Electrical characteristics early warning function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or Test Condition Number
Sense comparator input
Sense threshold high
VSI,high
1.34
1.45
1.54
V
–
P_5.9.1
Sense threshold low
VSI,low
1.26
1.36
1.44
V
–
P_5.9.2
Sense switching hysteresis
VSI,hy
50
90
130
mV
VSI,hy = VSI,high - VSI,low
P_5.9.3
Sense input current
ISI
-1
-0.1
1
µA
–
P_5.9.4
Data Sheet
25
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Block description and electrical characteristics
Electrical characteristics early warning function (cont’d)
Table 8
VI = 13.5 V, -40 °C ≤ Tj ≤ 150°C, all voltages with respect to ground, positive current flowing into pin (unless
otherwise specified)
Parameter
Symbol
Values
Min.
Typ. Max.
Unit
Note or Test Condition Number
Sense comparator output
Sense output low voltage
VSO,low
–
0.1
0.4
V
VSI < VSI,low
VI > 5.5 V
no external RSO,ext
P_5.9.5
Sense output internal
Pull-up resistor to VQ
RSO
10
20
40
kΩ
–
P_5.9.6
5.6
–
–
kΩ
VI > 5.5 V
VSO ≤ 0.4 V
P_5.9.7
Optional sense output external RSO,ext
pull-up resistor to VQ
5.9
Typical performance characteristics early warning
Sense thresholds VSI,high, VSI,low versus
junction temperature Tj
15_VSI_T J.VSD
1,45
V SI,high
1,4
1,35
V SI,low
V SI [V]
1,3
1,25
1,2
1,15
1,1
1,05
1
-40
10
60
110
160
T j [°C]
Data Sheet
26
Rev. 1.3
2018-11-20
OPTIREG™ Linear TLE42994
5 V low drop fixed voltage regulator
Application information
6
Application information
Note:
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
6.1
Application diagram
II
Supply
RSI1
CI1
10μF
100nF
IQ
Regulated
Output Voltage
CQ
22μF
SI
RSO
(ESR
工商网监
湘ICP备2023018690号
