TLE98792QXA40XUMA1

TLE9879-2QXA40 Microcontroller with LIN and BLDC MOSFET Driver for Automotive Applications BF-Step Features • 32-bit ARM Cortex M3 Core • 128 KByte Flash • 6 KByte RAM • On-chip OSC and PLL for clock generation • MOSFET driver including charge pump for B6-Bridge Motor Application • 1 LIN 2.2 transceiver • 2 differential Sigma Delta 14-bit ADC • High speed operational amplifier for motor current sensing via shunt • Single power supply from 5.5 V to 27 V • Temperature Range Tj = -40°C to +150°C Potential applications KL30 ARM® Cortex™-M3 Debug VS VDDP VDDC VDDEXT LIN DMA FLASH MON System Timer ROM VCP Motor Control Internal Supply External Supply Diagnostic ADC 8 Bit PLL Fail Safe GPT12 Communication Sensor Interface UART1 UART2 LIN LIN TRX SSC1 MON SRAM NVIC SYSTICK T2/T21 CAPCOM6 2x WDT T3 3~ Bridge Driver GHx SHx Charge Pump N-FET Stage Sigma Delta Meas-ADC 10 Bit ADC 14 Bit SSC2 GPIO VDH/VSD B6-Bridge M GLx SL OP2 Comparator VDDEXT Amplifier OP1 Input/Output KL15 Reverse Polarity xMR DBG Computation TMS SWD GPI / Analog In BEMF Comparator 5x Analog In* RESET 10x GPIO ADC3_p/_n ADC4_p/_n *) four inputs shared with SDADC Figure 1 Data Sheet TLE9879-2QXA40 simplified application diagram www.infineon.com 1 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Product validation Qualified for Automotive Applications. Product Validation according to AEC-Q100/101. Description Type Package TLE9879-2QXA40 VQFN-48-31 Data Sheet Marking 2 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Table of Contents 1 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 3.1 3.2 Device Pinout and Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 5.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.3.3 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMU Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Generation Unit (PGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator 5.0V (VDDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator 1.5V (VDDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Voltage Regulator 5.0V (VDDEXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 20 22 23 23 24 25 6 6.1 6.2 6.2.1 6.3 6.3.1 System Control Unit - Digital Modules (SCU-DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Precision Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 27 28 29 7 7.1 7.2 7.2.1 System Control Unit - Power Modules (SCU-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 30 30 8 8.1 8.2 8.2.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 33 33 9 9.1 9.2 9.2.1 9.3 9.3.1 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 35 35 36 36 10 Address Space Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 11.1 11.2 11.2.1 11.3 Memory Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Module (Flash Memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 3 38 38 38 38 40 Rev. 1.0 2018-01-16 TLE9879-2QXA40 12 12.1 12.2 12.2.1 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13.1 13.2 Watchdog Timer (WDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14 14.1 14.2 14.2.1 14.2.2 14.3 14.3.1 14.3.1.1 14.3.2 14.3.2.1 14.3.3 14.3.3.1 GPIO Ports and Peripheral I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE9879-2QXA40 Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 0 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 45 45 47 48 48 48 50 50 52 52 15 15.1 15.1.1 15.1.2 15.2 15.2.1 15.2.2 General Purpose Timer Units (GPT12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 54 54 54 54 55 56 16 16.1 16.2 16.2.1 Timer2 and Timer21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer2 and Timer21 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 57 57 57 17 17.1 17.2 17.3 17.3.1 Timer3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer3 Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 59 59 59 59 18 18.1 18.2 18.2.1 Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 62 63 19 19.1 19.2 19.2.1 19.3 UART1/UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 64 64 64 65 20 LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Data Sheet 4 41 41 41 41 Rev. 1.0 2018-01-16 TLE9879-2QXA40 20.1 20.2 20.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 21 21.1 21.2 21.2.1 High-Speed Synchronous Serial Interface (SSC1/SSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 68 69 69 22 Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.1.1 Block Diagram BEMF Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 70 70 71 72 23 23.1 23.2 23.2.1 23.2.2 Measurement Core Module (incl. ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Core Module Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 73 73 74 74 24 24.1 24.2 24.2.1 10-Bit Analog Digital Converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 76 76 25 25.1 25.2 25.2.1 25.2.2 14-Bit Sigma Delta ADC (ADC3 / ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage Range of SD ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interpretation of ADC output code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 77 77 78 78 26 26.1 26.2 26.2.1 High-Voltage Monitor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 79 79 79 27 27.1 27.2 27.2.1 27.2.2 Bridge Driver (incl. Charge Pump) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 80 80 81 81 28 28.1 28.2 28.2.1 Current Sense Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 82 82 82 29 29.1 29.2 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 BLDC Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ESD Immunity According to IEC61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 30 30.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Data Sheet 5 Rev. 1.0 2018-01-16 TLE9879-2QXA40 30.1.1 30.1.2 30.1.3 30.1.4 30.1.5 30.2 30.2.1 30.2.2 30.2.3 30.2.4 30.2.4.1 30.2.5 30.3 30.3.1 30.4 30.4.1 30.5 30.5.1 30.5.2 30.5.3 30.6 30.6.1 30.7 30.7.1 30.8 30.8.1 30.8.2 30.8.3 30.8.3.1 30.8.3.2 30.9 30.9.1 30.9.2 30.10 30.10.1 30.11 30.11.1 30.12 30.12.1 30.13 30.13.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Power Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PMU I/O Supply (VDDP) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PMU Core Supply (VDDC) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 VDDEXT Voltage Regulator (5.0V) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 VPRE Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Load Sharing Scenarios of VPRE Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Power Down Voltage Regulator (PMU Subblock) Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Oscillators and PLL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Flash Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Parallel Ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Description of Keep and Force Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 DC Parameters of Port 0, Port 1, TMS and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 DC Parameters of Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LIN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 SSC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Measurement Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 System Voltage Measurement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Central Temperature Sensor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ADC2-VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ADC2 Reference Voltage VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ADC2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 ADC1 Reference Voltage - VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Electrical Characteristics VAREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Electrical Characteristics ADC1 (10-Bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 14-Bit Sigma Delta ADC (ADC3 / ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 High-Voltage Monitoring Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 31 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 32 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Data Sheet 6 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Overview 1 Overview Summary of Features • 32-bit ARM Cortex M3 Core – up to 40 MHz clock frequency – one clock per machine cycle architecture • On-chip memory – 128 KByte Flash including – 4 KByte EEPROM (emulated in Flash) – 512 Byte 100 Time Programmable Memory (100TP) – 6 KByte RAM – Boot ROM for startup firmware and Flash routines • On-chip OSC and PLL for clock generation – PLL loss-of-lock detection • MOSFET driver including charge pump • 10 general-purpose I/O Ports (GPIO) • 5 analog inputs, 10-bit A/D Converter (ADC1) • 2 differential Sigma Delta 14-bit ADC (ADC3/4) • 16-bit timers - GPT12, Timer 2, Timer 21 and Timer 3 • Capture/compare unit for PWM signal generation (CCU6) • 2 full duplex serial interfaces (UART) with LIN support (for UART1 only) • 2 synchronous serial channels (SSC) • On-chip debug support via 2-wire SWD • 1 LIN 2.2 transceiver • 1 high voltage monitoring input • Single power supply from 5.5 V to 27 V • Extended power supply voltage range from 3 V to 28 V • Low-dropout voltage regulators (LDO) • High speed operational amplifier for motor current sensing via shunt • 5 V voltage supply for external loads (e.g. Hall sensor) • Core logic supply at 1.5 V • Programmable window watchdog (WDT1) with independent on-chip clock source • Power saving modes – MCU slow-down Mode – Sleep Mode – Stop Mode – Cyclic wake-up Sleep Mode • Power-on and undervoltage/brownout reset generator • Overtemperature protection • Short circuit protection Data Sheet 7 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Overview • Loss of clock detection with fail safe mode entry for low system power consumption • Temperature Range Tj = -40°C to +150°C • Package VQFN-48 with LTI feature • Green package (RoHS compliant) • AEC qualified Data Sheet 8 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Overview 1.1 Abbreviations The following acronyms and terms are used within this document. List see in Table 1. Table 1 Acronyms Acronyms Name AHB Advanced High-Performance Bus APB Advanced Peripheral Bus CCU6 Capture Compare Unit 6 CGU Clock Generation Unit CMU Cyclic Management Unit CP Charge Pump for MOSFET driver CSA Current Sense Amplifier DPP Data Post Processing ECC Error Correction Code EEPROM Electrically Erasable Programmable Read Only Memory EIM Exceptional Interrupt Measurement FSM Finite State Machine GPIO General Purpose Input Output H-Bridge Half Bridge ICU Interrupt Control Unit IEN Interrupt Enable IIR Infinite Impulse Response LDM Load Instruction LDO Low DropOut voltage regulator LIN Local Interconnect Network LSB Least Significant Bit LTI Lead Tip Inspection MCU Memory Control Unit MF Measurement Functions MSB Most Significant Bit MPU Memory Protection Unit MRST Master Receive Slave Transmit MTSR Master Transmit Slave Receive MU Measurement Unit NMI Non Maskable Interrupt NVIC Nested Vector Interrupt Controller NVM Non-Volatile Memory OTP One Time Programmable OSC Oscillator Data Sheet 9 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Overview Table 1 Acronyms Acronyms Name PBA Peripheral Bridge PCU Power Control Unit PD Pull Down PGU Power supply Generation Unit PLL Phase Locked Loop PPB Private Peripheral Bus PU Pull Up PWM Pulse Width Modulation RAM Random Access Memory RCU Reset Control Unit RMU Reset Management Unit ROM Read Only Memory SCU-DM System Control Unit - Digital Modules SCU-PM System Control Unit - Power Modules SFR Special Function Register SOW Short Open Window (for WDT) SPI Serial Peripheral Interface SSC Synchronous Serial Channel STM Store Instruction SWD ARM Serial Wire Debug TCCR Temperature Compensation Control Register TMS Test Mode Select TSD Thermal Shut Down UART Universal Asynchronous Receiver Transmitter VBG Voltage reference Band Gap VCO Voltage Controlled Oscillator VPRE Pre Regulator WDT Watchdog Timer in SCU-DM WDT1 Watchdog Timer in SCU-PM WMU Wake-up Management Unit 100TP 100 Time Programmable Data Sheet 10 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Block Diagram 2 Block Diagram TMS P0.0 TEST / DEBUG INTERFACE ARM CORTEX-M3 µDMA CONTROLL ER systembus FLASH slave SRAM slave ROM slave slave Multilayer AHB Matrix slave VAREF GND_REF MU-VAREF P2.0, P2.2, P2.3, P2.4, P2.5 (AN0, AN2, AN3, AN4, AN5) Figure 2 Data Sheet PBA1 SCU_DM ADC 3/4 ADC 1 DPP1 UART1 GPT12 PLL UART2 GPIO SSC1 SSC2 LIN T2 MOSFET Driver CCU6 T21 SCU_DM WDT SCU_PM WDT1/ CLKWDT µDMA Controller CP OP AMP VCP VSD CP2H CP2L CP1H CP1L PBA0 OP AMP VDH GH3 SH3 GL3 GH2 SH2 GL2 GH1 SH1 GL1 SL slave P0.1 – P0.4 P1.0 – P1.4 LIN GND_LIN MU MF / ADC2 DPP2 OP AMP OP1 OP2 PMU – Power Control System Functions VS RESET VDDEXT VDDP VDDC MON MON T3 Block Diagram 11 Rev. 1.0 2018-01-16 TLE9879-2QXA40 25 P0.2 27 P1.4 28 GND 29 P2.0/ADC3.P 30 P2.2/ADC3.N 31 P2.5/ADC4.N 32 P2.4/ADC4.P 33 GND_REF Device Pinout 34 VAREF 3.1 35 P2.3 Device Pinout and Pin Configuration 36 OP2 3 26 P1.3 Device Pinout and Pin Configuration OP1 37 24 P0.3 EP VDDC 38 23 P0.1 EP GND 39 22 RESET VDDP 40 21 P0.0 VDDEXT 41 20 TMS 19 GND GND_LIN 42 TLE 9879-2 LIN 43 18 P0.4 VDH 44 17 P1.2 VS 45 16 P1.1 SH3 46 15 P1.0 14 MON VSD 47 13 GL1 Note: Figure 3 Data Sheet GL2 12 SL 10 GL3 11 GH1 9 SH1 8 GH2 7 SH2 6 GH3 5 CP2L 4 CP2H 3 VCP 2 CP1L 1 CP1H 48 = Low voltage pins Device Pinout 12 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Device Pinout and Pin Configuration 3.2 Pin Configuration After reset, all pins are configured as input (except supply and LIN pins) with one of the following settings: • Pull-up device enabled only (PU) • Pull-down device enabled only (PD) • Input with both pull-up and pull-down devices disabled (I) • Output with output stage deactivated = high impedance state (Hi-Z) The functions and default states of the TLE9879-2QXA40 external pins are provided in the following table. Type: indicates the pin type. • I/O: Input or output • I: Input only • O: Output only • P: Power supply Not all alternate functions listed. Table 2 Symbol Pin Definitions and Functions Pin Number Type Reset Function State1) P0 Port 0 Port 0 is a 5-bit bidirectional general purpose I/O port. Alternate functions can be assigned and are listed in the port description. Main function is listed below. P0.0 21 I/O I/PU SWD Serial Wire Debug Clock P0.1 23 I/O I/PU GPIO General Purpose IO Alternate function mapping see Table 7 P0.2 25 I/O I/PD GPIO General Purpose IO Alternate function mapping see Table 7 Note: For a functional SWD connection this GPIO must be tied to zero! P0.3 24 I/O I/PU GPIO General Purpose IO Alternate function mapping see Table 7 P0.4 18 I/O I/PD GPIO General Purpose IO Alternate function mapping see Table 7 P1 Port 1 Port 1 is a 5-bit bidirectional general purpose I/O port. Alternate functions can be assigned and are listed in the Port description. The principal functions are listed below. P1.0 15 I/O I GPIO General Purpose IO Alternate function mapping see Table 8 P1.1 16 I/O I GPIO General Purpose IO Alternate function mapping see Table 8 P1.2 17 I/O I GPIO General Purpose IO Alternate function mapping see Table 8 Data Sheet 13 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Device Pinout and Pin Configuration Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function State1) P1.3 26 I/O I GPIO General Purpose IO, used for Inrush Transistor Alternate function mapping see Table 8 P1.4 27 I/O I GPIO General Purpose IO Alternate function mapping see Table 8 P2 Port 2 Port 2 is a 5-bit general purpose input-only port. Alternate functions can be assigned and are listed in the Port description. Main function is listed below. P2.0/ADC3.P 29 I/I I AN0 ADC analog input 0 (Sensor), ADC3+ Alternate function mapping see Table 9 P2.2/ADC3.N 30 I/O I AN2 ADC analog input 2 (Sensor), ADC3Alternate function mapping see Table 9 P2.3 35 I I AN3 ADC analog input 3 (Sensor), Alternate function mapping see Table 9 P2.4/ADC4.P 32 I I AN4 ADC analog input 4 (Sensor), ADC4+ Alternate function mapping see Table 9 P2.5/ADC4.N 31 I I AN5 ADC analog input 5 (Sensor), ADC4Alternate function mapping see Table 9 45 P – Battery supply input Power Supply VS VDDP 40 P – 2) VDDC 38 P – 3) Core supply (1.5 V during Active Mode). Do not connect external loads, connect external buffer capacitor. VDDEXT 41 P – External voltage supply output (5.0 V, 20 mA) GND 19 P – GND digital GND 28 P – GND digital GND 39 P – GND analog 14 I – High Voltage Monitor Input LIN 43 I/O – LIN bus interface input/output GND_LIN 42 P – LIN ground CP1H 48 P – Charge Pump Capacity 1 High, connect external C CP1L 1 P – Charge Pump Capacity 1 Low, connect external C CP2H 3 P – Charge Pump Capacity 2 High, connect external C CP2L 4 P – Charge Pump Capacity 2 Low, connect external C VCP 2 P – Charge Pump Capacity I/O port supply (5.0 V). Connect external buffer capacitor. Monitor Input MON LIN Interface Charge Pump Data Sheet 14 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Device Pinout and Pin Configuration Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number Type Reset Function State1) VSD 47 P – Battery supply input for Charge Pump VDH 44 P – Voltage Drain High Side MOSFET Driver SH3 46 P – Source High Side FET 3 SH2 6 P – Source High Side FET 2 GH2 7 P – Gate High Side FET 2 SH1 8 P – Source High Side FET 1 GH1 9 P – Gate High Side FET 1 SL 10 P – Source Low Side FET GL2 12 P – Gate Low Side FET 2 GL1 13 P – Gate Low Side FET 1 GH3 5 P – Gate High Side FET 3 GL3 11 P – Gate Low Side FET 3 GND_REF 33 P – GND for VAREF VAREF 34 I/O – 5V ADC1 reference voltage, optional buffer or input OP1 37 I – Negative operational amplifier input OP2 36 I – Positive operational amplifier input TMS 20 I I/O I/PD TMS SWD RESET 22 I/O – Reset input, not available during Sleep Mode EP – – – Exposed Pad, connect to GND MOSFET Driver Others Test Mode Select input Serial Wire Debug input/output 1) Only valid for digital IOs 2) Also named VDD5V. 3) Also named VDD1V5. Data Sheet 15 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Modes of Operation 4 Modes of Operation This highly integrated circuit contains analog and digital functional blocks. An embedded 32-bit microcontroller is available for system and interface control. On-chip, low-dropout regulators are provided for internal and external power supply. An internal oscillator provides a cost effective clock that is particularly well suited for LIN communications. A LIN transceiver is available as a communication interface. Driver stages for a Motor Bridge or BLDC Motor Bridge with external MOSFET are integrated, featuring PWM capability, protection features and a charge pump for operation at low supply voltage. A 10-bit SAR ADC and two differential 14-bit Sigma Delta ADCs are implemented for high precision sensor measurement. An 8-bit ADC is used for diagnostic measurements. The Micro Controller Unit supervision and system protection (including a reset feature) is complemented by a programmable window watchdog. A cyclic wake-up circuit, supply voltage supervision and integrated temperature sensors are available on-chip. All relevant modules offer power saving modes in order to support automotive applications connected to terminal 30. A wake-up from power-save mode is possible via a LIN bus message, via the monitoring input or using a programmable time period (cyclic wake-up). Featuring LTI, the integrated circuit is available in a VQFN-48-31 package with 0.5 mm pitch, and is designed to withstand the severe conditions of automotive applications. The TLE9879-2QXA40 has several operation modes mainly to support low power consumption requirements. Reset Mode The Reset Mode is a transition mode used e.g. during power-up of the device after a power-on reset, or after wake-up from Sleep Mode. In this mode, the on-chip power supplies are enabled and all other modules are initialized. Once the core supply VDDC is stable, the device enters Active Mode. If the watchdog timer WDT1 fails more than four times, the device performs a fail-safe transition to Sleep Mode. Active Mode In Active Mode, all modules are activated and the TLE9879-2QXA40 is fully operational. Stop Mode Stop Mode is one of two major low power modes. The transition to the low power modes is performed by setting the corresponding bits in the mode control register. In Stop Mode the embedded microcontroller is still powered, allowing faster wake-up response times. Wake-up from this mode is possible through LIN bus activity, by using the high-voltage monitoring pin or the corresponding 5V GPIOs. Stop Mode with Cyclic Wake-Up The Cyclic Wake-Up Mode is a special operating mode of the Stop Mode. The transition to the Cyclic Wake-Up Mode is done by first setting the corresponding bits in the mode control register followed by the Stop Mode command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal Stop Mode. Sleep Mode The Sleep Mode is a low-power mode. The transition to the low-power mode is done by setting the corresponding bits in the MCU mode control register or in case of failure, see below. In Sleep Mode the embedded microcontroller power supply is deactivated allowing the lowest system power consumption. A wake-up from this mode is possible by LIN bus activity, the High Voltage Monitor Input pin or Cyclic Wake-up. Data Sheet 16 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Modes of Operation Sleep Mode in Case of Failure Sleep Mode is activated after 5 consecutive watchdog failures or in case of supply failure (5 times). In this case, MON is enabled as the wake source and Cyclic Wake-Up is activated with 1s of wake time. Sleep Mode with Cyclic Wake-Up The Cyclic Wake-Up Mode is a special operating mode of the Sleep Mode. The transition to Cyclic Wake-Up Mode is performed by first setting the corresponding bits in the mode control register followed by the Sleep and Stop Mode command. In addition to the cyclic wake-up behavior (wake-up after a programmable time period), asynchronous wake events via the activated sources (LIN and/or MON) are available, as in normal Sleep Mode. When using Sleep Mode with cyclic wake-up the voltage regulator is switched off and started again with the wake. A limited number of registers is buffered during sleep, and can be used by SW e.g. for counting sleep/wake cycles. MCU Slow Down Mode In MCU Slow Down Mode the MCU frequency is reduced for saving power during operation. LIN communication is still possible. LS MOSFET can be activated. Wake-Up Source Prioritization All wake-up sources have the same priority. In order to handle the asynchronous nature of the wake-up sources, the first wake-up signal will initiate the wake-up sequence. Nevertheless all wake-up sources are latched in order to provide all wake-up events to the application software. The software can clear the wakeup source flags. This is to ensure that no wake-up event is lost. As default wake-up source, the MON input is activated after power-on reset only. Additionally, the device is in Cyclic Wake-Up Mode with the max. configurable dead time setting. The following table shows the possible power mode configurations including the Stop Mode. Table 3 Power Mode Configurations Module/Function Active Mode Stop Mode Sleep Mode Comment VDDEXT ON/OFF ON (no dynamic load)/OFF OFF – Bridge Driver ON/OFF OFF OFF LIN TRx ON/OFF wake-up only/ OFF wake-up only/ OFF VS sense ON/OFF brownout detection brownout detection POR on VS brownout det. done in PCU GPIO 5V (wake-up) n.a. disabled/static OFF – GPIO 5V (active) ON ON OFF – WDT1 ON OFF OFF – CYCLIC WAKE n.a. cyclic wake-up/ cyclic sense/OFF cyclic wake-up/ OFF – Measurement ON1) OFF OFF – OFF – MCU Data Sheet ON/slowdown/STOP 2) STOP 17 – Rev. 1.0 2018-01-16 TLE9879-2QXA40 Modes of Operation Table 3 Power Mode Configurations (cont’d) Module/Function Active Mode Stop Mode Sleep Mode Comment CLOCK GEN (MC) ON OFF OFF – LP_CLK (18 MHz) ON OFF OFF WDT1 LP_CLK2 (100 kHz) ON/OFF ON/OFF ON/OFF for cyclic wake-up 1) May not be switched off due to safety reasons 2) MC PLL clock disabled, MC supply reduced to 1.1 V Wake-Up Levels and Transitions The wake-up can be triggered by rising, falling or both signal edges for the monitor input, by LIN or by cyclic wake-up. Data Sheet 18 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Power Management Unit (PMU) 5 Power Management Unit (PMU) 5.1 Features • System modes control (startup, sleep, stop and active) • Power management (cyclic wake-up) • Control of system voltage regulators with diagnosis (overload, short, overvoltage) • Fail safe mode detection and operation in case of system errors (watchdog fail) • Wake-up sources configuration and management (LIN, MON, GPIOs) • System error logging 5.2 Introduction The power management unit is responsible for generating all required voltage supplies for the embedded MCU (VDDC, VDDP) and the external supply (VDDEXT). The power management unit is designed to ensure failsafe behavior of the system IC by controlling all system modes including the corresponding transitions. Additionally, the PMU provides well defined sequences for the system mode transitions and generates hierarchical reset priorities. The reset priorities control the reset behavior of all system functionalities especially the reset behavior of the embedded MCU. All these functions are controlled by a state machine. The system master functionality of the PMU make use of an independent logic supply and system clock. For this reason, the PMU has an "Internal logic supply and system clock" module which works independently of the MCU clock. Data Sheet 19 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Power Management Unit (PMU) 5.2.1 Block Diagram The following figure shows the structure of the Power Management Unit. Table 4 describes the submodules in more detail. VS Power Down Supply e.g. for WDT 1 e.g. for cyclic wake and sense Power Supply Generation Unit (PGU) I N T E R N A L LP_CLK Peripherals LP_CLK2 B U S PMU-PCU MON LIN P0.0...P0.4 P1.0...P1.4 LDO for External Supply VDDEXT VDDP VDDC VDDEXT PMU-SFR PMU-CMU PMU-WMU PMU-RMU PMU-Control Power Management Unit Power_Management_ 7x.vsd Figure 4 Power Management Unit Block Diagram Table 4 Description of PMU Submodules Mod. Name Modules Functions Power Down Supply Independent supply voltage generation for PMU This supply is dedicated to the PMU to ensure an independent operation from generated power supplies (VDDP, VDDC). LP_CLK (= 18 MHz) - Clock source for all PMU submodules - Backup clock source for System - Clock source for WDT1 This ultra low power oscillator generates the clock for the PMU. This clock is also used as backup clock for the system in case of PLL Clock failure and as an independent clock source for WDT1. LP_CLK2 (= 100 kHz) Clock source for PMU This ultra low power oscillator generates the clock for the PMU in Stop Mode and in the cyclic modes. Peripherals Peripheral blocks of PMU These blocks include the analog peripherals to ensure a stable and fail-safe PMU startup and operation (bandgap, bias). Data Sheet 20 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Power Management Unit (PMU) Table 4 Mod. Name Description of PMU Submodules (cont’d) Modules Functions Power Supply Voltage regulators for VDDP and Generation VDDC Unit (PGU) This block includes the voltage regulators for the pad supply (VDDP) and the core supply (VDDC). VDDEXT Voltage regulator for VDDEXT to supply external modules (e.g. sensors) This voltage regulator is a dedicated supply for external modules and can also be used for cyclic sense operations (e.g. with hall sensor). PMU-SFR All Extended Special Function registers that are relevant to the PMU. This module contains all registers needed to control and monitor the PMU. PMU-PCU Power Control Unit of the PMU This block is responsible for controlling all power related actions within the PGU Module. It also contains all regulator related diagnostics such as undervoltage and overvoltage detection as well as overcurrent and short circuit diagnostics. PMU-WMU Wake-Up Management Unit of the PMU This block is responsible for controlling all wake-up related actions within the PMU Module. PMU-CMU Cyclic Management Unit of the PMU This block is responsible for controlling all actions in cyclic mode. PMU-RMU Reset Management Unit of the PMU This block generates resets triggered by the PMU such as undervoltage or short circuit reset, and passes all resets to the relevant modules and their register. Data Sheet 21 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Power Management Unit (PMU) 5.2.2 PMU Modes Overview The following state diagram shows the available modes of the device. V S > 4V and VS ramp up or VS < 3V and VS ramp down LIN-wake or MON-wake or cyclic -wake start-up VDDC =stable and error_supp 2.2 µF Elco1) CVDDP Blocking capacitor at VDDP pin 470 nF + 100 nF Ceramic, ESR < 1 Ω CVDD_EXT Blocking capacitor at VDDEXT pin 100nF, Ceramic ESR < 1 Ω CVDDC Blocking capacitor at VDDC pin 470 nF + 100 nF Ceramic, ESR < 1 Ω CVAREF Blocking capacitor at VAREF pin 100 nF, Ceramic ESR < 1 Ω CLIN Standard C for LIN slave 220 pF CVSD Filter C for charge pump end driver 1 µF CCPS1 Charge pump capacitor 220 nF CCP2S Charge pump capacitor 220 nF CVCP Charge pump capacitor 470 nF CMON Filter C for ISO pulses 10 nF CVDH Capacitor 3.3 nF CPH1 Capacitor 220 µF CPH2 Capacitor 220 µF CPH3 Capacitor 220 µF COPAFILT Capacitor 100 nF CEMCP1 Capacitor 1 nF CEMCP2 Capacitor 1 nF CEMCP3 Capacitor 1 nF CPFILT1, CPFILT2 Capacitor RMON Resistor at MON pin RVSD Limitation of reverse current due to 2 Ω transient (-2V, 8ms) max. ratings of the VSD pin has to be met, alternatively the resistor shall be replaced by a diode RVDH Resistor 1 kΩ RGATE Resistor 2Ω ROPAFILT Resistor 12 Ω RSH1 Resistor optional RSH2 Resistor optional RSH3 Resistor optional 3.9 kΩ – LPFILT DVS Reverse-polarity protection diode – 1) The capacitor must be dimensioned so as to ensure that flash operations modifying the content of the flash are never interrupted (e.g. in case of power loss). Data Sheet 84 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Application Information 29.2 ESD Immunity According to IEC61000-4-2 Note: Tests for ESD immunity according to IEC61000-4-2 “Gun test” (150pF, 330Ω) has been performed. The results and test condition will be available in a test report. Table 15 ESD “Gun Test” Performed Test Result Unit Remarks ESD at pin LIN, versus GND1) >6 kV 2) ESD at pin LIN, versus GND1) < -6 kV 2) positive pulse negative pulse 1) ESD test “ESD GUN” is specified with external components; see application diagram: CMON = 100 nF, RMON = 1 kΩ, CLIN = 220 pF, CVS = >20 µF ELCO + 100 nF ESR < 1 Ω, CVSD = 1 µF, RVSD = 2 Ω. 2) ESD susceptibility “ESD GUN” according to LIN EMC Test Specification, Section 4.3 (IEC 61000-4-2). To be tested by external test house (IBEE Zwickau) Data Sheet 85 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30 Electrical Characteristics This chapter includes all relevant electrical characteristics of the product TLE9879-2QXA40. 30.1 General Characteristics 30.1.1 Absolute Maximum Ratings Table 16 Absolute Maximum Ratings1) Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Voltages – Supply Pins Supply voltage – VS VS -0.3 – 40 V Load dump P_1.1.1 Supply voltage – VSD VSD -0.3 – 48 V – P_1.1.2 Supply voltage – VSD VSD_max_exten -2.8 – 48 V Series resistor RVSD = P_1.1.32 2.2 Ω, t = 8 ms 2) d Voltage range – VDDP VDDP -0.3 – 5.5 V – Voltage range – VDDP VDDP_max_exte -0.3 – 7 V P_1.1.41 In case of voltage transients on VS with dVS/dt ≥ 1V/µs; duration: t ≤ 150µs; CVDDP ≤ 570 nF nd P_1.1.3 Voltage range – VDDEXT VDDEXT -0.3 – 5.5 V – Voltage range – VDDEXT VDDEXT_max_e -0.3 – 7 V In case of voltage P_1.1.42 transients on VS with dVS/dt ≥ 1V/µs; duration: t ≤ 150µs; CVDDEXT ≤ 570 nF xtend P_1.1.4 VDDC -0.3 – 1.6 V – P_1.1.5 Input voltage at LIN VLIN -28 – 40 V – P_1.1.7 Input voltage at MON VMON_maxrate -28 – 40 V 3) P_1.1.8 V 4) P_1.1.38 P_1.1.9 Voltage range – VDDC Voltages – High Voltage Pins Input voltage at VDH VVDH_maxrate -2.8 – 40 Voltage range at GHx VGH -8.0 – 48 V 5) Voltage range at GHx vs. SHx VGHvsSH 14 – – V – P_1.1.44 Voltage range at SHx VSH -8.0 – 48 V – P_1.1.11 Voltage range at GLx VGL -8.0 – 48 V 6) Voltage range at GLx vs. SL VGLvsSL 14 – – V – Data Sheet 86 – P_1.1.13 P_1.1.45 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 16 Absolute Maximum Ratings1) (cont’d) Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Min. Typ. Max. Unit Note or Test Condition VCPx -0.3 – 48 V 7) P_1.1.15 Vin -0.3 – VDDP +0.3 V VIN < VDDPmax8) P_1.1.16 IVCP -15 – – mA – P_1.1.35 Injection current on any port pin IGPIONM -5 – 5 mA 9) P_1.1.34 Sum of all injected currents in Normal Mode IGPIOAM_sum -50 – 50 mA 9) P_1.1.30 -5000 – 50 µA 9) P_1.1.36 – 5 mA 9) P_1.1.37 Voltage range at charge pump pins CP1H, CP1L, CP2H, CP2L, VCP Symbol Values Number Voltages – GPIOs Voltage on any port pin Current at VCP Pin Max. current at VCP pin Injection Current at GPIOs Sum of all injected currents in IGPIOPD_sum Power Down Mode (Stop Mode) Sum of all injected currents in Sleep Mode IGPIOSleep_sum -5 Other Voltages Input voltage VAREF VAREF -0.3 – VDDP +0.3 V – P_1.1.17 Input voltage OP1, OP2 VOAI -7 – 7 V – P_1.1.23 Junction temperature Tj -40 – 150 °C – P_1.1.18 Storage temperature Tstg -55 – 150 °C – P_1.1.19 ESD susceptibility all pins VESD1 -2 – 2 kV HBM 10) P_1.1.20 ESD susceptibility pins MON, VS, VSD vs.GND VESD2 -4 – 4 kV HBM 11) P_1.1.21 ESD susceptibility pins LIN vs. GND_LIN VESD3 -6 – 6 kV HBM 10) P_1.1.22 ESD susceptibility CDM all pins vs. GND VESD_CDM1 -500 – 500 V 12) P_1.1.28 ESD susceptibility CDM pins 1, 12, 13, 24, 25, 36, 37, 48 (corner pins) vs. GND VESD_CDM2 -750 – 750 V 12) P_1.1.43 Temperatures ESD Susceptibility 1) Not subject to production test, specified by design. Data Sheet 87 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 2) 3) 4) 5) Conditions and min. value is derived from application condition for reverse polarity event. Min voltage -28V with external 3.9kΩ series resistor only. Min voltage -2.8V with external 1kΩ series resistor only. To achieve max. ratings on this pin, Parameter P_1.1.44 has to be taken into account resulting in the following dependency: VGH < VSH + VGHvsSH_min and additionally VSH < VGH + 0.3V. 6) To achieve max. ratings on this pin, Parameter P_1.1.45 has to be taken into account resulting in the following dependency: VGL < VSL + VGLvsSL_min and additionally VSL < VGL + 0.3V. 7) These limits can be kept if max current drawn out of pin does not exceed limit of 200 µA. 8) Includes TMS and RESET. 9) Maximum rating for injection current of GPIO with VIN respected. 10) ESD susceptibility HBM according to ANSI/ESDA/JEDEC JS-001 (1.5kΩ, 100pF) 11) MON with external circuitry of a series resistor of 3.9kΩ and 10nF (at connector); VS with an external ceramic capacitor of 100nF; VSD with an external capacitor of 470nF; VDH with external circuitry of a series resistor of 1kΩ and 3.3nF (at pin). 12) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JESD22-C101F Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 88 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.1.2 Functional Range Table 17 Functional Range Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Number Test Condition Supply voltage in Active Mode VS_AM 5.5 – 28 V – Extended supply voltage in Active Mode VS_AM_exten 28 – 40 V 1) d Functional P_1.2.16 with parameter deviation Supply voltage in Active Mode for MOSFET Driver Supply VSD_AM 5.4 – 28 V Extended supply voltage in Active Mode for MOSFET Driver Supply VSD_AM_exte 28 – 32 V 1)3) nd P_1.2.1 P_1.2.18 Functional P_1.2.17 with parameter deviation Specified supply voltage for LIN Transceiver VS_AM_LIN 5.5 – 18 V Parameter Specification Extended supply voltage for LIN Transceiver VS_AM_LIN 4.8 – 28 V Functional with P_1.2.14 parameter deviation Supply voltage in Active Mode with reduced functionality (Microcontroller / Flash with full operation) VS_AMmin 3.0 – 5.5 V 2) P_1.2.3 Supply voltage in Sleep Mode VS_Sleep 3.0 – 28 V – P_1.2.4 V/µs 3) P_1.2.5 P_1.2.7 Supply voltage transients slew rate dVS/dt -1 – 1 P_1.2.2 Output sum current for all GPIO pins IGPIO,sum -50 – 50 mA 3) Operating frequency fsys 5 – 40 MHz 4) P_1.2.15 Junction temperature Tj -40 – 150 °C – P_1.2.9 1) This operation voltage range is only allowed for a short duration: tmax ≤ 400 ms (continuous operation at this voltage is not allowed), fsys = 24 MHz, IVDDP = 10 mA, IVDDEXT = 5 mA. In addition, the power dissipation caused by the Charge Pump + MOSFET driver have to be considered. 2) Reduced functionality (e.g. cranking pulse) - Parameter deviation possible. 3) Not subject to production test, specified by design. 4) Function not specified when limits are exceeded. Data Sheet 89 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.1.3 Current Consumption Table 18 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current consumption in IVs Active Mode at pin VS – 30 35 mA fsys = 20 MHz P_1.3.1 no loads on pins, LIN in recessive state1) Current consumption in IVSD Active Mode at pin VSD – – 40 mA 20 kHz PWM on Bridge Driver Current consumption in ISDM_3P Slow Down Mode – – 35 mA fsys = 5 MHz; LIN communication P_1.3.19 running; charge pump on (reverse polarity FET on), external Low Side FET static on (motor break mode); VDDEXT on; Sensor input read via SD ADC and calculate angle (fADC3/4 = 5 MHz) all other module set to power down;VS = 13.5V Current consumption in ISleep Sleep Mode – 30 35 µA System in Sleep Mode, microcontroller not powered, Wake capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: TJ = -40°C to 85°C; VS = 5.5 V to 18V;2) P_1.3.3 Current consumption in ISleep_exten – Sleep Mode extended d range 90 200 µA System in Sleep Mode, microcontroller not powered, Wake capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: TJ = -40°C to 150°C; VS = 5.5 V to 18V;2) P_1.3.15 Current consumption in ISleep Sleep Mode – 33 µA System in Sleep Mode, microcontroller not powered, Wake capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND: TJ = -40°C to 40°C; VS = 5.5 V to 18V;2) P_1.3.9 Current Consumption @VS pin Data Sheet – 90 P_1.3.8 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 18 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current consumption in ICyclic Sleep Mode with cyclic wake – – 110 µA TJ = -40°C to 85°C; VS = 5.5 V to 18V; tCyclic_ON = 4ms; tCyclic_OFF = 2048 ms;2) P_1.3.4 Current consumption in IStop Stop Mode – 110 160 µA System in Stop Mode, microcontroller not clocked, Wake capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND; TJ = 40°C to 85°C; VS = 5.5 V to 18V P_1.3.10 Current consumption in IStop_extend – Stop Mode-Extended temperature range 1 600 1800 µA System in Stop Mode, microcontroller not clocked, Wake capable via LIN and MON; MON connected to VS or GND; GPIOs open (no loads) or connected to GND; TJ = -40 °C to 150 °C; VS = 5.5 V to 18 V P_1.3.20 1) Current on VS, ADC1/2 active, timer running, LIN active (recessive). 2) Incl. leakage currents form VDH, VSD and MON Note: Data Sheet Within the functional range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 91 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.1.4 Table 19 Thermal Resistance Thermal Resistance Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Junction to Soldering Point RthJSP – 6 – K/W 1) measured to Exposed Pad P_1.4.1 Junction to Ambient RthJA – 33 – K/W 2) P_1.4.2 1) Not subject to production test, specified by design. 2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board. Board: 76.2x114.3x1.5mm3 with 2 inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm). 30.1.5 Timing Characteristics The transition times between the system modes are specified here. Generally the timings are defined from the time when the corresponding bits in register PMCON0 are set until the sequence is terminated. Table 20 System Timing1) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number Wake-up over battery tstart – – 3 ms Battery ramp-up time to code P_1.5.6 execution Wake-up over battery tstartSW – – 1.5 ms Battery ramp-up time to till P_1.5.1 MCU reset is released; VS > 3 V and RESET = 1 Sleep-Exit tsleep - exit – – 1.5 ms Rising/falling edge of any P_1.5.2 wake-up signal (LIN, MON) till MCU reset is released; Sleep-Entry tsleep - – – 330 µs 2) P_1.5.3 entry 1) Not subject to production test, specified by design. 2) Wake events during Sleep-Entry are stored and lead to wake-up after Sleep Mode is reached. Data Sheet 92 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.2 Power Management Unit (PMU) This chapter includes all electrical characteristics of the Power Management Unit 30.2.1 PMU I/O Supply (VDDP) Parameters This chapter describes all electrical parameters which are observable on SoC level. For this purpose only the pad-supply VDDP and the transition times between the system modes are specified here. Table 21 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Specified output current IVDDP 0 – 50 mA 1) P_2.1.1 Specified output current IVDDP 0 – 30 mA 1)2) P_2.1.22 3)4) Required decoupling capacitance CVDDP1 0.47 – 2.2 µF ESR < 1Ω; the specified capacitor value is a typical value. P_2.1.2 Required buffer capacitance for stability (load jumps) CVDDP2 1 – 2.2 µF 3)4) The specified capacitor value is a typical value. P_2.1.20 Output voltage including line and load regulation @ Active Mode VDDPOUT 4.9 5.0 5.1 V 5) P_2.1.3 Output voltage including line and load regulation @ Active Mode VDDPOUT 4.9 5.0 5.1 V 2)5) Output voltage including line and load regulation @ Stop Mode VDDPOUTST 4.5 5.0 5.5 V 5) Iload is only internal; VS > 5.5V P_2.1.21 Output drop @ Active Mode VSVDDPout – 50 400 mV IVDDP = 30mA6); 3.5V < VS < 5.0V P_2.1.4 Load regulation @ Active Mode VVDDPLOR -50 – 50 mV 2 ... 90mA; C = 570nF P_2.1.5 Line regulation @ Active Mode VVDDPLIR -50 – 50 mV VS = 5.5 ... 28V P_2.1.6 Overvoltage detection VDDPOV 5.14 – 5.4 V VS > 5.5V; Overvoltage leads to SUPPLY_NMI P_2.1.7 Overvoltage detection filter time tFILT_VDDPO – 735 – µs 3)7) P_2.1.24 V Voltage OK detection VDDPOK – 3 – V 3) P_2.1.25 Voltage stable detection range8) ∆VDDPSTB - 220 – + 220 mV 3) P_2.1.26 Undervoltage reset VDDPUV 2.5 2.6 2.7 V – P_2.1.8 Overcurrent diagnostic IVDDPOC 91 – 220 mA – P_2.1.9 Data Sheet OP 93 Iload < 90mA; VS > 5.5V Iload < 70mA; VS > 5.5V P_2.1.23 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 21 Electrical Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Overcurrent diagnostic filter time tFILT_VDDPO – Overcurrent diagnostic shutdown time tFILT_VDDPO – 1) 2) 3) 4) 5) 6) 7) 8) 9) Unit Note or Test Condition Number Typ. Max. 27 – µs 3)7) P_2.1.27 290 – µs 3)7)9) P_2.1.28 C C_SD Specified output current for port supply and additional other external loads already excluding VDDC current. This use case applies to cases where output current on VDDEXT is max. 40 mA. Not subject to production test, specified by design. Ceramic capacitor. Load current includes internal supply. Output drop for IVDDP without internal supply current. This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK. The absolute voltage value is the sum of parameters VDDP + ∆VDDPSTB. After tFILT_VDDCOC_SD is passed and the overcurrent condition is still present, the device will enter sleep mode. Data Sheet 94 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.2.2 PMU Core Supply (VDDC) Parameters This chapter describes all electrical parameters which are observable on SoC level. For this purpose only the core-supply VDDC and the transition times between the system modes are specified here. Table 22 Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Required decoupling capacitance CVDDC1 0.1 – 1 µF 1)2) ESR < 1Ω; the specified capacitor value is a typical value. P_2.2.1 Required buffer capacitance for stability (load jumps) CVDDC2 0.33 – 1 µF 2) the specified capacitor value is a typical value. P_2.2.17 Output voltage including line regulation @ Active Mode VDDCOUT 1.44 1.5 1.56 V Iload < 40mA P_2.2.2 Reduced output voltage including line regulation @ Stop Mode VDDCOUT_S 0.95 1.1 1.3 V with internal VDDC P_2.2.23 load only: Iload_internal < 1.5mA top_Red Number Load Regulation @ Active Mode VDDCLOR -50 – 50 mV 2 ... 40mA; C =430nF P_2.2.3 Line regulation @ Active Mode VDDCLIR -25 – 25 mV VDDP = 2.5 ... 5.5V Overvoltage detection VDDCOV 1.59 1.62 1.68 V Overvoltage leads to P_2.2.5 SUPPLY_NMI 735 – µs 1)3) P_2.2.18 – + 280 mV 1) P_2.2.19 + 110 mV 1) P_2.2.20 – P_2.2.6 Overvoltage detection filter time tFILT_VDDC – P_2.2.4 OV 4) ∆VDDCOK Voltage OK detection range 5) - 280 Voltage stable detection range ∆VDDCSTB - 110 Undervoltage reset VDDVUV 1.136 1.20 1.264 V Overcurrent diagnostic IVDDCOC 45 100 mA – P_2.2.7 P_2.2.21 P_2.2.22 Overcurrent diagnostic filter time tFILT_VDDC – – – 27 – µs 1)3) 290 – µs 1)3)6) OC Overcurrent diagnostic shutdown tFILT_VDDC – time OC_SD 1) 2) 3) 4) 5) 6) Not subject to production test, specified by design. Ceramic capacitor. This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK. The absolute voltage value is the sum of parameters VDDC + ∆VDDCSTB. The absolute voltage value is the sum of parameters VDDC + ∆VDDCOK. After tFILT_VDDCOC_SD is passed and the overcurrent condition is still present the device will enter sleep mode. Data Sheet 95 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.2.3 Table 23 VDDEXT Voltage Regulator (5.0V) Parameters Electrical Characteristics VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Specified output current IVDDEXT 0 – 20 mA – P_2.3.1 Specified output current IVDDEXT 0 – 40 mA 1) P_2.3.21 3) 2) Required decoupling capacitance CVDDEXT1 0.1 – 2.2 µF ESR < 1 Ω; the specified capacitor value is a typical value. P_2.3.22 Required buffer capacitance for stability (load jumps) CVDDEXT2 1 – 2.2 µF 3)2) the specified capacitor value is a typical value. P_2.3.20 Output voltage including line and load regulation VDDEXT 4.9 5.0 5.1 V 3) Iload 5.5V P_2.3.3 Output voltage including line and load regulation VDDEXT 4.8 5.0 5.2 V Iload 5.5V P_2.3.23 Output drop @ Active Mode VS-VDDEXT 50 +300 mV 3) Iload < 20mA; 3V < VS < 5.0V P_2.3.4 Output drop @ Active Mode VS-VDDEXT – +400 mV Iload < 40mA; 3V < VS < 5.0V P_2.3.14 Load regulation @ Active Mode VDDEXTLOR -50 – 50 mV 2 ... 40mA; C =200nF P_2.3.5 Line regulation @ Active Mode VVDDEXTLIR -50 – 50 mV VS = 5.5 ... 28V P_2.3.6 Power supply ripple rejection @ PSSRVDDEXT Active Mode 50 – – dB 3) VS = 13.5V; f =0 ... 1KHz; Vr=2Vpp P_2.3.7 Overvoltage detection 5.18 – 5.4 V P_2.3.8 735 – µs VS > 5.5V 3)4) 3 – V 3) P_2.3.25 mV 3) P_2.3.26 P_2.3.9 VVDDEXTOV Overvoltage detection filter time tFILT_VDDEXTO – P_2.3.24 V Voltage OK detection range VVDDEXTOK 5) Voltage stable detection range – ∆VVDDEXTSTB - 220 – + 220 Undervoltage trigger VVDDEXTUV 2.6 2.8 3.0 V 6) Overcurrent diagnostic IVDDEXTOC 50 – 160 mA – P_2.3.10 P_2.3.27 P_2.3.28 Overcurrent diagnostic filter time tFILT_VDDCOC – 27 – µs 3)4) Overcurrent diagnostic shutdown time tFILT_VDDCOC – 290 – µs 3)4) _SD 1) This use case requires the reduced utilization of VDDP output current by 20 mA, see P_2.1.22. 2) Ceramic capacitor. 3) Not subject to production test, specified by design. Data Sheet 96 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 4) This filter time and its variation is derived from the time base tLP_CLK = 1 / fLP_CLK. 5) The absolute voltage value is the sum of parameters VDDEXT + ∆VDDEXTSTB. 6) When the condition is met, the Bit VDDEXT_CTRL.bit.SHORT will be set. Data Sheet 97 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.2.4 VPRE Voltage Regulator (PMU Subblock) Parameters The PMU VPRE Regulator acts as a supply of VDDP and VDDEXT voltage regulators. Table 24 Functional Range Parameter Symbol Specified output current IVPRE Values Min. Typ. Max. Unit Note or Test Condition – – 110 mA Number 1) P_2.4.1 1) Not subject to production test, specified by design. 30.2.4.1 Load Sharing Scenarios of VPRE Regulator The figure below shows the possible load sharing scenarios of VPRE regulator. VS VPRE max. 110 mA VDDEXT VDDEXT - 5V 1: max. 20 mA 2: max. 40 mA VDDP - 5V 1: max. 90 mA 2: max. 70 mA VDDP CVDDEXT CVDDP GND (Pin 39) GND (Pin 39) VDDC VDDC - 1.5V max. 40 mA CVDDC GND (Pin 39) Load Sharing VPRE – Scenarios 1 & 2 Load_Sharing_VPRE.vsd Figure 36 Data Sheet Load Sharing Scenarios of VPRE Regulator 98 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.2.5 Power Down Voltage Regulator (PMU Subblock) Parameters The PMU Power Down voltage regulator consists of two subblocks: • Power Down Pre regulator: VDD5VPD • Power Down Core regulator: VDD1V5_PD (Supply used for GPUDATAxy registers) Both regulators are used as purely internal supplies. The following table contains all relevant parameters: Table 25 Functional Range Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition – 1.5 V Number VDD1V5_PD Power-On Reset Threshold VDD1V5_PD_ 1.2 1) P_2.5.1 RSTTH 1) Not subject to production test, specified by design Data Sheet 99 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.3 System Clocks 30.3.1 Oscillators and PLL Parameters Table 26 Electrical Characteristics System Clocks VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Unit Note or Test Condition Number Typ. Max. 14 18 22 MHz This clock is used at P_3.1.1 startup and can be used in case the PLL fails 70 100 130 kHz This clock is used for cyclic P_3.1.2 wake PMU Oscillators (Power Management Unit) Frequency of LP_CLK fLP_CLK Frequency of LP_CLK2 fLP_CLK2 CGU Oscillator (Clock Generation Unit Microcontroller) Short term frequency deviation1) fTRIMST -0.4 – +0.4 % 2)3) Absolute accuracy fTRIMABSA -1.5 – +1.5 % Including temperature and P_3.1.4 lifetime deviation – – 10 µs 3) CGU-OSC Start-up time tOSC Within any 10 ms, e.g. after synchronization to a LIN frame (PLL settings untouched within 10 ms) P_3.1.3 Startup time OSC from P_3.1.5 Sleep Mode, power supply stable PLL (Clock Generation Unit Microcontroller) 3) VCO frequency range Mode 0 fVCO-0 48 – 112 MHz VCOSEL =”0” P_3.1.6 VCO frequency range Mode 1 fVCO-1 96 – 160 MHz VCOSEL =”1” P_3.1.7 Input frequency range fOSC 4 – 16 MHz – P_3.1.8 Output freq. range fPLL 0.04687 – 80 MHz – P_3.1.10 Free-running frequency Mode 0 fVCOfree_0 – – 38 MHz VCOSEL =”0” P_3.1.11 Free-running frequency Mode 1 fVCOfree_1 – – 76 MHz VCOSEL =”1” P_3.1.12 Input clock high/low time thigh/low 10 – – ns – P_3.1.13 Peak period jitter tjp -500 – 500 ps 4) for K=1 P_3.1.14 for K=1 P_3.1.15 Accumulated jitter jacc – – 5 ns 4) Lock-in time tL – – 200 µs – Data Sheet 100 P_3.1.16 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 1) 2) 3) 4) The typical oscillator frequency is 5 MHz VDDC = 1.5 V, Tj = 25°C Not subject to production test, specified by design. This parameter is valid for PLL operation with an external clock source and thus reflects the real PLL performance. Data Sheet 101 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.4 Flash Memory This chapter includes the parameters for the 128 kByte embedded flash module. 30.4.1 Table 27 Flash Parameters Flash Characteristics1) VS = 3.0 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Unit Note or Test Condition Number Max. 2) 3.5 ms 3V < VS < 28V P_4.1.1 Programming time per 128 byte page tPR – 3 Erase time per sector/page tER – 42) 4.5 ms 3V < VS < 28V P_4.1.2 Data retention time tRET 20 – – years 1,000 erase / program cycles P_4.1.3 Data retention time tRET 50 – – years 1,000 erase / program cycles Tj = 30°C3) P_4.1.9 Flash erase endurance for user sectors NER 30 – – kcycles Data retention time 5 years Flash erase endurance for security pages NSEC 10 – – cycles 4) Drain disturb limit NDD 32 – – kcycles 5) P_4.1.4 Data retention P_4.1.5 time 20 years P_4.1.6 1) Not subject for production test, specified by design. 2) Programming and erase times depend on the internal Flash clock source. The control state machine needs a few system clock cycles. The requirement is only relevant for extremely low system frequencies. 3) Derived by extrapolation of lifetime tests. 4) Tj = 25 °C. 5) This parameter limits the number of subsequent programming operations within a physical sector without a given page in this sector being (re-)programmed. The drain disturb limit is applicable if wordline erase is used repeatedly. For normal sector erase/program cycles this limit will not be violated. For data sectors the integrated EEPROM emulation firmware routines handle this limit automatically, for wordline erases in code sectors (without EEPROM emulation) it is recommended to execute a software based refresh, which may make use of the integrated random number generator NVMBRNG to statistically start a refresh. Data Sheet 102 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.5 Parallel Ports (GPIO) 30.5.1 Description of Keep and Force Current VDDP keeper current PU Device PUDSEL P1.x P0.x \PUDSEL keeper current PD Device VSS Pull- Up- Down.vsd Figure 37 Pull-Up/Down Device UGPIO Logical "1" 7.5 kOhm (equivalent) (1.5V / 200uA) VIH - VDDP Undefined 2.33 kOhm (equivalent) (3.5V / 1.5mA) VIL - VDDP Logical "0" -I PLF Figure 38 Data Sheet I -IPLK Current_Diag.vsd Pull-Up Keep and Forced Current 103 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics UGPIO Logical "1" 2.33 kOhm (equivalent) (3.5V / 1.5mA) VIH Undefined 7.5 kOhm (equivalent) (1.5V / 200uA) VIL Logical "0" IPLK Figure 39 I I PLF Current_Diag-Pull _down.vsd Pull-Down Keep and Force Current 30.5.2 DC Parameters of Port 0, Port 1, TMS and Reset Note: Operating Conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the maximum allowed ocurrent which can be taken out of VDDP. Current Limits for Port Output Drivers1) Table 28 Port Output Driver Mode Maximum Output Current (IOLmax , - IOHmax) Maximum Output Current (IOLnom , - IOHnom) Number VDDP ≥ 4.5V 2.6V < VDDP < VDDP ≥ 4.5V 4.5V 2.6V < VDDP < 4.5V Strong driver2) 5 mA 3 mA 1.6 mA 1.0 mA P_5.1.15 Medium driver3) 3 mA 1.8 mA 1.0 mA 0.8 mA P_5.1.1 0.5 mA 0.3 mA 0.25 mA 0.15 mA P_5.1.2 3) Weak driver 1) Not subject to production test, specified by design. 2) Not available for port pins P0.4, P1.0, P1.1 and P1.2 3) All P0.x and P1.x Table 29 DC Characteristics Port0, Port1 VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number 1) Input hysteresis HYSP0_P1 0.11 x VDDP – – V Series P_5.1.5 resistance = 0 Ω; 4.5V ≤ VDDP ≤ 5.5V Input hysteresis HYSP0_P1_ – 0.09 x VDDP – V 1) exend Data Sheet 104 Series P_5.1.16 resistance = 0 Ω; 2.6V ≤ VDDP ≤ 4.5V Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 29 DC Characteristics Port0, Port1 (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Input low voltage VIL -0.3 – 0.3 x VDDP V 2) 4.5V ≤ VDDP ≤ 5.5V P_5.1.3 Input low voltage VIL_extend -0.3 0.42 x VDDP – V 1) 2.6V ≤ VDDP ≤ 4.5V P_5.1.17 Input high voltage VIH 0.7 x VDDP – VDDP + 0.3 V 2) 4.5V ≤ VDDP ≤ 5.5V P_5.1.4 Input high voltage VIH_extend – 0.52 x VDDP VDDP + 0.3 V 1) 2.6V ≤ VDDP ≤ 4.5V P_5.1.18 Output low voltage VOL – 1.0 V 3) 4) IOL ≤ IOLmax P_5.1.6 V 3) 5) IOL ≤ IOLnom P_5.1.7 IOH ≥ IOHmax P_5.1.8 IOH ≥ IOHnom P_5.1.9 Output low voltage VOL – – – 0.4 Output high voltage VOH VDDP - 1.0 – – V 3) 4) Output high voltage VOH VDDP - 0.4 – – V 3) 5) Input leakage current IOZ_extend1 -500 – +500 nA -40°C ≤ TJ ≤ 25°C, P_5.1.20 0.45 V < VIN < VDDP Input leakage current IOZ1 – +5 µA 6) Input leakage current IOZ_extend2 -15 – +15 µA 85°C < TJ ≤ 150°C, 0.45 V < VIN < VDDP P_5.1.11 Pull level keep current IPLK -200 – +200 µA 7) VPIN ≥ VIH (up) VPIN ≤ VIL (dn) P_5.1.12 Pull level force current IPLF -1.5 – +1.5 mA 7) VPIN ≤ VIL (up) VPIN ≥ VIH (dn) P_5.1.13 Pin capacitance CIO – – 10 pF 1) P_5.1.14 – 5 – µs 1) P_5.1.19 -5 25°C < TJ ≤ 85°C, P_5.1.10 0.45 V < VIN < VDDP Reset Pin Timing Reset Pin Input Filter Time tfilt_RESET 1) Not subject to production test, specified by design. 2) Tested at VDDP = 5V, specified for 4.5V < VDDP < 5.5V. 3) The maximum deliverable output current of a port driver depends on the selected output driver mode. The limit for pin groups must be respected. 4) Tested at 4.9V < VDDP < 5.1V, IOL = 4mA, IOH = -4mA, specified for 4.5V < VDDP < 5.5V. 5) As a rule, with decreasing output current the output levels approach the respective supply level (VOL→GND, VOH→VDDP). Tested at 4.9V < VDDP < 5.1V, IOL = 1mA, IOH = -1mA. Data Sheet 105 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 6) The given values are worst-case values. In production tests, this leakage current is only tested at 150°C; other values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 × e(1.5 + 0.028×TJ) [µA]. For example, at a temperature of 95°C the resulting leakage current is 3.2 µA. Leakage derating depending on voltage level (DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 × DV) [µA] This voltage derating formula is an approximation which applies for maximum temperature. 7) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN ≤ VIL for a pull-up; VPIN≥ VIH for a pull-down. These values apply to the fixed pull-devices in dedicated pins and to the user-selectable pull-devices in general purpose IO pins. Data Sheet 106 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.5.3 DC Parameters of Port 2 These parameters apply to the IO voltage range, 4.5 V ≤ VDDP ≤ 5.5 V. Note: Table 30 Operating Conditions apply. Keeping signal levels within the limits specified in this table ensures operation without overload conditions. For signal levels outside these specifications, also refer to the specification of the overload current IOV. DC Characteristics Port 2 VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Input low voltage VIL -0.3 – 0.3 x VDDP V 1) 4.5V ≤ VDDP ≤ 5.5V P_5.2.1 Input low voltage VIL_extend -0.3 0.42 x VDDP – V 2) 2.6V ≤ VDDP ≤ 4.5V P_5.2.10 Input high voltage VIH 0.7 x VDDP – VDDP + 0.3 V 1) 4.5V ≤ VDDP ≤ 5.5V P_5.2.2 Input high voltage VIH_extend – 0.52 x VDDP VDDP + 0.3 V 2) P_5.2.11 Input hysteresis HYSP2 – – V 2) Series P_5.2.3 resistance = 0 Ω; 4.5V ≤ VDDP ≤ 5.5V Input hysteresis HYSP2_ext – 0.09 x VDDP – V 2) Series P_5.2.12 resistance = 0 Ω; 2.6V ≤ VDDP < 4.5V 0.11 x VDDP end 2.6V ≤ VDDP ≤ 4.5V Input leakage current IOZ2 -400 – +400 nA TJ ≤ 85°C, 0 V < VIN < VDDP P_5.2.4 Pull level keep current IPLK -30 – +30 µA 3) VPIN ≥ VIH (up) VPIN ≤ VIL (dn) P_5.2.5 Pull level force current IPLF -750 – +750 µA 3) VPIN ≤ VIL (up) VPIN ≥ VIH (dn) P_5.2.6 Pin capacitance (digital inputs/outputs) CIO – – 10 pF 2) P_5.2.7 1) Tested at VDDP = 5V, specified for 4.5V < VDDP < 5.5V. 2) Not subject to production test, specified by design. 3) Keep current: Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level: VPIN ≥ VIH for a pull-up; VPIN ≤ VIL for a pull-down. Force current: Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device: VPIN ≤ VIL for a pull-up; VPIN≥ VIH for a pull-down. Data Sheet 107 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.6 LIN Transceiver 30.6.1 Electrical Characteristics Table 31 Electrical Characteristics LIN Transceiver Vs = 5.5V to 18V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number V SAE J2602 P_6.1.1 0.4 ×VS V LIN Spec 2.2 (Par. 17) P_6.1.2 0.47 x V 0.55 ×VS 0.6 ×VS V SAE J2602 P_6.1.3 1.15 ×VS V 1) LIN Spec 2.2 (Par. 18) P_6.1.4 0.525 × VS V 2) LIN Spec 2.2 (Par. 19) P_6.1.5 Min. Typ. Max. Bus Receiver Interface Receiver threshold voltage, recessive to dominant edge Vth_dom Receiver dominant state VBUSdom -27 Receiver threshold voltage, dominant to recessive edge Vth_rec Receiver recessive state VBUSrec Receiver center voltage VBUS_CNT 0.475 × VS Receiver hysteresis VHYS 0.07 VS 0.12 ×VS 0.175 × VS V 3) LIN Spec 2.2 (Par. 20) P_6.1.6 Wake-up threshold voltage VBUS,wk 0.4 ×VS 0.5 ×VS 0.6 ×VS V – P_6.1.7 Dominant time for bus wake-up (internal analog filter delay) tWK,bus 3 – 15 µs The overall dominant P_6.1.8 time for bus wake-up is a sum of tWK,bus + adjustable digital filter time. The digital filter time can be adjusted by PMU.CNF_WAKE_FILTE R.CNF_LIN_FT; Bus recessive output voltage VBUS,ro 0.8 ×VS – VS V VTxD = high Level P_6.1.9 Bus dominant output voltage VBUS,do – 0.22 ×VS V Driver Dominant Voltage RL = 500 Ohm P_6.1.78 0.4 ×VS 0.45 ×VS 0.53 x VS – S 0.6 ×VS – 0.5 ×VS Bus Transmitter Interface Data Sheet – 108 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 31 Electrical Characteristics LIN Transceiver (cont’d) Vs = 5.5V to 18V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Bus short circuit current Symbol IBUS,sc Bus short circuit filter time tBUS,sc Values Min. Typ. Max. Unit Note or Test Condition 40 100 150 mA Current Limitation for P_6.1.10 driver dominant state driver on VBUS = 18 V; LIN Spec 2.2 (Par. 12) – 5 – µs 6) The overall bus short P_6.1.71 circuit filter time is a sum of tBUS,sc + digital filter time. The digital filter time is 4 µs (typ.) -450 1000 µA VS = 12 V; 0 < VBUS < 18 V; P_6.1.11 LIN Spec 2.2 (Par. 15) 10 20 µA VS = 0 V; VBUS = 18 V; LIN Spec 2.2 (Par. 16) P_6.1.12 – – mA VS = 18 V; VBUS = 0 V; LIN Spec 2.2 (Par. 13) P_6.1.13 – 20 µA VS = 8 V; VBUS = 18 V; LIN Spec 2.2 (Par. 14) P_6.1.14 30 47 kΩ Normal mode LIN Spec P_6.1.15 2.2 (Par. 26) Leakage current (loss of ground) IBUS_NO_ -1000 GND Leakage current IBUS_NO_ – BAT Leakage current IBUS_PAS_ -1 dom Leakage current IBUS_PAS_ – rec Bus pull-up resistance RBUS 20 Number AC Characteristics - Transceiver Normal Slope Mode Propagation delay td(L),R bus dominant to RxD LOW 0.1 – 6 µs LIN Spec 2.2 (Param. 31) P_6.1.16 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 – 6 µs LIN Spec 2.2 (Param. 31) P_6.1.17 Receiver delay symmetry -2 – 2 µs tsym,R = td(L),R - td(H),R; LIN Spec 2.2 (Par. 32) P_6.1.18 0.396 – – tsym,R Duty cycle D1 tduty1 Normal Slope Mode (for worst case at 20 kbit/s) Data Sheet 109 4) P_6.1.19 duty cycle 1 THRec(max) = 0.744 ×VS; THDom(max) = 0.581 ×VS; VS = 5.5 … 18 V; tbit = 50 µs; D1 = tbus_rec(min)/2 tbit; LIN Spec 2.2 (Par. 27) Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 31 Electrical Characteristics LIN Transceiver (cont’d) Vs = 5.5V to 18V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol tduty2 Duty cycle D2 Normal Slope Mode (for worst case at 20 kbit/s) Values Min. Typ. Max. – – 0.581 Unit Note or Test Condition Number 4) P_6.1.20 duty cycle 2 THRec(min) = 0.422 ×VS; THDom(min) = 0.284 ×VS; VS = 5.5 … 18 V; tbit = 50 µs; D2 = tbus_rec(max)/2 tbit; LIN Spec 2.2 (Par. 28) AC Characteristics - Transceiver Low Slope Mode Propagation delay td(L),R bus dominant to RxD LOW 0.1 – 6 µs LIN Spec 2.2 (Param. 31) P_6.1.21 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 – 6 µs LIN Spec 2.2 (Param. 31) P_6.1.22 Receiver delay symmetry tsym,R -2 – 2 µs tsym,R = td(L),R - td(H),R; LIN Spec 2.2 (Par. 32) P_6.1.23 Duty cycle D3 (for worst case at 10.4 kbit/s) tduty1 0.417 – – P_6.1.24 duty cycle 3 THRec(max) = 0.778 ×VS; THDom(max) = 0.616 ×VS; VS = 5.5 … 18 V; tbit = 96 µs; D3 = tbus_rec(min)/2 tbit; LIN Spec 2.2 (Par. 29) Duty cycle D4 (for worst case at 10.4 kbit/s) tduty2 – – 0.590 4) 4) P_6.1.25 duty cycle 4 THRec(min) = 0.389 ×VS; THDom(min) = 0.251 ×VS; VS = 5.5 … 18 V; tbit = 96 µs; D4 = tbus_rec(max)/2 tbit; LIN Spec 2.2 (Par. 30) AC Characteristics - Transceiver Fast Slope Mode Propagation delay td(L),R bus dominant to RxD LOW 0.1 – 6 µs – P_6.1.26 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 – 6 µs – P_6.1.27 Receiver delay symmetry -1.5 – 1.5 µs tsym,R = td(L),R - td(H),R; P_6.1.28 Propagation delay td(L),R bus dominant to RxD LOW 0.1 – 6 µs – P_6.1.31 Propagation delay td(H),R bus recessive to RxD HIGH 0.1 – 6 µs – P_6.1.32 tsym,R AC Characteristics - Flash Mode Data Sheet 110 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 31 Electrical Characteristics LIN Transceiver (cont’d) Vs = 5.5V to 18V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Receiver delay symmetry Symbol tsym,R Values Min. Typ. Max. Unit Note or Test Condition -1.0 – 1.5 µs tsym,R = td(L),R - td(H),R; Number P_6.1.33 5) Duty cycle D7 (for worst case at 115 kbit/s) for +1 µs Receiver delay symmetry tduty1 0.399 – – duty cycle D7 P_6.1.34 THRec(max) = 0.744 ×VS; THDom(max) = 0.581 ×VS; VS = 13.5 V; tbit = 8.7 µs; D7 = tbus_rec(min)/2 tbit; Duty cycle D8 (for worst case at 115 kbit/s) for +1 µs Receiver delay symmetry tduty2 – – 0.578 5) LIN input capacity CLIN_IN – 15 30 pF 6) P_6.1.69 TxD dominant time out ttimeout 6 12 20 ms VTxD = 0 V P_6.1.36 P_6.1.35 duty cycle 8 THRec(min) = 0.422 ×VS; THDom(min) = 0.284 ×VS;VS = 13.5 V; tbit = 8.7 µs; D8 = tbus_rec(max)/2 tbit; Thermal Shutdown (Junction Temperature) Thermal shutdown temp. TjSD 190 200 215 °C 6) P_6.1.65 Thermal shutdown hyst. ∆T – 10 – K 6) P_6.1.66 1) 2) 3) 4) Maximum limit specified by design. VBUS_CNT = (Vth_dom +Vth rec)/2 VHYS = VBUSrec - VBUSdom Bus load concerning LIN Spec 2.2: Load 1 = 1 nF / 1 kΩ = CBUS / RBUS Load 2 = 6.8 nF / 660 Ω = CBUS / RBUS Load 3 = 10 nF / 500 Ω = CBUS / RBUS 5) Bus load Load 1 = 1 nF / 500 Ω = CBUS / RBUS 6) Not subject to production test, specified by design. Data Sheet 111 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.7 High-Speed Synchronous Serial Interface 30.7.1 SSC Timing Parameters The table below provides the SSC timing in the TLE9879-2QXA40. Table 32 SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. SCLK clock period 1) t0 Typ. 2 * TSSC – Unit Max. Note or Number Test Condition – 2) VDDP > 2.7 V P_7.1.1 VDDP > 2.7 V P_7.1.2 MTSR delay from SCLK t1 10 – – ns 2) MRST setup to SCLK t2 10 – – ns 2) VDDP > 2.7 V P_7.1.3 ns 2) VDDP > 2.7 V P_7.1.4 MRST hold from SCLK t3 15 – – 1) TSSCmin = TCPU = 1/fCPU. If fCPU = 20 MHz, t0 = 100 ns. TCPU is the CPU clock period. 2) Not subject to production test, specified by design. t0 SCLK1) t1 t1 MTSR1) t2 t3 Data valid MRST1) t1 1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_Tmg1 Figure 40 Data Sheet SSC Master Mode Timing 112 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.8 Measurement Unit 30.8.1 System Voltage Measurement Parameters Table 33 Supply Voltage Signal Conditioning VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Measurement output voltage range @ VAREF5 VA5 0 – 5 V – P_8.1.15 Measurement output voltage range @ VAREF1V2 VA1V2 0 – 1.23 V – P_8.1.16 ATTVS_1 – 0.055 – SFR setting 1 P_8.1.41 Nominal operating input VS,range1 voltage range VS 3 – 22 V 1) SFR setting 1; Max. value corresponds to typ. ADC full scale input; 3V < VS < 28V P_8.1.1 Accuracy of VS after calibration VS,range1 -220 – 220 mV SFR setting 1, VS = 5.5 V to 18V P_8.1.70 Input to output voltage attenuation: VS ATTVS_2 – 0.039 – SFR setting 2 P_8.1.42 Nominal operating input VS,range2 voltage range VS 3 – 31 V 1) P_8.1.40 Accuracy of VS after calibration -370 – 370 mV SFR setting 2, VS = 5.5V to P_8.1.44 18V – 0.039 – Nominal operating input VSD,range voltage range VSD 2.5 – 31 Accuracy of VSD sense after calibration -440 – 440 Battery / Supply Voltage Measurement Input to output voltage attenuation: VS VS,range2 SFR setting 2; Max. value corresponds to typ. ADC full scale input 3V < VS < 28V Driver Supply Voltage Measurement VSD Input to output voltage attenuation: VSD ATTVSD ∆VSD – P_8.1.21 V 1) P_8.1.2 mV VS = 5.5V to 18V P_8.1.47 Charge Pump Voltage Measurement VCP Data Sheet 113 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 33 Supply Voltage Signal Conditioning (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. – 0.023 – Nominal operating input VCP,range voltage range VCP 2.5 – 52 Accuracy of VCP sense after calibration -747 – 747 Input to output voltage attenuation: VCP ATTVCP ∆VCP Number – P_8.1.56 V 1) P_8.1.7 mV VS = 5.5V to 18V P_8.1.62 – P_8.1.49 Monitoring Input Voltage Measurement VMON Input to output voltage attenuation: VMON ATTVMON – 0.039 – Nominal operating input VMON,range voltage range VMON 2.5 – 31 V 1) P_8.1.8 Accuracy of VMON sense after calibration -440 – 440 mV VS = 5.5V to 18V P_8.1.68 – 0.164 – – P_8.1.33 Nominal operating input VDDP,range voltage range VDDP 0 – 7.50 V 1) P_8.1.50 Accuracy of VDDP sense after calibration -105 – 105 2) ∆VMON Pad Supply Voltage Measurement VVDDP Input-to-output voltage attenuation: VDDP ATTVDDP ∆VDDP_SENSE mV VS = 5.5 to 18V P_8.1.5 10-Bit ADC Reference Voltage Measurement VAREF Input to output voltage attenuation: VAREF ATTVAREF – 0.219 – – P_8.1.22 Nominal operating input VAREF,range voltage range VAREF 0 – 5.62 V 1) P_8.1.51 Accuracy of VAREF sense after calibration -79 – 79 VS = 5.5V to 18V P_8.1.48 ∆VAREF mV 8-Bit ADC Reference Voltage Measurement VBG Input-to-output voltage attenuation: VBG ATTVBG Nominal operating input VBG,range voltage range VBG Data Sheet – 0.75 – – P_8.1.57 0.8 – 1.64 V 1) P_8.1.52 114 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 33 Supply Voltage Signal Conditioning (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. 1.01 1.07 1.18 V – 0.75 – – P_8.1.34 Nominal operating input VDDC,range voltage range VDDC 0.8 – 1.64 V 1) P_8.1.53 Accuracy of VDDC sense after calibration -22 – 22 VS = 5.5 to 18V P_8.1.6 Value of ADC2-VBG measurement after calibration VBG_PMU P_8.1.73 Core supply Voltage Measurement VDDC Input-to-output voltage attenuation: VDDC ATTVDDC ∆VDDC_SENSE mV VDH Input Voltage Measurement VVDH10BITADC VDH Input to output voltage attenuation: ATTVDH_1 – 0.166 – SFR setting 1 P_8.1.64 VDH Input to output voltage attenuation: ATTVDH_2 – 0.224 – SFR setting 2 P_8.1.65 VDH Input to output voltage attenuation: ATTVDH_3 - 0.226 - 1) SFR setting 2 Tj = -40..85°C P_8.1.75 Nominal operating input VVDH,range1 voltage range VVDH, Range 1 – – 30 SFR setting 1 P_8.1.66 Nominal operating input VVDH,range2 voltage range VVDH, Range 2 – – 20 SFR setting 2 P_8.1.67 VVDH 10-bit ADC, Range 1 ∆VVDHADC10B -300 – 300 mV VDH= 5.5 to 17.5V, Tj = -40..150°C P_8.1.39 VVDH 10-bit ADC, Range 3 ∆VVDHADC10B -200 – 200 mV 1) VDH= 5.5V to 17.5V, Tj = -40..85°C ATTVDH_3 P_8.1.71 VVDH 10-bit ADC, Range 2 ∆VVDHADC10B_ext -400 – 400 mV VDH= 5.5V to 17.5V, Tj = -40..150°C P_8.1.74 390 470 kΩ PD_N=1 (on-state) P_8.1.3 2.0 µA PD_N=0 (off-state), P_8.1.10 end_T 10-Bit ADC measurement Rin_VDH,measure input resistance for VDH Measurement input leakage current for VVDH 200 Ileak_VDH, measure -0.05 – 1) Not subject to production test, specified by design. 2) Accuracy is valid for a calibrated device. Data Sheet 115 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.8.2 Table 34 Central Temperature Sensor Parameters Electrical Characteristics Temperature Sensor Module VS = 3.0 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. a – 0.666 – V 1) Temperature sensitivity b b – 2.31 – mV/K 1) Accuracy_1 -10 – 10 °C 2)1) -40°C < Tj < 85°C P_8.2.5 °C 2)1) 125°C < Tj < 150°C P_8.2.6 °C 2)1) 85°C < Tj < 125°C P_8.2.7 Output voltage VTEMP at T0=273 K (0°C) Accuracy_2 Accuracy_3 Acc_1 Acc_2 Acc_3 -10 -5 – – 10 5 T0=273 K (0°C) P_8.2.2 P_8.2.4 1) Not subject to production test, specified by design 2) Accuracy with reference to on-chip temperature calibration measurement, valid for Mode1 Data Sheet 116 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.8.3 ADC2-VBG 30.8.3.1 ADC2 Reference Voltage VBG Table 35 DC Specifications VS = 3.0 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Reference Voltage VBG Values Min. Typ. Max. 1.199 1.211 1.223 Unit Note or Test Condition Number V 1) P_8.3.1 1) Not subject to production test, specified by design 30.8.3.2 ADC2 Specifications Table 36 DC Specifications VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. – 8 – Bits Full P_8.3.18 ±0.3 2.0 LSB not calibrated P_8.3.19 ±0.5 2.0 %FSR not calibrated P_8.3.20 Differential non-linearity EADNL_8Bi -0.8 (DNL) t ±0 0.8 LSB Full P_8.3.21 EAINL_8Bit -1.2 ±0 1.2 LSB – P_8.3.22 Resolution RES Guaranteed offset error EAOFF_8Bi -2.0 t Gain error EAGain_8B -2.0 it Integral non-linearity (INL) Data Sheet 117 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.9 ADC1 Reference Voltage - VAREF 30.9.1 Electrical Characteristics VAREF Table 37 Electrical Characteristics VAREF VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Required buffer capacitance Symbol CVAREF Reference output voltage VAREF Values Unit Note or Test Condition Number Min. Typ. Max. 0.1 – 1 µF ESR < 1Ω P_9.1.1 4.95 5 5.05 V VS > 5.5V P_9.1.2 P_9.1.3 DC supply voltage rejection DCPSRVAREF 30 – – dB 1) Supply voltage ripple rejection ACPSRVAREF 26 – – dB 1) VS = 13.5V; f = 0 ... 1KHz; Vr = 2Vpp P_9.1.4 Turn ON time tso – – 200 µs 1) Cext = 100nF PD_N to 99.9% of final value P_9.1.5 – 100 – kΩ 1) P_9.1.20 Input resistance at VAREF RIN,VAREF Pin – input impedance in case of VAREF is applied from external 1) Not subject to production test, specified by design. Data Sheet 118 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.9.2 Electrical Characteristics ADC1 (10-Bit) These parameters describe the conditions for optimum ADC performance. Note: Table 38 Operating Conditions apply. A/D Converter Characteristics VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Number Test Condition Min. Typ. Max. Analog reference supply VAREF VAGND + 1.0 – VDDPA + 0.05 V 1) P_9.2.1 Analog reference ground VAGND VSS - 0.05 – 1.5 V – P_9.2.2 Analog input voltage range VAIN VAGND – VAREF V 2) P_9.2.3 Analog clock frequency fADCI 5 – 24 MHz 3) P_9.2.4 Conversion time for 10- tC10 bit result (13 + STC) (13 + STC) (13 + STC) – × tADCI × tADCI × tADCI + 2 x tSYS + 2 x tSYS + 2 x tSYS 1)4) P_9.2.5 Conversion time for 8bit result (11 + STC) (11 + STC) (11 + STC) – × tADCI × tADCI × tADCI + 2 × tSYS + 2 × tSYS + 2 × tSYS 1) P_9.2.6 Wakeup time from tWAF analog powerdown, fast mode – – 4 µs 1) P_9.2.7 Wakeup time from analog powerdown, slow mode tWAS – – 15 µs 1)5) P_9.2.8 Total unadjusted error (8 bit) TUE8B -2 ±1 +2 counts 6)7) Reference is internal VAREF P_9.2.9 Total unadjusted error (10 bit) TUE10B -12 ±6 +12 counts 7)8) P_9.2.22 DNL error EADNL -3 ±0.8 +3 counts – P_9.2.10 INL error EAINL_int_V -5 ±0.8 +5 counts Reference is internal VAREF P_9.2.11 ±0.4 +10 counts Reference is internal VAREF P_9.2.12 ±0.5 +2 counts – P_9.2.13 tC8 AREF Gain error EAGAIN_int_ -10 VAREF Offset error EAOFF -2 Reference is internal VAREF Total capacitance of an analog input CAINT – – 10 pF 1)5)9) Switched capacitance of an analog input CAINS – – 4 pF 1)5)9) Data Sheet 119 P_9.2.14 P_9.2.15 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 38 A/D Converter Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Number Test Condition Resistance of the analog input path RAIN – – 2 kΩ 1)5)9) P_9.2.16 Total capacitance of the reference input CAREFT – – 15 pF 1)5)9) P_9.2.17 Switched capacitance of the reference input CAREFS – – 7 pF 1)5)9) P_9.2.18 – – 2 kΩ 1)5)9) P_9.2.19 Resistance of RAREF the reference input path 1) Not subject to production test, specified by design. 2) VAIN may exceed VAGND or VAREFx up to the absolute maximum ratings. However, the conversion result in these cases will be 0000H or 03FFH, respectively. 3) The limit values for fADCI must not be exceeded when selecting the peripheral frequency and the prescaler setting. 4) This parameter includes the sample time (also the additional sample time specified by STC), the time to determine the digital result and the time to load the result register with the conversion result. 5) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 500 µs. 6) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual errors. All error specifications are based on measurement methods standardized by IEEE 1241.2000. 7) The specified TUE is valid only if the absolute sum of input overload currents (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the measurement time. 8) The total unadjusted error TUE is the maximum deviation from the ideal ADC transfer curve, not the sum of individual errors. All error specifications are based on measurement methods standardized by IEEE 1241.2000. 9) These parameter values cover the complete operating range. Under relaxed operating conditions (temperature, supply voltage) typical values can be used for calculation. At room temperature and nominal supply voltage the following typical values can be used: CAINTtyp = 12 pF, CAINStyp = 5 pF, RAINtyp = 1.0 kΩ, CAREFTtyp = 15 pF, CAREFStyp = 10 pF, RAREFtyp = 1.0 kΩ. Data Sheet 120 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.10 14-Bit Sigma Delta ADC (ADC3 / ADC4) 30.10.1 Analog/Digital Converter Parameters These parameters describe the conditions for optimum ADC performance. Note: Operating Conditions apply. Table 39 A/D Converter ADC3/4 Characteristics VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Analog clock frequency Symbol fADC3/4 Values Min. Typ. Max. Unit Note or Test Condition 5 – 20 MHz Number P_10.1.20 1) P_10.1.1 2) P_10.1.2 Single ended input capacitance Cin1 – 2 – Oversampling ratio OSR 128 – 2048 ADC full scale voltage (differential) VFs 3.75 – – V at VDIFF = ±VFS, P_10.1.3 DD.max resp. DD.min is reached Input voltage Vin 0 – VREF V P_10.1.21 input voltage on ADCx.P or ADCx.N VREF can be VAREF or VREF5V x={3,4} Differential non-linear input voltage Vdiff,nonlin -4.0 – 4.0 V 2) Vdiff = VADCx.P-VADCx.N VADCx.P, VADCx.P within Vin range x={3,4} P_10.1.4 Differential linear input voltage Vdiff,lin -3.75 – 3.75 V 2) P_10.1.6 Input common mode range Vin,com 0.48 × VREF – 0.52 × VREF V VREF can be VAREF or P_10.1.7 VREF5V Input frequency fin 0 – 1 kHz 2) RMS noise Vrms – 0.69 1.15 mV tested with OSR=128 P_10.1.22 and VREF = VREF5V Effective resolution RESeff 11.7 12.4 bit calculated, RESeff = ld(VFs / VRMS) P_10.1.23 Effective number of bits ENOB 11.7 bit 2) P_10.1.24 Data Sheet 121 pF decimation factor 2) Vdiff = VADCx.P-VADCx.N VADCx.P, VADCx.P within Vin range x={3,4} ENOB=(SNDR1.76dB)/6.02dB P_10.1.8 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 39 A/D Converter ADC3/4 Characteristics (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Min. Typ. Max. Unit Note or Test Condition – 72 – dB 2) P_10.1.10 Digital filtered data of raw DD ADC values -16384 – 16383 LSB 2) represented in two's complement DD = (Vdiff/VREF) * ATTadc34 * (214 - 1) P_10.1.13 ADC34 input attenuator – 4/3 – kΩ 2) P_10.1.15 – P_10.1.17 – P_10.1.18 SNDR with a fully differential sinus -6dBFS Symbol SNDR ATTadc34 Values Dynamic input impedance ZIN – 250 – ADC Gain Ratio GADC3 / GADC4 0.990 1 1.010 ADC Offset Drift OFFADC3/4 – 5.4 – Number P_10.1.25 mV 1) In addition to pin capacitance CIO, see P_5.2.7. 2) Not subject to production test, specified by design. Data Sheet 122 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.11 High-Voltage Monitoring Input 30.11.1 Electrical Characteristics Table 40 Electrical Characteristics Monitoring Input Tj = -40°C to +150°C; VS = 5.5 V to 28 V, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. 0.4*VS 0.5*VS 0.6*VS MON Input Pin characteristics Wake-up/monitoring threshold voltage VMONth V Without external serial resistor Rs (with Rs:DV = IPD/PU * Rs); VS = 5.5V to 18V P_11.1.1 Wake-up/monitoring threshold voltage extended range VMONth_ext 0.44*VS 0.53*VS 0.64*VS V Without external serial resistor Rs (with Rs:DV = IPD/PU * Rs) P_11.1.11 Threshold hysteresis VMONth,hys 0.015* 0.05* VS VS 0.1*VS Threshold hysteresis VMONth,hys 0.02*VS 0.06* VS 0.12*VS V In all modes; without P_11.1.2 external serial resistor Rs (with Rs:dV = IPD/PU * Rs); VS = 18V to 28V; Pull-up current IPU, MON -20 -10 -1 µA 0.6*VS P_11.1.3 Pull-down current IPD, MON 3 10 20 µA 0.4*VS P_11.1.4 P_11.1.5 Input leakage current end V In all modes; without P_11.1.12 external serial resistor Rs (with Rs:dV = IPD/PU * Rs); VS = 5.5V to 18V; ILK,MON -2.5 – 2.5 µA 1) tFT,MON – 500 – ns 2) 0 V < VMON_IN < 28 V Timing Wake-up filter time (internal analog filter delay) The overall filter time P_11.1.6 for MON wake-up is a sum of tFT,MON + adjustable digital filter time. The digital filter time can be adjusted by PMU.CNF_WAKE_FILTER .CNF_MON_FT; 1) Input leakage is valid for disabled state. 2) With pull-up, pull down current disabled. Data Sheet 123 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.12 MOSFET Driver 30.12.1 Electrical Characteristics Table 41 Electrical Characteristics MOSFET Driver VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Maximum total charge driver Qtot_max capability – – 100 nC 1) Source current - Charge current - High Side Driver ISoumax_HS 230 345 450 mA VSD ≥ 8 V, CLoad = 10 nF, ISou P_12.1.78 = CLoad * slew rate ( = 20%50% of VGHx1), ICHARGE = IDISCHG = 31(max) Sink current - Discharge current-High Side Driver ISinkmax_HS 230 330 450 mA VSD ≥ 8 V, CLoad = 10 nF, ISink P_12.1.79 = CLoad * slew rate ( = 50%20% of VGHx1), ICHARGE = IDISCHG = 31(max) Source current - Charge current - Low Side Driver ISoumax_LS 200 295 375 mA VSD ≥ 8 V, CLoad = 10 nF, ISou P_12.1.80 = CLoad * slew rate ( = 20%50% of VGLx1), ICHARGE = IDISCHG = 31(max) Sink current - Discharge current-Low Side Driver ISinkmax_LS 200 314 375 mA VSD ≥ 8 V, CLoad = 10 nF, ISink P_12.1.81 = CLoad * slew rate ( = 50%20% of VGHx1), ICHARGE = IDISCHG = 31(max) High level output voltage Gxx vs. Sxx VGxx1 10 – 14 V VSD ≥ 8V, CLoad = 10 nF, ICP=2.5 mA2). High level output voltage GHx vs. SHx VGxx2 8 – – V VSD = 6.4 V1), CLoad = 10 nF, P_12.1.4 ICP=2.5 mA2) High level output voltage GHx vs. SHx VGxx3 7 – – V VSD = 5.4 V, CLoad = 10 nF, ICP=2.5 mA2) High level output voltage GLx vs. GND VGxx6 8 – – V VSD = 6.4 V1), CLoad = 10 nF, P_12.1.6 ICP=2.5 mA2) MOSFET Driver Output Data Sheet 124 P_12.1.20 Due to Charge Pump currrent capability only 3 x MOSFETs + additional external capacitors with a total charge of max. 100nC can be driven simultaneous at a PWM frequency of 25 kHz. P_12.1.3 P_12.1.5 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 41 Electrical Characteristics MOSFET Driver (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number High level output voltage GLx vs. GND VGxx7 7 – – V VSD = 5.4 V, CLoad = 10 nF, ICP=2.5 mA2) P_12.1.7 Rise time trise3_3nf – 200 – ns 1) CLoad = 3.3 nF, VSD ≥ 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 31(max) P_12.1.8 Fall time tfall3_3nf – 200 – ns 1) CLoad = 3.3 nF, VSD ≥ 8 V, 75-25% of VGxx1, ICHARGE = IDISCHG = 31(max) P_12.1.9 Rise time trisemax 100 250 450 ns CLoad = 10 nF, VSD ≥ 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 31(max) P_12.1.57 Fall time tfallmax 100 250 450 ns CLoad = 10 nF, VSD ≥ 8 V, 75-25% of VGxx1, ICHARGE = IDISCHG = 31(max) P_12.1.58 Rise time trisemin 1.25 2.5 5 µs 1) CLoad = 10 nF, VSD ≥ 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 3(min) P_12.1.14 Fall time tfallmin 1.25 2.5 5 µs 1) CLoad = 10 nF, VSD ≥ 8 V, 75-25% of VGxx1, ICHARGE = IDISCHG = 3(min) P_12.1.15 Absolute rise - fall time difference for all LSx tr_f(diff)LSx – – 100 ns CLoad = 10 nF, VSD ≥ 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 31(max) P_12.1.35 Absolute rise - fall time difference for all HSx tr_f(diff)HSx – – 100 ns CLoad = 10 nF, VSD ≥ 8 V, 25-75% of VGxx1, ICHARGE = IDISCHG = 31(max) P_12.1.36 Resistor between GHx/GLx and GND RGGND 30 40 50 kΩ 1) P_12.1.11 Data Sheet 125 – Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 41 Electrical Characteristics MOSFET Driver (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number 1)3) Resistor between SHx and GND RSHGN 30 40 50 kΩ This resistance is the P_12.1.10 resistance between GHx and GND connected through a diode to SHx. As a consequence, the voltage at SHx can rise up to 0,6V typ. before it is discharged through the resistor. Low RDSON mode (boosted discharge mode) RONCCP – 9 12 Ω P_12.1.50 VVSD = 13.5 V, VVCP = VVSD + 14.0 V; ICHARGE = IDISCHG = 31(max); 50mA forced into Gx, Sx grounded Resistance between VDH and VSD IBSH – 4 – kΩ 1) P_12.1.24 Input propagation time (LS on) tP(ILN)min – 1.5 3 µs 1) CLoad = 10 nF, ICharge =3(min), 25% of VGxx1 P_12.1.37 Input propagation time (LS off) tP(ILF)min – 1.5 3 µs 1) CLoad = 10 nF, IDischarge =3(min), 75% of VGxx1 P_12.1.38 Input propagation time (HS tP(IHN)min on) – 1.5 3 µs 1) CLoad = 10 nF, ICharge =3(min) 25% of VGxx1 P_12.1.39 Input propagation time (HS tP(IHF)min off) – 1.5 3 µs 1) CLoad = 10 nF, IDisharge =3(min), 75% of VGxx1 P_12.1.40 Input propagation time (LS on) tP(ILN)max – 200 350 ns CLoad = 10 nF, ICharge =31(max), 25% of VGxx1 P_12.1.26 Input propagation time (LS off) tP(ILF)max – 200 300 ns CLoad = 10 nF, IDischarge =31(max), 75% of VGxx1 P_12.1.27 Input propagation time (HS tP(IHN)max on) – 200 350 ns CLoad = 10 nF, ICharge =31(max), 25% of VGxx1 P_12.1.28 Input propagation time (HS tP(IHF)max off) – 200 300 ns CLoad = 10 nF, IDischarge =31(max), 75% of VGxx1 P_12.1.29 Data Sheet 126 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 41 Electrical Characteristics MOSFET Driver (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Absolute input propagation tPon(diff)LSx time difference between propagation times for all LSx (LSx on) – – 100 ns CLoad = 10 nF, ICharge =31(max), 25% of VGxx1 P_12.1.30 Absolute input propagation tPoff(diff)LSx time difference between propagation times for all LSx (LSx off) – – 100 ns CLoad = 10 nF, IDischarge =31(max), 75% of VGxx1 P_12.1.41 Absolute input propagation tPon(diff)HSx time difference between propagation times for all HSx (HSx on) – – 100 ns CLoad = 10 nF, ICharge =31(max), 25% of VGxx1 P_12.1.42 Absolute input propagation tPoff(diff)HSx time difference between propagation times for all HSx (HSx off) – – 100 ns CLoad = 10 nF, IDischarge =31(max), 75% of VGxx1 P_12.1.43 – – – V 0.07 0.35 0.55 0.65 0.90 1.00 1.20 1.40 0.25 0.50 0.75 1.00 1.25 1.5 1.75 2.00 0.40 0.650 0.90 1.25 1.45 1.80 2.10 2.40 DRV_CTRL3.DSMONVTH< P_12.1.46 2:0> xxx 000 001 010 011 100 101 110 111 -220 -370 -520 µA IDISCHG = 1; VSHx = 5.0 V P_12.1.47 650 900 1100 µA IDISCHG = 1; VSHx = 5.0 V P_12.1.48 Drain source monitoring Drain source monitoring threshold VDSMONVTH Open load diagnosis currents Pull-up diagnosis current IPUDiag Pull-down diagnosis current IPDDiag Charge pump Output voltage VCP vs. VSD VCPmin1 8.5 – – V VVSD = 5.4V, ICP=5 mA, CCP1, CCP2 = 220 nF, Bridge Driver enabled P_12.1.53 Regulated output voltage VCP vs. VSD VCP 12 14 16 V 8 V ≤ VVSD ≤ 28, ICP=10mA, CCP1, CCP2=220 nF, fCP=250kHz P_12.1.49 Data Sheet 127 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 41 Electrical Characteristics MOSFET Driver (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Turn ON Time tON_VCP 10 24 40 us 8 V ≤ VVSD ≤ 28, ICP=2.5mA, (25%) of VCP1)4), CCP1, CCP2=220 nF, fCP=250kHz P_12.1.59 Rise time trise_VCP 20 60 88 us 8 V ≤ VVSD ≤ 28, ICP=2.5mA, (25-75%) of VCP1)5), CCP1, CCP2=220 nF, fCP=250kHz P_12.1.60 1) Not subject to production test. 2) The condition ICP = 2,5 mA emulates an BLDC Driver with 6 MOSFET switching at 20 KHz with a CLoad=3.3nF. Test condition: IGx = - 100 µA, ICHARGE = IDISCHARGE = 31(max), IDISCHARGEDIV2_N = 1 and ICHARGEDIV2_N = 1. 3) This resistance is connected through a diode between SHx and GHx to ground. 4) This time applies when Bit DRV_CP_CTRL_STS.bit.CP_EN is set 5) This time applies when Bit DRV_CP_CLK_CTRL.bit.CPCLK_EN is set Data Sheet 128 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics 30.13 Operational Amplifier 30.13.1 Electrical Characteristics Table 42 Electrical Characteristics Operational Amplifier VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Differential gain (uncalibrated) Symbol Values Unit Min. Typ. Max. 9.5 19 38 57 10 20 40 60 10.5 21 42 63 Note or Test Condition Number Gain settings GAIN: P_13.1.6 00 01 10 11 G Differential input operating VIX voltage range OP2 - OP1 -1.5 / G – 1.5 / G V G is the Gain specified below Operating. common mode VCM input voltage range (referred to GND (OP2 GND) or (OP1 - GND) -2.0 – 2.0 V Input common mode has P_13.1.2 to be checked in evaluation if it fits the required range Max. input voltage range (referred to GND (OP_2 GND) or (OP1 - GND) VIX_max -7.0 – 7.0 V Max. rating of operational amplifier inputs, where measurement is not done P_13.1.3 Single ended output voltage range (linear range) VOUT VZERO - 1.5 – VZERO + 1.5 V 1)2) typ. output offset voltage 2 V ± 1.5V P_13.1.4 Linearity error EPWM -15 – 15 mV P_13.1.5 Maximum deviation from best fit straight line divided by max. value of differential output voltage range (0.5V 3.5V); this parameter is determined at G = 10. Linearity error EPWM_% -1.0 – 1.0 % P_13.1.24 Maximum deviation from best fit straight line divided by max. value of differential output voltage range (0.5V 3.5V); this parameter is determined at G = 10. -1 – 1 % Gain drift after calibration at G = 10. Gain drift Data Sheet 129 P_13.1.1 P_13.1.7 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Electrical Characteristics Table 42 Electrical Characteristics Operational Amplifier (cont’d) VS = 5.5 V to 28 V, Tj = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. -40 10 40 mV VAIP= VAIN = 0 V and G = 40. P_13.1.17 DC input voltage common DCmode rejection ratio CMRR 58 80 – dB CMRR (in dB)=-20*log (differential mode gain/ common mode gain) VCMI= -2V... 2V, VAIP-VAIN=0V P_13.1.8 Settling time to 98% TSET – 800 1400 ns Derived from 80 - 20 % P_13.1.9 rise fall times for ± 2V overload condition (3 Tau value of settling time constant)2) Current Sense Amplifier Input Resistance @ OP1, OP2 Rin_OP1_ 1 1.25 1.5 kΩ 2) Adjusted output offset voltage VOOS – P_13.1.25 OP2 1) Typical VZERO = 0,4 * VAREF. 2) This parameter is not subject to production test. Data Sheet 130 Rev. 1.0 2018-01-16 TLE9879-2QXA40 Package Outlines Package Outlines 0. 13 ± +0.03 1) 0.4 x 45° Index Marking C 36 25 0.15 ±0.05 0.1 ±0.05 24 SEATING PLANE 7 ±0.1 6.8 48x 0.08 48 13 1 12 (0 (0.2) 2) 37 .3 5) 0.23 ±0.05 (5.2) 0.05 MAX. 1) Vertical burr 0.03 max., all sides 2) These four metal areas have exposed diepad potential Figure 41 0.5 0.5 ±0.07 0.1±0.03 B 26 0. 6.8 11 x 0.5 = 5.5 (6) A (5.2) 7 ±0.1 0.9 MAX. (0.65) 0. 05 31 Index Marking 48x 0.1 M A B C (6) PG-VQFN-48-29, -31-PO V05 Package outline VQFN-48-31 (with LTI) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 131 Dimensions in mm Rev. 1.0 2018-01-16 TLE9879-2QXA40 Revision History 32 Revision History Revision History Page or Item Subjects (major changes since previous revision) Rev. 1.0, 2018-01-16 all Data Sheet Initial Release. 132 Rev. 1.0 2018-01-16 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2018-01-16 Published by Infineon Technologies AG 81726 Munich, Germany © 2018 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.