TLS205B0LDV50XUMA1

TLS205B0 V50 Linear Voltage Post Regulator Low Dropout, Low Noise, 5 V, 500 mA TLS205B0EJV50 TLS205B0LDV50 Data Sheet Rev. 1.1, 2015-01-15 Automotive Power Linear Voltage Post Regulator Low Dropout, Low Noise, 5 V, 500 mA 1 TLS205B0EJV50 TLS205B0LDV50 Overview Features • • • • • • • • • • • • • • • • • • • Low Noise down to 42 µVRMS (BW = 10 Hz to 100 kHz) 500 mA Current Capability Low Quiescent Current: 30 µA Wide Input Voltage Range up to 20 V Internal circuitry working down to 2.3 V 2.5% Output Voltage Accuracy (over full temperature and load range) Low Dropout Voltage: 350 mV Very low Shutdown Current: < 1 µA No Protection Diodes needed Fixed Output Voltage: 5.0 V Stable with ≥ 3.3 µF Output Capacitor Stable with Aluminium, Tantalum or Ceramic Output Capacitors Reverse Polarity Protection No Reverse Current Overcurrent and Overtemperature Protected PG-DSO-8 Exposed Pad and PG-TSON-10 Exposed Pad Package Suitable for use in Automotive Electronics as Post Regulator Green Product (RoHS compliant) AEC Qualified PG-DSO-8 Exposed Pad PG-TSON-10 The TLS205B0 V50 is a micropower, low noise, low dropout voltage 5 V regulator. The device is capable of supplying an output current of 500 mA with a dropout voltage of 350 mV. Designed for use in battery-powered systems, the low quiescent current of 30 µA makes it an ideal choice. A key feature of the TLS205B0 V50 is its low output noise. By adding an external 10 nF bypass capacitor output noise values down to 42 µVRMS over a 10 Hz to 100 kHz bandwidth can be reached. The TLS205B0 V50 voltage regulator is stable with output capacitors as small as 3.3 µF. Small ceramic capacitors can be used without the series resistance required by many other linear voltage regulators. Internal protection circuitry includes reverse battery protection, current limiting and reverse current protection. The TLS205B0 V50 comes as 5.0 V fixed output voltage variant and is available in a PG-DSO-8 Exposed Pad as well as in a PG-TSON-10 Exposed Pad package. Type Package Marking TLS205B0EJV50 PG-DSO-8 Exposed Pad 205B0V50 TLS205B0LDV50 PG-TSON-10 205B0V5 Data Sheet 2 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Block Diagram 2 Block Diagram Note: Pin numbers in block diagrams refer to the PG-DSO-8 Exposed Pad package type. Saturation Control TLS205B0 I 8 1 EN 5 Bias BYP 4 Voltage reference Over Current Protection Q Temperature Protection Error Amplifier 2 SENSE 6 GND Figure 1 Data Sheet Block Diagram TLS205B0 V50 3 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment Q 1 8 I SENSE 2 7 NC NC 3 6 GND 5 EN 9 BYP 4 TLS205B0EJV50 Figure 2 Pin Configuration of TLS205B0EJV50 in PG-DSO-8 Exposed Pad Q Q NC SENSE BYP 1 2 3 4 5 11 10 9 8 7 6 I I NC EN GND TLS205B0LDV50 Figure 3 Data Sheet Pin Configuration of TLS205B0LDV50 in PG-TSON-10 4 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Pin Configuration 3.2 Pin Definitions and Functions Pin Symbol Function 1 (DSO-8 EP) 1,2 (TSON-10) Q Output. Supplies power to the load. For this pin a minimum output capacitor of 3.3 µF is required to prevent oscillations. Larger output capacitors may be required for applications with large transient loads in order to limit peak voltage transients or when the regulator is applied in conjunction with a bypass capacitor. For more details please refer to “Application Information” on Page 19. 2 (DSO-8 EP) 4 (TSON-10) SENSE Output Sense. The SENSE pin is the input to the error amplifier. This allows to achieve an optimized regulation performance in case of small voltage drops Rp that occur between regulator and load. In applications where such drops are relevant they can be eliminated by connecting the SENSE pin directly at the load. In standard configuration the SENSE pin can be directly connected to Q. For further details please refer to the section “Kelvin Sense Connection” on Page 19. 3, 7 (DSO-8 EP) NC 3, 8 (TSON-10) No Connect. The NC Pins have no connection to any internal circuitry. Connect either to GND or leave open. 4 (DSO-8 EP) 5 (TSON-10) BYP Bypass. The BYP pin is used to bypass the reference of the TLS205B0 V50 to achieve low noise performance. The BYP-pin is clamped internally to ±0.6 V (i.e. one VBE). A small capacitor from the output Q to the BYP pin will bypass the reference to lower the output voltage noise 1). If not used this pin must be left unconnected. 5 (DSO-8 EP) 7 (TSON-10) EN Enable. With the EN pin the TLS205B0 V50 can be put into a low power shutdown state. The output will be off when the EN is pulled low. The EN pin can be driven either by 3.3 V or 5 V logic or as well by open-collector logic with pull-up resistor. The pull-up resistor is required to supply the pull-up current of the open-collector gate 2) and the EN pin current 3). Please note that if the EN pin is not used it must be connected to VI. It must not be left floating. 6 (DSO-8 EP) 6,(TSON-10) GND Ground. 8 (DSO-8 EP) I 9, 10 (TSON-10) Input. The device is supplied by the input pin I. A capacitor at the input pin is required if the device is more than 6 inches away from the main input filter capacitor or if a non-negligible inductance is present at the input I 4). The TLS205B0 V50 is designed to withstand reverse voltages on the input pin I with respect to GND and output Q. In the case of reverse input (e.g. due to a wrongly attached battery) the device will act as if there is a diode in series with its input. In this way there will be no reverse current flowing into the regulator and no reverse voltage will appear at the load. Hence, the device will protect both - the device itself and the load. 9 (DSO-8 EP) 11 (TSON-10) Exposed Pad. To ensure proper thermal performance, solder Pin 11 of TSON-10 to the PCB ground and tie directly to Pin 6. In the case of DSO-8 EP as well solder Pin 9 (exposed pad) to the PCB ground and tie directly to Pin 6 (GND). 1) 2) 3) 4) Tab A maximum value of 10 nF can be used for reducing output voltage noise over the bandwidth from 10 Hz to 100 kHz. Normally several microamperes. Typical value is 1 µA. In general the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in batterypowered circuits. Depending on actual conditions an input capacitor in the range of 1 to 10 µF is sufficient. Data Sheet 5 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 1 Absolute Maximum Ratings 1) Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Number Test Condition Min. Typ. Max. VI -20 – 20 V – P_4.1.1 VQ VI - VQ -20 – 20 V – P_4.1.2 -20 – 20 V – P_4.1.3 VSENSE -20 – 20 V – P_4.1.4 VBYP -0.6 – 0.6 V VEN -20 – 20 V – P_4.1.6 Tj Tstg -40 – 150 °C – P_4.1.7 -55 – 150 °C – P_4.1.8 VESD VESD -2 – 2 kV HBM 2) kV 3) Input Voltage Voltage Output Voltage Voltage Input to Output Differential Voltage Sense Pin Voltage BYP Pin Voltage P_4.1.5 Enable Pin Voltage Temperatures Junction Temperature Storage Temperature ESD Susceptibility All Pins All Pins -1 – 1 CDM P_4.1.9 P_4.1.10 1) Not subject to production testing, specified by design. 2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) 3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101 Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 6 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 General Product Characteristics 4.2 Functional Range Table 2 Functional Range Parameter Symbol VI Output Capacitor’s Requirements CQ Input Voltage Range Values Min. Typ. Max. 5.5 – 20 Unit Note / Test Condition Number V – P_4.2.1 1) 3.3 – – µF CBYP = 0 nF Output Capacitor’s Requirements CQ for Stability 6.8 – – µF 0 nF < CBYP ≤ 10 nF 1) P_4.2.3 ESR Operating Junction Temperature Tj – 2) – 3 Ω – 1) P_4.2.4 -40 – 125 °C – P_4.2.5 P_4.2.2 for Stability ESR 1) for further details see corresponding graph. 2) CBYP = 0 nF, CQ ≥ 3.3 µF; please note that for cases where a bypass capacitor at BYP is used – depending on the actual applied capacitance of CQ and CBYP a minimum requirement for ESR of CQ may apply. Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. 4.3 Thermal Resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 3 Thermal Resistance 1) Parameter Symbol Values Unit Note / Test Condition Number K/W – P_4.3.1 Min. Typ. Max. – 7.0 – Junction to Ambient RthJC RthJA RthJA RthJA – 66 – Junction to Ambient RthJA – 52 – 6.4 Junction to Ambient RthJC RthJA RthJA RthJA – 69 – K/W 300 mm heatsink area on PCB 3) P_4.3.9 Junction to Ambient RthJA – 57 – K/W 600 mm2 heatsink area on PCB 3) P_4.3.10 TLS205B0EJV50 (PG-DSO-8 Exposed Pad) Junction to Case Junction to Ambient Junction to Ambient – – 39 155 – – K/W K/W – 2) P_4.3.2 Footprint only 3) P_4.3.3 K/W 2 300 mm heatsink area on PCB 3) P_4.3.4 – K/W 600 mm2 heatsink area on PCB 3) P_4.3.5 – K/W – P_4.3.6 TLS205B0LDV50 (PG-TSON-10) Junction to Case Junction to Ambient Junction to Ambient – – 53 183 – – K/W K/W – 2) P_4.3.7 Footprint only 3) 2 P_4.3.8 1) Not subject to production test, specified by design. Data Sheet 7 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 General Product Characteristics 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70 µm Cu). Data Sheet 8 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics 5 Electrical Characteristics Table 4 Electrical Characteristics -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. VI,min – 1.8 2.3 V IQ = 500 mA P_5.0.1 VQ 4.875 5.00 5.125 V 1mA < IQ < 500 mA ; 6 V < VI < 20 V P_5.0.2 ∆ VQ – 1 25 mV ∆VI = 5.5 V to 20 V ; IQ = 1 mA P_5.0.3 Load Regulation ∆ VQ – 16 32 mV TJ = 25 °C ; VI = 6.0 V ; ∆IQ = 1 - 500 mA P_5.0.4 Load Regulation ∆ VQ – – 57 mV VI = 6.0 V ; ∆IQ = 1 - 500 mA P_5.0.5 Dropout Voltage VDR – 130 190 mV IQ = 10 mA ; VI = VQ,nom ; P_5.0.6 TJ = 25 °C Dropout Voltage VDR – – 250 mV IQ = 10 mA ; VI = VQ,nom Dropout Voltage VDR – 170 220 mV IQ = 50 mA ; VI = VQ,nom ; P_5.0.8 TJ = 25 °C Dropout Voltage VDR – – 320 mV IQ = 50 mA ; VI = VQ,nom P_5.0.9 Dropout Voltage VDR – 200 240 mV IQ = 100 mA ; VI = VQ,nom ; TJ = 25 °C P_5.0.10 Dropout Voltage VDR – – 340 mV IQ = 100 mA ; VI = VQ,nom P_5.0.11 Dropout Voltage VDR – 350 380 mV IQ = 500 mA ; VI = VQ,nom ; TJ = 25 °C Dropout Voltage VDR – – 480 mV IQ = 500 mA ; VI = VQ,nom P_5.0.13 Quiescent Current (Active-Mode, EN-pin high) Iq – 30 60 µA VI = VQ,nom ; IQ = 0 mA P_5.0.14 Quiescent Current (Off-Mode, EN-pin low) Iq – 0.1 1 µA VI = 6 V ; VEN = 0 V ; TJ = 25 °C P_5.0.15 IGND – 50 100 µA VI = VQ,nom; IQ = 1 mA P_5.0.16 Minimum Operating Voltage Minimum Operating Voltage Output Voltage 1) 2) Output Voltage Line Regulation Line Regulation Load Regulation Dropout Voltage 3) P_5.0.7 P_5.0.12 Quiescent Current GND Pin Current 4) GND Pin Current Data Sheet 9 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics Table 4 Electrical Characteristics (cont’d) -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Number GND Pin Current IGND – 300 850 µA VI = VQ,nom ; IQ = 50 mA P_5.0.17 GND Pin Current IGND – 0.7 2.2 mA VI = VQ,nom ; IQ = 100 mA P_5.0.18 GND Pin Current IGND – 3 8 mA VI = VQ,nom ; IQ = 250 mA P_5.0.19 GND Pin Current IGND – 11 22 mA VI = VQ,nom ; IQ = 500 mA ; TJ ≥ 25 °C P_5.0.20 GND Pin Current IGND – 11 31 mA VI = VQ,nom ; IQ = 500 mA; P_5.0.21 TJ < 25 °C Enable Threshold High Vth,EN – 0.8 2.0 V VQ = Off to On P_5.0.22 Enable Threshold Low Vtl,EN 0.25 0.65 – V VQ = On to Off P_5.0.23 IEN – 0.01 – µA VEN = 0 V ; TJ = 25 °C P_5.0.24 IEN – 1 – µA VEN = 20V ; TJ = 25 °C P_5.0.25 eno – 55 – µVRMS CQ = 10 µF; CBYP = 10 nF ; IQ = 500 mA ; Enable EN Pin Current 5) EN Pin Current 5) Output Voltage Noise 6) Output Voltage Noise P_5.0.26 BW = 10 Hz to 100 kHz Output Voltage Noise eno – 44 – µVRMS CQ = 10 µF P_5.0.27 +250mΩ resistor in series; CBYP = 10 nF ; IQ = 500 mA ; BW = 10 Hz to 100 kHz Output Voltage Noise eno – 42 – µVRMS CQ = 22 µF CBYP = 10 nF ; IQ = 500 mA ; P_5.0.28 BW = 10 Hz to 100 kHz Output Voltage Noise eno – 42 – µVRMS CQ = 22 µF P_5.0.29 +250mΩ resistor in series; CBYP = 10 nF ; IQ = 500 mA ; BW = 10 Hz to 100 kHz Power Supply Ripple Rejection 6) Power Supply Ripple Rejection PSRR – 65 – dB P_5.0.30 VI - VQ = 1.5 V (avg) ; VRIPPLE = 0.5 Vpp ; fr = 120 Hz ; IQ = 500 mA 520 – – mA VI = 7 V ; VQ = 0 V Output Current Limitation Output Current Limit Data Sheet IQ,limit 10 P_5.0.31 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics Table 4 Electrical Characteristics (cont’d) -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless otherwise specified. Parameter Output Current Limit Symbol Values Unit Note / Test Condition Number Min. Typ. Max. 520 – – mA VI = VQ,nom + 1 V; ∆VQ = -0.1 V P_5.0.32 Ileak,rev – – 1 mA VI = -20 V ; VQ = 0 V P_5.0.33 IReverse – 10 20 µA VQ = VQ,nom ; VI < VQ,nom ; P_5.0.34 TJ = 25 °C IQ,limit Input Reverse Leakage Current Input Reverse Leakage Reverse Output Current 7) Reverse Output Current 1) This parameter defines the minimum input voltage for which the device is powered up and provides the maximum nominal output current of 500 mA. Under this minimum input voltage condition the TLS205B0 V50 starts to be in tracking mode and the output voltage will typically be in the range of around 1 V while providing the 500 mA. 2) The operation conditions are limited by the maximum junction temperature. The regulated output voltage specification will only apply for conditions where the limit of the maximum junction temperature is fulfilled. It will therefore not apply for all possible combinations of input voltage and output current. When operating at maximum input voltage, the output current must be limited for thermal reasons. The same holds true when operating at maximum output current where the input voltage range must be limited for thermal reasons. 3) The dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage will be equal to VI - VDR 4) GND-pin current is tested with VI = VQ,nom and a current source load. This means that this parameter is tested while being in the dropout region. The GND pin current will in most cases decrease slightly at higher input voltages - please also refer to the corresponding typical performance graphs. 5) The EN pin current flows into EN pin. 6) Not subject to production test, specified by design. 7) Reverse output current is tested with the I pin grounded and the Q pin forced to the rated output voltage. This current flows into the Q pin and out of the GND pin. Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specified mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Data Sheet 11 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics 5.1 Typical Performance Characteristics Dropout Voltage VDR versus Output Current IQ Guaranteed Dropout Voltage VDR versus Output Current IQ 500 500 450 450 400 400 350 350 300 300 VDR [mV] VDR [mV] Δ = Guaranteed Limits 250 250 200 200 150 150 100 100 Tj = −40 °C Tj = 25 °C 50 Tj ≤ 25 °C 50 Tj = 125 °C 0 0 100 200 300 400 Tj ≤ 125 °C 0 500 0 100 200 IQ [A] 300 400 500 IQ [A] Dropout Voltage VDR versus Junction Temperature Tj Quiescent Current versus Junction Temperature Tj 500 50 IQ = 10 mA 450 IQ = 100 mA 40 IQ = 500 mA 350 35 300 30 Iq [µA] VDR [mV] 400 45 IQ = 50 mA 250 25 200 20 150 15 100 10 50 5 0 −50 Data Sheet 0 50 Tj [°C] 0 −50 100 12 VI = 6 V IQ = 0 mA . VEN = VI 0 50 Tj [°C] 100 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics Output Voltage VQ versus Junction Temperature TJ Quiescent Current Iq versus Input Voltage VI 800 5.08 700 5.06 600 5.04 500 IGND [µA] VQ [V] 5.02 5 4.98 400 300 4.96 VQ,nom = 5.0 V IQ,nom = 0 mA VEN = VI Tj = 25 °C 200 4.94 100 4.92 IQ = 1 mA 4.9 −50 0 50 Tj [°C] 0 100 0 2 4 6 8 10 VI [V] GND Pin Current IGND versus Input Voltage VI GND Pin Current IGND versus Input Voltage VI 1600 16 RLoad = 50.0 Ω / IQ = 100 mA* RLoad = 5.0 kΩ / IQ = 1 mA* RLoad = 100 Ω / IQ = 50 mA* 1400 RLoad = 16.7 Ω / IQ = 300 mA* 14 RLoad = 10.0 Ω / IQ = 500 mA *. [* for VQ = 5.0 V] Tj = 25°C 1200 10 IGND [mA] IGND [µA] 1000 800 8 600 6 400 4 200 2 0 [* for VQ = 5.0 V] Tj = 25°C 12 0 2 4 6 8 0 10 VI [V] Data Sheet 0 2 4 6 8 10 VI [V] 13 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics GND Pin Current IGND versus Output Current IQ EN Pin Threshold (On-to-Off) versus Junction Temperature TJ 1.2 12 1 mA 500 mA 10 1 8 0.8 VEN,th [V] IGND [mA] VI = 6 V Tj = 25 ° C 6 0.6 4 0.4 2 0.2 0 0 100 200 300 IQ [mA] 400 EN Pin Threshold (Off-to-On) versus Junction Temperature TJ 0 −50 500 0 50 Tj [°C] 100 EN Pin Input Current versus EN Pin Voltage VEN 1.2 1.4 Tj = 25 °C VI = 20 V 1 mA 500 mA 1.2 1 1 IEN [µA] VEN,th [V] 0.8 0.6 0.8 0.6 0.4 0.4 0.2 0 −50 Data Sheet 0.2 0 50 Tj [°C] 0 100 14 0 5 10 VEN [V] 15 20 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics EN Pin Current versus Junction Temperature TJ Current Limit versus Input Voltage VI 1.6 1 VEN = 20 V VQ = 0 V Tj = 25 ° C 0.9 1.4 0.8 1.2 0.7 0.6 IQ,max [A] IEN [µA] 1 0.8 0.5 0.4 0.6 0.3 0.4 0.2 0.2 0 −50 0.1 0 50 Tj [°C] 0 100 0 1 2 3 4 5 6 7 VI [V] Current Limit versus Junction Temperature TJ Reverse Output Current versus Output Voltage VQ 1.2 90 VQ.nom = 5.0 V (V50) VI = 7 V VQ = 0 V 80 1 70 VI = 0 V Tj = 25 °C 60 IQ,rev [µA] IQ,max [A] 0.8 0.6 0.4 50 40 30 20 0.2 10 0 −50 Data Sheet 0 50 Tj [°C] 0 100 0 2 4 6 8 10 VQ [V] 15 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics Minimum Input Voltage 1) versus Junction Temperature TJ Reverse Output Current versus Junction Temperature TJ 22 2.5 VQ.nom = 5.0 V (V50) 20 18 16 2 VI = 0 V 14 VI,min [V] IQ,rev [µA] 1.5 12 10 1 8 6 0.5 4 IQ = 100 mA 2 IQ = 500 mA 0 −50 0 50 Tj [°C] 0 −50 100 0 50 Tj [°C] 100 Load Regulation versus Junction Temperature TJ 0 VI = 6.0 V; VQ.nom = 5.0 V −5 ΔVLoad [mV] −10 −15 −20 −25 ΔILoad = 1 mA to 500 mA −30 −50 1) 0 50 Tj [°C] 100 VI,min is referred here as the minimum input voltage for which the requested current is provided and VQ reaches 1 V. Data Sheet 16 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics ESR(CQ) with CBYP = 10 nF versus Output Capacitance CQ ESR Stability versus Output Current IQ (for CQ = 3.3 µF) 3 1 10 CByp = 10 nF measurement limit 2.5 ESRmax CByp = 0 nF 0 10 ESR(CQ) [Ω] ESR(CQ) [Ω] 2 ESRmin CByp = 0 nF ESRmax CByp = 10 nF ESRmin CByp = 10 nF stable region above blue line 1.5 1 CQ = 3.3 µF (0.06 Ω is measurement limit) 0.5 −1 10 0 100 200 300 IQ [mA] 400 0 500 2 3 4 5 6 7 CQ [µF] Input Ripple Rejection PSRR versus Frequency f Input Ripple Rejection PSRR versus Junction Temperature TJ 100 68 VI = VQnom + 1.5 V Vripple = 0.5 Vpp CQ = 10 µF 90 66 80 64 70 62 PSRR [dB] PSRR [dB] 60 50 40 60 58 56 30 20 54 IQ =500mA CBYP =0 nF IQ =500mA CBYP =10nF 10 52 IQ =50mA CBYP =0 nF IQ =50mA CBYP =10nF 0 10 Data Sheet 100 1k f [Hz] VI = VQnom + 1.5 V Vripple = 0.5 Vpp fripple = 120 Hz CQ = 10 µF IQ =500mA CBYP =0 nF IQ =500mA CBYP =10nF 10k 50 −50 100k 17 0 50 Tj [°C] 100 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Electrical Characteristics Output Noise Spectral Density versus Frequency f (CQ = 10 µF, IQ = 50 mA) Output Noise Spectral Density versus Frequency f (CQ = 22 µF, IQ = 50 mA) 1 10 1 10 CQ = 22 µF IQ = 50 mA √ Output Spectral Noise Density μV/ Hz √ Output Spectral Noise Density μV/ Hz CQ = 10 µF IQ = 50 mA 0 10 −1 10 CByp = 0 nF; ESR(CQ)=0 −1 10 CByp = 0 nF; ESR(CQ)=0 CByp = 10 nF; ESR(CQ)=0 CByp = 10 nF; ESR(CQ)=0 CByp = 10 nF; ESR(CQ)=250mΩ −2 10 1 2 10 3 10 4 10 f [Hz] 5 10 10 1 2 10 3 10 4 10 f [Hz] 5 10 10 Transient Response CBYP= 10 nF 0,2 0,4 CQ = 10 µF CBYP = 0 nF VI = 6V 0,3 CQ = 10 µF CBYP = 10 nF VI = 6V 0,15 0,1 VQ Deviation / [V] 0,2 0,1 0 0,05 0 -0,05 -0,1 -0,2 -0,1 -0,3 -0,15 -0,2 -0,4 0 100 200 300 400 500 Time (μs) 600 700 800 900 1000 0 600 20 40 60 80 100 Time / [μs] 120 140 160 180 200 600 IQ : 100 to 500mA IQ : 100 to 500mA 500 500 400 400 Load Step / [mA] Load Step / [mA] CByp = 10 nF; ESR(CQ)=250mΩ −2 10 Transient Response CBYP= 0 nF VQ Deviation / [V] 0 10 300 200 100 300 200 100 0 0 0 100 Data Sheet 200 300 400 500 Time (μs) 600 700 800 900 1000 0 18 20 40 60 80 100 Time / [μs] 120 140 160 180 200 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Application Information 6 Application Information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. TLS205B0 VI I VQ Q CI SENSE 1µF EN CBYP CQ 10nF 10µF R Load BYP GND GND Figure 4 Typical Application Circuit TLS205B0 V50 Note: This is a very simplified example of an application circuit. The function must be verified in the real application. 1) 2) The TLS205B0 V50 is a 500 mA low dropout regulator with very low quiescent current and Enable-functionality. The device is capable of supplying 500 mA at a dropout voltage of 350 mV. Output voltage noise numbers down to 42 µVRMS can be achieved over a 10 Hz to 100 kHz bandwidth with the addition of a 10 nF reference bypass capacitor. The usage of a reference bypass capacitor will additionally improve transient response of the regulator, lowering the settling time for transient load conditions. The device has a low operating quiescent current of typical 30 µA that drops to less than 1 µA in shutdown (EN-pin pulled to low level). The device also incorporates several protection features which makes it ideal for battery-powered systems. It is protected against both reverse input and reverse output voltages. 6.1 Kelvin Sense Connection The SENSE pin of the TLS205B0 V50 is the input to the error amplifier. An optimum regulation will be obtained at the point where the SENSE pin is connected to the output pin Q of the regulator. In critical applications however small voltage drops may be caused by the resistance Rp of the PC-traces and thus may lower the resulting voltage at the load. This effect may be eliminated by connecting the SENSE pin to the output as close as possible at the load (see Figure 5). Please note that the voltage drop across the external PC trace will add up to the dropout voltage of the regulator. 1) Please note that in case a non-negligible inductance at the input pin I is present, e.g. due to long cables, traces, parasitics, etc, a bigger input capacitor CI may be required to filter its influence. As a rule of thumb if the I pin is more than six inches away from the main input filter capacitor an input capacitor value of CI = 10 µF is recommended. 2) For specific needs a small optional resistor may be placed in series to very low ESR output capacitors CQ for enhanced noise performance (for details please see “Bypass Capacitance and Low Noise Performance” on Page 20). Data Sheet 19 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Application Information TLS205B0 I VI RP Q CI SENSE EN CQ R Load BYP GND RP Figure 5 Kelvin Sense Connection 6.2 Bypass Capacitance and Low Noise Performance The TLS205B0 V50 regulator may be used in combination with a bypass capacitor connecting the output pin Q to the BYP pin in order to minimize output voltage noise 1). This capacitor will bypass the reference of the regulator, providing a low frequency noise pole. The noise pole provided by such a bypass capacitor will lower the output voltage noise in the considered bandwidth. Actual numbers of the output voltage noise of the TLS205B0 V50 will - next to the bypass capacitor itself - be dependent on the capacitance of the applied output capacitor CQ and its ESR: In case of applying a bypass capacitor of 10 nF in combination with a (low ESR) ceramic CQ of 10 µF output voltage noise numbers will be in the range of typical 55 µVRMS. This output noise level can be reduced to typical 44 µVRMS under the same conditions by adding a small resistor of ~250 mΩ in series to the 10 µF ceramic output capacitor acting as additional ESR. A reduction of the output voltage noise can also be achieved by increasing capacitance of the output capacitor. For CQ = 22 µF (ceramic low ESR) the output voltage noise will be typically around 42 µVRMS. For output capacitor values of 22 µF or bigger adding resistance in series to CQ does not further lower output noise numbers significantly anymore. For further details please also see “Output Voltage Noise” on Page 10,, of the Electrical Characteristics. Please note that next to reducing the output voltage noise level the usage of a bypass capacitor has the additional benefit of improving transient response which will be also explained in the next chapter. However one needs to take into consideration that on the other hand the regulator start-up time is proportional to the size of the bypass capacitor and slows down to values around 15 ms when using a 10 nF bypass capacitor in combination with a 10 µF CQ output capacitor. 6.3 Output Capacitance and Transient Response The TLS205B0 V50 is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor is an essential parameter with regard to stability, most notably with small capacitors. A minimum output capacitor of 3.3 µF with an ESR of 3 Ω or less is recommended to prevent oscillations. Like in general for LDO’s the output transient response of the TLS205B0 V50 will be a function of the output capacitance. Larger values of output capacitance decrease peak deviations and thus improve transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the TLS205B0 V50 will increase the effective output capacitor value. Please note that with the usage of bypass capacitors for low noise operation either larger values of output capacitors may be needed or a minimum ESR requirement of CQ may have to be considered (see also typical performance graph “ESR(CQ) with CBYP = 10 nF versus Output 1) a good quality low leakage capacitor is recommended. Data Sheet 20 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Application Information Capacitance CQ” on Page 17 as example). In conjunction with the usage of a 10 nF bypass capacitor an output capacitor CQ ≥ 6.8 µF is recommended. The benefit of a bypass capacitor to the transient response performance is impressive and illustrated as one example in Figure 6 where the transient response of the TLS205B0 V50 to one and the same load step from 100 mA to 500 mA is shown with and without a 10 nF bypass capacitor: for the given configuration of CQ = 10 µF with no bypass capacitor the load step will settle in the range of less than 200 µs while for CQ = 10 µF in conjunction with a 10 nF bypass capacitor the same load step will settle in the range of 20 µs. Due to the shorter reaction time of the regulator by adding the bypass capacitor not only the settling time improves but also output voltage deviations due to load steps are sharply reduced. 0,4 0,2 VQ Deviation / [V] C_BYP = 0nF C_BYP = 10nF CQ = 10 µF CBYP = 0 vs 10nF VI = 6 V 0,3 0,1 0 -0,1 -0,2 -0,3 -0,4 0 100 200 300 400 500 Time (μs) 600 700 800 900 1000 Figure 6 Influence of CBYP: example of transient response to one and the same load step with and without CBYP of 10 nF (IQ: 100 mA to 500 mA) 6.4 Protection Features The TLS205B0 V50 regulators incorporate several protection features which make them ideal for use in batterypowered circuits. In addition to normal protection features associated with monolithic regulators like current limiting and thermal limiting the device is protected against reverse input voltage, reverse output voltage and reverse voltages from output to input. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation the junction temperature must not exceed 125 °C. The input of the device will withstand reverse voltages of 20 V. Current flowing into the device will be limited to less than 1 mA (typically less than 100 µA) and no negative voltage will appear at the output. The device will protect both itself and the load. This provides protection against batteries being plugged backwards. The output of the TLS205B0 V50 can be pulled below ground without damaging the device. If the input is left opencircuit or grounded, the output can be pulled below ground by 20 V. Under such conditions the output of the device by itself behaves like an open circuit with practically no current flowing out of the pin 1). In more application relevant cases however where the output is connected to the SENSE pin there will be a small current of typically less than 100 µA present from this origin. If the input is powered by a voltage source the output will source the short circuit current of the device and will protect itself by thermal limiting. In this case grounding the EN pin will turn off the device and stop the output from sourcing the short-circuit current. In circuits where a backup battery is required, several different input/output conditions can occur. The output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open-circuit. Current flow back into the output will follow the curve as shown in Figure 7 below. 1) typically < 1 µA for the mentioned conditions, VQ being pulled below ground with other pins either grounded or open. Data Sheet 21 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Application Information 90 VQ.nom = 5.0 V (V50) 80 70 VI = 0 V Tj = 25 °C IQ,rev [µA] 60 50 40 30 20 10 0 0 2 4 6 8 10 VQ [V] Figure 7 Data Sheet Reverse Output Current 22 Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Package Outlines 7 Package Outlines 0.35 x 45˚ 1.27 0.41±0.09 2) 0.2 8˚ MAX. 0.19 +0.06 0.08 C Seating Plane C M 0.1 C D 2x 1.7 MAX. Stand Off (1.45) 0.1+0 -0.1 3.9 ±0.11) 0.64 ±0.25 C A-B D 8x D 0.2 6 ±0.2 M D 8x Bottom View 8 1 5 1 4 2.65 ±0.2 3 ±0.2 A 4 8 5 B 4.9 ±0.11) 0.1 C A-B 2x Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width 3) JEDEC reference MS-012 variation BA 0 +0.05 0.36 ±0.1 1.63 ±0.1 Z 0.71 ±0.1 Pin 1 Marking 0.25 ±0.1 3.3 ±0.1 0.05 0.5 ±0.1 0.53 ±0.1 1.48 ±0.1 3.3 ±0.1 2.58 ±0.1 0.55 ±0.1 0.1 ±0.1 0.96 ±0.1 1±0.1 PG-DSO-8 Exposed Pad package outlines 0.2 ±0.1 Figure 8 PG-DSO-8-27-PO V01 Pin 1 Marking 0.25 ±0.1 PG-TSON-10-2-PO V02 Z (4:1) 0.07 MIN. Figure 9 PG-TSON-10 Package Outlines Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 23 Dimensions in mm Rev. 1.1, 2015-01-15 TLS205B0EJV50 TLS205B0LDV50 Revision History 8 Revision History Revision Date Changes 1.1 2015-01-15 Data Sheet - Revision 1.1: • PG-TSON-10 package variant added: Product Overview, Pin Configuration, Thermal Resistance, etc - wording and description added / updated accordingly. • Editorial changes. 1.0 2014-06-30 Data Sheet - Initial Release Data Sheet 24 Rev. 1.1, 2015-01-15 Edition 2015-01-15 Published by Infineon Technologies AG 81726 Munich, Germany © 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. 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