16-Bit
Architecture
XE161FL, XE161HL
16-Bit Single-Chip
Real Time Signal Controller
XE166 Family / Econo Line
Data Sheet
V1.2 2012-07
Microcontrollers
Edition 2012-07
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
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Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
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16-Bit
Architecture
XE161FL, XE161HL
16-Bit Single-Chip
Real Time Signal Controller
XE166 Family / Econo Line
Data Sheet
V1.2 2012-07
Microcontrollers
XE161FL, XE161HL
XE166 Family / Econo Line
XE161xL Data Sheet
Revision History: V1.2 2012-07
Previous Versions: V1.0 2010-12, V1.1 2011-09
Page
Subjects (major changes since last revision)
52, 53
The value of absolute sum of overload currents parameter in absolute
maximum rating parameter and operating conditions tables are switched.
74
Table description on coding of bit field LEVxV is updated.
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
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Data Sheet
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Table of Contents
Table of Contents
1
1.1
1.2
Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
2.1
2.2
General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Checker Module (MCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Unit (CC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . .
MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Window Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
22
25
27
27
28
29
30
33
35
39
41
42
44
45
45
46
47
48
49
4
4.1
4.1.1
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.4
4.5
4.6
4.7
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Range definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters for Upper Voltage Area . . . . . . . . . . . . . . . . . . . . . . . .
DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
52
53
55
55
56
58
60
62
66
72
75
77
Data Sheet
1
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Table of Contents
4.7.1
4.7.2
4.7.2.1
4.7.2.2
4.7.2.3
4.7.3
4.7.4
4.7.5
4.7.6
5
5.1
5.2
5.3
Data Sheet
Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wakeup Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting and Changing the Operating Frequency . . . . . . . . . . . . . .
External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
78
79
82
82
83
85
88
92
Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
2
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Summary of Features
16-Bit Single-Chip
Real Time Signal Controller
XE161xL (XE166 Family)
1
Summary of Features
For a quick overview and easy reference, the features of the XE161xL are summarized
here.
•
•
•
•
•
•
High-performance CPU with five-stage pipeline and MPU
– 12.5 ns instruction cycle @ 80 MHz CPU clock (single-cycle execution)
– One-cycle 32-bit addition and subtraction with 40-bit result
– One-cycle multiplication (16 × 16 bit)
– Background division (32 / 16 bit) in 21 cycles
– One-cycle multiply-and-accumulate (MAC) instructions
– Enhanced Boolean bit manipulation facilities
– Zero-cycle jump execution
– Additional instructions to support HLL and operating systems
– Register-based design with multiple variable register banks
– Fast context switching support with two additional local register banks
– 16 Mbytes total linear address space for code and data
– 1,024 Bytes on-chip special function register area (C166 Family compatible)
– Integrated Memory Protection Unit (MPU)
Interrupt system with 16 priority levels providing 64 interrupt nodes
– Selectable external inputs for interrupt generation and wake-up
– Fastest sample-rate 12.5 ns
Eight-channel interrupt-driven single-cycle data transfer with
Peripheral Event Controller (PEC), 24-bit pointers cover total address space
Clock generation from internal or external clock sources,
using on-chip PLL or prescaler
Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip
Memory Areas
On-chip memory modules
– 2 Kbytes on-chip dual-port RAM (DPRAM)
– 6 Kbytes on-chip data SRAM (DSRAM)
– 4 Kbytes on-chip program/data SRAM (PSRAM)
– Up to 160 Kbytes on-chip program memory (Flash memory)
– Memory content protection through Error Correction Code (ECC) for Flash
memory and through parity for RAMs
Data Sheet
3
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Summary of Features
•
•
•
•
•
•
•
•
•
On-Chip Peripheral Modules
– Synchronizable 12-bit A/D Converter with up to 10 channels,
conversion time below 1 μs, optional data preprocessing (data reduction, range
check), broken wire detection
– 16-channel general purpose capture/compare unit (CC2)
– Two capture/compare units for flexible PWM signal generation (CCU6x)
– Multi-functional general purpose timer unit with 5 timers
– Up to 4 serial interface channels to be used as UART, LIN, high-speed
synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s),
IIS interface
– On-chip MultiCAN interface (Rev. 2.0B active) with up to 32 message objects
(Full CAN/Basic CAN) on 2 CAN nodes and gateway functionality
– On-chip system timer and on-chip real time clock
Single power supply from 3.0 V to 5.5 V
Power reduction and wake-up modes with flexible power management
Programmable window watchdog timer and oscillator watchdog
Up to 33 general purpose I/O lines
On-chip bootstrap loaders
Supported by a full range of development tools including C compilers, macroassembler packages, emulators, evaluation boards, HLL debuggers, simulators,
logic analyzer disassemblers, programming boards
On-chip debug support via Device Access Port (DAP), Single-Pin DAP (SPD) or
JTAG interface
48-pin Green VQFN package, 0.5 mm (10.7 mil) pitch
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. This ordering code identifies:
•
•
•
the function set of the corresponding product type
the temperature range1):
– SAF-…: -40°C to 85°C
– SAK-…: -40°C to 125°C
the package and the type of delivery.
For ordering codes for the XE161xL please contact your sales representative or local
distributor.
1) Not all derivatives are offered in all temperature ranges.
Data Sheet
4
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Summary of Features
1.1
Device Types
The following XE161xL device types are available and can be ordered through Infineon’s
direct and/or distribution channels.
Table 1
Synopsis of XE161xL Device Types
1)
Derivative
Flash
Memory2)
PSRAM
DSRAM3)
Capt./Comp. ADC4) Interfaces4)
Modules
Chan.
XE161FL-12FxV
96 Kbytes
4 Kbytes
6 Kbytes
CC2
CCU60/3
10
2 CAN Nodes,
4 Serial Chan.
XE161HL-12FxV
96 Kbytes
4 Kbytes
6 Kbytes
CC2
CCU60/3
10
4 Serial Chan.
XE161FL-20FxV
160 Kbytes 4 Kbytes
6 Kbytes
CC2
CCU60/3
10
2 CAN Nodes,
4 Serial Chan.
XE161HL-20FxV
160 Kbytes 4 Kbytes
6 Kbytes
CC2
CCU60/3
10
4 Serial Chan.
1) x is a placeholder for available speed grade in MHz. Can be 66 or 80.
2) Specific information about the on-chip Flash memory in Table 3.
3) All derivatives additionally provide 2 Kbytes DPRAM.
4) Specific information about the available channels in Table 5.
Data Sheet
5
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Summary of Features
1.2
Definition of Feature Variants
The XE161xL types are offered with several Flash memory sizes. Table 3 and Table 4
describe the location of the available Flash memory.
Table 3
Continuous Flash Memory Ranges
Total Flash Size
1st Range1)
2nd Range
3rd Range
160 Kbytes
C0’0000H …
C0’EFFFH
C1’0000H …
C2’0FFFH
C4’0000H …
C4’7FFFH
96 Kbytes
C0’0000H …
C0’EFFFH
C1’0000H …
C1’0FFFH
C4’0000H …
C4’7FFFH
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
Table 4
Flash Memory Module Allocation (in Kbytes)
Total Flash Size
Flash 01)
Flash 1
160
128
32
96
64
32
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000H to C0’FFFFH).
The XE161xL types are offered with different interface options. Table 5 lists the available
channels for each option.
Table 5
Interface Channel Association
Total Number
Available Channels / Message Objects
10 ADC0 channels
CH0, CH2, CH3, CH4, CH8, CH9, CH16, CH17, CH19,
CH20
2 CAN nodes
CAN0, CAN1
32 message objects
4 serial channels
U0C0, U0C1, U1C0, U1C1
Data Sheet
6
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
2
General Device Information
The XE161xL series (16-Bit Single-Chip
Real Time Signal Controller) is a part of the Infineon XE166 Family of full-feature singlechip CMOS microcontrollers. These devices extend the functionality and performance of
the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They
combine high CPU performance (up to 80 million instructions per second) with extended
peripheral functionality and enhanced IO capabilities. Optimized peripherals can be
adapted flexibly to meet the application requirements. These derivatives utilize clock
generation via PLL and internal or external clock sources. On-chip memory modules
include program Flash, program RAM, and data RAM.
VAREF VAGND
(1)
VDDIMVDDPB VSS
(1)
(2)
(3)
(3)
XTAL1
XTAL2
Port 10
12 bit
Port 2
12 bit
Port 5
6 bit
Port 6
3 bit
PORST
TRST SPD/DAP/ Debug
JTAG
2 bit
TESTM
1 / 2 / 4 bit
via Port Pins
MC_XY _LOGSYMB 48
Figure 1
Data Sheet
XE161xL Logic Symbol
7
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
2.1
Pin Configuration and Definition
48
47
46
45
44
43
42
41
40
39
38
37
PORST
XTAL1
XTAL2
P10.12
P10.10
VDDIM
VSS
VDDPB
P10.9
P10.8
P10.7
P10.6
The pins of the XE161xL are described in detail in Table 6, which includes all alternate
functions. For further explanations please refer to the footnotes at the end of the table.
The following figure summarizes all pins, showing their locations on the four sides of the
package.
1
2
3
4
5
6
7
8
9
10
11
12
VQFN48
36
35
34
33
32
31
30
29
28
27
26
25
P10.5
P10.4
P10.3
P10.2
P10.1
P10.0
P2.13
P2.10
P2.9
P2.8
P2.7
P2.6
P5.4
P5.8
P5.9
P2.0
P2.1
VDDIM
VSS
VDDPB
P2.2
P2.3
P2.4
P2.5
13
14
15
16
17
18
19
20
21
22
23
24
TESTM
TRST
P6.3
P6.1
P6.0
VSS
VDDPB
VAREF
VAGND
P5.0
P5.2
P5.3
MC_XY_PIN48
Figure 2
Data Sheet
XE161xL Pin Configuration (top view)
8
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Key to Pin Definitions
•
•
Ctrl.: The output signal for a port pin is selected by bit field PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to
1x00B, output O1 is selected by 1x01B, etc.
Output signal OH is controlled by hardware.
Type: Indicates the pad type and its power supply domain (B, M).
– St: Standard pad
– Sp: Special pad e.g. XTALx
– DA: Digital IO and analog input
– In: Input only pad
– PS: Power supply pad
Table 6
Pin Definitions and Functions
Pin
Symbol
Ctrl.
Type Function
1
TESTM
I
In/B
Testmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to VDDPB).
An internal pullup device will hold this pin high
when nothing is driving it.
2
TRST
I
In/B
Test-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XE161xL’s debug system.
In this case, pin TRST must be driven low once to
reset the debug system.
An internal pulldown device will hold this pin low
when nothing is driving it.
3
P6.3
O0 / I St/B
Bit 3 of Port 6, General Purpose Input/Output
CCU63_COU O1
T62
St/B
CCU63 Channel 2 Output
T3OUT
O2
St/B
GPT12E Timer T3 Toggle Latch Output
U1C1_SELO
0
O3
St/B
USIC1 Channel 1 Select/Control 0 Output
U1C1_DX2D
I
St/B
USIC1 Channel 1 Shift Control Input
ADC0_REQT I
RyF
St/B
External Request Trigger Input for ADC0/1
Data Sheet
9
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
4
P6.1
O0 / I DA/B Bit 1 of Port 6, General Purpose Input/Output
5
ADC0_CH17
I
DA/B Analog Input Channel 17 for ADC0
EMUX1
O1
DA/B External Analog MUX Control Output 1 (ADC0)
T3OUT
O2
DA/B GPT12E Timer T3 Toggle Latch Output
U1C1_DOUT O3
DA/B USIC1 Channel 1 Shift Data Output
ADC0_REQT I
RyE
DA/B External Request Trigger Input for ADC0
CCU63_CTR
APB
I
DA/B CCU63 Emergency Trap Input
U1C1_DX0A
I
DA/B USIC1 Channel 1 Shift Data Input
DA/B ESR1 Trigger Input 6
ESR1_6
I
P6.0
O0 / I DA/B Bit 0 of Port 6, General Purpose Input/Output
ADC0_CH16
I
EMUX0
O1
11
12
DA/B Analog Input Channel 16 for ADC0
DA/B External Analog MUX Control Output 0 (ADC0)
CCU63_COU O2
T61
DA/B CCU63 Channel 1 Output
BRKOUT
DA/B OCDS Break Signal Output
O3
ADC0_REQG I
TyG
10
Type Function
DA/B External Request Gate Input for ADC0
U1C1_DX0E
I
DA/B USIC1 Channel 1 Shift Data Input
P5.0
I
In/B
Bit 0 of Port 5, General Purpose Input
ADC0_CH0
I
In/B
Analog Input Channel 0 for ADC0
P5.2
I
In/B
Bit 2 of Port 5, General Purpose Input
ADC0_CH2
I
In/B
Analog Input Channel 2 for ADC0
TDI_A
I
In/B
JTAG Test Data Input
P5.3
I
In/B
Bit 3 of Port 5, General Purpose Input
ADC0_CH3
I
In/B
Analog Input Channel 3 for ADC0
T3INA
I
In/B
GPT12E Timer T3 Count/Gate Input
Data Sheet
10
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
13
P5.4
I
In/B
Bit 4 of Port 5, General Purpose Input
ADC0_CH4
I
In/B
Analog Input Channel 4 for ADC0
CCU63_T12
HRB
I
In/B
External Run Control Input for T12 of CCU63
T3EUDA
I
In/B
GPT12E Timer T3 External Up/Down Control
Input
TMS_A
I
In/B
JTAG Test Mode Selection Input
14
15
16
P5.8
I
In/B
Bit 8 of Port 5, General Purpose Input
ADC0_CH8
I
In/B
Analog Input Channel 8 for ADC0
CCU6x_T12H I
RC
In/B
External Run Control Input for T12 of CCU60/3
CCU6x_T13H I
RC
In/B
External Run Control Input for T13 of CCU60/3
P5.9
I
In/B
Bit 9 of Port 5, General Purpose Input
ADC0_CH9
I
In/B
Analog Input Channel 9 for ADC0
CC2_T7IN
I
In/B
CAPCOM2 Timer T7 Count Input
P2.0
O0 / I DA/B Bit 0 of Port 2, General Purpose Input/Output
CCU63_CC6
0
O2
DA/B CCU63 Channel 0 Output
RxDC0C
I
DA/B CAN Node 0 Receive Data Input
CCU63_CC6
0INB
I
DA/B CCU63 Channel 0 Input
ADC0_CH19
I
DA/B Analog Input Channel 19 for ADC0
T5INB
I
DA/B GPT12E Timer T5 Count/Gate Input
Data Sheet
11
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
17
P2.1
O0 / I DA/B Bit 1 of Port 2, General Purpose Input/Output
21
22
Type Function
TxDC0
O1
DA/B CAN Node 0 Transmit Data Output
CCU63_CC6
1
O2
DA/B CCU63 Channel 1 Output
CCU63_CC6
1INB
I
DA/B CCU63 Channel 1 Input
ADC0_CH20
I
DA/B Analog Input Channel 20 for ADC0
T5EUDB
I
DA/B GPT12E Timer T5 External Up/Down Control
Input
ESR1_5
I
DA/B ESR1 Trigger Input 5
ERU_0A0
I
DA/B External Request Unit Channel 0 Input A0
P2.2
O0 / I St/B
Bit 2 of Port 2, General Purpose Input/Output
TxDC1
O1
St/B
CAN Node 1 Transmit Data Output
CCU63_CC6
2
O2
St/B
CCU63 Channel 2 Output
CCU63_CC6
2INB
I
St/B
CCU63 Channel 2 Input
ESR2_5
I
St/B
ESR2 Trigger Input 5
ERU_1A0
I
St/B
External Request Unit Channel 1 Input A0
P2.3
O0 / I St/B
Bit 3 of Port 2, General Purpose Input/Output
U0C0_DOUT O1
St/B
USIC0 Channel 0 Shift Data Output
CCU63_COU O2
T63
St/B
CCU63 Channel 3 Output
CC2_CC16
O3 / I St/B
CAPCOM2 CC16IO Capture Inp./ Compare Out.
ESR2_0
I
St/B
ESR2 Trigger Input 0
U0C0_DX0E
I
St/B
USIC0 Channel 0 Shift Data Input
U0C1_DX0D
I
St/B
USIC0 Channel 1 Shift Data Input
RxDC0A
I
St/B
CAN Node 0 Receive Data Input
Data Sheet
12
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
23
P2.4
O0 / I St/B
24
25
Type Function
Bit 4 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
TxDC0
O2
St/B
CAN Node 0 Transmit Data Output
CC2_CC17
O3 / I St/B
CAPCOM2 CC17IO Capture Inp./ Compare Out.
ESR1_0
I
St/B
ESR1 Trigger Input 0
U0C0_DX0F
I
St/B
USIC0 Channel 0 Shift Data Input
RxDC1A
I
St/B
CAN Node 1 Receive Data Input
P2.5
O0 / I St/B
Bit 5 of Port 2, General Purpose Input/Output
U0C0_SCLK
OUT
O1
St/B
USIC0 Channel 0 Shift Clock Output
TxDC0
O2
St/B
CAN Node 0 Transmit Data Output
CC2_CC18
O3 / I St/B
CAPCOM2 CC18IO Capture Inp./ Compare Out.
U0C0_DX1D
I
St/B
USIC0 Channel 0 Shift Clock Input
ESR1_10
I
St/B
ESR1 Trigger Input 10
P2.6
O0 / I St/B
Bit 6 of Port 2, General Purpose Input/Output
U0C0_SELO
0
O1
St/B
USIC0 Channel 0 Select/Control 0 Output
U0C1_SELO
1
O2
St/B
USIC0 Channel 1 Select/Control 1 Output
CC2_CC19
O3 / I St/B
CAPCOM2 CC19IO Capture Inp./ Compare Out.
CLKIN1
I
St/B
Clock Signal Input 1
U0C0_DX2D
I
St/B
USIC0 Channel 0 Shift Control Input
RxDC0D
I
St/B
CAN Node 0 Receive Data Input
ESR2_6
I
St/B
ESR2 Trigger Input 6
Data Sheet
13
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
26
P2.7
O0 / I St/B
Bit 7 of Port 2, General Purpose Input/Output
U0C1_SELO
0
O1
St/B
USIC0 Channel 1 Select/Control 0 Output
U0C0_SELO
1
O2
St/B
USIC0 Channel 0 Select/Control 1 Output
CC2_CC20
O3 / I St/B
CAPCOM2 CC20IO Capture Inp./ Compare Out.
U0C1_DX2C
I
St/B
USIC0 Channel 1 Shift Control Input
ESR2_7
I
St/B
ESR2 Trigger Input 7
RxDC1C
I
St/B
CAN Node 1 Receive Data Input
U1C0_DX0A
I
St/B
USIC1 Channel 0 Shift Data Input
27
28
29
Type Function
P2.8
O0 / I St/B
Bit 8 of Port 2, General Purpose Input/Output
U0C1_SCLK
OUT
O1
St/B
USIC0 Channel 1 Shift Clock Output
EXTCLK
O2
St/B
Programmable Clock Signal Output
CC2_CC21
O3 / I St/B
CAPCOM2 CC21IO Capture Inp./ Compare Out.
U0C1_DX1D
I
USIC0 Channel 1 Shift Clock Input
P2.9
O0 / I St/B
St/B
Bit 9 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
TxDC1
O2
St/B
CAN Node 1 Transmit Data Output
CC2_CC22
O3 / I St/B
CAPCOM2 CC22IO Capture Inp./ Compare Out.
C1
I
St/B
Configuration Pin 1
TCK_A
I
St/B
DAP0/JTAG Clock Input
P2.10
O0 / I St/B
Bit 10 of Port 2, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
U0C0_SELO
3
O2
St/B
USIC0 Channel 0 Select/Control 3 Output
CC2_CC23
O3 / I St/B
CAPCOM2 CC23IO Capture Inp./ Compare Out.
U0C1_DX0E
I
St/B
USIC0 Channel 1 Shift Data Input
CAPINA
I
St/B
GPT12E Register CAPREL Capture Input
Data Sheet
14
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
30,
P2.13
O0 / I St/B
31
32
33
Type Function
Bit 13 of Port 2, General Purpose Input/Output
U1C1_DOUT O1
St/B
USIC1 Channel 1 Shift Data Output
CCU63_COU O2
T60
St/B
CCU63 Channel 0 Output
U1C1_DX0B
I
St/B
USIC1 Channel 1 Shift Data Input
U1C0_DX0B
I
St/B
USIC1 Channel 0 Shift Data Input
P10.0
O0 / I St/B
Bit 0 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
CCU60_CC6
0
O2
St/B
CCU60 Channel 0 Output
CCU60_CC6
0INA
I
St/B
CCU60 Channel 0 Input
ESR1_2
I
St/B
ESR1 Trigger Input 2
U0C0_DX0A
I
St/B
USIC0 Channel 0 Shift Data Input
U0C1_DX0A
I
St/B
USIC0 Channel 1 Shift Data Input
U1C1_DX0C
I
St/B
USIC1 Channel 1 Shift Data Input
P10.1
O0 / I St/B
Bit 1 of Port 10, General Purpose Input/Output
U0C0_DOUT O1
St/B
USIC0 Channel 0 Shift Data Output
CCU60_CC6
1
O2
St/B
CCU60 Channel 1 Output
CCU60_CC6
1INA
I
St/B
CCU60 Channel 1 Input
U0C0_DX0B
I
St/B
USIC0 Channel 0 Shift Data Input
U0C0_DX1A
I
St/B
USIC0 Channel 0 Shift Clock Input
P10.2
O0 / I St/B
Bit 2 of Port 10, General Purpose Input/Output
U0C0_SCLK
OUT
O1
St/B
USIC0 Channel 0 Shift Clock Output
CCU60_CC6
2
O2
St/B
CCU60 Channel 2 Output
CCU60_CC6
2INA
I
St/B
CCU60 Channel 2 Input
U0C0_DX1B
I
St/B
USIC0 Channel 0 Shift Clock Input
Data Sheet
15
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
34
P10.3
O0 / I St/B
35
36
37
Type Function
Bit 3 of Port 10, General Purpose Input/Output
CCU60_COU O2
T60
St/B
CCU60 Channel 0 Output
U0C0_DX2A
St/B
USIC0 Channel 0 Shift Control Input
I
U0C1_DX2A
I
St/B
USIC0 Channel 1 Shift Control Input
RxDC1D
I
St/B
CAN Node 1 Receive Data Input
P10.4
O0 / I St/B
Bit 4 of Port 10, General Purpose Input/Output
U0C0_SELO
3
O1
St/B
USIC0 Channel 0 Select/Control 3 Output
CCU60_COU O2
T61
St/B
CCU60 Channel 1 Output
U0C0_DX2B
I
St/B
USIC0 Channel 0 Shift Control Input
U0C1_DX2B
I
St/B
USIC0 Channel 1 Shift Control Input
ESR1_9
I
St/B
ESR1 Trigger Input 9
P10.5
O0 / I St/B
Bit 5 of Port 10, General Purpose Input/Output
U0C1_SCLK
OUT
O1
St/B
USIC0 Channel 1 Shift Clock Output
CCU60_COU O2
T62
St/B
CCU60 Channel 2 Output
U0C1_DX1B
I
St/B
USIC0 Channel 1 Shift Clock Input
P10.6
O0 / I St/B
U0C0_DOUT O1
Bit 6 of Port 10, General Purpose Input/Output
St/B
USIC0 Channel 0 Shift Data Output
U1C0_DOUT O2
St/B
USIC1 Channel 0 Shift Data Output
U1C0_SELO
0
O3
St/B
USIC1 Channel 0 Select/Control 0 Output
U0C0_DX0C
I
St/B
USIC0 Channel 0 Shift Data Input
U1C0_DX2D
I
St/B
USIC1 Channel 0 Shift Control Input
CCU6x_CTR
APA
I
St/B
CCU60/CCU63 Emergency Trap Input
U1C0_DX0F
I
St/B
USIC1 Channel 0 Shift Data Input
Data Sheet
16
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
38
P10.7
O0 / I St/B
39
Type Function
Bit 7 of Port 10, General Purpose Input/Output
U0C1_DOUT O1
St/B
USIC0 Channel 1 Shift Data Output
CCU60_COU O2
T63
St/B
CCU60 Channel 3 Output
CCU63_COU O3
T61
St/B
CCU63 Channel 1 Output
U0C1_DX0B
I
St/B
USIC0 Channel 1 Shift Data Input
CCU60_CCP I
OS0A
St/B
CCU60 Position Input 0
T4INB
I
St/B
GPT12E Timer T4 Count/Gate Input
P10.8
O0 / I St/B
Bit 8 of Port 10, General Purpose Input/Output
U0C0_MCLK
OUT
O1
St/B
USIC0 Channel 0 Master Clock Output
U0C1_SELO
0
O2
St/B
USIC0 Channel 1 Select/Control 0 Output
U1C0_SCLK
OUT
O3
St/B
USIC1 Channel 0 Shift Clock Output
CCU60_CCP I
OS1A
St/B
CCU60 Position Input 1
U0C0_DX1C
St/B
USIC0 Channel 0 Shift Clock Input
I
BRKIN_B
I
St/B
OCDS Break Signal Input
T3EUDB
I
St/B
GPT12E Timer T3 External Up/Down Control
Input
U1C0_DX1A
I
St/B
USIC1 Channel 0 Shift Clock Input
ESR2_11
I
St/B
ESR2 Trigger Input 11
Data Sheet
17
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
40
P10.9
O0 / I St/B
Bit 9 of Port 10, General Purpose Input/Output
U0C0_SELO
4
O1
St/B
USIC0 Channel 0 Select/Control 4 Output
U0C1_MCLK
OUT
O2
St/B
USIC0 Channel 1 Master Clock Output
TxDC1
O3
44
45
46
Type Function
St/B
CAN Node 1 Transmit Data Output
CCU60_CCP I
OS2A
St/B
CCU60 Position Input 2
TCK_B
I
St/B
DAP0/JTAG Clock Input
T3INB
I
St/B
GPT12E Timer T3 Count/Gate Input
P10.10
O0 / I St/B
Bit 10 of Port 10, General Purpose Input/Output
U0C0_SELO
0
O1
St/B
USIC0 Channel 0 Select/Control 0 Output
CCU60_COU O2
T63
St/B
CCU60 Channel 3 Output
U1C0_DOUT O3
St/B
USIC1 Channel 0 Shift Data Output
U0C0_DX2C
I
St/B
USIC0 Channel 0 Shift Control Input
TDI_B
I
St/B
JTAG Test Data Input
U0C1_DX1A
I
St/B
USIC0 Channel 1 Shift Clock Input
P10.12
O0 / I St/B
Bit 12 of Port 10, General Purpose Input/Output
U1C0_DOUT O1
St/B
USIC1 Channel 0 Shift Data Output
U0C0_DOUT O2
St/B
USIC0 Channel 0 Shift Data Output
CCU63_COU O3
T62
St/B
CCU63 Channel 2 Output
TDO_A
OH
St/B
DAP1/JTAG Test Data Output
SPD_0
I/OH
St/B
SPD Input/Output
C0
I
St/B
Configuration Pin 0
U0C0_DX0D
I
St/B
USIC0 Channel 0 Shift Data Input
U1C0_DX0C
I
St/B
USIC1 Channel 0 Shift Data Input
U1C0_DX1E
I
St/B
USIC1 Channel 0 Shift Clock Input
XTAL2
O
Sp/M Crystal Oscillator Amplifier Output
Data Sheet
18
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Table 6
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
47
XTAL1
I
Sp/M Crystal Oscillator Amplifier Input
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Voltages on XTAL1 must comply to the core
supply voltage VDDIM.
ESR2_9
I
St/B
ESR2 Trigger Input 9
48
PORST
I
In/B
Power On Reset Input
A low level at this pin resets the XE161xL
completely. A spike filter suppresses input pulses
100 ns safely pass the filter.
The minimum duration for a safe recognition
should be 120 ns.
An internal pullup device will hold this pin high
when nothing is driving it.
8
VAREF
VAGND
VDDIM
-
PS/B Reference Voltage for A/D Converters ADC0
-
PS/B Reference Ground for A/D Converters ADC0
-
PS/M Digital Core Supply Voltage for Domain M
Decouple with a ceramic capacitor, see Data
Sheet for details.
All VDDIM pins must be connected to each other.
7,
20,
41
VDDPB
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
6,
19,
42
VSS
-
PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
9
18,
43
Data Sheet
19
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
2.2
Identification Registers
The identification registers describe the current version of the XE161xL and of its
modules.
Table 7
XE161xL Identification Registers
Short Name
Value
Address
SCU_IDMANUF
1820H
00’F07EH
SCU_IDCHIP
2801H
00’F07CH
SCU_IDMEM
3028H
00’F07AH
SCU_IDPROG
1313H
00’F078H
JTAG_ID
001D’6083H
---
Data Sheet
20
Notes
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Description
3
Functional Description
The architecture of the XE161xL combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 3). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XE161xL.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XE161xL.
DPRAM
DMU
Flash Memory
OCDS
Debug Support
DSRAM
CPU
PMU
IMB
PSRAM
MAC Unit
LXBUS
Controller
WWD
System Functions
Clock, Reset, Power
Control
MPU
Interrupt & PEC
RTC
LXBus
MCHK
ADC0
Module
GPT
CC2
Module
CCU6 x
Modules
8-/10- /
12 -Bit
5
Timers
16
Chan.
3+1
Chan.
each
Peripheral Data Bus
Interrupt Bus
USICx
Modules
Multi
CAN
2
Chan.
each
Analog and Digital General Purpose IO (GPIO) Ports
MC_L-SERIES_BLOCKDIAGRAM
Figure 3
Data Sheet
Block Diagram
21
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Description
3.1
Memory Subsystem and Organization
The memory space of the XE161xL is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XE161xL Memory Map 1)
Address Area
Start Loc. End Loc.
Area Size2)
IMB register space
FF’FF00H
FF’FFFFH
256 bytes
Reserved
F0’0000H
FF’FEFFH < 1 Mbyte
Minus IMB
registers.
Reserved for EPSRAM
E8’1000H
EF’FFFFH 508 Kbytes
Mirrors EPSRAM
Emulated PSRAM
E8’0000H
E8’0FFFH
up to 4 Kbytes With Flash timing.
Reserved for PSRAM
E0’1000H
E7’FFFFH
508 Kbytes
PSRAM
E0’0000H
E0’0FFFH
up to 4 Kbytes Program SRAM.
Reserved for Flash
C4’8000H
DF’FFFFH 1760 Kbytes
Flash 1
C4’0000H
C4’7FFFH
Reserved for Flash
C2’1000H
C3’FFFFH 124 Kbytes
Flash 0
C0’0000H
C2’0FFFH
40’0000H
BF’FFFFH 8 Mbytes
21’0000H
3F’FFFFH
1984 Kbytes
Reserved
20’B800H
20’FFFFH
18 Kbytes
USIC0-1 alternate regs.
20’B000H
20’B7FFH
2 Kbytes
Accessed via
LXBus Controller
MultiCAN alternate regs. 20’8000H
20’AFFFH
12 Kbytes
Accessed via
LXBus Controller
Reserved
20’5000H
20’7FFFH
12 Kbytes
USIC0-1 registers
20’4000H
20’4FFFH
4 Kbytes
Accessed via
LXBus Controller
MultiCAN registers
20’0000H
20’3FFFH
16 Kbytes
Accessed via
LXBus Controller
External memory area
01’0000H
1F’FFFFH
1984 Kbytes
SFR area
00’FE00H
00’FFFFH
0.5 Kbytes
Dual-port RAM
(DPRAM)
00’F600H
00’FDFFH
2 Kbytes
Reserved for DPRAM
00’F200H
00’F5FFH
1 Kbytes
External memory area
External IO area
Data Sheet
4)
22
Notes
Mirrors PSRAM
32 Kbytes
132 Kbytes3)
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Description
Table 8
XE161xL Memory Map (cont’d)1) (cont’d)
Address Area
Start Loc. End Loc.
Area Size2)
ESFR area
00’F000H
00’F1FFH
0.5 Kbytes
XSFR area
00’E000H
00’EFFFH
4 Kbytes
Data SRAM (DSRAM)
00’C800H
00’DFFFH
6 Kbytes
Reserved for DSRAM
00’8000H
00’C7FFH
18 Kbytes
External memory area
00’0000H
00’7FFFH
32 Kbytes
Notes
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2) The areas marked with “ VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
52
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.1.1
Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XE161xL. All parameters specified in the following sections refer to these operating
conditions, unless otherwise noticed.
Note: Typical parameter values refer to room temperature and nominal supply voltage,
minimum/maximum
parameter
values
also
include
conditions
of
minimum/maximum temperature and minimum/maximum supply voltage.
Additional details are described where applicable.
Table 13
Operating Conditions
Parameter
Symbol
Voltage Regulator Buffer
Capacitance for DMP_M
CEVRM
External Load
Capacitance
CL SR
Values
Unit
Min.
Typ.
Max.
1.0
−
4.7
μF
−
203)
−
pF
Note /
Test Condition
1)2)
SR
pin out
driver= default
4)
System frequency
Overload current for
analog inputs6)
fSYS SR −
IOVA SR -2
Overload current for digital IOVD SR -5
inputs6)
Overload current coupling KOVA
factor for analog inputs7)
CC
−
−
Data Sheet
53
−
80
MHz
5)
−
5
mA
not subject to
production test
−
5
mA
not subject to
production test
2.5 x
10-4
1.5 x
10-3
-
IOV< 0 mA; not
1.0 x
10-6
1.0 x
10-4
-
subject to
production test
IOV> 0 mA; not
subject to
production test
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 13
Operating Conditions (cont’d)
Parameter
Symbol
Overload current coupling KOVD
factor for digital I/O pins
CC
Values
Unit
Typ.
Max.
−
1.0 x
10-2
3.0 x
10-2
IOV< 0 mA; not
1.0 x
10-4
5.0 x
10-3
IOV> 0 mA; not
−
subject to
production test
subject to
production test
Σ|IOV|
SR
−
−
30
mA
Digital core supply voltage VDDIM
for domain M8)
CC
−
1.5
−
V
−
5.5
V
0
−
V
Absolute sum of overload
currents
Note /
Test Condition
Min.
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 3.0
Digital ground voltage
VSS SR
−
not subject to
production test
1) To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors. Separate
buffer capacitors with the recomended values shall be connected as close as possible to each VDDIM pin to
keep the resistance of the board tracks below 2 Ohm. Connect all VDDIM pins together. The minimum
capacitance value is required for proper operation under all conditions (e.g. temperature). Higher values
slightly increase the startup time.
2) Use one Capacitor for each pin.
3) This is the reference load. For bigger capacitive loads, use the derating factors listed in the PAD properties
section.
4) The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output
current may lead to increased delays or reduced driving capability (CL).
5) The operating frequency range may be reduced for specific device types. This is indicated in the device
designation (...FxxL). 66 MHz devices are marked ...F66L.
6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin ((IOV < 0). The absolute sum of input
overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified
limits. Proper operation under overload conditions depends on the application. Overload conditions must not
occur on pin XTAL1.
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pins leakage current (IOZ). The amount of error current depends on the overload
current and is defined by the overload coupling factor KOV. The polarity of the injected error current is inverse
compared to the polarity of the overload current that produces it.The total current through a pin is |ITOT| = |IOZ|
+ (|IOV| KOV). The additional error current may distort the input voltage on analog inputs.
Data Sheet
54
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
8) Value is controlled by on-chip regulator.
4.2
Voltage Range definitions
The XE161xL timing depends on the supply voltage. If such a dependency exists the
timing values are given for 2 voltage areas commonly used. The voltage areas are
defined in the following tables.
Table 14
Upper Voltage Range Definition
Parameter
Symbol
Values
Min.
Digital supply voltage for
IO pads and voltage
regulators
Table 15
VDDP SR 4.5
Max.
5.0
5.5
Note /
Test Condition
V
Lower Voltage Range Definition
Parameter
Symbol
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 3.0
Values
Min.
4.2.1
Unit
Typ.
Unit
Typ.
Max.
3.3
4.5
Note /
Test Condition
V
Parameter Interpretation
The parameters listed in the following include both the characteristics of the XE161xL
and its demands on the system. To aid in correctly interpreting the parameters when
evaluating them for a design, they are marked accordingly in the column “Symbol”:
CC (Controller Characteristics):
The logic of the XE161xL provides signals with the specified characteristics.
SR (System Requirement):
The external system must provide signals with the specified characteristics to the
XE161xL.
Data Sheet
55
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.3
DC Parameters
These parameters are static or average values that may be exceeded during switching
transitions (e.g. output current).
The XE161xL can operate within a wide supply voltage range from 3.0 V to 5.5 V.
However, during operation this supply voltage must remain within 10 percent of the
selected nominal supply voltage. It cannot vary across the full operating voltage range.
Because of the supply voltage restriction and because electrical behavior depends on
the supply voltage, the parameters are specified separately for the upper and the lower
voltage range.
During operation, the supply voltages may only change with a maximum speed of
dV/dt < 1 V/ms.
Leakage current is strongly dependent on the operating temperature and the voltage
level at the respective pin. The maximum values in the following tables apply under worst
case conditions, i.e. maximum temperature and an input level equal to the supply
voltage.
The value for the leakage current in an application can be determined by using the
respective leakage derating formula (see tables) with values from that application.
The pads of the XE161xL are designed to operate in various driver modes. The DC
parameter specifications refer to the pad current limits specified in Section 4.7.4.
Data Sheet
56
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Pullup/Pulldown Device Behavior
Most pins of the XE161xL feature pullup or pulldown devices. For some special pins
these are fixed; for the port pins they can be selected by the application.
The specified current values indicate how to load the respective pin depending on the
intended signal level. Figure 12 shows the current paths.
The shaded resistors shown in the figure may be required to compensate system pull
currents that do not match the given limit values.
VDDP
Pullup
Pulldown
VSS
MC_XC2X_PULL
Figure 12
Data Sheet
Pullup/Pulldown Current Definition
57
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.3.1
DC Parameters for Upper Voltage Area
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV.
Note: Operating Conditions apply.
Table 16 is valid under the following conditions: VDDP≤ 5.5 V; VDDPtyp. 5 V; VDDP≥ 4.5 V
Table 16
DC Characteristics for Upper Voltage Range
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
10
pF
not subject to
production test
−
−
V
RS= 0 Ohm
Pin capacitance (digital
inputs/outputs).
CIO CC
Input Hysteresis1)
HYS CC 0.11 x
VDDP
Absolute input leakage
current on pins of analog
ports2)
|IOZ1|
CC
−
10
200
nA
VIN> VSS ;
VIN< VDDP
Absolute input leakage
current for all other pins.
|IOZ2|
CC
−
0.2
5
μA
−
0.2
10
μA
−
−
μA
−
−
30
μA
TJ≤ 110 °C;
VIN> VSS ;
VIN< VDDP
TJ≤ 150 °C;
VIN> VSS ;
VIN< VDDP
VIN≥ VIHmin
(pulldown_ena
bled);
VIN≤ VILmax
(pullup_enable
d)
VIN≥ VIHmin
(pullup_enable
d);
VIN≤ VILmax
(pulldown_ena
bled)
0.7 x
−
2)3)
Pull Level Force Current4) |IPLF| SR 220
Pull Level Keep Current5)
|IPLK|
SR
Input high voltage (all
except XTAL1)
VIH SR
Data Sheet
VDDP
58
VDDP + V
0.3
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 16
DC Characteristics for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
-0.3
−
0.3 x
Input low voltage
(all except XTAL1)
VIL SR
Output High voltage6)
VOH CC VDDP - −
Note /
Test Condition
V
VDDP
−
V
IOH≥ IOHmax
−
V
IOH≥ IOHnom 7)
IOL≤ IOLnom 8)
IOL≤ IOLmax
1.0
VDDP - −
0.4
Output Low Voltage6)
VOL CC
−
−
0.4
V
−
−
1.0
V
1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
2) If the input voltage exceeds the respective supply voltage due to ground bouncing (VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
Please refer to the definition of the overload coupling factor KOV.
3) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
4) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull
device.
5) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level.
6) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
7) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
8) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
Data Sheet
59
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.3.2
DC Parameters for Lower Voltage Area
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV.
Note: Operating Conditions apply.
Table 17 is valid under the following conditions: VDDP≥ 3.0 V; VDDPtyp. 3.3 V;
VDDP≤ 4.5 V
Table 17
DC Characteristics for Lower Voltage Range
Parameter
Symbol
Values
Pin capacitance (digital
inputs/outputs).
CIO CC
Input Hysteresis1)
HYS CC 0.07 x
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
10
pF
not subject to
production test
−
−
V
RS= 0 Ohm
VDDP
Absolute input leakage
current on pins of analog
ports2)
|IOZ1|
CC
−
10
200
nA
VIN> VSS ;
VIN< VDDP
Absolute input leakage
current for all other pins.
|IOZ2|
CC
−
0.2
2
μA
−
0.2
6
μA
−
−
μA
−
10
μA
TJ≤ 110 °C;
VIN> VSS ;
VIN< VDDP
TJ≤ 150 °C;
VIN> VSS ;
VIN< VDDP
VIN≥ VIHmin
(pulldown_ena
bled);
VIN≤ VILmax
(pullup_enable
d) ;
VIN≥ VIHmin
(pullup_enable
d);
VIN≤ VILmax
(pulldown_ena
bled)
2)3)
Pull Level Force Current4) |IPLF| SR 150
Pull Level Keep Current5)
Data Sheet
|IPLK|
SR
−
60
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 17
DC Characteristics for Lower Voltage Range (cont’d)
Parameter
Symbol
Values
Min.
Typ.
0.7 x
−
Input high voltage (all
except XTAL1)
VIH SR
Input low voltage
(all except XTAL1)
VIL SR
Output High voltage6)
VOH CC VDDP - −
VDDP
Note /
Test Condition
VDDP + V
0.3
−
-0.3
Unit
Max.
0.3 x
V
VDDP
−
V
IOH≥ IOHmax
−
V
IOH≥ IOHnom 7)
IOL≤ IOLnom 8)
IOL≤ IOLmax
1.0
VDDP - −
0.4
Output Low Voltage6)
VOL CC
−
−
0.4
V
−
−
1.0
V
1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
2) If the input voltage exceeds the respective supply voltage due to ground bouncing (VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
Please refer to the definition of the overload coupling factor KOV.
3) The given values are worst-case values. In production test, this leakage current is only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
4) Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull
device.
5) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level.
6) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
7) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
8) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
Data Sheet
61
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.3.3
Power Consumption
The power consumed by the XE161xL depends on several factors such as supply
voltage, operating frequency, active circuits, and operating temperature. The power
consumption specified here consists of two components:
•
•
The switching current IS depends on the device activity
The leakage current ILK depends on the device temperature
To determine the actual power consumption, always both components, switching current
IS and leakage current ILK must be added:
IDDP = IS + ILK.
Note: The power consumption values are not subject to production test. They are
verified by design/characterization.
To determine the total power consumption for dimensioning the external power
supply, also the pad driver currents must be considered.
The given power consumption parameters and their values refer to specific operating
conditions:
•
•
Active mode:
Regular operation, i.e. peripherals are active, code execution out of Flash.
Stopover mode:
Crystal oscillator and PLL stopped, Flash switched off, clock in most parts of domain
DMP_M stopped.
Note: The maximum values cover the complete specified operating range of all
manufactured devices.
The typical values refer to average devices under typical conditions, such as
nominal supply voltage, room temperature, application-oriented activity.
After a power reset, the decoupling capacitors for VDDIM are charged with the
maximum possible current.
For additional information, please refer to Section 5.2, Thermal Considerations.
Note: Operating Conditions apply.
Data Sheet
62
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 18
Parameter
Switching Power Consumption
Symbol
Power supply current
ISACT
(active) with all peripherals CC
active and EVVRs on
Values
Unit
Note /
Test Condition
6 + 0.5 8 +
x fSYS1) 0.75 x
mA
power_mode=
active ;
voltage_range=
both 2)3)4)
0.7
mA
power_mode=
stopover ;
voltage_range=
both
Min.
Typ.
−
Max.
fSYS1)
Power supply current in
ISSO CC −
stopover mode, EVVRs on
2.0
1) fSYS in MHz
2) The pad supply voltage pins (VDDPB) provide the input current for the on-chip EVVRs and the current
consumed by the pin output drivers. A small current is consumed because the drivers input stages are
switched.
3) Please consider the additional conditions described in section "Active Mode Power Supply Current".
4) The pad supply voltage only has a minor influence on this parameter.
Active Mode Power Supply Current
The actual power supply current in active mode not only depends on the system
frequency but also on the configuration of the XE161xL’s subsystem.
Besides the power consumed by the device logic the power supply pins also provide the
current that flows through the pin output drivers.
A small current is consumed because the drivers’ input stages are switched.
Data Sheet
63
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
IS [mA]
80
ISACTmax
70
60
ISACTtyp
50
40
30
20
10
20
40
80
60
fSYS [MHz]
MC_XC2XL_IS
Figure 13
Supply Current in Active Mode as a Function of Frequency
Note: Operating Conditions apply.
Table 19
Parameter
Leakage Power Consumption
Symbol
Leakage supply current1)2) ILK1 CC
Values
Unit
Note /
Test Condition
0.04
mA
0.4
1.1
mA
1.7
4.9
mA
3.5
10.7
mA
TJ= 25 °C
TJ= 85 °C
TJ= 125 °C
TJ= 150 °C
Min.
Typ.
Max.
−
0.03
−
−
−
1) The supply current caused by leakage depends mainly on the junction temperature and the supply voltage.
The temperature difference between the junction temperature TJ and the ambient temperature TA must be
taken into account. As this fraction of the supply current does not depend on device activity, it must be added
to other power consumption values.
2) All inputs (including pins configured as inputs) are set at 0 V to 0.1 V or at VDDP - 0.1 V to VDDP and all outputs
(including pins configured as outputs) are disconnected.
Data Sheet
64
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Leakage Power Consumption Calculation
The leakage power consumption can be calculated according to the following formulas:
ILK1 = 470,000 + e-α with α = 5000 / (273 + B×TJ)
Parameter B must be replaced by
•
•
1.0 for typical values
1.3 for maximum values
ILK [mA]
ILK1max
12
10
8
6
ILK1typ
4
2
-50
0
50
100
125
150
TJ [°C]
MC_XC2XL_ILKN
Figure 14
Leakage Supply Current as a Function of Temperature
Data Sheet
65
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.4
Analog/Digital Converter Parameters
These parameters describe the conditions for optimum ADC performance.
Note: Operating Conditions apply.
Table 20
ADC Parameters for All Voltage Ranges
Parameter
Symbol
Switched capacitance at
an analog input
CAINSW
Values
Min.
Typ.
Max.
−
9
20
Unit
Note /
Test Condition
pF
not subject to
production test
CC
1)
Total capacitance at an
analog input
CAINT
−
20
30
pF
CC
not subject to
production test
1)
Switched capacitance at
the reference input
CAREFSW −
15
30
pF
CC
not subject to
production test
1)
Total capacitance at the
reference input
CAREFT
−
20
40
pF
CC
not subject to
production test
1)
Broken wire detection
delay against VAGND2)
tBWG CC −
−
503)
Broken wire detection
delay against VAREF2)
tBWR CC −
−
504)
Conversion time for 8-bit
result2)
tc8 CC
tSYS
Conversion time for 10-bit tc10 CC
result2)
Conversion time for 12-bit tc12 CC
result2)
Analog reference ground
Analog input voltage
range
Analog reference voltage
(10 + STC x tADCI + 2 x
(12 + STC x tADCI + 2 x
tSYS
(16 + STC x tADCI + 2 x
VAGND
tSYS
VSS -
SR
0.05
−
1.5
V
VAIN SR VAGND
−
VAREF
V
VAREF
VAGND
−
VDDPB
V
SR
+ 1.0
5)
+ 0.05
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
Data Sheet
66
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
2) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result. Values for the
basic clock tADCI depend on programming.
3) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 500 µs. Result below 10% (66H)
4) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10 µs. This function is influenced by leakage current, in particular at high
temperature. Result above 80% (332H)
5) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
Table 21
ADC Parameters for Upper Voltage Range
Parameter
Symbol
Values
Input resistance of the
selected analog channel
RAIN CC −
Min.
Typ.
Max.
0.9
1.5
Unit
Note /
Test Condition
kOh
m
not subject to
production test
1)
Input resistance of the
reference input
RAREF
−
0.5
1
CC
kOh
m
not subject to
production test
1)
Differential Non-Linearity
Error2)3)4)5)
|EADNL|
CC
−
2.5
5.0
LSB
Gain Error2)3)4)5)
|EAGAIN| −
CC
2.5
6.0
LSB
Integral NonLinearity2)3)4)5)
|EAINL|
CC
−
2.0
4.0
LSB
Offset Error2)3)4)5)
|EAOFF|
CC
−
2.0
4.0
LSB
Analog clock frequency
fADCI SR 2
−
20
MHz Std. reference
input (VAREF)
2
−
17.5
MHz Alt. reference
input (CH0)
−
2.5
5.5
LSB
Wakeup time from analog tWAF CC −
powerdown, fast mode
−
7.0
μs
Wakeup time from analog tWAS CC −
powerdown, slow mode
−
11.5
μs
Total Unadjusted Error3)4)
Data Sheet
|TUE|
CC
67
6)7)
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
3) If a reduced analog reference voltage between 1V and VDDPB / 2 is used, then there are additional decrease
in the ADC speed and accuracy.
4) If the analog reference voltage range is below VDDPB but still in the defined range of VDDPB / 2 and VDDPB is
used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k VDDPB, then the ADC converter errors increase.
6) TUE is based on 12-bit conversion.
7) TUE is tested at VAREF = VDDPB = 5.0 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog
port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
Table 22
ADC Parameters for Lower Voltage Range
Parameter
Symbol
Values
Min.
Input resistance of the
selected analog channel
RAIN CC −
Typ.
Max.
1.4
2.5
Unit
Note /
Test Condition
kOh
m
not subject to
production test
1)
Input resistance of the
reference input
RAREF
−
1.0
2.0
CC
kOh
m
not subject to
production test
1)
Differential Non-Linearity
Error2)3)4)5)
|EADNL|
CC
−
2.5
5.5
LSB
Gain Error2)3)4)5)
|EAGAIN| −
CC
3.0
8.0
LSB
Integral NonLinearity2)3)4)5)
|EAINL|
CC
−
2.5
7.5
LSB
Offset Error2)3)4)5)
|EAOFF|
CC
−
2.0
5.5
LSB
Analog clock frequency
fADCI SR 2
−
16.7
MHz Std. reference
input (VAREF)
2
−
12.1
MHz Alt. reference
input (CH0)
−
2.5
7.5
LSB
Total Unadjusted Error3)4)
Data Sheet
|TUE|
CC
68
6)7)
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 22
ADC Parameters for Lower Voltage Range (cont’d)
Parameter
Symbol
Values
Min.
Unit
Typ.
Max.
Wakeup time from analog tWAF CC −
powerdown, fast mode
−
8.5
μs
Wakeup time from analog tWAS CC −
powerdown, slow mode
−
15.0
μs
Note /
Test Condition
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
3) If a reduced analog reference voltage between 1V and VDDPB / 2 is used, then there are additional decrease
in the ADC speed and accuracy.
4) If the analog reference voltage range is below VDDPB but still in the defined range of VDDPB / 2 and VDDPB is
used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k VDDPB, then the ADC converter errors increase.
6) TUE is based on 12-bit conversion.
7) TUE is tested at VAREF = VDDPB = 3.3 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog
port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
RSource
V AIN
R AIN, On
C AINT - C AINS
C Ext
A/D Converter
CAINS
MCS05570
Figure 15
Equivalent Circuitry for Analog Inputs
Sample time and conversion time of the XE161xL’s A/D converters are programmable.
The timing above can be calculated using Table 23.
The limit values for fADCI must not be exceeded when selecting the prescaler value.
Data Sheet
69
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 23
A/D Converter Computation Table
GLOBCTR.5-0
(DIVA)
A/D Converter
Analog Clock fADCI
INPCRx.7-0
(STC)
000000B
fSYS
fSYS / 2
fSYS / 3
fSYS / (DIVA+1)
fSYS / 63
fSYS / 64
00H
000001B
000010B
:
111110B
111111B
01H
02H
:
FEH
FFH
Sample Time1)
tS
tADCI × 2
tADCI × 3
tADCI × 4
tADCI × (STC+2)
tADCI × 256
tADCI × 257
1) The selected sample time is doubled if broken wire detection is active (due to the presampling phase).
Converter Timing Example A:
Assumptions:
Analog clock
Sample time
fSYS
fADCI
tS
= 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H
= fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns
= tADCI × 2 = 100 ns
Conversion 12-bit:
tC12
= 16 × tADCI + 2 × tSYS = 16 × 50 ns + 2 × 12.5 ns = 0.825 μs
Conversion 10-bit:
tC10
= 12 × tADCI + 2 × tSYS = 12 × 50 ns + 2 × 12.5 ns = 0.625 μs
Conversion 8-bit:
tC8
= 10 × tADCI + 2 × tSYS = 10 × 50 ns + 2 × 12.5 ns = 0.525 μs
Converter Timing Example B:
Assumptions:
Analog clock
Sample time
fSYS
fADCI
tS
= 66 MHz (i.e. tSYS = 15.2 ns), DIVA = 03H, STC = 00H
= fSYS / 4 = 16.5 MHz, i.e. tADCI = 60.6 ns
= tADCI × 2 = 121.2 ns
Conversion 12-bit:
tC12
= 16 × tADCI + 2 × tSYS = 16 × 60.6 ns + 2 × 15.2 ns = 1.0 μs
Conversion 10-bit:
tC10
Data Sheet
= 12 × tADCI + 2 × tSYS = 12 × 60.6 ns + 2 × 15.2 ns = 0.758 μs
70
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Conversion 8-bit:
tC8
Data Sheet
= 10 × tADCI + 2 × tSYS = 10 × 60.6 ns + 2 × 15.2 ns = 0.636 μs
71
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.5
System Parameters
The following parameters specify several aspects which are important when integrating
the XE161xL into an application system.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 24
Various System Parameters
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
ΔTJ = ≤ 10°C
Short-term deviation of
internal clock source
frequency1)
ΔfINT CC -1
−
1
%
Internal clock source
frequency
fINT CC
4.8
5.0
5.2
MHz
Wakeup clock source
frequency2)
fWU CC
400
−
700
kHz
FREQSEL= 00
210
−
390
kHz
FREQSEL= 01
140
−
260
kHz
FREQSEL= 10
110
−
200
kHz
FREQSEL= 11
1.9
2.4
ms
fWU = 500 kHz
−
12 /
μs
Startup time from poweron with code execution
from Flash
tSPO CC 1.4
Startup time from stopover tSSO CC 11 /
mode with code execution
fWU3)
from PSRAM
Core voltage (PVC)
supervision level
VPVC CC VLV -
Supply watchdog (SWD)
supervision level
VSWD
fWU3)
VLV
0.03
CC
VLV +
0.07
V
5)
4)
VLV -
VLV
VLV +
0.15
V
voltage_range=
lower 5)
VLV 0.15
VLV
VLV +
0.15
V
voltage_range=
upper 5)
0.106)
1) The short-term frequency deviation refers to a timeframe of a few hours and is measured relative to the current
frequency at the beginning of the respective timeframe. This parameter is useful to determine a time span for
re-triggering a LIN synchronization.
2) This parameter is tested for the fastest and the slowest selection. The medium selections are not subject to
production test - verified by design/characterization.
3) fWU in MHz.
Data Sheet
72
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4) This value includes a hysteresis of approximately 50 mV for rising voltage.
5) VLV = selected SWD voltage level
6) The limit VLV - 0.10 V is valid for the OK1 level. The limit for the OK2 level is VLV - 0.15 V.
Conditions for tSPO Timing Measurement
The time required for the transition from Power-On to Base mode is called tSPO. It is
measured under the following conditions:
Precondition: The pad supply is valid, i.e. VDDPB is above 3.0 V and remains above 3.0 V
even though the XE161xL is starting up. No debugger is attached.
Start condition: Power on reset is removed (PORST = 1).
End condition: External pin toggle caused by first user instruction executed from Flash
after startup.
Conditions for tSSO Timing Measurement
The time required for the transition from Stopover to Stopover Waked-Up mode is
called tSSO. It is measured under the following conditions:
Precondition: The Stopover mode has been entered using the procedure defined in the
Programmer’s Guide.
Start condition: Pin toggle on ESR pin triggering the startup sequence.
End condition: External pin toggle caused by first user instruction executed from PSRAM
after startup.
Data Sheet
73
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Coding of bit fields LEVxV in SWD Configuration Registers
After power-on the supply watch dog is preconfigured to operate in the lower voltage
range.
Table 25
Coding of bit fields LEVxV in Register SWDCON0
Code
Default Voltage Level
Notes1)
0000B
-
out of valid operation range
0001B
3.0 V
LEV1V: reset request
0010B - 0101B
3.1 V - 3.4 V
step width is 0.1 V
0110B
3.6 V
0111B
4.0 V
1000B
4.2 V
1001B
4.5 V
LEV2V: no request
1010B - 1110B
4.6 V - 5.0 V
step width is 0.1 V
1111B
5.5 V
1) The indicated default levels are selected automatically after a power reset.
Coding of bit fields LEVxV in PVC Configuration Registers
The core voltages are controlled internally to the nominal value of 1.5 V; a variation of
±10 % is allowed. These operation conditions limit the possible PVC monitoring values
to the predefined reset values shown in Table 26.
Table 26
Coding of bit fields LEVxV in Registers PVCyCONz
Code
Default Voltage Level
Notes1)
000B - 011B
-
out of valid operation range
100B
1.35 V
LEV1V: reset request
101B
1.45 V
LEV2V: interrupt request2)
110B - 111B
-
out of valid operation range
1) The indicated default levels are selected automatically after a power reset.
2) Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and PVC levels, this
interrupt can be triggered inadvertently, even though the core voltage is within the normal range. It is,
therefore, recommended not to use this warning level.
Data Sheet
74
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.6
Flash Memory Parameters
The XE161xL is delivered with all Flash sectors erased and with no protection installed.
The data retention time of the XE161xL’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 27
Flash Parameters
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
−
−
21)
−
−
2)
1
Parallel Flash module
program/erase limit
depending on Flash read
activity
NPP SR
Flash erase endurance
for security pages
NSEC SR 10
−
−
Flash wait states3)
NWSFLASH 1
−
−
SR
2
−
−
3
−
−
4
−
NFL_RD≤ 1
NFL_RD> 1
cycle tRET≥ 20 years
s
fSYS≤ 8 MHz
fSYS≤ 13 MHz
fSYS≤ 17 MHz
fSYS> 17 MHz
−
Erase time per
sector/page
tER CC
−
7
8.0
ms
Programming time per
page
tPR CC
−
34)
3.5
ms
Data retention time
tRET CC
20
−
−
year
s
Drain disturb limit
Data Sheet
NDD SR
−
32
75
4)
−
Note /
Test Condition
NER≤ 1,000 cycl
es
cycle
s
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 27
Flash Parameters (cont’d)
Parameter
Number of erase cycles
Symbol
NER SR
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
15000 cycle tRET≥ 5 years;
s
Valid for up to
64 user
selected
sectors (data
storage)
−
−
1000
cycle tRET≥ 20 years
s
1) All Flash module(s) can be erased/programmed while code is executed and/or data is read from only one Flash
module or from PSRAM. The Flash module that delivers code/data can, of course, not be erased/programmed.
2) Flash module 1 can be erased/programmed while code is executed and/or data is read from Flash module 0.
3) Value of IMB_IMBCTRL.WSFLASH.
4) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
few system clock cycles. This increases the stated durations noticably only at extremely low system clock
frequencies.
Access to the XE161xL Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Data Sheet
76
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.7
AC Parameters
These parameters describe the dynamic behavior of the XE161xL.
4.7.1
Testing Waveforms
These values are used for characterization and production testing (except pin XTAL1).
O utput delay
O utput delay
H old tim e
H old tim e
0.8 V DDP
0.7 V DDP
Input Signal
(driven by tester)
0.3 V DDP
0.2 V DDP
O utput S ignal
(m easured)
O utput tim ings refer to the rising edge of C LKO U T.
Input tim ings are calculated from the tim e, w hen the input signal reaches
V IH or V IL , respectively.
M C D05556C
Figure 16
Input Output Waveforms
VLoad + 0.1 V
V OH - 0.1 V
Timing
Reference
Points
V Load - 0.1 V
V OL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 mV
change from the loaded V OH /V OL level occurs (IOH / IOL = 20 mA).
MCA05565
Figure 17
Data Sheet
Floating Waveforms
77
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.7.2
Definition of Internal Timing
The internal operation of the XE161xL is controlled by the internal system clock fSYS.
Because the system clock signal fSYS can be generated from a number of internal and
external sources using different mechanisms, the duration of the system clock periods
(TCSs) and their variation (as well as the derived external timing) depend on the
mechanism used to generate fSYS. This must be considered when calculating the timing
for the XE161xL.
Phase Locked Loop Operation (1:N)
fI N
f SYS
TCS
Direct Clock Drive (1:1)
fI N
f SYS
TCS
Prescaler Operation (N:1)
fI N
f SYS
TCS
M C_XC2X_CLOCKGEN
Figure 18
Generation Mechanisms for the System Clock
Note: The example of PLL operation shown in Figure 18 uses a PLL factor of 1:4; the
example of prescaler operation uses a divider factor of 2:1.
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
Data Sheet
78
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is
derived directly from the input clock signal CLKIN1:
fSYS = fIN.
The frequency of fSYS is the same as the frequency of fIN. In this case the high and low
times of fSYS are determined by the duty cycle of the input clock fIN.
Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY =
1B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
fSYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of fSYS equals the frequency of fOSC. In
this case the high and low times of fSYS are determined by the duty cycle of the input
clock fOSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
fSYS = fOSC / 1024.
4.7.2.1
Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (fSYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the onchip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of fSYS so that it is
locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage VDDIM.
Data Sheet
79
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the
minimum TCS possible under the given circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is
constantly adjusting its output frequency to correspond to the input frequency (from
crystal or oscillator), the accumulated jitter is limited. This means that the relative
deviation for periods of more than one TCS is lower than for a single TCS (see formulas
and Figure 19).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles
is K2 × T, where T is the number of consecutive fSYS cycles (TCS).
The maximum accumulated jitter (long-term jitter) DTmax is defined by:
DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3)
This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or
the prescaler value K2 > 17.
In all other cases for a timeframe of T × TCS the accumulated jitter DT is determined by:
DT [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2]
fSYS in [MHz] in all formulas.
Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:
Dmax = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)
D3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]
= 5.97 × [0.768 × 2 / 26.39 + 0.232]
= 1.7 ns
Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:
Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)
D3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]
= 7.63 × [0.884 × 2 / 26.39 + 0.116]
= 1.4 ns
Data Sheet
80
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Acc. jitter DT
ns
±9
fSYS = 33 MHz fSYS = 66 MHz
fVCO = 66 MHz
±8
±7
f VCO = 132 MHz
±6
±5
±4
±3
±2
±1
Cycles T
0
1
20
40
60
80
100
MC_XC2X_JITTER
Figure 19
Approximated Accumulated PLL Jitter
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL = 20 pF.
The maximum peak-to-peak noise on the pad supply voltage (measured between
VDDPB pin and VSS pin) is limited to a peak-to-peak voltage of VPP = 50 mV. This
can be achieved by appropriate blocking of the supply voltage as close as possible
to the supply pins and using PCB supply and ground planes.
PLL frequency band selection
Different frequency bands can be selected for the VCO so that the operation of the PLL
can be adjusted to a wide range of input and output frequencies:
Data Sheet
81
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 28
System PLL Parameters
Parameter
Symbol
Values
Min.
VCO output frequency
4.7.2.2
Unit
Note /
Test Condition
Typ.
Max.
fVCO CC 50
−
110
MHz VCOSEL= 00B;
VCOmode=
controlled
10
−
40
MHz VCOSEL= 00B;
VCOmode= free
running
100
−
160
MHz VCOSEL= 01B;
VCOmode=
controlled
20
−
80
MHz VCOSEL= 01B;
VCOmode= free
running
Wakeup Clock
When wakeup operation is selected (SYSCON0.CLKSEL = 00B), the system clock is
derived from the low-frequency wakeup clock source:
fSYS = fWU.
In this mode, a basic functionality can be maintained without requiring an external clock
source and while minimizing the power consumption.
4.7.2.3
Selecting and Changing the Operating Frequency
When selecting a clock source and the clock generation method, the required
parameters must be carefully written to the respective bit fields, to avoid unintended
intermediate states.
Many applications change the frequency of the system clock (fSYS) during operation in
order to optimize system performance and power consumption. Changing the operating
frequency also changes the switching currents, which influences the power supply.
To ensure proper operation of the on-chip EVRs while they generate the core voltage,
the operating frequency shall only be changed in certain steps. This prevents overshoots
and undershoots of the supply voltage.
To avoid the indicated problems, recommended sequences are provided which ensure
the intended operation of the clock system interacting with the power system.
Please refer to the Programmer’s Guide.
Data Sheet
82
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.7.3
External Clock Input Parameters
These parameters specify the external clock generation for the XE161xL. The clock can
be generated in two ways:
•
•
By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2.
By supplying an external clock signal. This clock signal can be supplied either to
pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain).
If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH.
If connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for
the operation of the on-chip oscillator.
Note: The given clock timing parameters (t1 … t4) are only valid for an external clock
input signal.
Note: Operating Conditions apply.
Table 29
External Clock Input Characteristics
Parameter
Symbol
Values
Min.
Oscillator frequency
XTAL1 input current
absolute value
XTAL11)
fOSC SR 4
−
40
MHz Input= Clock
Signal
4
−
16
MHz Input= Crystal
or Resonator
−
−
20
μA
6
−
−
ns
6
−
−
ns
−
8
8
ns
−
8
8
ns
0.3 x
−
−
V
−
−
V
−
−
V
−
1.7
V
|IIL| CC
VDDIM
0.4 x
VDDIM
0.5 x
VDDIM
Input voltage range limits
for signal on XTAL1
Note /
Test Condition
Max.
t1 SR
Input clock low time
t2 SR
Input clock rise time
t3 SR
t4 SR
Input clock fall time
Input voltage amplitude on VAX1 SR
Input clock high time
Unit
Typ.
VIX1 SR -1.7 +
VDDIM
fOSC≥ 4 MHz;
fOSC≤ 16 MHz
fOSC≥ 16 MHz;
fOSC≤ 25 MHz
fOSC≥ 25 MHz;
fOSC≤ 40 MHz
2)
1) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the
operation and the resulting voltage peaks must remain within the limits defined by VIX1.
Data Sheet
83
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
2) Overload conditions must not occur on pin XTAL1.
Note: For crystal/resonator operation, it is strongly recommended to measure the
oscillation allowance (negative resistance) in the final target system (layout) to
determine the optimum parameters for oscillator operation.
The manufacturers of crystals and ceramic resonators offer an oscillator
evaluation service. This evaluation checks the crystal/resonator specification
limits to ensure a reliable oscillatior operation.
t1
VOFF
t3
0.9 V AX1
0.1 V AX1
VAX1
t2
t4
tOSC = 1/fOSC
MC_ EXTCLOCK
Figure 20
External Clock Drive XTAL1
Data Sheet
84
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.7.4
Pad Properties
The output pad drivers of the XE161xL can operate in several user-selectable modes.
Strong driver mode allows controlling external components requiring higher currents
such as power bridges or LEDs. Reducing the driving power of an output pad reduces
electromagnetic emissions (EME). In strong driver mode, selecting a slower edge
reduces EME.
The dynamic behavior, i.e. the rise time and fall time, depends on the applied external
capacitance that must be charged and discharged. Timing values are given for a
capacitance of 20 pF, unless otherwise noted.
In general, the performance of a pad driver depends on the available supply voltage
VDDP. Therefore the following tables list the pad parameters for the upper voltage range
and the lower voltage range, respectively.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 30 is valid under the following conditions: VDDP≤ 5.5 V; VDDPtyp. 5 V; VDDP≥ 4.5 V
Table 30
Standard Pad Parameters for Upper Voltage Range
Parameter
Maximum output driver
current (absolute value)1)
Nominal output driver
current (absolute value)
Data Sheet
Symbol
IOmax
Values
Unit
Note /
Test Condition
3.0
mA
Driver_Strength
= Medium
−
5.0
mA
Driver_Strength
= Strong
−
−
0.5
mA
Driver_Strength
= Weak
−
−
1.0
mA
Driver_Strength
= Medium
−
−
1.6
mA
Driver_Strength
= Strong
−
−
0.25
mA
Driver_Strength
= Weak
Min.
Typ.
Max.
−
−
−
CC
IOnom
CC
85
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 30
Standard Pad Parameters for Upper Voltage Range (cont’d)
Parameter
Symbol
Rise and Fall times (10% - tRF CC
90%)
Values
Min.
Typ.
Max.
−
−
38 +
0.6 x
Unit
Note /
Test Condition
ns
CL≥ 20 pF;
CL≤ 100 pF;
CL
−
−
1+
0.45 x
Driver_Strength
= Medium
ns
CL
−
−
16 +
0.45 x
Driver_Strength
= Strong ;
Driver_Edge=
Soft
ns
CL
−
−
200 +
2.5 x
CL≥ 20 pF;
CL≤ 100 pF;
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Strong ;
Driver_Edge=
Slow
ns
CL
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Weak
1) The total output current that may be drawn at a given time must be limited to protect the supply rails from
damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and ΣIOH) must remain below 25 mA.
Table 31
Standard Pad Parameters for Lower Voltage Range
Parameter
Symbol
Maximum output driver
current (absolute value)1)
IOmax
Data Sheet
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
1.8
mA
Driver_Strength
= Medium
−
−
3.0
mA
Driver_Strength
= Strong
−
−
0.3
mA
Driver_Strength
= Weak
CC
86
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 31
Standard Pad Parameters for Lower Voltage Range (cont’d)
Parameter
Nominal output driver
current (absolute value)
Symbol
IOnom
Values
Unit
Note /
Test Condition
0.8
mA
Driver_Strength
= Medium
−
1.0
mA
Driver_Strength
= Strong
−
−
0.15
mA
Driver_Strength
= Weak
−
−
73 +
0.85 x
ns
CL≥ 20 pF;
CL≤ 100 pF;
Min.
Typ.
Max.
−
−
−
CC
Rise and Fall times (10% - tRF CC
90%)
−
−
CL
Driver_Strength
= Medium
6 + 0.6 ns
x CL
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Strong ;
Driver_Edge=
Soft
−
−
33 +
0.6 x
ns
CL
−
−
385 +
3.25 x
CL
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Strong ;
Driver_Edge=
Slow
ns
CL≥ 20 pF;
CL≤ 100 pF;
Driver_Strength
= Weak
1) The total output current that may be drawn at a given time must be limited to protect the supply rails from
damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and ΣIOH) must remain below 25 mA.
Data Sheet
87
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.7.5
Synchronous Serial Interface Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 32
is valid under the following conditions: CL= 20 pF; SSC= master ;
voltage_range= upper
Table 32
USIC SSC Master Mode Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
tSYS -
−
−
ns
Slave select output SELO t1 CC
active to first SCLKOUT
transmit edge
81)
Slave select output SELO t2 CC
inactive after last
SCLKOUT receive edge
tSYS -
−
−
ns
61)
t3 CC
-6
−
9
ns
Receive data input setup t4 SR
time to SCLKOUT receive
edge
31
−
−
ns
t5 SR
-4
−
−
ns
Data output DOUT valid
time
Data input DX0 hold time
from SCLKOUT receive
edge
Note /
Test Condition
1) tSYS = 1 / fSYS
Data Sheet
88
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 33
is valid under the following conditions: CL= 20 pF; SSC= master ;
voltage_range= lower
Table 33
USIC SSC Master Mode Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
tSYS -
−
−
ns
tSYS -
−
−
ns
t3 CC
-7
−
11
ns
Receive data input setup t4 SR
time to SCLKOUT receive
edge
40
−
−
ns
t5 SR
-5
−
−
ns
Slave select output SELO t1 CC
active to first SCLKOUT
transmit edge
101)
Slave select output SELO t2 CC
inactive after last
SCLKOUT receive edge
91)
Data output DOUT valid
time
Data input DX0 hold time
from SCLKOUT receive
edge
Note /
Test Condition
1) tSYS = 1 / fSYS
Table 34
is valid under the following conditions: CL= 20 pF; SSC= slave ;
voltage_range= upper
Table 34
USIC SSC Slave Mode Timing for Upper Voltage Range
Parameter
Symbol
Select input DX2 setup to
first clock input DX1
transmit edge1)
t10 SR
Values
Unit
Min.
Typ.
Max.
10
−
−
ns
Select input DX2 hold after t11 SR
last clock input DX1
receive edge1)
7
−
−
ns
t12 SR
7
−
−
ns
Receive data input setup
time to shift clock receive
edge1)
Data Sheet
89
Note /
Test Condition
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 34
USIC SSC Slave Mode Timing for Upper Voltage Range (cont’d)
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Data input DX0 hold time
from clock input DX1
receive edge1)
t13 SR
5
−
−
ns
Data output DOUT valid
time
t14 CC
7
−
33
ns
Note /
Test Condition
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Table 35
is valid under the following conditions: CL= 20 pF; SSC= slave ;
voltage_range= lower
Table 35
USIC SSC Slave Mode Timing for Lower Voltage Range
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
10
−
−
ns
Select input DX2 hold after t11 SR
last clock input DX1
receive edge1)
7
−
−
ns
Receive data input setup
time to shift clock receive
edge1)
t12 SR
7
−
−
ns
Data input DX0 hold time
from clock input DX1
receive edge1)
t13 SR
5
−
−
ns
Data output DOUT valid
time
t14 CC
8
−
41
ns
Select input DX2 setup to
first clock input DX1
transmit edge1)
t10 SR
Note /
Test Condition
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Data Sheet
90
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Master Mode Timing
t1
Select Output
SELOx
t2
Inactive
Inactive
Active
Clock Output
SCLKOUT
Receive
Edge
First Transmit
Edge
t3
Last Receive
Edge
Transmit
Edge
t3
Data Output
DOUT
t4
Data Input
DX0
t4
t5
Data
valid
t5
Data
valid
Slave Mode Timing
t10
Select Input
DX2
Clock Input
DX1
t11
Active
Inactive
Receive
Edge
First Transmit
Edge
t12
Data Input
DX0
Inactive
t12
t13
Data
valid
t 14
Last Receive
Edge
Transmit
Edge
t 13
Data
valid
t14
Data Output
DOUT
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched
.
Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
USIC_SSC_TMGX.VSD
Figure 21
USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration where the slave select signal
is low-active and the serial clock signal is not shifted and not inverted.
Data Sheet
91
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
4.7.6
Debug Interface Timing
The debugger can communicate with the XE161xL via 1-pin SPD interface, via the 2-pin
DAP interface or via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 36 is valid under the following conditions: CL= 20 pF; voltage_range= upper
Table 36
DAP Interface Timing for Upper Voltage Range
Parameter
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
t11 SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
1001)
−
−
ns
8
−
−
ns
8
−
−
ns
−
−
4
ns
−
−
4
ns
6
−
−
ns
pad_type= stan
dard
DAP1 hold after DAP0
rising edge
t17 SR
6
−
−
ns
pad_type= stan
dard
DAP1 valid per DAP0
clock period2)
t19 CC
92
95
−
ns
pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
Data Sheet
92
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 37 is valid under the following conditions: CL= 20 pF; voltage_range= lower
Table 37
DAP Interface Timing for Lower Voltage Range
Parameter
Symbol
Values
Min.
t11 SR
t12 SR
t13 SR
t14 SR
t15 SR
t16 SR
DAP0 clock period
DAP0 high time
DAP0 low time
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Unit
Typ.
Max.
100
−
−
ns
8
−
−
ns
1)
Note /
Test Condition
8
−
−
ns
−
−
4
ns
−
−
4
ns
6
−
−
ns
pad_type= stan
dard
DAP1 hold after DAP0
rising edge
t17 SR
6
−
−
ns
pad_type= stan
dard
DAP1 valid per DAP0
clock period2)
t19 CC
87
92
−
ns
pad_type= stan
dard
1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t 11
0.9 VDDP
0.5 VDDP
t15
t12
t 14
0.1 VDDP
t13
MC_DAP0
Figure 22
Data Sheet
Test Clock Timing (DAP0)
93
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
DAP0
t1 6
t1 7
DAP1
MC_ DAP1_RX
Figure 23
DAP Timing Host to Device
t1 1
DAP1
t1 9
MC_ DAP1_TX
Figure 24
DAP Timing Device to Host
Note: The transmission timing is determined by the receiving debugger by evaluating the
sync-request synchronization pattern telegram.
Data Sheet
94
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 38 is valid under the following conditions: CL= 20 pF; voltage_range= upper
Table 38
JTAG Interface Timing for Upper Voltage Range
Parameter
Symbol
TCK clock period
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
t7 SR
Values
Unit
Min.
Typ.
Max.
1001)
−
−
ns
16
−
−
ns
16
−
−
ns
−
−
8
ns
−
−
8
ns
6
−
−
ns
6
−
−
ns
TDO valid from TCK falling t8 CC
edge (propagation delay)3)
−
29
32
ns
TDO high impedance to
valid output from TCK
falling edge4)3)
t9 CC
−
29
32
ns
TDO valid output to high
impedance from TCK
falling edge3)
t10 CC
−
29
32
ns
TDO hold after TCK falling t18 CC
edge3)
5
−
−
ns
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup to TCK
rising edge
TDI/TMS hold after TCK
rising edge
Note /
Test Condition
2)
1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS.
2) Under typical conditions, the JTAG interface can operate at transfer rates up to 10 MHz.
3) The falling edge on TCK is used to generate the TDO timing.
4) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
95
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Table 39 is valid under the following conditions: CL= 20 pF; voltage_range= lower
Table 39
JTAG Interface Timing for Lower Voltage Range
Parameter
Symbol
Values
Min.
TCK clock period
TCK high time
t1 SR
t2 SR
t3 SR
t4 SR
t5 SR
t6 SR
Unit
Typ.
Max.
−
−
ns
16
−
−
ns
100
1)
16
−
−
ns
−
−
8
ns
−
−
8
ns
6
−
−
ns
t7 SR
6
−
−
ns
TDO valid from TCK falling t8 CC
edge (propagation delay)2)
−
39
43
ns
TDO high impedance to
valid output from TCK
falling edge3)2)
t9 CC
−
39
43
ns
TDO valid output to high
impedance from TCK
falling edge2)
t10 CC
−
39
43
ns
TDO hold after TCK falling t18 CC
edge2)
5
−
−
ns
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup to TCK
rising edge
TDI/TMS hold after TCK
rising edge
Note /
Test Condition
1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS.
2) The falling edge on TCK is used to generate the TDO timing.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Data Sheet
96
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
t1
0.9 VD D P
0.5 VDD P
t5
t2
0.1 VD D P
t4
t3
MC_ JTAG_ TCK
Figure 25
Test Clock Timing (TCK)
TCK
t6
t7
t6
t7
TMS
TDI
t9
t8
t1 0
TDO
t18
MC_JTAG
Figure 26
Data Sheet
JTAG Timing
97
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Debug via SPD
The SPD interface will work with standard SPD tools having a sample/output clock
frequency deviation of +/- 5% or less.
Note: For further details please refer to application note AP24004 in section SPD Timing
Requirements.
Note: Operating Conditions apply.
Data Sheet
98
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
5
Package and Reliability
The XE166 Family devices use the package type:
•
PG-VQFN (Plastic Green - Very Thin Profile Quad Flat Non-Leaded Package)
The following specifications must be regarded to ensure proper integration of the
XE161xL in its target environment.
5.1
Packaging
These parameters specify the packaging rather than the silicon.
Table 40
Package Parameters (PG-VQFN-48-54)
Parameter
Symbol
Limit Values
Min.
Exposed Pad Dimension
Ex × Ey –
5.2 x 5.2
Power Dissipation
PDISS
RΘJA
–
–
Thermal resistance
Junction-Ambient
Unit Notes
Max.
mm
–
0.7
W
–
73
K/W No thermal via,
2-layer1)
49
K/W No thermal via,
4-layer2)
43
K/W 4-layer, no pad3)
34
K/W 4-layer, pad4)
1) Device mounted on a 2-layer JEDEC board (according to JESD 51-3) without thermal vias; exposed pad not
soldered.
2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) without thermal vias; exposed pad not
soldered.
3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not
soldered.
4) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered
to the board.
Note: To improve the EMC behavior, it is recommended to connect the exposed pad to
the board ground, independent of the thermal requirements.
Board layout examples are given in an application note.
Package Compatibility Considerations
The XE161xL is a member of the XE166 Family of microcontrollers. It is also compatible
to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
Data Sheet
99
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
particular, the size of the Exposed Pad (if present) may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
Package Outlines
0.9 MAX.
(0.65)
0.5
0.4 x 45˚
Index Marking
24
3
0.0
5±
(0.2)
0.05 MAX.
(6.2)
48
13
12
0.1
C
37
6
48x
0.08
36
25
(5.2)
0.5
+0.03
0.2
6.8
7 ±0.1
B
SEATING PLANE
6.8
11 x 0.5 = 5.5
0.4 ±0.07
A
11 x 0.5 = 5.5
7 ±0.1
1
0.23 ±0.05
(5.2)
Index Marking
48x
0.1 M A B C
(6.2)
PG-VQFN-48-15, -19, -20, -22, -24, -48, -51, -52, -53, -55, -56-PO V12
Figure 27
PG-VQFN-48-54 (Plastic Green Thin Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
Data Sheet
100
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
5.2
Thermal Considerations
When operating the XE161xL in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
•
•
•
•
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
Data Sheet
101
V1.2, 2012-07
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
5.3
Quality Declarations
The operation lifetime of the XE161xL depends on the operating temperature. The
lifetime decreases with increasing temperature as shown in Table 42.
Table 41
Quality Parameters
Parameter
Symbol
Operation lifetime
tOP CC
VHBM
Table 42
Unit
Note /
Test Condition
Min.
Typ.
Max.
−
−
20
a
See Table 42
−
−
2000
V
EIA/JESD22A114-B
MSL CC −
−
3
−
JEDEC
J-STD-020C
ESD susceptibility
according to Human Body SR
Model (HBM)
Moisture sensitivity level
Values
Lifetime Dependency on Temperature
Operating Time
Operating Temperature
20 a
14 500 h
TJ ≤ 110°C
TJ = 120°C
TJ = 125°C
TJ = 130°C
TJ = 140°C
TJ = 150°C
Data Sheet
102
95 500 h
68 500 h
49 500 h
26 400 h
V1.2, 2012-07
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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