SP505

SP505 WAN Multi-Mode Serial Transceiver • +5V Only Operation • Seven (7) Drivers and Seven (7) Receivers • Driver and Receiver Tri-state Control • Internal Transceiver Termination Resistors for V. and V.35 Protocols • Loopback Self-Test Mode • Software Selectable Protocol Selection • Interface Modes Supported: • RS-232 (V.28) • X.2/RS-422 (V.) • EIA-530 (V.0 & V.) • EIA-530A (V.0 & V.) • RS-449 (V.0 & V.) • V.35 (V.35 & V.28) • V.36 (V.0 & V.) • RS-485 (un-terminated V.) • Improved ESD Tolerance for Analog I/Os • High Differential Transmission Rates • SP505A - 0Mbps • SP505B - over 6Mbps • Compliant to NET/2 and TBR2 Physical Layer Requirements (TUV Test Report NET2/0520/98) (TUV Test Report CTR2/0520/98) 77 SCT(b) 76 SCT(a) 69 DM(b) 68 DM(a) 71 RD(b) 70 RD(a) 67 CS(b) 66 CS(a) 61 SD(a) 75 GND 72 GND 64 GND 65 TT(b) 63 TT(a) 78 DSR 79 SCT 80 CTS 74 VCC 73 VCC 62 VCC RxD 1 SDEN 2 TREN 3 RSEN 4 LLEN 5 TTEN 6 SCTEN7 LATCH 8 DEC3 9 DEC2 10 DEC1 11 DEC0 12 DTR 13 TxD 14 TxC 15 RTS 16 RL 17 RLEN 18 DCD 19 RxC 20 60 GND 59 SD(b) 58 TR(a) 57 GND 56 TR(b) 55 VCC 54 RS(a) 53 GND 52 RS(b) 51 LL(a) 50 GND 49 LL(b) 48 VCC 47 RL(a) 46 GND 45 RL(b) 44 ST(b) 43 GND 42 ST(a) 41 VCC SP505 STEN 23 ST 22 RI 21 LL 24 IC(a) 39 RR(a) 35 RR(b) 36 R T(a) 37 The SP505 is a monolithic device that supports eight (8) popular serial interface standards for DTE to DCE connectivity. The SP505 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Seven (7) drivers and seven (7) receivers can be configured via software for any of the above interface modes at any time. The SP505 requires no additional external components for compliant operation for all of the eight (8) modes of operation. All necessary termination is integrated within the SP505 and is switchable when V.35 drivers, V.35 receivers, and V. receivers are used. The SP505 can operate as either a DTE or DCE. Additional features with the SP505 include internal loopback that can be initiated in either single-ended or differential modes. While in loopback mode, driver outputs are internally connected to receiver inputs creating an internal signal path convenient for diagnostic testing. This eliminates the need for an external loopback plug. The SP505 also includes a latch enable pin with the driver and receiver address decoder. Tri-state ability for the driver and receiver outputs is controlled by supplying a 4-bit word into the address decoder. Seven (7) drivers and one () receiver in the SP505 include separate enable pins for added convenience. The SP505 is ideal for WAN serial ports in networking equipment such as routers, switches, DSU/CSU's, and other access devices. DESCRIPTION V.35 EIA-530 WAN Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com R T(b) 38 SP505_00_08308  IC(b) 40 GND 29 C1– 30 C – 31 GND 34 VCC 25 C1+ 26 VDD 27 C2+ 28 VCC 33 VSS 32 2 These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VCC.......................................................................+7V Input Voltages: Logic............................-0.3V to (VCC+0.5V) Drivers.........................-0.3V to (VCC+0.5V) Receivers........................................±5.5V Output Voltages: Logic............................-0.3V to (VCC+0.5V) Drivers................................................±5V Receivers.....................-0.3V to (VCC+0.5V) Storage Temperature.......................-65˚C to +150˚C Power Dissipation.........................................2000mW Package Derating: øJA.................................................46 °C/W øJC.................................................6 °C/W TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. ABSOLUTE MAXIMUM RATINGS STORAGE CONSIDERATIONS Due to the relatively large package size of the 80-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 25°C in order remove moisture prior to soldering. Exar ships the 80-pin QFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH. ELECTRICAL CHARACTERISTICS MAX 0.8 UNITS Volts Volts 0.4 Volts Volts +/-5 Volts Volts mA Ω .5 30 µs V/ µs µs µs kbps 7 +2.0 kΩ Volts Volts Volts Per Figure 7 Per Figure 8 IOUT = -3.2mA IOUT = .0mA Per Figure  Per Figure 2 Per Figure 4 Per Figure 5 Per Figure 6; +3V to -3V Per Figure 3 CONDITIONS PARAMETER LOGIC INPUTS VIL VIH LOGIC OUTPUTS VOL VOH Open Circuit Voltage Loaded Voltage Short-Circuit Current Power-Off Impedance Transition Time Instantaneous Slew Rate Propagation Delay tPHL Propagation Delay tPLH Max. Transmission Rate Input impedance Open-Circuit Bias HIGH Threshold LOW Threshold MIN TYP 2.0 2.4 V.28 DRIVER OUTPUT DC PARAMETERS +/-5.0 300 +/-5 +/-00 V.28 DRIVER OUTPUT AC PARAMETERS (Vcc = +5V for AC Parameters) 0.5 0.5 20 3   230 5 5 V.28 RECEIVER INPUT DC PARAMETERS .7 0.8 .2 3.0 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 2 TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. ELECTRICAL CHARACTERISTICS MAX. 500 500 UNITS ns ns kbps +/-6.0 +/-50 +/-00 200 Volts Volts mA mA ns ns ns kbps +3.25 +/-0.3 mA kΩ Volts ns ns kbps +/-5.0 Volts Volts 0.67VOC +/-0.4 +3.0 +/-50 +/-00 20 Volts Volts Volts mA µA ns ns ns ns Mbps Mbps Per Figure 6 Per Figure 7 Per Figure 7 Per Figure 7 Per Figure 7 Per Figure 8 Per Figure 9 Per Figures 2 and 36; 0% to 90% Per Figures 33 and 36; CL = 50pF Per Figures 33 and 36; CL = 50pF Per Figures 33 and 36; CL = 50pF Per Figure 33; CL = 50pF, fIN = 5MHz Per Figure 33; CL = 50pF, fIN = 8.2MHz Per Figures 4 and 5 Per Figure 9 Per Figure 0 Per Figure  Per Figure 2 Per Figure 3; 0% to 90% CONDITIONS PARAMETER Propagation Delay tPHL Propagation Delay tPLH Max Transmission Rate Open Circuit Voltage Test Terminated Voltage Short-Circuit Current Power-Off Current Transition Time Propagation Delay tPHL Propagation Delay tPLH Max Transmission Rate Input Current Input Impedance Sensitivity Propagation Delay tPHL Propagation Delay tPLH Max Transmission Rate Open Circuit Voltage Test Terminated Voltage Balance Offset Short-Circuit Current Power-Off Current Transition Time Propagation Delay tPHL Propagation Delay tPLH Differential Skew Max. Transmission Rate SP505ACM-L Max. Transmission Rate SP505BCM-L MIN. 50 50 20 +/-4.0 0.9Vcc TYP. 00 00 230 V.28 RECEIVER AC PARAMETERS (Vcc = +5V for AC Parameters) V.10 DRIVER OUTPUT DC PARAMETERS V.10 DRIVER AC PARAMETERS (Vcc = +5V for AC Parameters) 50 50 20 -3.25 4 00 00 230 500 500 V.10 RECEIVER INPUT DC PARAMETERS V.10 RECEIVER AC PARAMETERS (Vcc = +5V for AC Parameters) 50 50 20 20 20 250 250 V.11 DRIVER OUTPUT DC PARAMETERS +/-2.0 0.5VOC V.11 DRIVER OUTPUT AC PARAMETERS (Vcc = +5V for AC Parameters) 50 50 0 6.4 85 85 0 2 8 0 0 20 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 3 TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. ELECTRICAL CHARACTERISTICS MAX +7 +/-0.3 +3.25 +/-60.75 UNITS Volts Volts mA mA kΩ Per Figures 20 and 22 Per Figures 23 and 24 CONDITIONS PARAMETER Common Mode Range Sensitivity Input Current Current w/ 100Ω Termination Input Impedance Propagation Delay tPHL Propagation Delay tPLH Differential Skew Max. Transmission Rate SP505ACM-L Max. Transmission Rate SP505BCM-L Open Circuit Voltage Test Terminated Voltage Offset Source Impedance Short Circuit Impedance Transition Time Propagation Delay tPHL Propagation Delay tPLH Differential Skew Max. Transmission Rate SP505ACM-L Max. Transmission Rate SP505BCM-L Sensitivity Source Impedance Short Circuit Impedance Propagation Delay tPHL Propagation Delay tPLH Differential Skew Max. Transmission Rate SP505ACM-L Max. Transmission Rate SP505BCM-L MIN -7 -3.25 4 80 80 0 6.4 TYP V.11 RECEIVER INPUT DC PARAMETERS V.11 RECEIVER INPUT AC PARAMETERS (Vcc = +5V for AC Parameters) 0 0 20 2 8 30 30 ns ns ns Mbps Mbps Per Figures 33 and 38; CL = 50pF Per Figures 33 and 38; CL = 50pF Per Figures 33; CL = 50pF Per Figure 33; CL = 50pF, fIN = 5MHz Per Figure 33; CL = 50pF, fIN = 8.2MHz Per Figure 6 Per Figure 25 Per Figure 25 Per Figure 27; ZS = V2/V x 50 Ω Per Figure 28 Per Figure 29; 0% to 90% Per Figures 33 and 36; CL = 20pF Per Figures 33 and 36; CL = 20pF Per Figure 33; CL = 20pF Per Figure 33; CL = 20pF, fIN = 5MHz Per Figure 33; CL = 20pF, fIN = 8.2MHz V.35 DRIVER OUTPUT DC PARAMETERS +/-.20 +/-0.44 50 35 30 50 50 0 6.4 90 90 20 2 8 +/-0.66 +/-0.6 50 65 40 0 0 30 Volts Volts Volts Ω Ω ns ns ns ns Mbps Mbps V.35 DRIVER OUTPUT AC PARAMETERS (Vcc = +5V for AC Parameters) V.35 RECEIVER INPUT DC PARAMETERS +/-80 90 35 80 80 0 6.4 0 0 20 2 8 0 65 30 30 mV Ω Ω ns ns ns Mbps Mbps Per Figure 30; ZS = V2/V x 50 Ω Per Figure 3 Per Figures 33 and 38; CL = 20pF Per Figures 33 and 38; CL = 20pF Per Figures 33; CL = 20pF Per Figure 33; CL = 20pF, fIN = 5MHz Per Figure 33; CL = 20pF, fIN = 8.2MHz SP505_00_08308 V.35 RECEIVER INPUT AC PARAMETERS (Vcc = +5V for AC Parameters) Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com 4 TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. ELECTRICAL CHARACTERISTICS MAX. 500 0 UNITS µA µA CONDITIONS Per Figure 32; Drivers disabled DECX = 0000, 0.4V ≤ VO ≤ 2.4V PARAMETER Driver Output 3-state Current Receiver Output 3-state Current MIN. TYP. 00  TRANSCEIVER LEAKAGE CURRENTS TA = +25°C and VCC = +5.0V unless otherwise noted. AC CHARACTERISTICS TYP. MAX. Units CONDITIONS PARAMETER RS-232/V.28 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-232/V.28 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state MIN. DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE 0.70 0.40 0.20 0.40 0.5 0.20 0.20 0.5 2.80 0.0 0.0 0.0 2.60 0.0 0.0 0.5 5.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 0.0 2.0 2.0 2.0 0.0 2.0 2.0 2.0 µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs CL = 00pF, Fig. 34 & 40; S1 closed CL = 00pF, Fig. 34 & 40; S2 closed CL = 00pF, Fig. 34 & 40; S1 closed CL = 00pF, Fig. 34 & 40; S2 closed CL = 00pF, Fig. 34 & 40; S1 closed CL = 00pF, Fig. 34 & 40; S2 closed CL = 00pF, Fig. 34 & 40; S1 closed CL = 00pF, Fig. 34 & 40; S2 closed CL = 00pF, Fig. 34 & 37; S1 closed CL = 00pF, Fig. 34 & 37; S2 closed CL = 5pF, Fig. 34 & 37; S1 closed CL = 5pF, Fig. 34 & 37; S2 closed CL = 00pF, Fig. 34 & 37; S1 closed CL = 00pF, Fig. 34 & 37; S2 closed CL = 5pF, Fig. 34 & 37; S1 closed CL = 5pF, Fig. 34 & 37; S2 closed RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE 0.2 0.0 0.0 0.0 0.0 0.0 0.0 0.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 µs µs µs µs µs µs µs µs CL = 00pF, Fig. 35 & 38; S1 closed CL = 00pF, Fig. 35 & 38; S2 closed CL = 00pF, Fig. 35 & 38; S1 closed CL = 00pF, Fig. 35 & 38; S2 closed CL = 00pF, Fig. 35 & 38; S1 closed CL = 00pF, Fig. 35 & 38; S2 closed CL = 00pF, Fig. 35 & 38; S1 closed CL = 00pF, Fig. 35 & 38; S2 closed SP505_00_08308 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com 5 TA = +25°C and VCC = +5.0V unless otherwise noted. AC CHARACTERISTICS TYP. MAX. UNITS CONDITIONS PARAMETER RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.28 Driver V.28 Driver V.28 Receiver V.28 Receiver V. Driver V. Driver V. Receiver V. Receiver V.0 Driver V.0 Driver V.0 Receiver V.0 Receiver V.35 Driver V.35 Driver V.35 Receiver V.35 Receiver MIN. RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE (Continued) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 00 00 20 20 2 2 3 3 5 5 5 5 4 4 6 6 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 µs µs µs µs µs µs µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 00pF, Fig. 35 & 39; S1 closed CL = 00pF, Fig. 35 & 39; S2 closed CL = 5pF, Fig. 35 & 39; S1 closed CL = 5pF, Fig. 35 & 39; S2 closed CL = 00pF, Fig. 35 & 39; S1 closed CL = 00pF, Fig. 35 & 39; S2 closed CL = 5pF, Fig. 35 & 39; S1 closed CL = 5pF, Fig. 35 & 39; S2 closed | (tPHL)Tx1 - (tPHL)Tx6,7 | | (tPLH)Tx1 - (tPLH)Tx6,7 | | (tPHL)Rx1 - (tPHL)Rx2,7 | | (tPLH)Rx1 - (tPLH)Rx2,7 | | (tPHL)Tx1 - (tPHL)Tx6,7 | | (tPLH)Tx1 - (tPLH)Tx6,7 | | (tPHL)Rx1 - (tPHL)Rx2,7 | | (tPLH)Rx1 - (tPLH)Rx2,7 | | (tPHL)Tx2 - (tPHL)Tx3,4,5 | | (tPLH)Tx2 - (tPLH)Tx3,4,5 | | (tPHL)Rx2 - (tPHL)Rx3,4,5 | | (tPLH)Rx2 - (tPLH)Rx3,4,5 | | (tPHL)Tx1 - (tPHL)Tx6,7 | | (tPLH)Tx1 - (tPLH)Tx6,7 | | (tPHL)Rx1 - (tPHL)Rx2,7 | | (tPLH)Rx1 - (tPLH)Rx2,7 | TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 33, 36 and 38) POWER REQUIREMENTS PARAMETER VCC ICC (No Mode Selected) ICC (V.28/RS-232) ICC (V./RS-422) ICC (RS-449) ICC (V.35) ICC (EIA-530) ICC (EIA-530A) ICC (V.36) MIN. 4.75 TYP. 5.00 30 60 300 250 05 260 250 65 MAX. 5.25 UNITS Volts mA mA mA mA mA mA mA mA SP505_00_08308 CONDITIONS All ICC values are with Vcc = +5V, T = 25°C, all drivers loaded to their specified maximum load and all drivers are active at their maximum specified data transmission rates Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com 6 TEST CIRCUITS A A VOC 3 kΩ VT C C Figure . V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage A A 7 kΩ VT O s c illo s c o pe Is c C Scope used f or sle w r ate measurement. C Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current V C C = 0V A A Ix 3 kΩ ±2V 2 50 0 pF O s c illo s c o pe C C Figure 5. V.28 Driver Output Power-Off Impedance Figure 6. V.28 Driver Output Rise/Fall Times Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 7 A A I ia ±15V V oc C C Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias A A 3 . 9k Ω VOC 4 5 0Ω Vt C C Figure 9. V.0 Driver Output Open-Circuit Voltage Figure 0. V.0 Driver Output Test Terminated Voltage V C C = 0V A A Ix ±0 .2 5V Is c C C Figure . V.0 Driver Output Short-Circuit Current Figure 2. V.0 Driver Output Power-Off Current Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 8 A A Iia ±10V 4 5 0Ω O s c illo s c o pe C C Figure 3. V.0 Driver Output Transition Time Figure 4. V.0 Receiver Input Current V. 1 0 R E C E I V E R +3 . 2 5mA A V OCA 3 . 9k Ω VOC V OCB – 10 V – 3V +3 V +1 0V C B Ma x imum Input C urre nt ve rs us Vo ltage – 3. 25 mA Figure 5. V.0 Receiver Input IV Graph Figure 6. V. and V.35 Driver Output Open-Circuit Voltage A A 50Ω VT 50Ω Is a B B V OS Is b C C Figure 7. V. Driver Output Test Terminated Voltage Figure 8. V. Driver Output Short-Circuit Current Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 9 V C C = 0V A A Ixa ±0 .2 5V Iia ±1 0V B B C C V C C = 0V A A ±0 .2 5V ±1 0V B Ixb B Iib C C Figure 9. V. Driver Output Power-Off Current Figure 20. V. Receiver Input Current V. 1 1 R E C E I V E R A 50Ω O s c illo s c o pe +3 . 2 5mA 50Ω B VE – 10 V 50Ω – 3V +3 V +1 0V C Ma ximum Input C urre nt ve rs us Voltage – 3. 25 mA Figure 22. V. Receiver Input IV Graph Figure 2. V. Driver Output Rise/Fall Time Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 0 V. 1 1 R E C E I V E R A Iia ±6 V w / O pt io n al C abl e T e rm i n a ti o n (1 00 Ω t o 15 0Ω ) i [mA ] = V [ V ] / 0 . 1 i [mA ] = ( V [V ] – 3) / 4 . 0 – 6V – 3V +3 V +6 V 100Ω to 150Ω B i [mA ] = ( V [V ] – 3) / 4 . 0 C i [mA ] = V [ V ] / 0 . 1 Ma x imum Input C urre nt ve rs us Voltage Figure 24. V. Receiver Input Graph w/ Termination A A ±6 V 100Ω to 150Ω Iib B 50Ω VT 50Ω B VOS C C Figure 23. V. Receiver Input Current w/ Termination Figure 25. V.35 Driver Output Test Terminated Voltage V1 A 50Ω VT 50Ω B VOS A 50Ω 2 4kH z , 55 0 mV p-p S ine W a ve V2 B C C Figure 26. V.35 Driver Output Offset Voltage Figure 27. V.35 Driver Output Source Impedance Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308  A A 50Ω O s c illo s c o pe B ISC 50Ω B ±2V 50Ω C C Figure 28. V.35 Driver Output Short-Circuit Impedance Figure 29. V.35 Driver Output Rise/Fall Time A V1 A 50Ω 2 4kH z , 55 0 mV p-p S ine W a ve V2 B Isc B ±2V C C Figure 30. V.35 Receiver Input Source Impedance Figure 3. V.35 Receiver Input Short-Circuit Impedance A ny one of the two c onditions for dis a bling the drive r. V CC = +5V 0 0 0 0 DEC 3 DEC 2 DEC 1 DEC 0 V CC A IZ S C ±15 V TIN A B CL1 A B ROUT 15pF CL2 P-P L ogic “1 ” fIN (50% Duty Cycle, 2.5V B ) Figure 32. Driver Output Leakage Current Test Figure 33. Driver/Receiver Timing Test Circuit Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 2 O u tpu t U nde r Te s t 5 00 Ω CL S1 VCC R ec e ive r O u tpu t CR L Te s t P o int S1 1K Ω S2 1K Ω VCC S2 Figure 34. Driver Timing Test Load Circuit Figure 35. Receiver Timing Test Load Circuit f ≥ 5MHz; tR ≤ 10ns; tF ≤ 10ns 1.5V tPLH tPHL 1/2VO tDPLH tDPHL 1.5V DRIVER INPUT DRIVER OUTPUT +3V 0V A B VO 1/2VO DIFFERENTIAL VO+ OUTPUT 0V VA - VB VO– tSKEW = │tDPLH - tDPHL │ tR tF Figure 36. Driver Propagation Delays TXENABLE +3V DECX A, B 0V 5V VOL VOH 0V f = 1MHz; tR ≤ 10ns; tF ≤ 10ns 1.5V tZL 2.3V Output normally LOW Output normally HIGH 1.5V tLZ 0.5V 0.5V tHZ A, B 2.3V tZH Figure 37. Driver Enable and Disable Times A–B V 0D2 + V 0D2 – V OH V OL tPLH f > 5M H z ; tR < 10 ns ; tF < 10 ns 0V I NP UT O UT P UT (V OH - V OL )/2 tPHL (V OH - V OL )/2 0V R E C E I VE R O UT tSKEW = | tPHL - tPLH | Figure 38. Receiver Propagation Delays Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 3 D E C X +3V R C V R ENABLE 0V f = 1 MH z ; tR ≤ 1 0n s ; tF ≤ 1 0n s 1 .5 V tZL 1 .5 V O utput no rma lly L O W O utput no rma lly H I G H 1 .5 V tLZ 0 .5 V 0 .5 V tHZ 5V R E C E I VE R O UT V IL V IH R E C E I VE R O UT 0V 1 .5 V tZH Figure 39. Receiver Enable and Disable Times +3V DE C X or T x_ E n able 0V 0V T OUT V OL f = 6 0kH z ; tR < 1 0 ns ; tF < 10 ns 1 .5 V tZL V OL – . 5V 1 .5 V tLZ O utput LO W V OL – . 5V +3V DE C X or T x_ E n able 0V T OUT V OH 0V f = 6 0kH z ; tR < 1 0 ns ; tF < 10 ns 1 .5 V tZH V OH – . 5V O utput H I G H 1 .5 V tHZ V OH – . 5V Figure 40. V.28 (RS-232) and V.0 (RS-423) Driver Enable and Disable Times Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 4 INPUT OUTPUT Figure 4. Typical V.28 Driver Output Waveform Figure 42. Typical V.0 Driver Output Waveform INPUT AOUT BOUT DIFFOUT Figure 43. Typical V. Driver Output Waveform Figure 44. Typical V.35 Driver Output Waveform Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 5 PINOUT… Pin 6 — SD(a) — Analog Out — Send data, inverted; sourced from TxD. 77 SCT(b) 76 SCT(a) 69 DM(b) 68 DM(a) 71 RD(b) 70 RD(a) 67 CS(b) 66 CS(a) 61 SD(a) 75 GND 72 GND 64 GND 65 TT(b) 63 TT(a) 78 DSR 80 CTS 79 SCT 74 VCC 73 VCC 62 VCC Pin 63 — TT(a) — Analog Out — Terminal Timing, inverted; sourced from TxC Pin 65 — TT(b) — Analog Out — Terminal Timing, non–inverted; sourced from TxC. Pin 70 — RD(a) — Receive Data, analog input; inverted; source for RxD. Pin 7 — RD(b) — Receive Data; analog input; non-inverted; source for RxD. Pin 76 — SCT(a) — Serial Clock Transmit; analog input, inverted; source for SCT. Pin 77 — SCT(b) — Serial Clock Transmit: analog input, non–inverted; source for SCT Pin 79 — SCT — Serial Clock Transmit; TTL output; sources from SCT(a) and SCT(b) inputs. CONTROL LINE GROUP Pin 3 — DTR — Data Terminal Ready; TTL input; source for TR(a) and TR(b) outputs. Pin 6 — RTS — Ready To Send; TTL input; source for RS(a) and RS(b) outputs. Pin 7 — RL — Remote Loopback; TTL input; source for RL(a) and RL(b) outputs. Pin 9 — DCD— Data Carrier Detect; TTL output; sourced from RR(a) and RR(b) inputs. Pin 2 — RI — Ring In; TTL output; sourced from IC(a) and IC(b) inputs. Pin 24 — LL — Local Loopback; TTL input; source for LL(a) and LL(b) outputs. Pin 35 — RR(a)— Receiver Ready; analog input, inverted; source for DCD. Pin 36 — RR(b)— Receiver Ready; analog input, non-inverted; source for DCD. Pin 39 — IC(a)— Incoming Call; analog input, inverted; source for RI. Pin 40 — IC(b)— Incoming Call; analog input,non-inverted; source for RI. SP505_00_08308 RxD 1 SDEN 2 TREN 3 RSEN 4 LLEN 5 TTEN 6 SCTEN7 LATCH 8 DEC3 9 DEC2 10 DEC1 11 DEC0 12 DTR 13 TxD 14 TxC 15 RTS 16 RL 17 RLEN 18 DCD 19 RxC 20 60 GND 59 SD(b) 58 TR(a) 57 GND 56 TR(b) 55 VCC 54 RS(a) 53 GND 52 RS(b) 51 LL(a) 50 GND 49 LL(b) 48 VCC 47 RL(a) 46 GND 45 RL(b) 44 ST(b) 43 GND 42 ST(a) 41 VCC SP505 STEN 23 ST 22 RI 21 GND 29 C – 30 GND 34 IC(a) 39 RR(a) 35 RR(b) 36 RT(a) 37 PIN ASSIGNMENTS… CLOCK AND DATA GROUP Pin  — RxD — Receive Data; TTL output, sourced from RD(a) and RD(b) inputs. Pin 4 — TxD — TTL input ; transmit data source for SD(a) and SD(b) outputs. Pin 5 — TxC — Transmit Clock; TTL input for TT driver outputs. Pin 20 — RxC — Receive Clock; TTL output sourced from RT(a) and RT(b) inputs. Pin 22 — ST — Send Timing; TTL input; source for ST(a) and ST(b) outputs. Pin 37 — RT(a) — Receive Timing; analog input, inverted; source for RxC. Pin 38 — RT(b) — Receive Timing; analog input, non-inverted; source for RxC. Pin 42 — ST(a) — Send Timing; analog output, inverted; sourced from ST. Pin 44 — ST(b) — Send Timing; analog output, non-inverted; sourced from ST. Pin 59 — SD(b) — Analog Out — Send data, non-inverted; sourced from TxD. Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com RT(b) 38 IC(b) 40 LL 24 VCC 25 C + 26 VDD 27 C2+ 28 C2– 31 VCC 33 VSS 32 1 1 6 Pin 45 — RL(b) — Remote Loopback; analog output, non-inverted; sourced from RL. Pin 47 — RL(a) — Remote Loopback; analog output inverted; sourced from RL. Pin 49— LL(b) — Local Loopback; analog output, non-inverted; sourced from LL. Pin 5 — LL(a) — Local Loopback; analog output, inverted; sourced from LL. Pin 52 — RS(b) — Ready To Send; analog output, non-inverted; sourced from RTS. Pin 54 — RS(a) — Ready To Send; analog output, inverted; sourced from RTS. Pin 56 — TR(b) — Terminal Ready; analog output, non-inverted; sourced from DTR. Pin 58 — TR(a) — Terminal Ready; analog output, inverted; sourced from DTR. Pin 66 — CS(a)— Clear To Send; analog input, inverted; source for CTS. Pin 67 — CS(b)— Clear To Send; analog input, non-inverted; source for CTS. Pin 68 — DM(a)— Data Mode; analog input, inverted; source for DSR. Pin 69 — DM(b)— Data Mode; analog input, non-inverted; source for DSR Pin 78 — DSR— Data Set Ready; TTL output; sourced from DM(a), DM(b) inputs. Pin 80 — CTS— Clear To Send; TTL output; sourced from CS(a) and CS(b) inputs. CONTROL REGISTERS Pins 2 — SDEN — Enables TxD driver, active low; TTL input. Pins 3 — TREN — Enables DTR driver, active low; TTL input. Pins 4 — RSEN — Enables RTS driver, active low; TTL input. Pins 5 — LLEN — Enables LL driver, active low; TTL input. Pin 6 — TTEN — Enables TT driver, active low; TTL input. Pin 7 — SCTEN — Enables SCT receiver; active high; TTL input. Pin 8 — LATCH — Latch control for decoder bits (pins 9-2), active low. Logic high input will make decoder transparent. Pins 2–9 — DEC0 – DEC3 — Transmitter and receiver decode register; configures transmitter and receiver modes; TTL inputs. Pin 8 — RLEN — Enables RL driver; active low; TTL input. Pin 23 — STEN — Enables ST driver; active low; TTL input. POWER SUPPLIES Pins 25, 33, 4, 48, 55, 62, 73, 74 — VCC — +5V input. Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 — GND — Ground. Pin 27 — VDD +0V Charge Pump Capacitor — Connects from VDD to VCC. Suggested capacitor size is 22µF, 6V. Pin 32 — VSS –0V Charge Pump Capacitor — Connects from ground to VSS. Suggested capacitor size is 22µF, 6V. Pins 26 and 30 — C+ and C– — Charge Pump Capacitor — Connects from C+ to C–. Suggested capacitor size is 22µF, 6V. Pins 28 and 3 — C2+ and C2– — Charge Pump Capacitor — Connects from C2+ to C2–. Suggested capacitor size is 22µF, 6V. Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 7 FEATURES… The SP505 is a highly integrated serial transceiver that allows software control of its interface modes. Similar to the SP504, the SP505 offers the same hardware interface modes for RS-232 (V.28), RS-422A (V.), RS-449, RS-485, V.35, EIA-530 and includes V.36 and EIA-530A. The interface mode selection is done via a 4–bit switch for the drivers and receivers. The SP505 is fabricated using low–power BiCMOS process technology, and incorporates a Exar–patented (5,306,954) charge pump allowing +5V only operation. Each device is packaged in an 80–pin JEDEC Quad FlatPack package. The SP505 is ideally suited for wide area network connectivity based on the interface modes offered and the driver and receiver configurations. The SP505 has seven (7) independent drivers and seven (7) independent receivers. In V.35 mode, the SP505 includes the necessary components and termination resistors internal within the device for compliant V.35 operation. THEORY OF OPERATION The SP505 is made up of five separate circuit blocks — the charge pump, drivers, receivers, decoder and switching array. Each of these circuit blocks is described in more detail below. Charge–Pump The SP505 charge pump is based on the SP504 design where Exar's patented charge pump design (5,306,954) uses a four–phase voltage shifting technique to attain symmetrical 0V power supplies. The charge pump still requires external capacitors to store the charge. In addition the SP504 charge pump supplies +0V or +5V on VSS and VDD depending on the mode of operation. There is a free–running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. The SP505 charge pump is used for RS232 where the output voltage swing is typically +0V and also used for RS-423. However, RS-423 requires the voltage swing on the driver output be between 8 +4V to +6V during an open-circuit (no load). The charge pump would need to be regulated down from +0V to +5V. A typical +0V charge pump would require external clamping such as 5V zener diodes on VDD and VSS to ground. The +5V output has symmetrical levels as in the +0V output. The +5V is used in the following modes where RS-423 (V.0) are used: RS-449, EIA-530, EIA-530A and V.36. Phase 1 (±10V) — VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C and C2 are initially charged to +5V. Cl+ is then switched to ground and the charge on C– is transferred to C2–. Since C2+ is connected to +5V, the voltage potential across capacitor C2 is now 0V. Phase 1 (±5V) — VSS & VDD charge storage and transfer — With the C and C2 capacitors initially charged to +5V, Cl+ is then switched to ground and the charge on C– is transferred to the VSS storage capacitor. Simultaneously the C2– is switched to ground and 5V charge on C2+ is transferred to the VDD storage capacitor. V CC = + 5V + 5V C1 + – C4 + – C2 –5 V + – V DD S tora g e C a pa ci to r – + V SS S tora g e C a pa ci to r –5 V C3 Figure 45. Charge Pump Phase  for +0V. V CC = + 5V + 5V C1 + – C4 + – C2 + – V DD S tora g e C a pa ci to r –5 V – + V SS S tora g e C a pa ci to r C3 Figure 46. Charge Pump Phase  for +5V. Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 Phase 2 (±10V) — VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to ground, and transfers the generated –l0V or the generated –5V to C3. Simultaneously, the positive side of capacitor C  is switched to +5V and the negative side is connected to ground. Phase 2 (±5V) — VSS & VDD charge storage — C+ is reconnected to VCC to recharge the C capacitor. C2+ is switched to ground and C2– is connected to C3. The 5V charge from Phase  is now transferred to the VSS storage capacitor. VSS receives a continuous charge from either C or C2. With the C capacitor charged to 5V, the cycle begins again. Phase 3 — VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C produces –5V in the negative terminal of C, which is applied to the negative side of capacitor C2. Since C2+ is at +5V, the voltage potential across C2 is l0V. For the 5V output, C2+ is connected to ground so that the potential on C2 is only +5V. Phase 4 — VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to ground and transfers the generated l0V or the generated 5V across C2 to C4, the VDD storage capacitor. Again, simultaneously with this, the positive side of capacitor C is switched to +5V and the negative side is connected to ground, and the cycle begins again. Since both VDD and VSS are separately generated from VCC in a no–load condition, VDD and VSS will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 5kHz. The external capacitors must be a minimum of 22µF with a 6V breakdown rating. 9 External Power Supplies For applications that do not require +5V only, external supplies can be applied at the V+ and V– pins. The value of the external supply voltages must be no greater than +l0.5V. The tolerance should be +5% from +0V. The current drain for the supplies is used for RS-232 and RS-423 drivers. For the RS-232 driver, the current requirement will be 3.5mA per driver. The RS-423 driver worst case current drain will be mA per driver. Power sequencing is required for the SP505. The supplies must be sequenced accordingly: +0V, +5V and –0V. It is important to prevent VSS from starting up before VCC or VDD. V CC = + 5V C4 C1 + – C2 + – + – V DD S tora g e C a pa ci to r – 1 0V – + V SS S tora g e C a pa ci to r C3 Figure 47. Charge Pump Phase 2 for +0V. V CC = + 5V C4 C1 + – C2 + – + – V DD S tora g e C a pa ci to r –5 V – + V SS S tora g e C a pa ci to r C3 Figure 48. Charge Pump Phase 2 for +5V. V CC = + 5V + 5V C1 + – C4 + – C2 –5 V + – V DD S tora g e C a pa ci to r – + V SS S tora g e C a pa ci to r –5 V C3 Figure 49. Charge Pump Phase 3. V CC = + 5V + 10V C1 + – C4 + – C2 + – V DD S tora g e C a pa ci to r – + V SS S tora g e C a pa ci to r C3 Figure 50. Charge Pump Phase 4. SP505_00_08308 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com Drivers The SP505 has seven (7) enhanced independent drivers. Control for the mode selection is done via a four–bit control word. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line signal levels. Table  shows the mode of each driver in the different interface modes that can be selected. There are four basic types of driver circuits — V.28, V., V.0 and V.35. V.28 Drivers The V.28 drivers output single–ended signals with a minimum of +5V (with 3kΩ & 2500pF loading), and can operate to at least 20kbps under full load. Since the SP505 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +0V. The V.28 drivers are used in RS-232 mode for all signals, and also in V.35 mode where four (4) drivers are used as the control line signals (DTR, RTS, LL, and RL). V.10 Drivers The V.0 (RS-423) drivers are also single– ended signals which produce open circuit VOL and VOH measurements of +4.0V to +6.0V. When terminated with a 450Ω load to ground, the driver output will not deviate more than 0% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.0 drivers are used in RS-449, EIA530, EIA-530A and V.36 modes as Category II signals from each of their corresponding specifications. V.11 Drivers The third type of driver is a V. (RS-422) type differential driver. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain typically +2.2V differential output levels with 20 a load of 00Ω. The signal levels and drive capability of these drivers allow the drivers to also support RS-485 requirements of ±.5V minimum differential output levels with a 54Ω load. The driver is designed to operate over a common mode range of +2V to -7V, which follows the RS-485 specification. This also covers the +7V to -7V common mode range for V. (RS-422) requirements. The V. drivers are used in RS-449, EIA-530, EIA530A and V.36 modes as Category I signals which are used for clock and data signals. V.35 Drivers The fourth type of driver is the V.35 driver. These drivers were specifically designed to comply with the requirements of V.35. Unique to the industry, the Sipex's V.35 driver architecture used in the SP505 does not need external termination resistors to operate and comply with V.35. This simplifies existing V.35 implementations that use external termination schemes. The V.35 drivers can produce +0.55V driver output signals with minimum deviation (maximum 20%) given an equivalent load of 00Ω. With the help of internal resistor networks, the drivers achieve the 50Ω to 50Ω source impedance and the 35Ω to 65Ω short-circuit impedance for V.35. The V.35 driver is disabled and transparent when the decoder is in all other modes. All of the differential drivers; V. (RS-422) and V.35, can operate over 0Mbps. Driver Enable and Input All the drivers in the SP505 contain individual enable lines which can tri-state the driver outputs when a logic "" is applied. This simplifies half-duplex configurations for some applications and also provides simpler DTE/DCE flexibility with one integrated circuit. The driver inputs are both TTL or CMOS compatible. Each driver input should have a pull-down or pull-up resistor so that the output will be at a defined state. Unused driver inputs should not be left floating. Receivers The SP505 has seven (7) independent receivers which can be programmed for the different interface modes. Control for the SP505_00_08308 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com mode selection is done via a 4–bit control word, which is the same as the driver's 4-bit control word. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line receivers. Table 2 shows the mode of each receiver in the different interface modes that can be selected. There are three basic types of receiver circuits — V.28, V.0, and V.. V.28 Receivers The V.28 receiver is single–ended and accepts V.28 signals from the V.28 driver. The V.28 receiver has an operating voltage range of +5V and can receive signals down to +3V. The input sensitivity complies with RS-232 and V.28 specifications at +3V. The input impedance is 3kΩ to 7kΩ in accordance to RS-232 and V.28 over a +5V input range. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic "" and a +0.8V maximum for a logic "0". V.28 receivers are used in RS-232 mode for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The V.28 receivers can operate to at least 20kbps. V.10 Receivers The V.0 receivers are also single–ended as with the V.28 receivers but have an input threshold as low as +200mV. The input impedance is guaranteed to be greater than 4KΩ, with an operating voltage range of +7V. The V.0 receivers can operate to at least 20kbps. V.0 receivers are used in RS449, EIA-530, EIA-530A and V.36 modes as Category II signals as indicated by their corresponding specifications. V.11 Receivers The third type of receiver is a differential which supports V. and RS-485 signals. This receiver has a typical input impedance of 0kΩ and a typical differential threshold of +200mV, which complies with the V. specification. Since the characteristics of the 2 V. receivers are actually subsets of RS485, the V. receivers can accept RS-485 signals. However, these receivers cannot support 32-transceivers on the signal bus due to the lower input impedance as specified in the RS-485 specification. Three receivers (RxD, RxC, and SCT) include a typical 20Ω cable termination resistor across the A and B inputs. The resistor for the three receivers is switched on when the SP505 is configured in a mode which uses V. receivers. The V. cable termination resistor is switched off when the receiver is disabled or in another operating mode not using V. receivers. The V. receivers are used in X.2, RS-449, EIA-530, EIA-530A and V.36 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.0 circuits. The differential receivers can receive signals over 0Mbps. V.35 Receiver The V. receivers are also used for the V.35 mode. Unlike the older implementations of differential receivers used for V.35, the SP505 contains an internal resistor termination network that ensures a V.35 input impedance of 00Ω (+0Ω) and a short-circuit impedance of 50Ω (+5Ω). The traditional V.35 implementations required external termination resistors to achieve the proper V.35 impedances. The internal network is connected via low on-resistance FET switches when the decoder is changed to V.35 mode. These FET switches can accept input signals of up to +5V without any forward biasing and other parasitic affects. The V.35 termination resistor network is switched off when the receiver is disabled either by the decoder or receiver enable pin. The termination network is transparent when all other modes are selected. The V.35 receivers can operate over 0Mbps. To In ve rtin g In pu t o f R e c eive r V.11 TERMINA TION MODE [0100] R IN [ a] V.35 MODE rON = 2 0 Ω rON = 1 Ω 51Ω rON = 1 Ω 1 2 4Ω 51Ω To N on -In ve r tin g In put o f R e c eive r R IN [ b] Figure 51. Simplified RIN Termination Circuit SP505_00_08308 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com Receiver Enable and Output Only one receiver includes an enable line. The SCTEN input for the SCT receiver can enable or tri-state the output of the receiver. When the pin is at a logic "0", the receiver output is high impedance and any input termination internal connected is switched off. The inputs will be at approximately 0kΩ during tri-state. All receivers include a fail-safe feature that outputs a logic "" when the receiver inputs are open. The differential receivers allocated for data and clock signals (RxD, RxC, and SCT) have advanced fail-safe that outputs a logic "" when the inputs are either open, shorted, or terminated. Other discrete or integrated implementations require external pull-up and pull-down resistors to define the receiver output state. For single-ended V.28 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high ("") at the receiver outputs. The single-ended V.0 receivers produce a logic LOW ("0") on the output when the inputs are open. This is due to an internal pull-up device connected to the input. The differential receivers have the same internal pull-up device on the non-inverting input which produces a logic HIGH ("") at the receiver output, representing an "OFF" state to the HDLC controller. The three differential receivers when configured in V.35 mode (RxD, RxC & SCT) will also include fail-safe even when the internal termination resistor network is connected and the inputs are either shorted or floating. Decoder The SP505 has the ability to change the interface mode of the drivers or receivers via a 4–bit switch. The decoder for the drivers and receivers can be latched through a control pin. The control word can be latched either high or low to write the appropriate code into the SP505. The codes shown in Tables  and 2 are the only specified, valid modes for the SP505. Undefined codes may represent other interface modes not specified (consult the factory for more information). The drivers and receivers are controlled with the data bits labeled DEC3–DEC0. All of the drivers outputs and receiver outputs can be put into tri-state mode by writing 0000 to the driver decode switch. All internal termination networks are switched off during this mode. Individual tri-state capability is possible for all drivers through each driver's own enable control input. The SCT receiver also contains an individual enable input. When this control pin is disabled (logic "0"), the V. and V.35 input termination is deactivated. The 0000 decoder word will override the enable control line for the one receiver (SCT). The SP505 contains internal loopback capabilities for self-diagnostic tests. Loopback is enabled through the decoder. To initiate single-ended mode loopback, the decoder word is 00. To initiate differential mode loopback, the decoder word is 0. The minimum transmission rates into the SP505 under loopback conditions are 20kbps for single-ended mode and 5Mbps for differential mode. The driver outputs are tri-stated and the receiver inputs are disabled during loopback. The receiver input impedance during loopback is approximately 0kΩ. The SP505 is equipped with a latch control for the four (4) decoder bits. The latch control pin is pin 8 of the SP505. The latch control is active low, a logic low on pin 8 will latch the decoder signals. A logic "" on pin 8 will force the latch to be transparent to the user. A pulse width of at least 30ns is required to latch the decoder for the next mode. The resultant output is typically 600ns after the latch control pin is toggled assuming that the decoder word is set. NET1/2 & TBR2 European Compliancy As with all of Sipex's previous multi-protocol serial transceiver ICs, the drivers and receivers have been designed to meet all the requirements to NET/2. The SP505 is internally tested to all the NET/2 physical layer testing parameters and the ITU Series V specifications. With the emergence of ETSI TBR2 (Technical Basis for Regulation) document now in place as an alternative for European compliancy, Sipex has tested the SP505 to TBR2 specifications to ensure "CE" approval for either testing method. SP505_00_08308 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com 22 The SP505 was externally tested by TUV Telecom Services, Division of TUV Rheinland, and passed both NET/2 and TBR2 requirements. Test reports (NET2/0520/98 for NET/2 and CTR2/050/98 for TBR2) can be furnished upon request. Please note that although the SP505 adheres to NET/2 testing; any complex or unusual configuration should be doublechecked to ensure NET compliance. Consult factory for details. SP505 Driver Mode Selection Pin Label DEC3 – DEC 0 SD(a) SD(b) TR(a) TR(b) RS(a) RS(b) RL(a) RL(b) LL(a) LL(b) ST(a) ST(b) TT(a) TT(b) Mode: 0000 tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state tri-state RS232 0010 V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.28 tri-state V.35 1110 V.35– V.35+ V.28 tri-state V.28 tri-state V.28 tri-state V.28 tr i-state V.35– V.35+ V.35– V.35+ RS422 w/Term 0100 V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ RS422 0101 V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ RS449 1100 V.11– V.11+ V.11– V.11+ V.11– V.11+ V.10 tri-state V.10 tri-state V.11– V.11+ V.11– V.11+ EIA530 1101 V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.10 tri-state V.11– V.11+ V.11– V.11+ EIA-530A 1111 V.11– V.11+ V.10 tri-state V.11– V.11+ V.11– V.11+ V.10 tri-state V.11– V.11+ V.11– V.11+ V.36 0110 V.11– V.11+ V.10 tri-state V.10 tri-state V.10 tri-state V.10 tri-state V.11– V.11+ V.11– V.11+ Table . SP505 Driver Decoder Table SP505 Receiver Mode Selection Pin Label Mode: 0000 >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND RS232 0010 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.35 1110 V.35– V.35+ V.35– V.35+ V.28 V.28 V.28 V.28 >10k Ω to GND V.35– V.35+ RS422 w/Term 0100 120 Ω RS422 0101 V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ RS449 1100 120 Ω EIA530 1101 120 Ω EIA-530A 1111 120 Ω V.36 0110 V.11+ V.11– V.11+ V.10 >10k Ω to GND V.10 >10kΩ to GND V.10 >10kΩ to GND V.10 V.11– V.11+ 120 Ω 120 Ω 120 Ω DEC3 – DEC 0 RD(a) RD(b) RT(a) RT(b) CS(a) CS(b) DM(a) DM(b) RR(a) RR(b) IC(a) IC(b) SCT(a) SCT(b) V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11+ V.11– V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.10 V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.11– V.11+ V.10 V.11– V.11+ V.11– V.11+ V.11– V.11+ V.10 V.11– >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND 120 Ω 120 Ω 120 Ω >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND >10k Ω to GND V.11– V.11+ V.10 V.11– V.11+ >10kΩ to GND 120 Ω >10kΩ to GND 120 Ω >10kΩ to GND >10kΩ to GND 120 Ω 120 Ω V.11– V.11+ V.11– V.11+ Table 2. SP505 Receiver Decoder Table Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 23 120 Ω (SEE PINOUT FOR VCC PINS) 1N5819 22µF 10µF 22µF 22µF +5V 25 VCC 27 26 30 28 31 22µF VDD C1+ C1- C2+ C232 Charge Pump VSS A RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM (b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 IC(b) 40 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 9 10 11 12 8 LATCH B 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RS-422 Mode Input Word DECODER LATCH 0 1 0 0 MODEX SP505 A — Receiver Tr-State circuitry V.11 & V.35 termination resistor c ircuitry ( RxD, RxC & SCT) . B — Driver Tri-State circuitry & V.35 Termination circuitry (TxD, TxC & ST) . (SEE PINOUT ASSIGNMENTS FOR GROUND PINS) Figure 52. SP505 Typical Operating Circuit Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 24 MODE: RS-232 (V.28) DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 0 0 1 0 14 TxD RD(a) 70 RxD 1 RT(a) 37 RxC 20 61 SD(a) 2 SDEN 13 DTR 58 TR(a) 3 TREN CS(a) 66 CTS 80 16 RTS 54 RS(a) 4 RSEN DM(a) 68 DSR 78 17 RL 47 RL(a) 18 RLEN RR(a) 35 DCD 19 24 LL 51 LL(a) 5 LLEN IC(a) 39 RI 21 22 ST 42 ST(a) 23 STEN 15 TxC 63 TT(a) 6 TTEN SCT(a) 76 SCT 79 SCTEN 7 RECEIVERS DRIVERS Figure 53. Mode Diagram — RS-232 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 25 MODE V.35 DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 1 1 0 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 V.35 Ntwk V.35 Ntwk 14 TxD V.35 Ntwk 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 3 TREN 16 RTS 54 RS(a) 4 RSEN RxC 20 RT(b) 38 CS(a) 66 CTS 80 DM(a) 68 DSR 78 17 RL 47 RL(a) 18 RLEN RR(a) 35 DCD 19 24 LL 51 LL(a) 5 LLEN V.35 Ntwk IC(a) 39 RI 21 SCT(a) 76 V.35 Ntwk 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC V.35 Ntwk SCT 79 SCTEN 7 SCT(b) 77 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 54. Mode Diagram — V.35 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 26 MODE: RS-422 (w/ termination) DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 0 1 0 0 RD(a) 70 RxD 1 RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 IC(b) 40 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 120 Ω 120 Ω 120 Ω 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 55. Mode Diagram — RS-422 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 27 MODE: RS-449 DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 1 0 0 RD(a) 70 RxD 1 120 Ω 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 120 Ω RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 18 RLEN 24 LL 51 LL(a) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 120 Ω 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 56. Mode Diagram — RS-449 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 28 MODE: RS-422 (w/o termination) DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 0 1 0 1 RD(a) 70 RxD 1 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 49 LL(b) 5 LLEN 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RD(b) 71 RT(a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 IC(b) 40 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 RECEIVERS DRIVERS Figure 57. Mode Diagram — RS-422 w/o termination Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 29 MODE: EIA-530 DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 RD(a) 70 RxD 1 RD(b) 71 RT (a) 37 RxC 20 RT (b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 SCT(a) 76 120 Ω 120 Ω 120 Ω 1 0 1 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 51 5 22 42 44 23 15 63 65 6 LL LL(a) LLEN ST ST(a) ST(b) STEN TxC TT(a) TT(b) TTEN SCT 79 SCTEN 7 SCT(b) 77 RECEIVERS DRIVERS Figure 58. Mode Diagram — EIA-530 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 30 MODE: EIA-530A DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 RD(a) 70 RxD 1 RD(b) 71 RT (a) 37 RxC 20 RT (b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 120 Ω 120 Ω 1 1 1 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 LL 51 LL(a) 5 LLEN RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 120 Ω 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 59. Mode Diagram — EIA-530A Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 3 MODE:V.36 DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 0 1 1 0 RD(a) 70 RxD 1 RD(b) 71 RT (a) 37 RxC 20 RT (b) 38 CS(a) 66 CTS 80 120 Ω 120 Ω 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 3 TREN 16 RTS 54 RS(a) 4 RSEN DM(a) 68 DSR 78 17 RL 47 RL(a) 18 RLEN RR(a) 35 DCD 19 24 LL 51 LL(a) 5 LLEN IC(a) 39 RI 21 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 120 Ω 22 ST 42 ST(a) 44 ST(b) 23 STEN 15 TxC 63 TT(a) 65 TT(b) 6 TTEN RECEIVERS DRIVERS Figure 60. Mode Diagram — V.36 Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 32 LOOPBACK MODE... The SP505 is equipped with two loopback modes. Single-ended loopback internally connects V.28 driver outputs to V.28 receiver inputs. The signal path is non-inverting and will support data rates up to 20kbps. The propagation delay times are as specified in the electrical specifications. To initiate a single-ended loopback, the code "00" should be written to the driver decoder. Differential loopback is implemented by applying "0" to the driver decoder. This MODE: Single-Ended Loopback DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 0 1 0 14 TxD RD(a) 70 RxD 1 RT (a) 37 RxC 20 61 SD(a) 2 SDEN 13 DTR 58 TR(a) 3 TREN CS(a) 66 CTS 80 16 RTS 54 RS(a) 4 RSEN DM(a) 68 DSR 78 17 RL 47 RL(a) 18 RLEN RR(a) 35 DCD 19 24 LL 51 LL(a) 5 LLEN IC(a) 39 RI 21 22 ST 42 ST(a) 23 STEN 15 TxC 63 TT(a) 6 TTEN internally connects V. driver outputs to V. receiver inputs. The signal path again is non-inverting; the differential loopback data rate can be at least 5Mbps. Under loopback conditions the receiver decoder is disabled. While the SP505 is in either single-ended or differential loopback mode, the driver outputs are tri-stated and the receiver inputs are disabled. MODE: Differential Loopback DRIVER/RECEIVER DEC3 DEC2 DEC1 DEC0 1 0 1 1 RD(a) 70 RxD 1 RD(b) 71 RT (a) 37 RxC 20 RT(b) 38 CS(a) 66 CTS 80 CS(b) 67 DM(a) 68 DSR 78 DM(b) 69 RR(a) 35 DCD 19 RR(b) 36 IC(a) 39 RI 21 IC(b) 40 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 14 TxD 61 SD(a) 59 SD(b) 2 SDEN 13 DTR 58 TR(a) 56 TR(b) 3 TREN 16 RTS 54 RS(a) 52 RS(b) 4 RSEN 17 RL 47 RL(a) 45 RL(b) 18 RLEN 24 51 49 5 22 42 44 23 15 63 65 6 LL LL(a) LL(b) LLEN ST ST(a) ST(b) STEN TxC TT(a) TT(b) TTEN SCT(a) 76 SCT 79 SCTEN 7 RECEIVERS DRIVERS RECEIVERS DRIVERS Mode Loopback DEC = 1010 DEC = 1011 Power down VCC=VDD=VSS=0V Tri-state DEC = 0000 non-inverting tri-state tri-state tri-state tri-state Driver Output inverting non-inverting Receiver Input inverting Driver Receiver Input Output active active active active tri-state tri-state tri-state tri-state >10KΩ to GND >10KΩ to GND >10KΩ to GND >10KΩ to GND clamped >10KΩ to GND >10KΩ to GND inactive at ±0.6V >10KΩ to GND >10KΩ to GND inactive tri-state Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 33 PACKAGE: 80 PIN LQFP Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 34 ORDERING INFORMATION Model Temperature Range Package Types SP505ACM-L..........................0°C to +70°C.................................................80–pin LQFP SP505BCM-L......................... 0°C to +70°C.................................................80–pin LQFP REVISION HISTORY Date 2-24-05 8-3-08 REVISION --.0.0 DESCRIPTION Legacy Sipex Data Sheet SP505A/SP505B are no longer available in MQFP package per PCN 07-02-06a. Device is now only available in LQFP package. Package drawing and ordering information have been updated. Changed to Exar data sheet format and revision to .0.0. Notice EXAR Corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2008 EXAR Corporation Datasheet August 2008 Send your Interface technical inquiry with technical details to: uarttechsupport@exar.com Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Exar Coporation 48720 Kato Road, Fremont CA, 94538 • (50) 668-7000 • Fax (50) 668-707 • www.exar.com SP505_00_08308 35