100336QI

100336 Low Power 4-Stage Counter/Shift Register August 1989 Revised August 2000 100336 Low Power 4-Stage Counter/Shift Register General Description The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select (Sn) inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable (CEP, CET) inputs are provided for ease of cascading in multistage counters. One Count Enable (CET) input also doubles as a Serial Data (D0) input for shift-up operation. For shift-down operation, D3 is the Serial Data input. In counting operations the Terminal Count (TC) output goes LOW when the counter reaches 15 in the count/up mode or 0 (zero) in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q3 output and the D0/CET input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The individual Preset (Pn) inputs are used to enter data in parallel or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously clears the flipflops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 kΩ pull-down resistors. Features s 40% power reduction of the 100136 s 2000V ESD protection s Pin/function compatible with 100136 s Voltage compensated operating range = −4.2V to −5.7V s Available to industrial grade temperature range Ordering Code: Order Number 100336SC 100336PC 100336QC 100336QI Package Number M24B N24E V28A V28A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP/SOIC 28-Pin PLCC Logic Symbol © 2000 Fairchild Semiconductor Corporation DS010584 www.fairchildsemi.com 100336 Function Select Table S2 L L L L H H H H S1 L L H H L L H H S0 L H L H L H L H Function Parallel Load Complement Shift Left Shift Right Count Down Clear Count Up Hold Pin Descriptions Pin Names CP CEP D0/CET S0–S2 MR P0–P3 D3 TC Q0–Q3 Q0–Q3 Description Clock Pulse Input Count Enable Parallel Input (Active LOW) Serial Data Input/Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs Truth Table Q0 = LSB Inputs Outputs MR S2 S1 S0 CEP D0/CET D3 CP Q3 Q2 Q1 Q0 L L L L L L L L L L L L H H H H H H H H H L L L L H H H H H H H H L L L L H H H H H L L H H L L L L H H H H L L H H L L L H H L H L H L L L H L L L H L H L H L L H L H X X X X L H X X L H X X X X X X X X X X X X X X X L L H X L L H X X X X X L H X X X X X X X X X X X X X X X X X X X X X X X X        X X X X X X X X X TC L L D3 1 1 H H 2 2 H H L L L L L H H H H Mode Preset (Parallel Load) Invert Shift to LSB Count Down Count Down with CEP not active Count Down with CET not active Clear Count Up Count Up with CEP not active Count Up with CET not active Hold P3 P2 P1 P0 Q3 Q2 Q1 Q0 D3 Q3 Q2 Q1 (Q0–3) minus 1 Q2 Q1 Q0 D0 Q3 (Note 1) Shift to MSB X Q3 Q2 Q1 Q0 X Q3 Q2 Q1 Q0 L L L L (Q0–3) plus 1 X Q3 Q2 Q1 Q0 X Q3 Q2 Q1 Q0 X Q3 Q2 Q1 Q0 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L Asynchronous Master Reset 1 = L if Q0–Q3 = LLLL H if Q0–Q3 ≠ LLLL 2 = L if Q0–Q3 = HHHH H if Q0–Q3 ≠ HHHH H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition  Note 1: Before the clock, TC is Q3 After the clock, TC is Q2 www.fairchildsemi.com 2 100336 Logic Diagram 3 www.fairchildsemi.com 100336 Absolute Maximum Ratings(Note 2) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 3) −65°C to +150 °C +150 °C −7.0V to +0.5V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C −40°C to +85°C −5.7V to −4.2V −50 mA ≥ 2000V Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 4) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Symbol Parameter Min Typ VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current −165 −1165 −1830 0.50 240 −80 −1025 −1830 −1035 −1610 −870 −1475 −955 −1705 Max −870 −1620 Units mV mV mV mV mV mV µA µA VIN =VIH (Max) or VIL (Min) VIN = VIH(Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs Open Conditions Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. www.fairchildsemi.com 4 100336 Commercial Version (Continued) DIP AC Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fSHIFT tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Shift Frequency Propagation Delay CP to Qn, Qn Propagation Delay CP to TC (Shift) Propagation Delay CP to TC (Count) Propagation Delay MR to Qn, Qn Propagation Delay MR to TC (Count) Propagation Delay MR to TC (Shift) Propagation Delay D0/CET to TC Propagation Delay Sn to TC Transition Time 20% to 80%, 80% to 20% Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) tH Hold Time D3 Pn D0/CET CEP Sn tPW(H) Pulse Width HIGH CP, MR 0.40 0.30 0.30 0.20 0.10 2.00 0.40 0.30 0.30 0.20 0.10 2.00 0.40 0.30 0.30 0.20 0.10 2.00 ns Figures 3, 4 ns Figure 6 1.00 1.50 1.30 1.40 3.40 2.60 1.00 1.50 1.30 1.40 3.40 2.60 1.00 1.50 1.30 1.40 3.40 2.60 ns Figures 6, 4 TC = 0°C Min 300 1.00 2.10 2.40 1.40 2.80 2.40 1.80 1.90 0.35 2.00 3.50 4.40 2.50 5.10 4.00 3.10 4.10 1.20 Max TC = +25°C Min 300 1.00 2.10 2.40 1.40 2.90 2.40 1.80 1.90 0.35 2.00 3.50 4.40 2.50 5.20 4.00 3.10 4.10 1.20 Max TC = +85°C Min 300 1.00 2.10 2.60 1.50 3.10 2.50 1.90 2.10 0.35 2.00 3.70 4.70 2.60 5.50 4.10 3.30 4.40 1.20 Max MHz ns ns ns ns ns ns ns ns ns Figures 2, 3 Figures 1, 3 (Note 5) Figures 1, 7, 8 (Note 5) Figures 1, 9 (Note 5) Figures 1, 4 (Note 5) Figures 1, 12 (Note 5) Figures 1, 10, 11 (Note 5) Figures 1, 5 (Note 5) Units Conditions Figures 1, 3 Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 5 www.fairchildsemi.com 100336 SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fSHIFT tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Shift Frequency Propagation Delay CP to Qn, Qn Propagation Delay CP to TC (Shift) Propagation Delay CP to TC (Count) Propagation Delay MR to Qn, Qn Propagation Delay MR to TC (Count) Propagation Delay MR to TC (Shift) Propagation Delay D0/CET to TC Propagation Delay Sn to TC Transition Time 20% to 80%, 80% to 20% Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) tH Hold Time D3 Pn D0/CET CEP Sn tPW(H) tOSHL Pulse Width HIGH CP, MR Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Clock to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Clock to Output Path Note 6: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design TC = 0°C Min 350 1.00 2.10 2.40 1.40 2.80 2.40 1.80 1.90 0.35 1.80 3.30 4.20 2.30 4.90 3.80 2.90 3.90 1.10 Max TC = +25°C Min 350 1.00 2.10 2.40 1.40 2.90 2.40 1.80 1.90 0.35 1.80 3.30 4.20 2.30 5.00 3.80 2.90 3.90 1.10 Max TC = +85°C Min 350 1.00 2.10 2.60 1.50 3.10 2.50 1.90 2.10 0.35 1.80 3.50 4.50 2.40 5.30 3.90 3.10 4.20 1.10 Max Units MHz ns ns ns ns ns ns ns ns ns Conditions Figures 2, 3 Figures 1, 2 (Note 6) Figures 1, 7, 8 (Note 6) Figures 1, 9 (Note 6) Figures 1, 4 (Note 6) Figures 1, 12 (Note 6) Figures 1, 10, 11 (Note 6) Figures 1, 5 (Note 6) Figures 1, 3 0.90 1.40 1.20 1.30 3.30 2.50 0.30 0.20 0.20 0.10 0.00 2.00 0.90 1.40 1.20 1.30 3.30 2.50 0.30 0.20 0.20 0.10 0.00 2.00 0.90 1.40 1.20 1.30 3.30 2.50 0.30 0.20 0.20 0.10 0.00 2.00 ns Figures 3, 4 PLCC Only ns Figure 6 ns Figures 4, 6 200 200 200 ps (Note 7) PLCC Only 200 200 200 ps (Note 7) PLCC Only 230 230 230 ps (Note 7) PLCC Only 245 245 245 ps (Note 7) www.fairchildsemi.com 6 100336 Industrial Version PLCC DC Electrical Characteristics (Note 8) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C TC = −40°C TC = 0°C to +85°C Symbol Parameter Min Max Min Max VOH VOL VOHC VOLC VIH VIL IIL IIH IEE Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current −165 −1170 −1830 0.50 240 −75 −165 −1085 −1830 −1095 −1565 −870 −1480 −1165 −1830 0.50 240 −80 −870 −1575 −1025 −1830 −1035 −1610 −870 −1475 −870 −1620 Units mV mV mV mV mV mV µA µA mA VIN =VIH (Max) or VIL (Min) VIN = VIH(Min) or VIL (Max) Conditions Loading with 50Ω to −2.0V Loading with 50Ω to −2.0V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs Open Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol fSHIFT tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Shift Frequency Propagation Delay CP to Qn, Qn Propagation Delay CP to TC (Shift) Propagation Delay CP to TC (Count) Propagation Delay MR to Qn, Qn Propagation Delay MR to TC (Count) Propagation Delay MR to TC (Shift) Propagation Delay D0/CET to TC Propagation Delay Sn to TC Transition Time 20% to 80%, 80% to 20% Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) tH Hold Time D3 Pn D0/CET CEP Sn tPW(H) Pulse Width HIGH CP, MR 0.90 1.00 0.70 0.60 0.00 2.20 0.30 0.20 0.20 0.10 0.00 2.00 0.30 0.20 0.20 0.10 0.00 2.00 ns Figures 3, 4 ns Figure 6 1.40 1.70 1.80 1.80 3.30 2.60 0.90 1.40 1.20 1.30 3.30 2.50 0.90 1.40 1.20 1.30 3.30 2.50 ns Figure 6 TC = −40°C Min 325 1.00 2.00 2.40 1.40 2.80 2.40 1.70 1.80 0.20 1.80 3.30 4.20 2.30 4.90 3.80 2.90 3.90 1.90 Max TC = +25°C Min 350 1.00 2.10 2.40 1.40 2.90 2.40 1.80 1.90 0.35 1.80 3.30 4.20 2.30 5.00 3.80 2.90 3.90 1.10 Max TC = +85°C Min 350 1.00 2.10 2.60 1.50 3.10 2.50 1.90 2.10 0.35 1.80 3.50 4.50 2.40 5.30 3.90 3.10 4.20 1.10 Max Units MHz ns ns ns ns ns ns ns ns ns Conditions Figures 2, 3 Figures 1, 3 (Note 9) Figures 1, 7, 8 (Note 9) Figures 1, 9 (Note 9) Figures 1, 4 (Note 9) Figures 1, 12 (Note 9) Figures 1, 10, 11 (Note 9) Figures 1, 5 (Note 9) Figures 1, 3 Note 9: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 7 www.fairchildsemi.com 100336 Test Circuitry Notes: VCC, VCCA = +2V, VEE = −2.5V L1, L2 and L3 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Notes: For shift right mode, +1.05V is applied at S0. The feedback path from output to input should be as short as possible. FIGURE 2. Shift Frequency Test Circuit (Shift Left) www.fairchildsemi.com 8 100336 Switching Waveforms FIGURE 3. Propagation Delay (Clock) and Transition Times FIGURE 4. Propagation Delay (Reset) 9 www.fairchildsemi.com 100336 Switching Waveforms (Continued) FIGURE 5. Propagation Delay (Serial Data, Selects) Notes: tS is the minimum time before the transition of the clock that information must be present at the data input. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 6. Setup and Hold Time Note: Shift Right Mode; S0 = H , S1 = H, S2 = L. FIGURE 7. Propagation Delay, Clock to Terminal Count (Shift Right Mode) Note: Shift Left Mode; S0 = L, S1 = H, S2 = L. FIGURE 8. Propagation Delay, Clock to Terminal Count (Shift Left Mode) www.fairchildsemi.com 10 100336 Switching Waveforms (Continued) Note: *Decimal representation of binary outputs. Count Up: S0 = L, S1 = H, S2 = H; Count Down: S 0 = L, S1 = L, S2 = H. Measurement taken at 50% point of waveform. FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes) Note: Shift Right Mode; S0 = H, S1 = H, S2 = L. FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode) Note: Shift Left Mode; S0 = L, S1 = H, S2 = L. FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode) Note: *Decimal representation of binary outputs. Count Up Mode: S0 = L, S1 = H, S2 = H. Note: *Decimal representation of binary outputs. Count Down Mode: S0 = L, S1 = L, S2 = H . FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes) 11 www.fairchildsemi.com 100336 Applications 3-Stage Divider, Preset Count Down Mode Note: If S0 = S1 = S 2 = LOW, then TC = LOW Slow Expansion Scheme Fast Expansion Scheme www.fairchildsemi.com 12 100336 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 13 www.fairchildsemi.com 100336 Low Power 4-Stage Counter/Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 14 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com