100344

100344 Low Power 8-Bit Latch with Cut-Off Drivers July 1988 Revised August 2000 100344 Low Power 8-Bit Latch with Cut-Off Drivers General Description The 100344 contains eight D-type latches, individual inputs (Dn), outputs (Qn), a common enable pin (E), latch enable (LE), and output enable pin (OEN). A Q output follows its D input when both E and LE are LOW. When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to E or LE going HIGH. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100344 outputs are designed to drive a doubly terminated 50Ω transmission line (25Ω load impedance). All inputs have 50 kΩ pull-down resistors. Features s Cut-off drivers s Drives 25Ω load s Low power operation s 2000V ESD protection s Voltage compensated operating range = −4.2V to −5.7V Ordering Code: Order Number 100344PC 100344QC 100344QI Package Number N24E V28A V28A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP 28-Pin PLCC Logic Symbol © 2000 Fairchild Semiconductor Corporation DS009883 www.fairchildsemi.com 100344 Pin Descriptions Pin Names D0 – D7 E LE OEN Q0–Q7 Description Data Inputs Enable Input Latch Enable Input Output Enable Input Data Outputs Truth Table Inputs Dn L H X X X E L L H X X LE L L X H X OEN L L L L H Outputs Qn L H Latched (Note 1) Latched (Note 1) Cutoff H = H IGH Voltage level L = LOW Voltage level Cutoff = lower-than-LOW state X = Don’t Care Note 1: Retains data present before either LE or E go HIGH. Logic Diagram www.fairchildsemi.com 2 100344 Absolute Maximum Ratings(Note 2) Storage Temperature (TSTG) Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 3) −65°C to +150°C +150°C −7.0V to +0.5V VEE to +0.5V Recommended Operating Conditions Case Temperature (TC) Commercial Industrial Supply Voltage (VEE) 0°C to +85°C −40°C to +85° −5.7V to −4.2V −100 mA ≥2000V Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics Symbol VOH VOL VOHC VOLC VOLZ VIH VIL IIL IIH IEE Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Cutoff LOW Voltage Input HIGH Voltage Input LOW Voltage Input LOW Current Input HIGH Current Power Supply Current −178 −185 −85 −85 mA −1165 −1830 0.50 240 Min −1025 −1830 −1035 −1610 −1950 −870 −1475 (Note 4) Typ −955 −1705 Max −870 −1620 Units mV mV mV mV mV mV mV µA µA VIN = VIH (Max) or VIL (Min) VIN = VIH (Min) or VIL (Max) VIN = VIH (Min) or VIL (Max) Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VIN = VIL (Min) VIN = VIH (Max) Inputs Open VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V Conditions Loading with 25Ω to −2.0V Loading with 25Ω to −2.0V OEN = HIGH VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL tPLH tPHL tPZH tPHZ tTLH tTHL tS tH tPW(H) Parameter Propagation Delay Dn to Output Propagation Delay LE, E to Output Propagation Delay OEN to Output Transition Time 20% to 80%, 80% to 20% Setup Time Hold Time Pulse Width HIGH LE, E D0–D7 D0–D7 TC = 0°C Min 0.90 1.60 1.60 1.00 0.45 1.00 0.10 2.00 Max 2.10 3.10 4.20 2.70 2.00 TC = +25°C Min 0.90 1.60 1.60 1.00 0.45 1.00 0.10 2.00 Max 2.10 3.10 4.20 2.70 2.00 TC = +85°C Min 1.00 1.80 1.60 1.00 0.45 1.10 0.10 2.00 Max 2.30 3.40 4.20 2.70 2.00 ns ns ns ns ns ns ns Figures 1, 2 (Note 5) Figures 1, 4 (Note 5) Figures 1, 2 (Note 5) Figures 1, 3 Figures 1, 3 Figures 1, 3 Figures 1, 3 Units Conditions Note 5: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. 3 www.fairchildsemi.com 100344 Commercial Version (Continued) PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol tPLH tPHL tPLH tPHL tPZH tPHZ tTLH tTHL tS tH tPW(H) tOSHL Parameter Propagation Delay Dn to Output Propagation Delay LE, E to Output Propagation Delay OEN to Output Transition Time 20% to 80%, 80% to 20% Setup Time Hold Time Pulse Width HIGH LE, E Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation Data to Output Path Note 6: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design. TC = 0°C Min 0.90 1.60 1.60 1.00 0.45 D0–D7 D0–D7 0.90 0.00 2.00 Max 1.90 2.90 4.00 2.50 1.90 TC = +25°C Min 0.90 1.60 1.60 1.00 0.45 0.90 0.00 2.00 Max 1.90 2.90 4.00 2.50 1.90 TC = +85°C Min 1.00 1.80 1.60 1.00 0.45 1.00 0.00 2.00 Max 2.10 3.20 4.00 2.50 1.90 Units Conditions Figures 1, 2 (Note 6) Figures 1, 4 (Note 6) Figures 1, 2 (Note 6) Figures 1, 3 Figures 1, 3 Figures 1, 3 Figures 1, 3 PLCC Only ns ns ns ns ns ns ns 330 330 330 ps (Note 7) PLCC Only 330 330 330 ps (Note 7) PLCC Only 330 330 330 ps (Note 7) PLCC Only 230 230 230 ps (Note 7) www.fairchildsemi.com 4 100344 Test Circuitry Note: • • • • • • VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 25Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delay and Cutoff Times FIGURE 3. Setup, Hold and Pulse Width Times FIGURE 4. Propagation Delay LE, E to Q 5 www.fairchildsemi.com 100344 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E www.fairchildsemi.com 6 100344 Low Power 8-Bit Latch with Cut-Off Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com