74ABT377

74ABT377 Octal D-Type Flip-Flop with Clock Enable January 1993 Revised November 1999 74ABT377 Octal D-Type Flip-Flop with Clock Enable General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Features s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See ABT273 for master reset version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus contention Ordering Code: Order Number 74ABT377CSC 74ABT377CSJ 74ABT377CMSA 74ABT377CMTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names D0–D7 CE CP Q0–Q7 Descriptions Data Inputs Clock Enable (Active LOW) Clock Pulse Input Data Outputs Truth Table Operating Mode CP Load “1” Load “0” Hold (Do Nothing) Inputs Output Dn h I X X Qn H L No Change No Change    X CE I I h H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition  © 1999 Fairchild Semiconductor Corporation DS011550 www.fairchildsemi.com 74ABT377 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74ABT377 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-OFF State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current (Across Comm Operating Range) Over Voltage Latchup VCC + 4.5V Twice the rated IOL (mA) −500 mA −0.5V to +4.75V −0.5V to VCC −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (∆V/∆t) Data Input Enable Input 50 mV/ns 20 mV/ns −40°C to +85°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOS ICEX ICCH ICCL ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Short-Circuit Current Output HIGH Leakage Current Power Supply Current Power Supply Current Maximum ICC/Input Outputs Enabled 1.5 ICCD Dynamic ICC No Load 0.3 mA mA/ MHz Note 3: Guaranteed but not tested. Note 4: For 8 bits toggling, ICCD < 0.5 mA/MHz. Min 2.0 Typ Max Units V VCC Conditions Recognized HIGH Signal Recognized LOW Signal 0.8 −1.2 2.5 2.0 0.55 1 1 7 −1 −1 4.75 −100 −275 50 50 30 V V V V µA µA µA V mA µA µA mA Min Min Min Max Max Max 0.0 Max Max Max Max Max Max IIN = −18 mA IOH = −3 mA IOH = −32 mA IOL = 64 mA VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 µA All Other Pins Grounded VOUT = 0.0V VOUT = VCC All Outputs HIGH All Outputs LOW VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at V CC or GND Outputs Open (Note 4) One bit Toggling, 50% Duty Cycle 3 www.fairchildsemi.com 74ABT377 AC Electrical Characteristics (SOIC Package) TA = +25°C Symbol Parameter Min fMAX tPLH tPHL Maximum Clock Frequency Propagation Delay CP to On 150 2.2 2.8 VCC = +5.0V CL = 50 pF Typ 200 6.0 6.8 Max TA = −40°C to +85°C VCC = 4.5V to 5.5V CL = 50 pF Min 150 2.2 2.8 6.0 6.8 Max MHz ns Units AC Operating Requirements TA = +25°C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW CE to CP Hold Time, HIGH or LOW CE to CP Pulse Width, CP, HIGH or LOW 2.0 2.0 1.8 1.8 3.0 3.0 1.0 1.0 3.3 3.3 VCC = +5.0V CL = 50 pF Max Min 2.0 2.0 1.8 1.8 3.0 3.0 1.0 1.0 3.3 3.3 TA = −40°C to +85°C VCC = 4.5V to 5.5V CL = 50 pF Max ns ns ns Units ns ns Capacitance (SOIC Package) (Note 5) Symbol CIN COUT (Note 5) Parameter Typ 5 9 Units pF pF VCC = 5.0V Conditions VCC = 0V, TA = 25°C Input Capacitance Output Capacitance Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74ABT377 AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns FIGURE 2. VM = 1.5V tf 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT377 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M20B www.fairchildsemi.com 6 74ABT377 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74ABT377 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 8 74ABT377 Octal D-Type Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com