74ABT543

74ABT543 Octal Registered Transceiver with 3-STATE Outputs November 1992 Revised January 1999 74ABT543 Octal Registered Transceiver with 3-STATE Outputs General Description The ABT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. s Separate controls for data flow in each direction s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Features s Back-to-back registers for storage s Bidirectional data path s A and B outputs have current sourcing capability of 32 mA and current sinking capability of 64 mA Ordering Code: Order Number 74ABT543CSC 74ABT543CMSA 74ABT543CMTC Package Number M24B MSA24 MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignment for SOIC, SSOP and TSSOP Pin Descriptions Pin Names OEAB, OEBA LEAB, LEBA CEAB, CEBA A0–A7 B0–B7 Description Output Enable Inputs Latch Enable Inputs Chip Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS011508.prf www.fairchildsemi.com 74ABT543 Functional Description The ABT543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable (CEAB) input must be low in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on (LEAB) input makes the A to B latches transparent; a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Data I/O Control Table Inputs CEAB LEAB OEAB H X L X L X H L X X X X X H L Latched Latched Transparent — — HIGH Z — — HIGH Z Driving Latch Status Output Buffers H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram www.fairchildsemi.com 2 74ABT543 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to +5.5V −0.5V to VCC −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −65°C to +150°C −55°C to +125°C −55°C to +150°C DC Latchup Source Current Over Voltage Latchup (I/O) −500 mA 10V Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (∆V/∆t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100 mV/ns −40°C to +85°C +4.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current −1 −1 IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS ICEX IZZ ICCLH ICCL ICCZ ICCT ICCD Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 5) No Load 0.18 mA/MHz Max −100 10 −10 −275 50 100 50 30 50 2.5 µA µA mA µA µA µA mA µA mA µA Max VIN = 0.5V (Non-I/O Pins) (Note 3) VIN = 0.0V (Non-I/O Pins) 0V–5.5V VOUT = 2.7V (An, Bn); OEAB or CEAB = 2V 0V–5.5V VOUT = 0.5V (An, Bn); OEAB or CEAB = 2V Max Max 0.0V Max Max Max Max VOUT = 0V (An, Bn) VOUT = VCC (An, Bn) VOUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs 3-STATE All Others at VCC or GND VI = VCC − 2.1V All Others at VCC or GND Outputs Open, CEAB and OEAB = GND, CEBA = VCC, One Bit Toggling, 50% Duty Cycle, (Note 4) Note 3: Guaranteed but not tested. Note 4: For 8-bit toggling. ICCD < 1.4 mA/MHz. Note 5: Guaranteed, but not tested. Min 2.0 0.8 Typ Max Units V V VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) IOH = −32 mA, (An, Bn) −1.2 2.5 2.0 0.55 4.75 1 1 7 100 V V V µA µA µA Min 0.0 Max Max Max IOL = 64 mA, (An, Bn) IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) (Note 3) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn) 3 www.fairchildsemi.com 74ABT543 DC Electrical Characteristics (SOIC Package) Conditions Symbol Parameter Min Typ Max Units VCC CL = 50 pF, RL = 500Ω VOLP VOLV VOHV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage −1.2 2.5 2.0 0.7 −0.8 3.0 1.7 0.7 0.9 1.0 V V V V V 5.0 5.0 5.0 5.0 5.0 TA = 25°C (Note 6) TA = 25°C (Note 6) TA = 25°C (Note 7) TA = 25°C (Note 8) TA = 25°C (Note 8) Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 7: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 8: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. AC Electrical Characteristics (SOIC and SSOP Packages) TA = +25°C Symbol Parameter Min tPLH tPHL tPLH tPHL Propagation Delay An to Bn or Bn to An Propagation Delay LEAB to Bn, LEBA to An OEBA or OEAB to An or Bn tPZH tPZL Enable Time LEAB to Bn, LEBA to An OEBA or OEAB to An or Bn tPHZ tPLZ Disable Time CEBA or CEAB to An or Bn 1.5 1.5 2.0 2.0 4.0 3.6 5.8 5.8 6.5 6.5 1.5 1.5 2.0 2.0 5.8 5.8 6.5 6.5 ns ns 1.6 1.6 3.4 5.3 5.3 1.6 1.6 5.3 5.3 ns 1.5 1.5 VCC = +5.0V CL = 50 pF Typ 3.1 Max 4.8 4.8 1.5 1.5 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 50 pF Min Max 4.8 4.8 ns Units AC Operating Requirements (SOIC and SSOP Packages) TA = +25°C Symbol Parameter VCC = +5.0V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(L) Setup Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An or Bn to LEBA or LEAB Setup Time, HIGH or LOW An or Bn to CEAB or CEBA Hold Time, HIGH or LOW An or Bn to CEAB or CEBA Pulse Width, LOW 1.5 1.5 1.0 1.0 1.5 1.5 1.3 1.3 3.0 Max Min 1.5 1.5 1.0 1.0 1.5 1.5 1.3 1.3 3.0 ns ns ns ns TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 50 pF Max ns Units www.fairchildsemi.com 4 74ABT543 Extended AC Electrical Characteristics (SOIC Package) TA = −40°C to +85°C VCC = 4.5V–5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 9) Min fTOGGLE tPLH tPHL tPLH tPHL tPZH tPZL Max Toggle Frequency Propagation Delay An to Bn or Bn to An Propagation Delay LEAB to Bn, LEBA to An Output Enable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn tPHZ tPLZ Output Disable Time OEBA or OEAB to An or Bn CEBA or CEAB to An or Bn 1.5 1.5 8.5 8.5 (Note 12) (Note 12) ns 1.5 1.5 7.5 7.5 2.0 2.0 8.5 8.5 2.5 2.5 11.0 11.0 ns 1.5 1.5 1.5 1.5 Typ 100 6.2 6.2 6.5 6.5 2.0 2.0 2.0 2.0 7.5 7.5 8.0 8.0 2.5 2.5 2.5 2.5 10.0 10.0 10.5 10.5 ns Max TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 1 Output Switching (Note 10) Min Max TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 8 Outputs Switching (Note 11) Min Max MHz ns Units Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 12: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet Skew (SOIC Package) TA = −40°C to +85°C VCC = 4.5V–5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 13) Max tOSHL (Note 15) tOSLH (Note 15) tPS (Note 16) tOST (Note 15) tPV (Note 17) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH–HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 2.5 4.5 ns 2.0 4.0 ns 2.0 4.0 ns 1.3 2.0 ns 1.0 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 8 Outputs Switching (Note 14) Max 2.0 ns Units Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 14: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. 5 www.fairchildsemi.com 74ABT543 Capacitance Symbol CIN CI/O (Note 18) Parameter Input Capacitance Output Capacitance Typ 5.0 11.0 Units pF pF Conditions: TA = 25°C VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn) Note 18: CI/O is measured at frequency, f = 1 MHz, PER MLT-STD-883B, METHOD 3012. AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. VM = 1.5V Input Pulse Requirements Amplitude Rep. Rate 3V 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 6 74ABT543 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24 7 www.fairchildsemi.com 74ABT543 Octal Registered Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.