74ABT899

74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker November 1992 Revised January 1999 74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description The ABT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. The ABT899 features independent latch enables for the Ato-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. s Ability to simultaneously generate and check parity s May be used in systems applications in place of the 543 and 280 s May be used in system applications in place of the 657 and 373 (no need to change T/R to check parity) s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability s Disable time less than enable time to avoid bus contention Features s Latchable transceiver with output sink of 64 mA s Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A s Independent latch enables for A-to-B and B-to-A directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking Ordering Code: Order Number 74ABT899CSC 74ABT899CMSA 74ABT899CQC Package Number M28B MSA28 V28A Package Description 28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body 28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for PLCC Pin Assignment for SOIC and SSOP © 1999 Fairchild Semiconductor Corporation DS011509.prf www.fairchildsemi.com 74ABT899 Pin Descriptions Pin Names A0–A7 B0–B7 APAR, BPAR ODD/EVEN GBA, GAB SEL Descriptions A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs/Outputs ODD/EVEN Parity Select, Active LOW for EVEN Parity Output Enables for A or B Bus, Active LOW Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode Latch Enables for A and B Latches, HIGH for Transparent Mode Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs Functional Description The ABT899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. • Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW, the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA). • Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU). • Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table below). LEA, LEB ERRA, ERRB Function Table Inputs GAB GBA SEL LEA LEB H H H H L L X L L X L H X H H Busses A and B are 3-STATE. Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generates parity from B[0:7] based on O/E. Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity from B latch data based on O/E. Generated parity → APAR. Generated parity checked against latched BPAR and output as ERRB. BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. BPAR/B[0:7] → APAR/A[0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L L H H L L H H L H Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. Generates parity from A latch data based on O/E. Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA. APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. L H H H H APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note 1: O/E = ODD/EVEN Operation H H H L L L L H H X X H L H H L L H H L H L H X L www.fairchildsemi.com 2 74ABT899 Functional Block Diagram 3 www.fairchildsemi.com 74ABT899 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or PowerOff State in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) −0.5V to +5.5V −0.5V to VCC −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −55°C to +150°C −65°C to +150°C −55°C to +125°C DC Latchup Source Current Over Voltage Latchup (I/O) −500 mA 10V Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (∆V/∆t) Data Input Enable Input 50 mV/ns 20 mV/ns −40°C to +85°C +4.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current −5 50 −50 −100 −275 50 100 250 34 250 2.5 0.4 µA µA µA mA µA µA µA mA µA mA mA/MHz Max VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) IIH + IOZH Output Leakage Current IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Output Leakage Current 0V–5.5V VOUT = 2.7V (An, Bn); GAB and GBA = 2.0V 0V–5.5V VOUT = 0.5V (An, Bn); GAB and GBA = 2.0V Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC: (Note 4) No Load Max Max 0.0V Max Max Max Max Max VOUT = 0V (An, B n, APAR, BPAR) VOUT = VCC (An, Bn, APAR, BPAR) VOUT = 5.5V (An, Bn, APAR, BPAR); All Others GND All Outputs HIGH All Outputs LOW, ERRA/B = HIGH (Note 5) Outputs 3-STATE All Others at VCC or GND VI = VCC − 2.1V All Others at VCC or GND Outputs Open GAB or GBA = GND, LE = HIGH Non-I/O = GND or VCC One bit toggling, 50% duty cycle Note 4: Guaranteed, but not tested. Note 5: Add 3.75 mA for each ERR LOW. Min 2.0 Typ Max Units V VCC Conditions Recognized HIGH Signal Recognized LOW Signal 0.8 −1.2 2.5 2.0 0.55 4.75 5 7 100 V V V V V µA µA µA Min Min Min 0.0 Max Max Max IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, B n, APAR, BPAR) IOH = −32 mA, (An, Bn, APAR, BPAR) IOL = 64 mA, (An, Bn, APAR, BPAR) IID = 1.9 µA, (Non-I/O Pins) All Other Pins Grounded VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (An, Bn, APAR, BPAR) www.fairchildsemi.com 4 74ABT899 DC Electrical Characteristics (PLCC package) Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage −1.3 2.5 2.2 Min Typ 0.8 −0.8 3.0 1.8 0.8 0.5 Max 1.1 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF, RL = 500Ω TA = 25°C (Note 6) TA = 25°C (Note 6) TA = 25°C (Note 8) TA = 25°C (Note 7) TA = 25°C (Note 7) Note 6: M ax number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 8: M ax number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics (SOIC and PLCC Package) TA = +25°C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPLHtPHL Propagation Delay An, to Bn Propagation Delay An, Bn to BPAR, APAR Propagation Delay An, Bn to ERRA, ERRB Propagation Delay APAR, BPAR to ERRA, ERRB Propagation Delay ODD/EVEN to APAR, BPAR Propagation Delay ODD/EVEN to ERRA, ERRB Propagation Delay SEL to APAR, BPAR Propagation Delay LEA, LEB to Bn, An Propagation Delay LEA, LEB to BPAR, APAR Generate Mode Propagation Delay LEA, LEB to BPAR, APAR, Feed Thru Mode Propagation Delay LEA, LEB to ERRA, ERRB Output Enable Time GBA or GAB to An, APAR or Bn, BPAR Output Disable Time GBA or GAB to An, APAR or Bn, BPAR Propagation Delay APAR to BPAR, BPAR to APAR 1.5 1.5 3.3 3.8 5.4 5.4 1.5 1.5 5.4 5.4 ns 1.0 1.0 4.0 3.3 6.0 6.0 1.0 1.0 6.0 6.0 ns 1.6 1.6 1.5 1.5 5.4 5.4 3.6 3.4 8.4 8.4 6.0 6.0 1.6 1.6 1.5 1.5 8.4 8.4 6.0 6.0 ns ns 1.5 1.5 3.6 3.6 5.1 5.1 1.5 1.5 5.1 5.1 ns 1.5 1.5 2.5 2.5 2.5 2.5 1.5 1.5 2.0 2.0 1.8 1.8 1.5 1.5 1.5 1.5 2.5 2.5 VCC = +5.0V CL = 50 pF Typ 3.0 3.5 5.9 5.8 5.4 5.4 3.7 3.7 4.4 4.4 4.0 4.0 3.8 3.8 3.2 3.2 5.9 5.7 Max 4.8 4.8 9.2 9.2 8.5 8.5 6.0 6.0 6.9 6.9 6.0 6.0 6.0 6.0 4.6 4.6 8.8 8.8 1.5 1.5 2.5 2.5 2.5 2.5 1.5 1.5 2.0 2.0 1.8 1.8 1.5 1.5 1.5 1.5 2.5 2.5 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 50 pF Min Max 4.8 4.8 9.2 9.2 8.5 8.5 6.0 6.0 6.9 6.9 6.0 6.0 6.0 6.0 4.6 4.6 8.8 8.8 ns ns ns ns ns ns ns ns ns Units 5 www.fairchildsemi.com 74ABT899 AC Electrical Characteristics (SSOP Package) TA = +25°C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL Propagation Delay An, to Bn Propagation Delay An, Bn to BPAR, APAR Propagation Delay An, Bn to ERRA, ERRB Propagation Delay APAR, BPAR to ERRA, ERRB Propagation Delay ODD/EVEN to APAR, BPAR Propagation Delay ODD/EVEN to ERRA, ERRB Propagation Delay SEL to APAR, BPAR Propagation Delay LEA, LEB to Bn, An Propagation Delay LEA, LEB to BPAR, APAR Generate Mode Propagation Delay LEA, LEB to BPAR, APAR, Feed Thru Mode Propagation Delay LEA, LEB to ERRA, ERRB Output Enable Time GBA or GAB to An, APAR or Bn, BPAR Output Disable Time GBA or GAB to An, APAR or Bn, BPAR Propagation Delay APAR to BPAR, BPAR to APAR 1.5 1.5 3.3 3.8 5.9 5.9 1.5 1.5 5.9 5.9 ns 1.0 1.0 4.0 3.3 6.5 6.5 1.0 1.0 6.5 6.5 ns 1.6 1.6 1.5 1.5 5.4 5.4 3.6 3.4 8.9 8.9 6.5 6.5 1.6 1.6 1.5 1.5 8.9 8.9 6.5 6.5 ns ns 1.5 1.5 3.6 3.6 5.6 5.6 1.5 1.5 5.6 5.6 ns 1.5 1.5 2.5 2.5 2.5 2.5 1.5 1.5 2.0 2.0 1.8 1.8 1.5 1.5 1.5 1.5 2.5 2.5 VCC = +5.0V CL = 50 pF Typ 3.0 3.5 5.9 5.8 5.4 5.4 3.7 3.7 4.4 4.4 4.0 4.0 3.8 3.8 3.2 3.2 5.9 5.7 Max 5.3 5.3 9.9 9.9 9.4 9.4 6.5 6.5 7.4 7.4 6.5 6.5 6.5 6.5 5.1 5.1 9.2 9.2 1.5 1.5 2.5 2.5 2.5 2.5 1.5 1.5 2.0 2.0 1.8 1.8 1.5 1.5 1.5 1.5 2.5 2.5 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 50 pF Min Max 5.3 5.3 9.9 9.9 9.4 9.4 6.5 6.5 7.4 7.4 6.5 6.5 6.5 6.5 5.1 5.1 9.2 9.2 ns ns ns ns ns ns ns ns ns Units AC Operating Requirements TA = +25°C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tW(H) Setup Time, HIGH or LOW An, APAR to LEA or Bn, BPAR to LEB Hold Time, HIGH or LOW An, APAR to LEA or Bn, BPAR to LEB Pulse Width, HIGH LEA or LEB 1.5 1.5 1.0 1.0 3.0 VCC = +5.0V CL = 50 pF Max Min 1.5 1.5 1.0 1.0 3.0 ns ns TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 50 pF Max ns Units www.fairchildsemi.com 6 74ABT899 Extended AC Electrical Characteristics (SOIC and PLCC Package) TA = +25°C VCC = +5.0V Symbol Parameter CL = 50 pF 9 Outputs Switching (Note 9) Min fTOGGLE tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Max Toggle Frequency Propagation Delay An to Bn Propagation Delay APAR to BPAR Propagation Delay An, Bn to BPAR, APAR Propagation Delay An, Bn to ERRA, ERRB Propagation Delay APAR, BPAR to ERRA, ERRB Propagation Delay ODD/EVEN to APAR, BPAR Propagation Delay ODD/EVEN to ERRA, ERRB Propagation Delay SEL to APAR, BPAR Propagation Delay LEA, LEB to Bn, An Propagation Delay LEA, LEB to BPAR, APAR Propagation Delay LEA, LEB to ERRA, ERRB Output enable time GBA or GAB to An, APAR or Bn, BPAR Output disable time GBA or GAB to An, APAR or Bn, BPAR Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load Note 12: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 13: Not applicable for multiple output switching. TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF (Note 10) Max 6.2 6.2 6.8 6.8 10.0 10.0 Min 2.0 2.0 2.0 2.0 3.0 3.0 3.0 3.0 Max 7.2 7.2 8.0 8.0 12.5 12.5 12.0 12.0 9.0 9.0 9.9 9.9 8.8 8.8 9.5 9.5 7.9 7.9 12.0 12.0 11.5 11.5 8.5 8.5 2.5 2.5 10.5 10.5 ns 2.5 2.5 2.5 2.5 10.0 10.0 13.0 13.0 ns ns ns (Note 13) ns (Note 13) ns (Note 13) ns (Note 13) ns VCC = 4.5V–5.5V CL = 250 pF (Note 11) Min 2.5 2.5 2.5 2.0 3.5 3.5 Max MHz 9.5 9.5 10.0 10.0 13.5 13.5 ns ns ns ns Units 1 Output Switching 9 Outputs Switching Typ 100 1.5 1.5 1.5 1.5 2.5 2.5 (Note 13) (Note 13) (Note 13) 2.0 2.0 (Note 13) (Note 13) 2.5 2.5 2.0 2.0 (Note 13) 1.5 1.5 1.5 1.5 (Note 13) 5.7 5.7 9.5 9.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 (Note 13) 1.5 1.5 7.0 7.0 2.0 2.0 1.0 1.0 6.5 6.5 (Note 12) (Note 12) ns 7 www.fairchildsemi.com 74ABT899 Extended AC Electrical Characteristics (SSOP Package) TA = +25°C VCC = +5.0V Symbol Parameter CL = 50 pF 9 Outputs Switching (Note 14) Min fTOGGLE tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Max Toggle Frequency Propagation Delay An to Bn Propagation Delay APAR to BPAR Propagation Delay An, Bn to BPAR, APAR Propagation Delay An, Bn to ERRA, ERRB Propagation Delay APAR, BPAR to ERRA, ERRB Propagation Delay ODD/EVEN to APAR, BPAR Propagation Delay ODD/EVEN to ERRA, ERRB Propagation Delay SEL to APAR, BPAR Propagation Delay LEA, LEB to Bn, An Propagation Delay LEA, LEB to BPAR, APAR Propagation Delay LEA, LEB to ERRA, ERRB Output enable time GBA or GAB to An, APAR or Bn, BPAR Output disable time GBA or GAB to An, APAR or Bn, BPAR Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 15: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 16: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load Note 17: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 18: Not applicable for multiple output switching. TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF (Note 15) Max 6.7 6.7 7.3 7.3 10.7 10.7 Min 2.0 2.0 2.0 2.0 3.0 3.0 3.0 3.0 Max 7.7 7.7 8.5 8.5 13.2 13.2 12.9 12.9 9.5 9.5 10.4 10.4 9.3 9.3 10.0 10.0 8.4 8.4 12.5 12.5 12.0 12.0 9.0 9.0 2.5 2.5 11.1 11.1 ns 2.5 2.5 2.5 2.5 10.6 10.6 13.6 13.6 ns ns ns (Note 18) ns (Note 18) ns (Note 18) ns (Note 18) ns VCC = 4.5V–5.5V CL = 250 pF (Note 16) Min 2.5 2.5 2.5 2.0 3.5 3.5 Max MHz 10.1 10.1 10.6 10.6 14.3 14.3 ns ns ns ns Units 1 Output Switching 9 Outputs Switching Typ 100 1.5 1.5 1.5 1.5 2.5 2.5 (Note 18) (Note 18) (Note 18) 2.0 2.0 (Note 18) (Note 18) 2.5 2.5 2.0 2.0 (Note 18) 1.5 1.5 1.5 1.5 (Note 18) 6.2 6.2 10.0 10.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 (Note 18) 1.5 1.5 7.5 7.5 2.0 2.0 1.0 1.0 7.0 7.0 (Note 17) (Note 17) ns www.fairchildsemi.com 8 74ABT899 Skew (PLCC package) (Note 2) TA = −40°C to +85°C VCC = 4.5V–5.5V Symbol Parameter CL = 50 pF 9 Outputs Switching (Note 19) Max tOSHL (Note 21) tOSLH (Note 21) tPS (Note 22) tOST (Note 21) tPV (Note 23) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH–HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 3.0 4.0 ns 2.0 3.5 ns 2.0 3.5 ns 1.1 2.1 ns 1.0 TA = −40°C to +85°C VCC = 4.5V–5.5V CL = 250 pF 9 Outputs Switching (Note 20) Max 2.0 ns Units Note 19: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.). Note 20: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 21: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (t OSLH), or any combination switching LOW to HIGH and/or HIGH to LOW (tOST). This specification is guaranteed but not tested. Skew applies to propagation delays individually; i.e., An to Bn separate from LEA to An. Note 22: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 23: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Symbol CIN CI/O (Note 24) Parameter Input Pin Capacitance Output Capacitance Typ 5.0 11.0 Units pF pF Conditions TA = 25°C VCC = 0V VCC = 5.0V Note 24: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012. 9 www.fairchildsemi.com 74ABT899 AC Path An, APAR → Bn, BPAR (Bn, BPAR → An, APAR) FIGURE 1. An → BPAR (Bn → APAR) FIGURE 2. An → ERRA (Bn → ERRB) FIGURE 3. O/E → ERRA O/E → ERRB FIGURE 4. www.fairchildsemi.com 10 74ABT899 AC Path (Continued) O/E → BPAR (O/E → APAR) FIGURE 5. APAR → ERRA (BPAR → ERRB) FIGURE 6. FIGURE 7. ZH, HZ FIGURE 8. 11 www.fairchildsemi.com 74ABT899 AC Path (Continued) ZL, LZ FIGURE 9. SEL → BPAR (SEL → APAR) FIGURE 10. LEA → BPAR, B[0:7] (LEB → APAR, A[0:7]) FIGURE 11. TS(H), TH(H) LEA → APAR, A[0:7] (LEB → BPAR, B[0:7]) FIGURE 12. www.fairchildsemi.com 12 74ABT899 AC Path (Continued) TS(L), TH(L) LEA → APAR, A[0:7] (LEB → BPAR, B[0:7]) FIGURE 13. FIGURE 14. 13 www.fairchildsemi.com 74ABT899 AC Loading *Includes jig and probe capacitance FIGURE 15. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns VM = 1.5V FIGURE 16. tf 2.5 ns FIGURE 17. Test Input Signal Requirements AC Waveforms FIGURE 18. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 20. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 19. Propagation Delay, Pulse Width Waveforms FIGURE 21. Setup Time, Hold Time and Recovery Time Waveforms www.fairchildsemi.com 14 74ABT899 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body Package Number M28B 28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA28 15 www.fairchildsemi.com 74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square Package Number V28A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.