74ACTQ18825

74ACTQ18825 18-Bit Buffer/Line Driver with 3-STATE Outputs September 1991 Revised January 2000 74ACTQ18825 18-Bit Buffer/Line Driver with 3-STATE Outputs General Description The ACTQ18825 contains eighteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 18-bit operation. The ACTQ18825 utilizes Fairchild FACT Quiet Series™ technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO™ output control and undershoot corrector for superior performance. Features s Utilizes Fairchild FACT Quiet Series technology s Broadside pinout allows for easy board layout s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s Extra data width for wider address/data paths or buses carrying parity s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number 74ACTQ18825SSC 74ACTQ18825MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn I0–I17 O0–O17 Description Output Enable Input (Active LOW) Inputs Outputs FACT™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010955 www.fairchildsemi.com 74ACTQ18825 Connection Diagram Functional Description The ACTQ18825 contains eighteen non-inverting buffers with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independently of the other. The control pins may be shorted together to obtain full 18-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each byte. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Truth Table Inputs Outputs Byte 1 (0:8) Byte 2 (8:17) I0–I8 I9–I17 O0–O8 O9–O17 OE1 L H X L L H L OE2 L X H L L H L OE3 L L L H X H L OE4 L L L X H H L H X X L H X L H L H X X X L H Z Z L H Z L H L H Z Z Z L H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance Logic Diagram www.fairchildsemi.com 2 74ACTQ18825 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current Per Output Pin Storage Temperature ESD Last Passing Voltage (Min) ±50 mA −65°C to +150°C 4000V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA −20 mA +20 mA −0.5V to +7.0V Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V∆t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT™ circuits outside databook specifications. 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns DC Electrical Characteristics Symbol VIH VIL VOH Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage Parameter VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD VOLP VOLV VOHP VOHV VIHD VILD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current Minimum Dynamic Output Current (Note 2) Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum Overshoot Minimum VCC VCC Droop Minimum HIGH Dynamic Input Voltage Level Maximum LOW Dynamic Input Voltage Level 5.0 5.0 5.0 0.5 −0.5 0.8 −0.8 5.5 5.5 5.5 5.5 5.5 0.6 8.0 0.001 0.001 TA = +25°C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 ±0.5 ± 0.1 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 ±5.0 ± 1.0 1.5 80.0 75 −75 µA µA mA µA mA mA V V V V V V V VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V IOUT = −50 µA VIN = VIL or VIH V IOH = −24 mA IOH = −24 mA (Note 2) IOUT = 50 µA VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 2) VI = VIL, VIH VO = VCC, GND VI = VCC, GND VI = VCC −2.1V VIN = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 5)(Note 6) Figure 1, Figure 2 (Note 4)(Note 6) 5.0 5.0 5.0 VOH − 1.0 VOH − 1.8 1.7 1.2 2.0 0.8 V V V Figure 1, Figure 2 (Note 4)(Note 6) (Note 4)(Note 7) (Note 4)(Note 7) Units Conditions VOH + 1.0 VOH + 1.5 Note 2: All outputs loaded; thresholds associated with output under test. Note 3: M aximum test duration 2.0 ms, one output loaded at a time. Note 4: Worst case package. Note 5: M aximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW. Note 6: M aximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH. Note 7: M aximum number of data inputs (n) switching (n-1) input switching 0V to 3V. Input under test switching 3V to threshold (VILD). 3 www.fairchildsemi.com 74ACTQ18825 AC Electrical Characteristics VCC Symbol tPHL tPLH tPZL tPZH tPLZ tPHZ Parameter Propagation Delay Data to Output Output Enable Time Output Disable Time 5.0 5.0 (V) (Note 8) 5.0 Min 2.0 2.0 2.0 2.0 1.5 1.5 TA = +25°C CL = 50 pF Typ 5.3 5.6 6.3 6.5 4.5 5.1 Max 8.4 8.7 9.6 9.7 7.3 8.5 TA = −40°C to +85°C CL = 50 pF Min 2.0 2.0 2.0 2.0 1.5 1.5 Max 9.0 9.2 10.3 10.4 7.6 8.8 ns ns ns Units Note 8: Voltage Range 5.0 is 5.0V ± 0.5V. Extended AC Electrical Characteristics TA = −40°C to +85°C VCC = Com Symbol Parameter CL = 50 pF 16 Outputs Switching (Note 9) Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL (Note 13) tOSLH (Note 13) tOST (Note 13) Pin to Pin Skew HL Data to Output Pin to Pin Skew LH Data to Output Pin to Pin Skew LH/HL Data to Output Output Disable Time Propagation Delay Data to Output Output Enable Time 6.5 5.5 6.1 6.5 3.1 3.5 Typ 8.0 6.5 7.6 7.8 5.0 5.2 Max 9.8 8.9 9.2 9.4 6.1 6.5 1.5 2.0 2.0 (Note 11) (Note 12) Min (Note 10) Max ns ns ns ns ns ns TA = −40°C to +85°C VCC = Com CL = 250 pF Units Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 11: 3-STATE delays are load dominated and have been excluded from the datasheet. Note 12: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). Capacitance Symbol CIN CPD Parameter Input Pin Capacitance Power Dissipation Capacitance Typ 4.5 95 Units pF pF VCC = 5.0V VCC = 5.0V Conditions www.fairchildsemi.com 4 74ACTQ18825 FACT Noise Characteristics The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500Ω. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. VOLP/VOLV and VOHP/VOHV: • Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable. Measure VOHP and VOHV on the quiet output during the worst case transition for active and enable • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: • Monitor one of the switching outputs using a 50Ω coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. • First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. • Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. • Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. Note 14: VOHV and VOLP are measured with respect to ground reference. Note 15: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps. FIGURE 1. Quiet Output Noise Voltage Waveforms 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. FIGURE 2. Simultaneous Switching Test Circuit 5 www.fairchildsemi.com 74ACTQ18825 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A www.fairchildsemi.com 6 74ACTQ18825 18-Bit Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com