74F174_00

74F174 Hex D-Type Flip-Flop with Master Reset April 1988 Revised September 2000 74F174 Hex D-Type Flip-Flop with Master Reset General Description The 74F174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. Features s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s Asynchronous common reset s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number 74F174SC 74F174SJ 74F174PC Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009489 www.fairchildsemi.com 74F174 Unit Loading/Fan Out Pin Names D0 – D5 CP MR Q0–Q5 Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) Outputs Description U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 74F174 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The 74F174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs MR L H H CP Dn X H L Outputs Qn L H L H = H IGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition   X  Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F174 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to VCC −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCH ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current Power Supply Current −60 30 30 4.75 3.75 −0.6 −150 45 45 10% VCC 5% VCC 10% VCC 10% VCC 2.5 2.7 0.5 0.5 5.0 7.0 50 Min 2.0 0.8 −1.2 Typ Max Units V V V V V µA µA µA V µA mA mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IOL = 20 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 0V CP = Dn = MR = HIGH VO = LOW  3 www.fairchildsemi.com 74F174 AC Electrical Characteristics TA = +25°C Symbol Parameter Min fMAX tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay MR to Qn 80 3.5 4.0 5.0 5.5 7.0 10.0 8.0 10.0 14.0 VCC = +5.0V CL = 50 pF Typ Max TA = −55°C to +125°C VCC = +5.0V CL = 50 pF Min 70 3.0 4.0 5.0 10.0 12.0 16.0 Max TA = 0°C to +70°C VCC = +5.0V CL = 50 pF Min 80 3.5 4.0 5.0 9.0 11.0 15.0 Max MHz ns ns Units AC Operating Requirements TA = +25°C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW MR Pulse Width, LOW Recovery Time, MR to CP 4.8 4.0 0 0 4.0 6.0 5.0 5.0 Max TA = −55°C to +125° VCC = +5.0V Min 5.0 5.0 2.0 2.0 5.0 7.5 6.5 6.0 Max TA = 0°C to +70°C VCC = +5.0V Min 4.8 4.0 0 0 4.0 6.0 5.0 5.0 ns ns ns Max Units www.fairchildsemi.com 4 74F174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com 74F174 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 74F174 Hex D-Type Flip-Flop with Master Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com