74LCX573BQX2

74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs February 2006 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Features ■ 5V tolerant inputs and outputs ■ 2.3V–3.6V VCC specifications provided ■ 7.0 ns tPD max (VCC = 3.3V), 10µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal1 ■ ±24mA output drive (VCC = 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds JEDEC 78 conditions ■ ESD performance General Description The LCX573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) input. The LCX573 is functionally identical to the LCX373 but has inputs and outputs on opposite sides. The LCX573 is designed for low voltage applications with capability of interfacing to a 5V signal environment. The LCX573 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. – Human body model > 2000V – Machine model > 200V ■ Leadless Pb-Free DQFN package Ordering Information Order Number 74LCX573WM 74LCX573SJ 74LCX573BQX2 74LCX573MSA 74LCX573MTC 74LCX573MTCX_NL3 Package Number M20B M20D MLP020B MSA20 MTC20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Notes 1. To ensure the high impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value of the resistor is determined by the current-sourcing capability of the driver. 2. DQFN package available in Tape and Reel only. 3. “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. ©2006 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com 74LCX573 Rev. 2.0.0 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Logic Symbol D0 D1 D2 D3 D4 D5 D6 D7 LE OE O0 O1 O2 O3 O4 O5 O6 O7 Pin Descriptions Pin Names D0–D7 LE OE O0–O7 Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs Description Connection Diagrams Pin Assignments for SOIC, SOP, SSOP, TSSOP Truth Table Inputs OE LE H H L X Outputs D H L X X OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC O0 O1 O2 O3 O4 O5 O6 O7 LE On H L O0 Z L L L H Pad Assignments for DQFN OE VCC 1 20 19 O0 18 O1 17 O2 16 O3 15 O4 14 O5 13 O6 12 O7 10 11 H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Functional Description The LCX573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND LE (Top View) Logic Diagram D0 D Q D1 D Q D2 D Q D3 D Q D4 D Q D5 D Q D6 D Q D7 D Q LE LE LE LE LE LE LE LE LE OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Absolute Maximum Ratings The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Conditions Value −0.5 to +7.0 −0.5 to +7.0 Units V V V mA mA mA mA mA °C Output in 3-STATE Output in HIGH or LOW VI < GND VO < GND VO > VCC State4 −0.5 to +7.0 −0.5 to VCC + 0.5 −50 −50 +50 ±50 ±100 ±100 −65 to +150 Recommended Operating Conditions5 Symbol VCC VI VO IOH / IOL Parameter Supply Voltage Input Voltage Output Voltage Output Current Operating Conditions Data Retention HIGH or LOW State 3-STATE VCC = 3.0V − 3.6V VCC = 2.7V − 3.0V VCC = 2.3V − 2.7V Min. 2.0 1.5 0 0 0 Max. 3.6 3.6 5.5 VCC 5.5 ±24 ±12 ±8 Units V V V mA TA ∆t / ∆V Free-Air Operating Temperature Input Edge Rate VIN = 0.8V − 2.0V, VCC = 3.0V −40 0 85 10 °C ns / V Notes: 4. IO Absolute Maximum Rating must be observed. 5. Unused (inputs or I/Os) must be held HIGH or LOW. They may not float. 3 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs DC Electrical Characteristics TA = −40°C to +85°C Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage Conditions VCC (V) 2.3 − 2.7 2.7 − 3.6 2.3 − 2.7 2.7 − 3.6 Min. 1.7 2.0 Max. Units V 0.7 0.8 VCC − 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 ±5.0 ±5.0 10 10 ±10 500 V V IOH = −100µA IOH = −8mA IOH = −12mA IOH = −18mA IOH = −24mA 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 2.7 3.0 3.0 2.3 − 3.6 2.3 − 3.6 0 2.3 − 3.6 2.3 − 3.6 2.3 − 3.6 VOL LOW Level Output Voltage IOL = 100µA IOL = 8mA IOL = 12mA IOL = 16mA IOL = 24mA V II IOZ IOFF ICC ∆ICC Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input 0 ≤ VI ≤ 5.5V 0 ≤ VO ≤ 5.5V, VI = VIH or VIL VI or VO = 5.5V VI = VCC or GND 3.6V ≤ VI, VO ≤ 5.5V6 VIH = VCC −0.6V µA µA µA µA µA AC Electrical Characteristics TA = −40°C to +85°C, RL = 500 Ω VCC = 3.3V ± 0.3V CL = 50pF Symbol tPHL, tPLH tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tS tH tW tOSHL, tOSLH VCC = 2.7V CL = 50pF Min. 1.5 1.5 1.5 1.5 2.5 1.5 3.3 VCC = 2.5 ± 0.2V CL = 30pF Min. 1.5 1.5 1.5 1.5 4.0 2.0 4.0 Parameter Propagation Delay, Dn to On Propagation Delay, LE to On Output Enable Time Output Disable Time Setup Time, Dn to LE Hold Time, Dn to LE LE Pulse Width Output to Output Skew7 Min. 1.5 1.5 1.5 1.5 2.5 1.5 3.3 Max. 8.0 8.5 8.5 6.5 Max. 9.0 9.5 9.5 7.0 Max. 9.6 10.5 10.5 7.8 Units ns ns ns ns ns ns ns ns 1.0 Notes: 6. Outputs disabled or 3-STATE only. 7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL) or LOW-toHIGH (tOSLH). 4 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Dynamic Switching Characteristics TA = 25°C Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50pF, VIH = 3.3V, VIL = 0V CL = 30pF, VIH = 2.5V, VIL = 0V CL = 50pF, VIH = 3.3V, VIL = 0V CL = 30pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 Typical 0.8 0.6 −0.8 −0.6 Units V V Capacitance Symbol CIN COUT CPD Parameter Input Capacitance Output Capacitance Power Dissipation Capacitance Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 25 Units pF pF pF 5 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs AC Loading and Waveforms (Generic for LCX Family) VCC TEST SIGNAL 500Ω DUT OPEN GND VI tPLH, tPHL tPZH, tPHZ tPZL, tPLZ CL 500Ω Figure 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH, tPHZ Switch Open 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V GND DATA IN tpxx DATA OUT Vmi tpxx Vmo VCC GND OUTPUT CONTROL tPZH DATA OUT Vmo tPHZ Vmi VCC GND VOH VY Waveform for Inverting and Non-Inverting Functions tW CONTROL IN Vmi trec CLOCK tPHL OUTPUT Vmo Vmi tPLH Vmo VCC GND 3-STATE Output High Enable and Disable Times for Logic DATA IN tS CONTROL INPUT tS MR OR CLEAR trec Vmi tH Vmi Vmi VCC GND VCC GND Propagation Delay, Pulse Width and trec Waveforms OUTPUT CONTROL tPZL DATA OUT Vmo tPLZ Vmi VCC GND VX VOL ANY OUTPUT Setup Time, Hold Time and Recovery Time for Logic tr tf VOH VOL 90% 10% 90% 10% 3-STATE Output Low Enable and Disable Times for Logic trise and tfall Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns) VCC Symbol Vmi Vmo Vx Vy 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.5V ± 0.2V VCC / 2 VCC / 2 VOL + 0.15V VOH − 0.15V 6 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Schematic Diagram (Generic for LCX Family) Input Stage P2 P1 VCC Data ESD D2 N+/P– N1 N2 GTO™ Input Stage P4 D6 N+/P– P5 X1 VDD Output P3 N5 Enable ESD D4 N+/P– N3 N4 7 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Tape and Reel Specification Tape Format for DQFN Package Designator BQX Tape Section Leader (Start End) Carrier Trailer (Hub End) Number Cavities 125 (typ) 3000 75 (typ) Cavity Status Empty Filled Empty Cover Tape Status Sealed Sealed Sealed Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size 12 mm A 13.0 (330.0) B 0.059 (1.50) C 0.512 (13.00) D 0.795 (20.20) N 2.165 (55.00) W1 0.488 (12.4) W2 0.724 (18.4) 8 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 9 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) inches (millimeters) unless otherwise noted 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 10 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) inches (millimeters) unless otherwise noted Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B 11 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) inches (millimeters) unless otherwise noted 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20 12 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) inches (millimeters) unless otherwise noted 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 13 74LCX573 Rev. 2.0.0 www.fairchildsemi.com 74LCX573 Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I18 14 74LCX573 Rev. 2.0.0 www.fairchildsemi.com