FAN1655

FAN1655 3A DDR Bus Termination Regulator January 2006 FAN1655 3A DDR Bus Termination Regulator Description The FAN1655 is a low-cost bi-directional LDO specifically designed for terminating DDR memory bus. It can both sink and source up to 2.1A continuous, 3A peak, providing enough current for most DDR applications. Load regulation meets the JEDEC spec, VTT = VREFOUT ± 40mV. The FAN1655 includes a buffered reference voltage capable of supplying up to 5mA current. On-chip thermal limiting provides protection against a combination of power overload and ambient temperature that would create an excessive junction temperature. A shutdown input puts the FAN1655 into a low power mode. The FAN1655 regulator is available in a power-enhanced eTSSOP™-16, standard SOIC-14, and an 8-Lead MLP package. Features ■ Sinks and sources 2.1A continuous, 3A peak ■ 0 to +125°C operating temperature range ■ 5mA Buffered VREFOUT = VDDQ/2 ■ Load regulation: VTT = VREFOUT ± 40mV ■ On-chip thermal limiting ■ Low Cost SO-14, Power-Enhanced eTSSOP or 8-pin 5x6mm MLP packages ■ Low-Current Shutdown Mode ■ Output Short Circuit Protection Applications ■ DDR Terminator VTT supply Ordering Information Part Number FAN1655M FAN1655MX FAN1655MTF FAN1655MTFX FAN1655MPX Temperature Range 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C 0°C to 125°C Package SOIC-14 SOIC-14 eTSSOP-16 eTSSOP-16 MLP-8 Packing Rails Tape and Reel Rails Tape and Reel Tape and Reel Block Diagram VDDQ 200k – VREFOUT VREFIN + VTTFORCE + VTTFORCE – 200k VTTSENSE FAN1655 VSSQ VSS VSS VSS VDD VDD VDD SHDN ©2006 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FAN1655 Rev. 1.1.5 FAN1655 3A DDR Bus Termination Regulator Pin Assignments VDD VDD VTTFORCE VSS VSS VTTFORCE VDD VSS 1 2 3 4 5 6 7 8 FAN1655 16 15 14 13 12 11 10 9 NC VDDQ VREFOUT VSSQ SHDN VREFIN VTTSENSE NC VDD VDD VTTFORCE VSS VSS VTTFORCE VDD 1 2 3 4 5 6 7 FAN1655M 14 13 12 11 10 9 8 VDDQ VREFOUT VSSQ SHDN VREFIN VTTSENSE VSS 16-Lead Plastic eTSSOP-16 θJC = 4˚C/W* *Thermal impedance is measured with the power pad soldered to a 0.5 square inch copper area. The copper area should be connected to Vss (ground) and positioned over an internal power or ground plane to assist in heat dissipation. 14-Lead Plastic SOIC θJC = 37˚C/W, θJA = 88˚C/W VDD VTTFORCE VTTFORCE VDD 1 2 3 4 8 7 6 5 VDDQ VREFOUT SHDN VTTSENSE GND 8-Lead MLP Package (5x6mm) θJC = 4˚C/W, θJA = 34˚C/W as measured on FAN1655MP Eval Board Pin Definitions Pin MLP 1, 4 2, 3 PAD 5 eTSSOP 1, 2, 7 3, 6 4, 5, 8 10 11 SOIC-14 1, 2, 7 3, 6 4, 5, 8 9 10 11 Pin Name VDD VTTFORCE VSS VTTSENSE VREFIN SHDN Pin Function Input power for the LDO. The VTT output voltage. IC Ground. Feedback for remote sense of the VTT voltage. Alternative input for direct control of VTTOUT and VREFOUT. Shutdown. This active low shutdown turns off both VTT and VREFOUT. This pin has an internal pull-down, and must be externally driven high for the IC to be on. Signal Ground. Buffered Voltage Reference Output. VDDQ Input. Attach this pin to the VDDQ supply to generate VTT and VREFOUT. No Internal Connection Connect PAD to Vss Ground Plane 6 12 13 7 8 14 15 9, 16 PAD PAD 12 13 14 VSSQ VREFOUT VDDQ NC 2 www.fairchildsemi.com FAN1655 Rev. 1.1.5 FAN1655 3A DDR Bus Termination Regulator Typical Application VDDQ VDD VTTFORCE 470µF 1 2 3 4 5 6 7 8 10µF 16 15 14 FAN1655 13 12 11 10 9 1nF 10k 10µF VREFOUT SHDN VTTSENSE GND 100µF 6V 1nF (connect to VTTFORCE at the load) GND Figure 1. (eTSSOP pinout shown) Typical Performance Characteristics Quiescent Current vs. Temperature 9 7.5 VREF Output Change vs. IREF 1.0 VDD = VDDQ = 2.5V TA = 25˚C 0.5 QUIESCENT CURRENT (mA) 6 ∆ VREFOUT (mV) 4.5 3 0 -0.5 1.5 0 -60 -1.0 -6 -40 -20 0 20 40 60 80 100 120 140 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 VREF LOAD CURRENT (mA) AMBIENT TEMPERATURE (˚C) Figure 2. Quiescent Current vs. Ambient Temperature Figure 3. Reference Output Load Regulation 1.260 100.0 Current Pulse Duration (S) 1.255 VTT OUTPUT (V) TA=70°C 1.250 10.0 TA=25°C 1.245 1.240 -3000 1.0 -2000 -1000 0 1000 2000 3000 1 1.5 2 2.5 3 VTT Load Current (mA) Peak Load Current (A) Figure 4. VTT Load Regulation Figure 5. Maximum Non-Repetitive Output Current vs. Pulse Width (FAN1655M SO-14 Package) 3 www.fairchildsemi.com FAN1655 Rev. 1.1.5 FAN1655 3A DDR Bus Termination Regulator Absolute Maximum Ratings Supply Voltage VDD, VDDQ Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Power Dissipation, PD FAN1655M (SOIC-14) FAN1655MTF (e-TSSOP) FAN1655MP (MLP) 6V 150˚C -65 to 150˚C 300˚C 1.4W See “Power Dissipation and Derating” Recommended Operating Conditions Parameter Supply Voltage VDD Supply Voltage VDDQ Ambient Operating Temperature VREFIN Conditions Min. 2.3 2.2 0 1.1 Typ. 2.5 2.5 1.25 Max. 3.6 3.0 125 1.5 Units V V ˚C V Electrical Characteristics (VDD = VDDQ = 2.5V ± 0.2V, and TA = 25˚C using circuit in Figure 1, unless otherwise noted.) The • denotes specifications which apply over the specified operating temperature range. Parameter VTT Output Voltage Conditions IOUT = 0A, VREFIN = open VDDQ = 2.3V • VDDQ = 2.5V • VDDQ = 2.7V • IOUT = ±2.1A, VREFIN = open VDDQ = 2.3V VDDQ = 2.5V VDDQ = 2.7V Min. 1.135 1.235 1.335 1.110 1.210 1.310 -50 ±3.1 Typ. 1.150 1.250 1.350 1.150 1.250 1.350 0.3 Max. 1.165 1.265 1.365 1.190 1.290 1.390 50 Units V V V V V V V/µS µA A KΩ VTT Output Slew Rate VTT Leakage Current VTT Current Limit VREFIN Input Impedance VREFOUT Output Voltage Cload = 10µF SHDN = 0V • 100 No load VREFIN = 1.150V • VREFIN = 1.250V • VREFIN = 1.350V • 1.145 1.245 1.345 -5 -10 1.667 0.800 7.5 6 3 50 155 30 20 10 50 75 1.150 1.250 1.350 1.155 1.255 1.355 5 10 V V V mA µA V V mA µA µA µA ˚C ˚C VREFOUT Output Current VREFOUT Leakage Current SHDN Logic High SHDN Logic Low IDD Supply Current VDDQ Leakage Current VDD Leakage Current SHDN Input Current Over-Temperature Shutdown Over-Temperature Hysteresis VDDQ = 2.3V SHDN = 0V • • • • No load, SHDN = 2.7V SHDN = 0V SHDN = 0V SHDN = 2.7V • • • • 4 www.fairchildsemi.com FAN1655 Rev. 1.1.5 FAN1655 3A DDR Bus Termination Regulator Applications Information Output Capacitor selection The JEDEC specification for DDR termination requires that VTT stay within ±40mV of VREF, which must track VDDQ/2 within 1%. During the initial load transient, the output capacitor keeps the output within spec. To stay within the 40mV window, the “load step” due to the load transient current dropping across the output capacitor’s ESR should be kept to around 25mV: where ESR < 25 ----- is given in mΩ, and ∆I is the maximum load current. ∆I For example, to handle a 3A maximum load transient, the ESR should be no greater than 8mΩ. Furthermore, the output capacitor must be able to hold the load in spec while the regulator recovers (about 15µS). A minimum value of 470µF is recommended. The FAN1655 requires a minimum of 100µF of input capacitance with a maximum ESR value of 100mΩ to insure stability. Power Dissipation and Derating The maximum output current (sink or source) for a 1.25V output is: P D ( MAX I OUT ( MAX ) = ---------------------) 1.25 where PD(MAX) is the maximum power dissipation which is: T J ( MAX ) – T A P D ( MAX ) = --------------------------------θ JA where TJ(MAX) is the maximum die temperature of the IC and TA is the operating ambient temperature. FAN1655 has an internal thermal limit at 150°C, which defines TJ(MAX). For the SOIC-14 package, θJA is given at 88°C/W. Using equation 2, the maximum dissipation at TA = 25°C is 1.4W, which is its rated maximum dissipation. The e-TSSOP or MLP package, however, use the PCB copper to cool the IC through the thermal pad on the package bottom. For maximum dissipation, this pad should be soldered to the PCB copper, with as much copper area as possible surrounding it to cool the package. Thermal vias should be placed as close to the thermal pad as possible to transfer heat to other layers of copper on the PCB. With large areas of PCB copper for heat sinking, a θJA of under 40°C/W can easily be achieved. 5 www.fairchildsemi.com FAN1655 Rev. 1.1.5 FAN1655 3A DDR Bus Termination Regulator Mechanical Dimensions 16-Lead eTSSOP 0.10 TYP 16 5.0 ± 0.1 9 -A4.00 -B16 9 6.4 4.4 ± 0.1 3.40 3.2 4.16 7.72 1 8 0.2 C B A ALL LEAD TIPS PIN #1 IDENT. (1.78) 1 8 1.2 MAX ALL LEAD TIPS 0.1 C +0.15 (0.90) –0.10 0.65 TYP 0.42 TYP LAND PATTERN RECOMMENDATION -C0.65 TYP 0.10±0.05 TYP (0.19–0.30) 0.10 M C B A SEE DETAIL A (0.09–0.20) 1.7 MIN 9 16 1.5 MIN 12° TOP & BOTTOM R0.09MIN 0°–8° GAGE PLANE 0.25 8 1 BOTTOM VIEW 0.75 0.45 (1.00) SEATING PLANE DETAIL A NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION ABT, DATED 10/97. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND THE BAR EXTENSIONS. D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 6 www.fairchildsemi.com FAN1655 Rev. 1.1.5 FAN1655 3A DDR Bus Termination Regulator Mechanical Dimensions 14-Lead SOIC S8.71-8.51; 7.62 14 13 12 11 10 9 8 0.50 5.75 1.00 S6.20-5.80; S4.00-3.80 1 2 3 4 1.27 5 6 7 S0.51-0.35; 1.27 7.62 LAND PATTERN RECOMMENDATION S0.50-0.25;X45˚ S0.25-0.10;z S1.75-1.35; S0.25-0.19; S8˚-0˚ S1.27-0.40; SEATING PLANE Notes: 1. This package conforms to JEDEC MS-012, variation AB, ISSUEC dated May, 1990. 2. All dimensions are in millimeters 3. Standard lead finished 200 microinches / 5.08 microns min. Lead/Tin (solder) oncopper 7 www.fairchildsemi.com FAN1655 Rev. 1.1.5 FAN1655 3A DDR Bus Termination Regulator Mechanical Dimensions 5mm x 6mm 8-Lead MLP 5.0 A B 4.50 6.0 3.50 4.25 6.25 0.25 2X C (1.00) 0.25 2X C TOP VIEW 1.27 TYP 0.65 TYP LAND PATTERN RECOMMENDATION 0.10 C (0.25) 1.0 MAX 0.08 C 0.05 0.00 SIDE VIEW 4.25 A 1.75 1 2 3 4 C SEATING PLANE PIN #1 IDENT. (OPTIONAL) 0.75 A 0.35 3.25 A 1.25 NOTES: A) B) C) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-229, DATED 11/2001. DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCES PER ASME Y14.5–1994. 8 1.27 7 6 5 0.28–0.40 A 0.10 M C A B 3.81 A 0.05 M C BOTTOM VIEW 8 www.fairchildsemi.com FAN1655 Rev. 1.1.5 FAN1655 3A DDR Bus Termination Regulator TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST® ActiveArray™ FASTr™ Bottomless™ FPS™ Build it Now™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DOME™ HiSeC™ EcoSPARK™ I2C™ E2CMOS™ i-Lo™ EnSigna™ ImpliedDisconnect™ FACT™ IntelliMAX™ FACT Quiet Series™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I17 9 www.fairchildsemi.com FAN1655 Rev. 1.1.5