FAN6300HNY

FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller December 2009 FAN6300A / FAN6300H Highly Integrated Quasi-Resonant Current Mode PWM Controller Features High-Voltage Startup Quasi-Resonant Operation Cycle-by-Cycle Current Limiting Peak-Current-Mode Control Leading-Edge Blanking (LEB) Internal Minimum tOFF Internal 5ms Soft-Start Over Power Compensation GATE Output Maximum Voltage Auto-Recovery Over-Current Protection(FB Pin) Auto-Recovery Open-Loop Protection(FB Pin) VDD Pin and Output Voltage (DET Pin) OVP Latched Low Frequency Operation (below 100kHz) for FAN6300A High Frequency Operation (up to 190kHz) for FAN6300H Description The highly integrated FAN6300A/H of PWM controller provides several features to enhance the performance of flyback converters. FAN6300A is applied on quasiresonant flyback converters where maximum operating frequency is below 100kHz. FAN6300H is suitable for high-frequency operation (up to 190kHz). A built-in HV startup circuit can provide more startup current to reduce the startup time of the controller. Once the VDD voltage exceeds the turn-on threshold voltage, the HV startup function is disabled immediately to reduce power consumption. An internal valley voltage detector ensures power system operates at quasi-resonant operation over a wide-range of line voltage and any load conditions, as well as reducing switching loss to minimize switching voltage on drain of power MOSFET. To minimize standby power consumption and light-load efficiency, a proprietary green-mode function provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching voltage. The operating frequency is limited by minimum toff time, which is 38µs to 8µs in FAN6300A and 13µs to 3µs in FAN6300H, so FAN6300H can operate at higher switching frequency than FAN6300A. FAN6300A/H controller also provides many protection functions. Pulse-by-pulse current limiting ensures the fixed-peak current limit level, even when a short circuit occurs. Once an open-circuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. As long as VDD drops below the turn-off threshold voltage, the controller also disables PWM output. The gate output is clamped at 18V to protect the power MOS from high gate-source voltage conditions. The minimum tOFF time limit prevents the system frequency from being too high. If the DET pin triggers OVP, internal OTP is triggered and the power system enters latch-mode until AC power is removed. The FAN6300A/H controller is available in the 8-pin Small Outline Package (SOP) and the Dual Inline Package (DIP). Applications AC/DC NB Adapters Open-Frame SMPS © 2009 Fairchild Semiconductor Corporation FAN6300A/H • Rev. 1.0.1 www.fairchildsemi.com FAN6300A/H — Highly-Integrated Quasi-Resonant Current Mode PWM Controller Ordering Information Part Number FAN6300AMY FAN6300HMY FAN6300ANY FAN6300HNY Eco Status Green Green Green Green Operating Temperature Range -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C Package 8-Lead, Small Outline Package (SOP) 8-Lead, Small Outline Package (SOP) 8-Lead, Dual In-line Package (DIP) 8-Lead, Dual In-line Package (DIP) Packing Method Tape & Reel Tape & Reel Tube Tube For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html Application Diagram Figure 1. Typical Application © 2009 Fairchild Semiconductor Corporation FAN6300A(H) Rev. 1.0.1 www.fairchildsemi.com 2 FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller Internal Block Diagram HV 8 4 .2V IH V 27 V T im er 52 m s 2 .1m s 30 µs Starter F B OLP OVP VDD 6 Internal Bias T w o Steps U VLO 16 V/10 V/ 8V FB 2 Soft -Start 5ms 2R Latched R CS 3 Blanking C ircuit PW M C ur rent Lim it ID ET Latched tO F F - M IN 0.3 V V D ET V D ET 2. 5V D ET OVP Latched Valley D etector D RV S SE T Q 18 V 5 GA T E Over-Pow er C om pensation R C LR Q tT IM E -O U T tO F F Blanking S/ H DET 1 5V I D ET 0 .3 V Inter nal OTP Latched 4 GN D 7 NC Figure 2. Functional Block Diagram Marking Information : Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package Type (N = DIP, M = SOP) P: Y = Green Package M: Manufacturing Flow Code Figure 3. Marking Diagram © 2009 Fairchild Semiconductor Corporation FAN6300A / FAN6300H • Rev. 1.0.1 www.fairchildsemi.com 3 FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # Name Description This pin is connected to an auxiliary winding of the transformer via resistors of the divider for the following purposes: - Generates a ZCD signal once the secondary-side switching current falls to zero. - Produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant power limit. The offset is generated in accordance with the input voltage when PWM signal is enabled. - Detects the valley voltage of the switching waveform to achieve the valley voltage switching and minimize the switching losses. A voltage comparator and a 2.5V reference voltage develop a output OVP protection. The ratio of the divider decides what output voltage to stop gate, as an optical coupler and secondary shunt regulator are used. The feedback pin should to be connected to the output of the error amplifier for achieving the voltage control loop. The FB should be connected to the output of the optical coupler if the error-amplifier is equipped at the secondary-side of the power converter. 2 FB For the primary-side control application, FB is applied to connect a RC network to the ground for feedback-loop compensation. The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator connected between the FB and the PWM circuit is used for the loop-gain attenuation. FAN6300A/H performs an open-loop protection once the FB voltage is higher than a threshold voltage (around 4.2V) more than 55ms. 3 4 5 6 7 8 CS GND GATE VDD NC HV Input to the comparator of the over-current protection. A resistor senses the switching current and the resulting voltage is applied to this pin for the cycle-by-cycle current limit. The power ground and signal ground. A 0.1µF decoupling capacitor placed between VDD and GND is recommended. Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 18V. Power supply. The threshold voltages for startup and turn-off are 16V and 10V, respectively. The startup current is less than 20µA and the operating current is lower than 4.5mA. No connect High-voltage startup. 1 DET © 2009 Fairchild Semiconductor Corporation FAN6300A / FAN6300H • Rev. 1.0.1 www.fairchildsemi.com 4 FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VHV VH VL PD TJ TSTG TL ESD DC Supply Voltage HV GATE VFB, VCS, VDET Power Dissipation Parameter Min. Max. 30 500 Unit V V V V mW °C °C °C KV -0.3 -0.3 SOP-8 DIP-8 -55 25.0 7.0 400 800 +150 +150 +270 3.0 1.5 Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering 10 Seconds) Human Body Model, JEDEC:JESD22-A114 Charged Device Model, JEDEC:JESD22-C101 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature Conditions Min. -40 Typ. Max. +125 Unit °C © 2009 Fairchild Semiconductor Corporation FAN6300A / FAN6300H • Rev. 1.0.1 www.fairchildsemi.com 5 FAN6300A/H — Highly Integrated Quasi-Resonant Current Mode PWM Controller Electrical Characteristics Unless otherwise specified, VDD=10~25V, TA=-40°C~125°C (TA=TJ). Symbol VDD Section VOP VDD-ON VDD-PWM-OFF VDD-OFF IDD-ST IDD-OP IDD-GREEN IDD-PWM-OFF VDD-OVP tVDD-OVP IDD-LATCH VHV-MIN IHV IHV-LC Parameter Continuously Operating Voltage Turn-On Threshold Voltage PWM Off Threshold Voltage Turn-Off Threshold Voltage Startup Current Operating Current Green-Mode Operating Supply Current (Average) Operating Current at PWM-Off Phase VDD Over-Voltage Protection (Latch-Off) VDD OVP Debounce Time VDD OVP Latch-Up Holding Current Minimum Startup Voltage on Pin HV Supply Current Drawn from Pin HV Leakage Current After Startup Conditions Min. Typ. Max. 25 Unit V V V V µA mA mA µA V µs µA 15 9 7 VDD=VDD-ON -0.16V GATE Open VDD=15V, fS=60KHz, CL=2nF VDD=15V, fS=2KHz, CL=2nF VDD=VDD-PWM-OFF0.5V 70 26 100 VDD=5V 16 10 8 10 4.5 17 11 9 20 5.5 3.5 80 27 150 42 90 28 200 HV Startup Current Source Section 50 VAC=90V(VDC=120V) VDD=0V HV=500V, VDD=VDD-OFF +1V AV =ΔVCS/ΔVFB 0